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[209.51.188.17]) by mx.google.com with ESMTPS id y5si897175ybk.197.2020.09.08.17.17.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:17:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=APzT0ssM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnnw-0007hx-63 for patch@linaro.org; Tue, 08 Sep 2020 20:17:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37174) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnH-0007eh-Ch for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:16:59 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:36996) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnC-00028Y-K2 for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:16:59 -0400 Received: by mail-pj1-x1044.google.com with SMTP id kk9so432551pjb.2 for ; Tue, 08 Sep 2020 17:16:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qseC2YwIOefPH/0qbFQ7mgbdCBiS9lx6tHPE8i+cDZQ=; b=APzT0ssMUK+Zw5uCrba6nyrgaPnOrf614op5YMdLNMsDiLlepAFNFsuXc9zhpV5Dqi iaWbJoN+woPCDrHnOPfV9fngMgS4alfOgK4Aq0bU9tL9FzMKeQYe2rWImpFvwLLFsoSS 33qbP3mHOPtumRLCZ1tTcLASdkN+uy21pPf1JITbgaP320ZAo3z2lYgZu/wmRqi32dgD Kid/epDWCYsITOxSSexebMLeA9qXuZeB9uBMyIWhdOX/6KNcL7Nf2dxk87lsQE50ohCc FRBfYs25HEOAaWdCsm7pdbSyddONniYa47JAVjygnd3TeQN5A+3JdpE+Fpeh1t31rTQv 45yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qseC2YwIOefPH/0qbFQ7mgbdCBiS9lx6tHPE8i+cDZQ=; b=AivSHO9VSaK35TpWn8Y+UZnvoYCcTNm3z9XlQ5cpgaBC5zsMgfozIh/vUIbOYekEqk 97xhtX/eLL7fScOcw2kYccdhfV0SsTeAxDbc9PvSfaZPNm75ek5iIf8MEp8hCkZgF843 s2TtNQC4zKaooe2pU15gmPqJmOlBCTWef/jZeJqRCGnNDxiu279MhgNPsI/skNJGCQTi zdv47EtCiwzF+LVw3+MNIaOxskMW1EvIwxLS3yEGu2oGjZHFf1gmc0AcEYB9Bln+A3yW atCvRvV4gwUsn0mw4uBQLG/yDlUXgCmSEJsVVMG1/SFRKVH6HF5RAxYBKwte+nrH3yW8 PGVQ== X-Gm-Message-State: AOAM5314VhMnQy/SWKEJa8cwttQfEsNN4Iy58hjz3ymM6R33cqOC0GbA SJvC4DFhtVSiL+ZoDcyV+zZ36EFh/MhhMA== X-Received: by 2002:a17:90b:4acd:: with SMTP id mh13mr1220025pjb.147.1599610611113; Tue, 08 Sep 2020 17:16:51 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:16:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/43] tcg: Adjust simd_desc size encoding Date: Tue, 8 Sep 2020 17:16:05 -0700 Message-Id: <20200909001647.532249-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With larger vector sizes, it turns out oprsz == maxsz, and we only need to represent mismatch for oprsz <= 32. We do, however, need to represent larger oprsz and do so without reducing SIMD_DATA_BITS. Reduce the size of the oprsz field and increase the maxsz field. Steal the oprsz value of 24 to indicate equality with maxsz. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-gvec-desc.h | 38 ++++++++++++++++++++++++------------- tcg/tcg-op-gvec.c | 35 ++++++++++++++++++++++++++-------- 2 files changed, 52 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h index 0224ac3e78..704bd86454 100644 --- a/include/tcg/tcg-gvec-desc.h +++ b/include/tcg/tcg-gvec-desc.h @@ -20,29 +20,41 @@ #ifndef TCG_TCG_GVEC_DESC_H #define TCG_TCG_GVEC_DESC_H -/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */ -#define SIMD_OPRSZ_SHIFT 0 -#define SIMD_OPRSZ_BITS 5 +/* + * This configuration allows MAXSZ to represent 2048 bytes, and + * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32. + * + * Encode this with: + * 0, 1, 3 -> 8, 16, 32 + * 2 -> maxsz + * + * This steals the input that would otherwise map to 24 to match maxsz. + */ +#define SIMD_MAXSZ_SHIFT 0 +#define SIMD_MAXSZ_BITS 8 -#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS) -#define SIMD_MAXSZ_BITS 5 +#define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS) +#define SIMD_OPRSZ_BITS 2 -#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS) +#define SIMD_DATA_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS) #define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT) /* Create a descriptor from components. */ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data); -/* Extract the operation size from a descriptor. */ -static inline intptr_t simd_oprsz(uint32_t desc) -{ - return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8; -} - /* Extract the max vector size from a descriptor. */ static inline intptr_t simd_maxsz(uint32_t desc) { - return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8; + return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8; +} + +/* Extract the operation size from a descriptor. */ +static inline intptr_t simd_oprsz(uint32_t desc) +{ + uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS); + intptr_t o = f * 8 + 8; + intptr_t m = simd_maxsz(desc); + return f == 2 ? m : o; } /* Extract the operation-specific data from a descriptor. */ diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 7ebd9e8298..ddbe06b71a 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -37,11 +37,21 @@ static const TCGOpcode vecop_list_empty[1] = { 0 }; of the operand offsets so that we can check them all at once. */ static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs) { - uint32_t opr_align = oprsz >= 16 ? 15 : 7; - uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7; - tcg_debug_assert(oprsz > 0); - tcg_debug_assert(oprsz <= maxsz); - tcg_debug_assert((oprsz & opr_align) == 0); + uint32_t max_align; + + switch (oprsz) { + case 8: + case 16: + case 32: + tcg_debug_assert(oprsz <= maxsz); + break; + default: + tcg_debug_assert(oprsz == maxsz); + break; + } + tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS)); + + max_align = maxsz >= 16 ? 15 : 7; tcg_debug_assert((maxsz & max_align) == 0); tcg_debug_assert((ofs & max_align) == 0); } @@ -77,12 +87,21 @@ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data) { uint32_t desc = 0; - assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS)); - assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS)); - assert(data == sextract32(data, 0, SIMD_DATA_BITS)); + check_size_align(oprsz, maxsz, 0); + tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS)); oprsz = (oprsz / 8) - 1; maxsz = (maxsz / 8) - 1; + + /* + * We have just asserted in check_size_align that either + * oprsz is {8,16,32} or matches maxsz. Encode the final + * case with '2', as that would otherwise map to 24. + */ + if (oprsz == maxsz) { + oprsz = 2; + } + desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz); desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz); desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data); From patchwork Wed Sep 9 00:16:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249385 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5013301ilg; Tue, 8 Sep 2020 17:18:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIVdkRkKcbzXSpL1lviiY60GEA4IQ3xEW2JlX/2xcZFoP12k/io7ArA2d1on35ECS9Uncj X-Received: by 2002:a05:6902:6cb:: with SMTP id m11mr1975782ybt.310.1599610718188; Tue, 08 Sep 2020 17:18:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610718; cv=none; d=google.com; s=arc-20160816; b=KrO3Pxbfq4qbSBdOceJ+an6ksQwrfNTDQB64rx/nNL2Sa9/Cc3pJTVkNblViEGQML2 jF71nPQ6wdKzwFmChs6H9tW3UjREes6CtECLsMCU9ok82UEaC6B0MDy0IXM5KeCEswPc hsxu1SJ0BvOavT0wQsKXxVP90g3jlY8osBVduA8bFpm7oBgI8Wl0q3lIrtTpuV/+uMnM PLGp4Mk1zMuvBiumJIlZnXqeGTgp4guqiSsldqG+/ZPJl0KCviXvjrG/RmavhrgcAx41 ugs/4DN6xNUqjPJYWSlX8YDyzuLLDS4B9M51aEBO2ap3uQtNcaNY/4/xImCOnH6nK+ab IYGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M09JP0KdqdEA5c3gLeZjmjXMCeg1I39HpfglkqXepjM=; b=OYZTP6IkAdN5Ym0F/SjrlWnZeF07ec+H0LiBdXzVEGml7nKPhn4GUEUoIGABBo6elS OrSiC+i+IyE+e+iYWQgJec1/cpS6ywW0HTJOzCHj3yRVbcbYx9QYT9oCNhkQwVflJwLI BbMhXNXgorL/9JY6zLFnZvkTCHBFlzf9H1StEydsLLgqy5bPKb9zh9915kCUxxgbbnD0 LyQUCNTawto1E50o70OhFL7bw0va1pZVVPnYLi4iN4yAeFcfkcwAKrxymC5ivy4Kye6E h35Xo0yJ0BBnjRyTwAzef8WwSOXdNnS8TJ5jyH+CtK5jy0ajcJJX49whnmaui/Yqxr0V wPSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vaQDhdSw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d205si1006761ybd.264.2020.09.08.17.18.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:18:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vaQDhdSw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33016 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnor-0002Vu-EH for patch@linaro.org; Tue, 08 Sep 2020 20:18:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnH-0007eI-0Z for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:16:59 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:32977) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnD-00028z-8h for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:16:58 -0400 Received: by mail-pf1-x444.google.com with SMTP id c196so693147pfc.0 for ; Tue, 08 Sep 2020 17:16:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=M09JP0KdqdEA5c3gLeZjmjXMCeg1I39HpfglkqXepjM=; b=vaQDhdSw3hzXC13vmH0HnKfLmh2BSTuwvelqVnb0ujOhNcWzVxRFJYLJ3ct46AYcEP ZMm1L38v75+w1AKq8EhTYLepTK/10W2xeVZPYmeLT6LhCARwjRppnt9a5KcO9SKST5H1 6YcBIOoTPtghVGLYYR+NzuUBTHE/e2ctVqJnM6CLfTUq5HLPIMf/U26CPJGKggwDDoZV eAelzZpKs8OxNmKWwlBwqjgVsLV2trvLXXzCtTLjsPhbEkY79/uV/10xG2ZgxyDoU1ev hzORVG6jt6SgdX+YlNylZ/59ZnS9l5pNxilcGumlFBVgftQLp3s+5T6MnucKWUmVkF1x WQIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M09JP0KdqdEA5c3gLeZjmjXMCeg1I39HpfglkqXepjM=; b=pGtk88EIqaSz3k1lkIO2r4qNaseJZWhWNuZEGZyaKaMG/vl+H7c+w+t9b2KbqfsDGr UJ7eNoJhI/tcIorbwkiT96IxHFDz7kxIEe/gTssum9cad3MQCte+BuqU5xtPq7tFGYWI IeT0c1U0aOz+sweG8eUj1NP5CKTGjb/ktrW8OE3wp8iiOqQn5/47nELFTzKlKqu0wodo D5rWCUXbIBBj6Iv4gasCPkgg3r+YInKssHO+bxF5Gye7CgqZ5G2gyhToyEvFSsnPF3+j bZ9FMDnxBConb9Me1cyHLpLI1+ccAKOCsEQhtSc68MQjyHiQ2+iSWb8iylO2jpRiwzzh mi1w== X-Gm-Message-State: AOAM5318x5cReTe5IDQb0BJIPRmiWw06cSJI1FHXt/LIBFLJf+pDpTnc TIBjlBVY0wI6gaeT1+mKkmVo9qaCLALacQ== X-Received: by 2002:a63:4f66:: with SMTP id p38mr963861pgl.284.1599610612758; Tue, 08 Sep 2020 17:16:52 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.16.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:16:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/43] tcg: Drop union from TCGArgConstraint Date: Tue, 8 Sep 2020 17:16:06 -0700 Message-Id: <20200909001647.532249-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The union is unused; let "regs" appear in the main structure without the "u.regs" wrapping. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 4 +--- tcg/tcg.c | 22 +++++++++++----------- tcg/aarch64/tcg-target.c.inc | 14 +++++++------- tcg/arm/tcg-target.c.inc | 26 +++++++++++++------------- tcg/i386/tcg-target.c.inc | 26 +++++++++++++------------- tcg/mips/tcg-target.c.inc | 18 +++++++++--------- tcg/ppc/tcg-target.c.inc | 24 ++++++++++++------------ tcg/riscv/tcg-target.c.inc | 14 +++++++------- tcg/s390/tcg-target.c.inc | 18 +++++++++--------- tcg/sparc/tcg-target.c.inc | 16 ++++++++-------- tcg/tci/tcg-target.c.inc | 2 +- 11 files changed, 91 insertions(+), 93 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 53ce94c2c5..a5a0ea4ada 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -985,9 +985,7 @@ void tcg_dump_op_count(void); typedef struct TCGArgConstraint { uint16_t ct; uint8_t alias_index; - union { - TCGRegSet regs; - } u; + TCGRegSet regs; } TCGArgConstraint; #define TCG_MAX_OP_ARGS 16 diff --git a/tcg/tcg.c b/tcg/tcg.c index 62f299e36e..dcb38bf1e0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2210,7 +2210,7 @@ static int get_constraint_priority(const TCGOpDef *def, int k) return 0; n = 0; for(i = 0; i < TCG_TARGET_NB_REGS; i++) { - if (tcg_regset_test_reg(arg_ct->u.regs, i)) + if (tcg_regset_test_reg(arg_ct->regs, i)) n++; } } @@ -2268,7 +2268,7 @@ static void process_op_defs(TCGContext *s) /* Incomplete TCGTargetOpDef entry. */ tcg_debug_assert(ct_str != NULL); - def->args_ct[i].u.regs = 0; + def->args_ct[i].regs = 0; def->args_ct[i].ct = 0; while (*ct_str != '\0') { switch(*ct_str) { @@ -2855,13 +2855,13 @@ static void liveness_pass_1(TCGContext *s) pset = la_temp_pref(ts); set = *pset; - set &= ct->u.regs; + set &= ct->regs; if (ct->ct & TCG_CT_IALIAS) { set &= op->output_pref[ct->alias_index]; } /* If the combination is not possible, restart. */ if (set == 0) { - set = ct->u.regs; + set = ct->regs; } *pset = set; } @@ -3551,8 +3551,8 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) return; } - dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs; - dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs; + dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; + dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs; /* Allocate the output register now. */ if (ots->val_type != TEMP_VAL_REG) { @@ -3706,10 +3706,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } } - temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs); + temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs); reg = ts->reg; - if (tcg_regset_test_reg(arg_ct->u.regs, reg)) { + if (tcg_regset_test_reg(arg_ct->regs, reg)) { /* nothing to do : the constraint is satisfied */ } else { allocate_in_reg: @@ -3717,7 +3717,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) and move the temporary register into it */ temp_load(s, ts, tcg_target_available_regs[ts->type], i_allocated_regs, 0); - reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, + reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { /* @@ -3772,11 +3772,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) && !const_args[arg_ct->alias_index]) { reg = new_args[arg_ct->alias_index]; } else if (arg_ct->ct & TCG_CT_NEWREG) { - reg = tcg_reg_alloc(s, arg_ct->u.regs, + reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs | o_allocated_regs, op->output_pref[k], ts->indirect_base); } else { - reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, + reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, op->output_pref[k], ts->indirect_base); } tcg_regset_set_reg(o_allocated_regs, reg); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 948c35d825..d4b7cb4867 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -129,22 +129,22 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': /* general registers */ ct->ct |= TCG_CT_REG; - ct->u.regs |= 0xffffffffu; + ct->regs |= 0xffffffffu; break; case 'w': /* advsimd registers */ ct->ct |= TCG_CT_REG; - ct->u.regs |= 0xffffffff00000000ull; + ct->regs |= 0xffffffff00000000ull; break; case 'l': /* qemu_ld / qemu_st address, data_reg */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffffu; + ct->regs = 0xffffffffu; #ifdef CONFIG_SOFTMMU /* x0 and x1 will be overwritten when reading the tlb entry, and x2, and x3 for helper args, better to avoid using them. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3); + tcg_regset_reset_reg(ct->regs, TCG_REG_X0); + tcg_regset_reset_reg(ct->regs, TCG_REG_X1); + tcg_regset_reset_reg(ct->regs, TCG_REG_X2); + tcg_regset_reset_reg(ct->regs, TCG_REG_X3); #endif break; case 'A': /* Valid for arithmetic immediate (positive or negative). */ diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index bc1e1b5a71..978eb1dd70 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -254,40 +254,40 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; + ct->regs = 0xffff; break; /* qemu_ld address */ case 'l': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; + ct->regs = 0xffff; #ifdef CONFIG_SOFTMMU /* r0-r2,lr will be overwritten when reading the tlb entry, so don't use these. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); + tcg_regset_reset_reg(ct->regs, TCG_REG_R0); + tcg_regset_reset_reg(ct->regs, TCG_REG_R1); + tcg_regset_reset_reg(ct->regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->regs, TCG_REG_R14); #endif break; /* qemu_st address & data */ case 's': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; + ct->regs = 0xffff; /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) and r0-r1 doing the byte swapping, so don't use these. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); + tcg_regset_reset_reg(ct->regs, TCG_REG_R0); + tcg_regset_reset_reg(ct->regs, TCG_REG_R1); #if defined(CONFIG_SOFTMMU) /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->regs, TCG_REG_R2); #if TARGET_LONG_BITS == 64 /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #endif - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); + tcg_regset_reset_reg(ct->regs, TCG_REG_R14); #endif break; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 0155c0691c..8661ec3393 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -209,42 +209,42 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch(*ct_str++) { case 'a': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX); + tcg_regset_set_reg(ct->regs, TCG_REG_EAX); break; case 'b': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX); + tcg_regset_set_reg(ct->regs, TCG_REG_EBX); break; case 'c': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX); + tcg_regset_set_reg(ct->regs, TCG_REG_ECX); break; case 'd': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX); + tcg_regset_set_reg(ct->regs, TCG_REG_EDX); break; case 'S': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI); + tcg_regset_set_reg(ct->regs, TCG_REG_ESI); break; case 'D': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); + tcg_regset_set_reg(ct->regs, TCG_REG_EDI); break; case 'q': /* A register that can be used as a byte operand. */ ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; + ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; break; case 'Q': /* A register with an addressable second byte (e.g. %ah). */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xf; + ct->regs = 0xf; break; case 'r': /* A general register. */ ct->ct |= TCG_CT_REG; - ct->u.regs |= ALL_GENERAL_REGS; + ct->regs |= ALL_GENERAL_REGS; break; case 'W': /* With TZCNT/LZCNT, we can have operand-size as an input. */ @@ -253,15 +253,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'x': /* A vector register. */ ct->ct |= TCG_CT_REG; - ct->u.regs |= ALL_VECTOR_REGS; + ct->regs |= ALL_VECTOR_REGS; break; /* qemu_ld/st address constraint */ case 'L': ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); + ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; + tcg_regset_reset_reg(ct->regs, TCG_REG_L0); + tcg_regset_reset_reg(ct->regs, TCG_REG_L1); break; case 'e': diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index bd5b8e09a0..d49a02bb03 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -196,28 +196,28 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch(*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; break; case 'L': /* qemu_ld input arg constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); + ct->regs = 0xffffffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); + tcg_regset_reset_reg(ct->regs, TCG_REG_A2); } #endif break; case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); + ct->regs = 0xffffffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3); + tcg_regset_reset_reg(ct->regs, TCG_REG_A2); + tcg_regset_reset_reg(ct->regs, TCG_REG_A3); } else { - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1); + tcg_regset_reset_reg(ct->regs, TCG_REG_A1); } #endif break; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 393c4b30e0..450b555522 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -225,33 +225,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'A': case 'B': case 'C': case 'D': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A'); + tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A'); break; case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; break; case 'v': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff00000000ull; + ct->regs = 0xffffffff00000000ull; break; case 'L': /* qemu_ld constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + ct->regs = 0xffffffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); + tcg_regset_reset_reg(ct->regs, TCG_REG_R4); + tcg_regset_reset_reg(ct->regs, TCG_REG_R5); #endif break; case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + ct->regs = 0xffffffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); + tcg_regset_reset_reg(ct->regs, TCG_REG_R4); + tcg_regset_reset_reg(ct->regs, TCG_REG_R5); + tcg_regset_reset_reg(ct->regs, TCG_REG_R6); #endif break; case 'I': diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2dfb07e247..0a69839adb 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -138,19 +138,19 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; break; case 'L': /* qemu_ld/qemu_st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ #if defined(CONFIG_SOFTMMU) - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]); #endif break; case 'I': diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 985115acfb..9cd266a2d0 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -409,24 +409,24 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': /* all registers */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; + ct->regs = 0xffff; break; case 'L': /* qemu_ld/st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); + ct->regs = 0xffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->regs, TCG_REG_R4); break; case 'a': /* force R2 for division */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0; - tcg_regset_set_reg(ct->u.regs, TCG_REG_R2); + ct->regs = 0; + tcg_regset_set_reg(ct->regs, TCG_REG_R2); break; case 'b': /* force R3 for division */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0; - tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); + ct->regs = 0; + tcg_regset_set_reg(ct->regs, TCG_REG_R3); break; case 'A': ct->ct |= TCG_CT_CONST_S33; diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 0f1d91fc21..c662293fc7 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -326,27 +326,27 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; break; case 'R': ct->ct |= TCG_CT_REG; - ct->u.regs = ALL_64; + ct->regs = ALL_64; break; case 'A': /* qemu_ld/st address constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; + ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; reserve_helpers: - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); + tcg_regset_reset_reg(ct->regs, TCG_REG_O0); + tcg_regset_reset_reg(ct->regs, TCG_REG_O1); + tcg_regset_reset_reg(ct->regs, TCG_REG_O2); break; case 's': /* qemu_st data 32-bit constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; goto reserve_helpers; case 'S': /* qemu_st data 64-bit constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = ALL_64; + ct->regs = ALL_64; goto reserve_helpers; case 'I': ct->ct |= TCG_CT_CONST_S11; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 992d50cb1e..a7215f346f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -393,7 +393,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'L': /* qemu_ld constraint */ case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1; + ct->regs = BIT(TCG_TARGET_NB_REGS) - 1; break; default: return NULL; From patchwork Wed Sep 9 00:16:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249382 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5012548ilg; Tue, 8 Sep 2020 17:17:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9YlxxA/bp+J/uOoJWnpZv8MQ6fJI+dTf6ixYnAJlh5FLuapA7N0H4RraNcEUqOmPYkwxY X-Received: by 2002:a25:afd0:: with SMTP id d16mr2291390ybj.177.1599610630539; Tue, 08 Sep 2020 17:17:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610630; cv=none; d=google.com; s=arc-20160816; b=rG7zIjiCFd4tZ3Phy/UNSzXSRDpnresLiDjeyNoKnEgs+10YqjRM62oK2X5QrQ37dZ ZSnN99Hlg6j43ljH1Vu7O5H7Z+DEq5VXLIp483K6/77HSHwPnjdu0hRCTGBIqIAz0qpb phCydGY4wjKj1oKuZ+IR/HhwD3r8cTL/mTScQGofAO+tuOMYwNSq0PwRTo6jo9BG22eU neqOBPydaRqvteE3VUzxBj/JbMFxh8wu/SnWnPXF9QVrr0BscjWYMpbkFNEmV44RAWFr wZ1WNQ79TM21rqyfeww5jwA7cM+YTtqty94ixkIyUD5bLJdMA/XkrpKhptq+k+5ghdZs +c9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2hOHW45ulVj15284ZrX31Jc4JgC7jvorBgpIK9v2dLM=; b=fPy/7vaQHTk6D06JkzlzemZwMusL57+KcnH9xDYK1XMUMkMOJdCs6Bl5WyEf4l9VjT ZaWmhr/mm2tA7kb+z7o75A07nPxHf9VRNx/OExUG9Nogm7BjrBMY/Ai7utG5DMQRbo9K RBSqKoVr8LyjWgsPSw166KZY1wwYD4FZNsgUlFSuyfxsk7jqHv5HUi+UuKDpBBmChOks NFK+7eA2fGaEWK7irQGas8jvBcF6ZdzkD8YsYVOqZBq49ZEQRds9R9WZIbsvk1cYSYfV qDAUd1KgFbF+sqYB+TqTTAUk3XZxLsLtcH1mEB0x0tCCNB1HONbB6mccNsQCQKpJ1YhU smzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pScfQrMz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This uses an existing hole in the TCGArgConstraint structure and will be convenient for keeping the data in one place. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 35 +++++++++++++++++------------------ 2 files changed, 18 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index a5a0ea4ada..63955ac85b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -985,6 +985,7 @@ void tcg_dump_op_count(void); typedef struct TCGArgConstraint { uint16_t ct; uint8_t alias_index; + uint8_t sort_index; TCGRegSet regs; } TCGArgConstraint; @@ -1015,7 +1016,6 @@ typedef struct TCGOpDef { uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; uint8_t flags; TCGArgConstraint *args_ct; - int *sorted_args; #if defined(CONFIG_DEBUG_TCG) int used; #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index dcb38bf1e0..0a04b6cbd9 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -944,7 +944,6 @@ void tcg_context_init(TCGContext *s) int op, total_args, n, i; TCGOpDef *def; TCGArgConstraint *args_ct; - int *sorted_args; TCGTemp *ts; memset(s, 0, sizeof(*s)); @@ -960,14 +959,11 @@ void tcg_context_init(TCGContext *s) } args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args); - sorted_args = g_malloc(sizeof(int) * total_args); for(op = 0; op < NB_OPS; op++) { def = &tcg_op_defs[op]; def->args_ct = args_ct; - def->sorted_args = sorted_args; n = def->nb_iargs + def->nb_oargs; - sorted_args += n; args_ct += n; } @@ -2220,20 +2216,23 @@ static int get_constraint_priority(const TCGOpDef *def, int k) /* sort from highest priority to lowest */ static void sort_constraints(TCGOpDef *def, int start, int n) { - int i, j, p1, p2, tmp; + int i, j; + TCGArgConstraint *a = def->args_ct; - for(i = 0; i < n; i++) - def->sorted_args[start + i] = start + i; - if (n <= 1) + for (i = 0; i < n; i++) { + a[start + i].sort_index = start + i; + } + if (n <= 1) { return; - for(i = 0; i < n - 1; i++) { - for(j = i + 1; j < n; j++) { - p1 = get_constraint_priority(def, def->sorted_args[start + i]); - p2 = get_constraint_priority(def, def->sorted_args[start + j]); + } + for (i = 0; i < n - 1; i++) { + for (j = i + 1; j < n; j++) { + int p1 = get_constraint_priority(def, a[start + i].sort_index); + int p2 = get_constraint_priority(def, a[start + j].sort_index); if (p1 < p2) { - tmp = def->sorted_args[start + i]; - def->sorted_args[start + i] = def->sorted_args[start + j]; - def->sorted_args[start + j] = tmp; + int tmp = a[start + i].sort_index; + a[start + i].sort_index = a[start + j].sort_index; + a[start + j].sort_index = tmp; } } } @@ -3659,7 +3658,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) for (k = 0; k < nb_iargs; k++) { TCGRegSet i_preferred_regs, o_preferred_regs; - i = def->sorted_args[nb_oargs + k]; + i = def->args_ct[nb_oargs + k].sort_index; arg = op->args[i]; arg_ct = &def->args_ct[i]; ts = arg_temp(arg); @@ -3695,7 +3694,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) int k2, i2; reg = ts->reg; for (k2 = 0 ; k2 < k ; k2++) { - i2 = def->sorted_args[nb_oargs + k2]; + i2 = def->args_ct[nb_oargs + k2].sort_index; if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && reg == new_args[i2]) { goto allocate_in_reg; @@ -3760,7 +3759,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* satisfy the output constraints */ for(k = 0; k < nb_oargs; k++) { - i = def->sorted_args[k]; + i = def->args_ct[k].sort_index; arg = op->args[i]; arg_ct = &def->args_ct[i]; ts = arg_temp(arg); From patchwork Wed Sep 9 00:16:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249383 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5012587ilg; Tue, 8 Sep 2020 17:17:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJygKbD7WTLM4QnSCpYQt3xUpaiTHf2iuYlSS4oXxuZl3VwI1cqkw1LlJvItVPgElzoHdmOU X-Received: by 2002:a25:8b06:: with SMTP id i6mr2439386ybl.74.1599610634213; Tue, 08 Sep 2020 17:17:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610634; cv=none; d=google.com; s=arc-20160816; b=FC0E+CeGYzmMRra39bYWUgGcjNMoWj7I/QMJni8WOE+UklJhHwdVpBV1V+dRh+YyHw /WAvjJXZf5/CQviFfNQvBWCqowPPQIBoXzU7vz7FjYZOGRree80OjC/MNYBcV20o6YoD yWR8QuEMGQJD8TevjlCDSYSdT33qq59Zw+z/TNfd9/jrCQYxOzTv+B6azzJv6t0hEQ1p stPXlU2VD4BKgRBx3zqBe0LNqYvckk7kdt+jWWu/IILoK+ywBo8HEwRKs9zKFBkc3Iub NiZWpgIq+GDHQFXtsP0vW7niqsocBgBrSFn1T7dLABQxN72kTU0zLP4XEsQd/FLyPayv OaWw== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This wasn't actually used for anything, really. All variable operands must accept registers, and which are indicated by the set in TCGArgConstraint.regs. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 - tcg/tcg.c | 15 ++++----------- tcg/aarch64/tcg-target.c.inc | 3 --- tcg/arm/tcg-target.c.inc | 3 --- tcg/i386/tcg-target.c.inc | 11 ----------- tcg/mips/tcg-target.c.inc | 3 --- tcg/ppc/tcg-target.c.inc | 5 ----- tcg/riscv/tcg-target.c.inc | 2 -- tcg/s390/tcg-target.c.inc | 4 ---- tcg/sparc/tcg-target.c.inc | 5 ----- tcg/tci/tcg-target.c.inc | 1 - 11 files changed, 4 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 63955ac85b..3168315bb8 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -979,7 +979,6 @@ void tcg_dump_op_count(void); #define TCG_CT_ALIAS 0x80 #define TCG_CT_IALIAS 0x40 #define TCG_CT_NEWREG 0x20 /* output requires a new register */ -#define TCG_CT_REG 0x01 #define TCG_CT_CONST 0x02 /* any constant of register size */ typedef struct TCGArgConstraint { diff --git a/tcg/tcg.c b/tcg/tcg.c index 0a04b6cbd9..a618497c94 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2194,21 +2194,14 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) /* we give more priority to constraints with less registers */ static int get_constraint_priority(const TCGOpDef *def, int k) { - const TCGArgConstraint *arg_ct; + const TCGArgConstraint *arg_ct = &def->args_ct[k]; + int n; - int i, n; - arg_ct = &def->args_ct[k]; if (arg_ct->ct & TCG_CT_ALIAS) { /* an alias is equivalent to a single register */ n = 1; } else { - if (!(arg_ct->ct & TCG_CT_REG)) - return 0; - n = 0; - for(i = 0; i < TCG_TARGET_NB_REGS; i++) { - if (tcg_regset_test_reg(arg_ct->regs, i)) - n++; - } + n = ctpop64(arg_ct->regs); } return TCG_TARGET_NB_REGS - n + 1; } @@ -2276,7 +2269,7 @@ static void process_op_defs(TCGContext *s) int oarg = *ct_str - '0'; tcg_debug_assert(ct_str == tdefs->args_ct_str[i]); tcg_debug_assert(oarg < def->nb_oargs); - tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG); + tcg_debug_assert(def->args_ct[oarg].regs != 0); /* TCG_CT_ALIAS is for the output arguments. The input is tagged with TCG_CT_IALIAS. */ def->args_ct[i] = def->args_ct[oarg]; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d4b7cb4867..479a9d26be 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -128,15 +128,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': /* general registers */ - ct->ct |= TCG_CT_REG; ct->regs |= 0xffffffffu; break; case 'w': /* advsimd registers */ - ct->ct |= TCG_CT_REG; ct->regs |= 0xffffffff00000000ull; break; case 'l': /* qemu_ld / qemu_st address, data_reg */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffffu; #ifdef CONFIG_SOFTMMU /* x0 and x1 will be overwritten when reading the tlb entry, diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 978eb1dd70..62c37a954b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -253,13 +253,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; break; /* qemu_ld address */ case 'l': - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; #ifdef CONFIG_SOFTMMU /* r0-r2,lr will be overwritten when reading the tlb entry, @@ -274,7 +272,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, /* qemu_st address & data */ case 's': - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) and r0-r1 doing the byte swapping, so don't use these. */ diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 8661ec3393..2f696074ab 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -208,42 +208,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch(*ct_str++) { case 'a': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EAX); break; case 'b': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EBX); break; case 'c': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_ECX); break; case 'd': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EDX); break; case 'S': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_ESI); break; case 'D': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EDI); break; case 'q': /* A register that can be used as a byte operand. */ - ct->ct |= TCG_CT_REG; ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; break; case 'Q': /* A register with an addressable second byte (e.g. %ah). */ - ct->ct |= TCG_CT_REG; ct->regs = 0xf; break; case 'r': /* A general register. */ - ct->ct |= TCG_CT_REG; ct->regs |= ALL_GENERAL_REGS; break; case 'W': @@ -252,13 +243,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'x': /* A vector register. */ - ct->ct |= TCG_CT_REG; ct->regs |= ALL_VECTOR_REGS; break; /* qemu_ld/st address constraint */ case 'L': - ct->ct |= TCG_CT_REG; ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; tcg_regset_reset_reg(ct->regs, TCG_REG_L0); tcg_regset_reset_reg(ct->regs, TCG_REG_L1); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d49a02bb03..98c6a41caf 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -195,11 +195,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch(*ct_str++) { case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'L': /* qemu_ld input arg constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; tcg_regset_reset_reg(ct->regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) @@ -209,7 +207,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, #endif break; case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; tcg_regset_reset_reg(ct->regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 450b555522..7a5760bb23 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -224,19 +224,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'A': case 'B': case 'C': case 'D': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A'); break; case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'v': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff00000000ull; break; case 'L': /* qemu_ld constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU @@ -245,7 +241,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, #endif break; case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 0a69839adb..d536f3ccc1 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -137,12 +137,10 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'L': /* qemu_ld/qemu_st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ #if defined(CONFIG_SOFTMMU) diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 9cd266a2d0..c5e096449b 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -408,23 +408,19 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': /* all registers */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; break; case 'L': /* qemu_ld/st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; tcg_regset_reset_reg(ct->regs, TCG_REG_R2); tcg_regset_reset_reg(ct->regs, TCG_REG_R3); tcg_regset_reset_reg(ct->regs, TCG_REG_R4); break; case 'a': /* force R2 for division */ - ct->ct |= TCG_CT_REG; ct->regs = 0; tcg_regset_set_reg(ct->regs, TCG_REG_R2); break; case 'b': /* force R3 for division */ - ct->ct |= TCG_CT_REG; ct->regs = 0; tcg_regset_set_reg(ct->regs, TCG_REG_R3); break; diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index c662293fc7..44373d742b 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -325,15 +325,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'R': - ct->ct |= TCG_CT_REG; ct->regs = ALL_64; break; case 'A': /* qemu_ld/st address constraint */ - ct->ct |= TCG_CT_REG; ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; reserve_helpers: tcg_regset_reset_reg(ct->regs, TCG_REG_O0); @@ -341,11 +338,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, tcg_regset_reset_reg(ct->regs, TCG_REG_O2); break; case 's': /* qemu_st data 32-bit constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; goto reserve_helpers; case 'S': /* qemu_st data 64-bit constraint */ - ct->ct |= TCG_CT_REG; ct->regs = ALL_64; goto reserve_helpers; case 'I': diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index a7215f346f..231b9b1775 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -392,7 +392,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'r': case 'L': /* qemu_ld constraint */ case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = BIT(TCG_TARGET_NB_REGS) - 1; break; default: From patchwork Wed Sep 9 00:16:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249386 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5013365ilg; Tue, 8 Sep 2020 17:18:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy1qYj5xqdQspaDz5osntApyhxjCm9M8LZgd/fDuIm1090lgPXtjrTy6ZSE4z3apdcmTvYH X-Received: by 2002:a5b:904:: with SMTP id a4mr2275787ybq.59.1599610724886; Tue, 08 Sep 2020 17:18:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610724; cv=none; d=google.com; s=arc-20160816; b=a59t+B1qcc0ZHTZmW5mk6EKVqMN0vEm78hU/ZlSeFh8jlI37GxEO/kz6BYjrTQET48 /ybYsV6PF1f55ktESFrqMMftC4khQ2wK/Ot4DkaB2UQryO7avLbilG+KkERvnmumrwqL 53E0ThqKOB8nNhWW0d4yA0vP4EEPrtyqft58u5P2bYltQwtvQT7FVkaKmzu2CBbb/lv1 Feh3Y2me7QAEMWBXKH13zZBxtAOuK154CmnP6XYd7XjwPqLnKEt9uVs4Nrs4OOOfnU2u waUJifqJ5N3jVEFp+Mbo+p0mqXf3te0IXpnsWtjx+bzTCwYfVPBSx3PS2ufIf1RLC6Ki l6xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=71Q465nC1T+L79svLwzYh0YmBPONC9zJSTGU30GzRog=; b=xRPlVjHPUo52RLCd5Z70bNH7cyBbz00evXf8sbs5lzvCzo5v/gy/U+Bq3XrgXXTnF8 FGsveH3iqdv11iUCJb7KavH58kPygwnREnAtJfqiG5e24zEmwToa/oXbEKtgEKPVpyry wKzWJzy0X44xTmsmul4k17slxErtf169VlE/pjnTbxuuDDI/aKm1Pk5huUV1d1UuUS2G pbtUGWeC64BPZ+pJDdZ4po3rFUcPSnlZgQ2+hInGkOi+/w77R/5T/AeBtR1NSuKJkbBo Eri4uTG8534xuWGVnLcXjr68XwwxRpzR6tQDQfmV4r/FLgkG8XrAnxVd1zeaj9HF+2JF RrRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="nZ/A8Nd1"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are easier to set and test when they have their own fields. Reduce the size of alias_index and sort_index to 4 bits, which is sufficient for TCG_MAX_OP_ARGS. This leaves only the bits indicating constants within the ct field. Move all initialization to allocation time, rather than init individual fields in process_op_defs. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 14 +++++++------- tcg/tcg.c | 28 ++++++++++++---------------- 2 files changed, 19 insertions(+), 23 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 3168315bb8..e8629b58c8 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -976,15 +976,15 @@ int64_t tcg_cpu_exec_time(void); void tcg_dump_info(void); void tcg_dump_op_count(void); -#define TCG_CT_ALIAS 0x80 -#define TCG_CT_IALIAS 0x40 -#define TCG_CT_NEWREG 0x20 /* output requires a new register */ -#define TCG_CT_CONST 0x02 /* any constant of register size */ +#define TCG_CT_CONST 1 /* any constant of register size */ typedef struct TCGArgConstraint { - uint16_t ct; - uint8_t alias_index; - uint8_t sort_index; + unsigned ct : 16; + unsigned alias_index : 4; + unsigned sort_index : 4; + bool oalias : 1; + bool ialias : 1; + bool newreg : 1; TCGRegSet regs; } TCGArgConstraint; diff --git a/tcg/tcg.c b/tcg/tcg.c index a618497c94..ad4b7fb90f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -958,7 +958,7 @@ void tcg_context_init(TCGContext *s) total_args += n; } - args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args); + args_ct = g_new0(TCGArgConstraint, total_args); for(op = 0; op < NB_OPS; op++) { def = &tcg_op_defs[op]; @@ -2197,7 +2197,7 @@ static int get_constraint_priority(const TCGOpDef *def, int k) const TCGArgConstraint *arg_ct = &def->args_ct[k]; int n; - if (arg_ct->ct & TCG_CT_ALIAS) { + if (arg_ct->oalias) { /* an alias is equivalent to a single register */ n = 1; } else { @@ -2260,8 +2260,6 @@ static void process_op_defs(TCGContext *s) /* Incomplete TCGTargetOpDef entry. */ tcg_debug_assert(ct_str != NULL); - def->args_ct[i].regs = 0; - def->args_ct[i].ct = 0; while (*ct_str != '\0') { switch(*ct_str) { case '0' ... '9': @@ -2270,18 +2268,18 @@ static void process_op_defs(TCGContext *s) tcg_debug_assert(ct_str == tdefs->args_ct_str[i]); tcg_debug_assert(oarg < def->nb_oargs); tcg_debug_assert(def->args_ct[oarg].regs != 0); - /* TCG_CT_ALIAS is for the output arguments. - The input is tagged with TCG_CT_IALIAS. */ def->args_ct[i] = def->args_ct[oarg]; - def->args_ct[oarg].ct |= TCG_CT_ALIAS; + /* The output sets oalias. */ + def->args_ct[oarg].oalias = true; def->args_ct[oarg].alias_index = i; - def->args_ct[i].ct |= TCG_CT_IALIAS; + /* The input sets ialias. */ + def->args_ct[i].ialias = true; def->args_ct[i].alias_index = oarg; } ct_str++; break; case '&': - def->args_ct[i].ct |= TCG_CT_NEWREG; + def->args_ct[i].newreg = true; ct_str++; break; case 'i': @@ -2848,7 +2846,7 @@ static void liveness_pass_1(TCGContext *s) set = *pset; set &= ct->regs; - if (ct->ct & TCG_CT_IALIAS) { + if (ct->ialias) { set &= op->output_pref[ct->alias_index]; } /* If the combination is not possible, restart. */ @@ -3665,7 +3663,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } i_preferred_regs = o_preferred_regs = 0; - if (arg_ct->ct & TCG_CT_IALIAS) { + if (arg_ct->ialias) { o_preferred_regs = op->output_pref[arg_ct->alias_index]; if (ts->fixed_reg) { /* if fixed register, we must allocate a new register @@ -3688,8 +3686,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) reg = ts->reg; for (k2 = 0 ; k2 < k ; k2++) { i2 = def->args_ct[nb_oargs + k2].sort_index; - if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && - reg == new_args[i2]) { + if (def->args_ct[i2].ialias && reg == new_args[i2]) { goto allocate_in_reg; } } @@ -3760,10 +3757,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* ENV should not be modified. */ tcg_debug_assert(!ts->fixed_reg); - if ((arg_ct->ct & TCG_CT_ALIAS) - && !const_args[arg_ct->alias_index]) { + if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { reg = new_args[arg_ct->alias_index]; - } else if (arg_ct->ct & TCG_CT_NEWREG) { + } else if (arg_ct->newreg) { reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs | o_allocated_regs, op->output_pref[k], ts->indirect_base); From patchwork Wed Sep 9 00:16:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249390 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5014231ilg; Tue, 8 Sep 2020 17:20:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzq0VcaL0Jy0pJNVBGtdbOqySJbloUaBkEhPiEKhyaKMs7r6SHpbr/IOqJ2eJqhWs8hZCXH X-Received: by 2002:a25:2d48:: with SMTP id s8mr2374476ybe.8.1599610828414; Tue, 08 Sep 2020 17:20:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610828; cv=none; d=google.com; s=arc-20160816; b=pQ755f8LT7QN2mDyMCSR9YEr2mjkv04g1M0uPgsLiKmRGx/yIeE0uCLANvmj+IauHj Y15Cbf6q/1CFrBL8MosG9fxOa+gF/P1C5p0dnid0ngwkC20qYX+Uel/yDnYcf9A5skHn QNOV6z5u7DOd9VFMB4wHpeoMBXEtger2KlWtXuDiIb2AosWv0LR15roSiQZkn33L+bMa pykPSm/yYYarb5/QN5fid6prjjG1N2qgA/YiIF4GO0IB/8SVRLOmEl1oYQ2dKatBf2RA wTiKlv5gQMae6l8HWCQd04SXmb97pwgNrxNHFxTDTDYciXkw8JAqK/AsbGyx8tJmP6sZ 92gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8mf4rmkmBN5Xe+gj6aRnmRXtibnvJ52kCblqiE5PJ2w=; b=lx+mwomTiDJ8Pkgo+sFppKNbGK7OWRc3v2UordZEkY6tnA1XVt/IMLGqWogF5WER+3 2BJiYLP9NAjnxz8RggEpZNI4UwAm4e2+PiIe4kyUD9eyTidQtKFj1AtVoH5Kaxni3aRb 6eVMBzvMi9rapFgl5tq9MfmP2AX7i6/7/n7zROIAkSyExiKy5z/7V3hh73wRbYxM6Dgz uKkb0TGa/Q1yvW8F74wayOebzwbNsAdJPqZdbwwzXKBuUC/upSp9pr5g8GqBRUFGJdSH E/99rO2jgqKFo4inf0DxwnzIWCREhF26pQQFP1ID5sD2lxb3SQSz1HIuMo++ed9So/TB WKcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uov3iGyE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 3 --- 1 file changed, 3 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e8629b58c8..8804a8c4a2 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1015,9 +1015,6 @@ typedef struct TCGOpDef { uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; uint8_t flags; TCGArgConstraint *args_ct; -#if defined(CONFIG_DEBUG_TCG) - int used; -#endif } TCGOpDef; extern TCGOpDef tcg_op_defs[]; From patchwork Wed Sep 9 00:16:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249393 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5014781ilg; Tue, 8 Sep 2020 17:21:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz9rfC8CDYNWpk496u93a4ajRoM52Fe25ltHwxev1T0EWQq8OeZKomY7WlzCFOBzR1yZ+mp X-Received: by 2002:a25:dc13:: with SMTP id y19mr2109528ybe.247.1599610897307; Tue, 08 Sep 2020 17:21:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610897; cv=none; d=google.com; s=arc-20160816; b=QQAB32vNjo+wRzgGMUiS8UdghwGuW94B5VwZHz7Jin3qocPI3j63KOxU9h/QzOA7A4 Ys5bCuHzaIQtX75QPO6ZbadQUVTKmK9Im3u2QF//u3iHVIbCR7H40HSGs7H0fQO4cu18 nM4lkgzsfgPkZ2gTiS1RAEFO/co1Pg5AJKt4xb4QrMQO72zK+Sttd6NYYPEqePW8BBmA fg1oZrnO6LqKOs2CLStC1iTbdavt8r02+V66zh+RCoRkgvT8mvYQO23ATbYb0igyLSAk f4t90GqPehGbssC3Pc7VCbUetlbgku2dnND8jGfItHzXkLwQTO2IbCznB3a8aBaxpTOz EXjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gnZVZh1VIOx2Bn7nb5JDBu+SrUOXUk1VIW8AryTGMI0=; b=PDZTQDWkgybI0moZaiyp8KjPrJhz7Bh1lJWbVRGFINy9lswzRTNAKM/Y7N8Ew0miLF FWZd7Ml5kjR/6XM8dNDRb768UO9byX8FfYMYDMWGHU5Ei7EfEdXewCszE+Q8JxMfsEZA hWTRlw1DbBEt8xhf40RRNusmh3eA/BXLu7VCPAsaSd817VBJW+qkIOQDsJuE14ZvHcki YU631xFdqCL50vfxr7yH5xk2pHDByfvQdVseWAbR9iOiBzq8MQYbh8eO33i3SqpirtcU SpWe0OBPnzmlFsCgwMcdCy2/zfgBsZxbTo9Gg26Z/3zUufih85jqQNO7hthsz1B9S8rW D5MQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XGYUHYqA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p12si1114347ybl.42.2020.09.08.17.21.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:21:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XGYUHYqA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnrk-0000xh-Lg for patch@linaro.org; Tue, 08 Sep 2020 20:21:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnJ-0007kO-Uj for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:01 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:39648) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnH-0002C0-Vr for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:01 -0400 Received: by mail-pf1-x444.google.com with SMTP id n14so556664pff.6 for ; Tue, 08 Sep 2020 17:16:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gnZVZh1VIOx2Bn7nb5JDBu+SrUOXUk1VIW8AryTGMI0=; b=XGYUHYqAUUq/8y4Cz0ZjWF+WnH66TRjbnO1jZNAA915M5s6p3iTE8QiYOpsH7+nz/M Jse2yzQo38sh9ppjA2KcJnNgjN8QF6ckYUe0JcTvcvafmpJL6qCyHP8ZqGeaycVCL0VG r3tNyiJFqZhieSINao9WmbcmKO/wZv/48xXJ9ZZpzLD+6pglNhRkpWFGjVBFi1/gvh7/ lBRtJgcRVb1M3QTa8LDm9Z7jmYwkKqlWRAYEChI0sRM2kkR/dvimFVPWYa4bFkAeo6My xEwLbPDJnaDDn7QdeEsQrohg3I19/upMbY3TMUQEWCJFv2tsU1bldGCNMWGLRoDDjqLx CvJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gnZVZh1VIOx2Bn7nb5JDBu+SrUOXUk1VIW8AryTGMI0=; b=QYx5hI5u2DfSgl22Qe0NpeK4ieBNwVqMPIA1b+3G+GPG+A6aLLBR7+j3KVE9fLDyZE szgH40mdGoFjZwzV5z35TRWuCkMzT+qw0JwheKGQGyO9iBw6BxPxXnJch7WC7bWf8aLk QVcI2pM4+KgpIgsXpUAti+aD0eNCh8vzuL6476kQD5g84Cdoak6LZWSGohmnFntRLlff YtZEJIpkr8Wy4WGLPRZ71G8hLUqJKJm9MNlDdTwc1i+GsBcFH46C/6Je8KwZTSp85CPi snh2USOoaS3A6rPuIwriiQmoD5FMKlQrrhukIStPCDhA5df+7gJWB3ipW27WgpBacGEr AYCg== X-Gm-Message-State: AOAM532Ohreuagge2Bs2TytyYoQGLXF1+1/bOPk7LwkgP/VJn+IRITVM GIq5ZeMStfE6+I4jSm/ARPHkmyXNAY6Bkw== X-Received: by 2002:a62:3812:0:b029:13e:d13d:a062 with SMTP id f18-20020a6238120000b029013ed13da062mr1343542pfa.40.1599610618435; Tue, 08 Sep 2020 17:16:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:16:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/43] tcg/i386: Fix dupi for avx2 32-bit hosts Date: Tue, 8 Sep 2020 17:16:11 -0700 Message-Id: <20200909001647.532249-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The previous change wrongly stated that 32-bit avx2 should have used VPBROADCASTW. But that's a 16-bit broadcast and we want a 32-bit broadcast. Fixes: 7b60ef3264e Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 2f696074ab..d8797ed398 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -958,7 +958,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); } else { if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret); + tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); } else { tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); } From patchwork Wed Sep 9 00:16:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249404 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5015833ilg; Tue, 8 Sep 2020 17:23:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZERdpJheU5KCGE4eP7SrXv/Gg56yrz85WLiCZATm9DA9d3SYEwpYMHmDX+wY/kf0dMUEf X-Received: by 2002:a25:1ec5:: with SMTP id e188mr2320337ybe.492.1599611021747; Tue, 08 Sep 2020 17:23:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611021; cv=none; d=google.com; s=arc-20160816; b=tJu85r8a/PYUVx2J4MN/YD4LLA/rdbjApyY9zOfmomHiYxV0u4oE/+dncDPW5TSP18 le/DMosr24WBJVp2zR9aH8REmVYgIopgZCpqZBO4+0i/EowXj3+rs4lWHtqpwOs9yziu qF5ln8EXLhDbJoSkeYDlBLu06VfQU/D+IfPjgiRE6Dq8yx3Px34Wg04mT9LEx7VeD+yV 8oj7dZaaf7g2qfS+tzcayOTQuyPosZTVJFFQF/ElTTiWzL4OVUucZ9d0aLi0cryXtWAm uDgGBGcC6jms/9S+MTnxBzPEDKJh4yhhfI/0y6egaVJIadFZujZYO6O458tIPAwWcUEv gzjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iyDgOefakgRBrjZznHAuamMZUpzKL16pwL2bnPHHK48=; b=gOz+L/22a9osB4dpmGL37ZjpOn7sWTPW5LWMMJKH9ppRqDX96LYuhCrOhf177zjEcB 0lKDZti1kBCD6rbNf9f44TWqkdENyEpmbJEXczC9/MLaKIMKnXqd+gCu89ZgAP1vhf60 gqtTnqwzQb4II8sR1N/EUzzLrnp3J737wzdTU8/uIRbfaBHmX/Ms6Y/SrTcUkiAXQCC8 /j4M0+nA/tAAWRciU5AagQc0rCEbjOkyVyoOGRCeNGkiAz7sNIKceGYyhjEZ1KhGIBpR XOGdhGGXd+rKJwaDEnSWngUWG3Ng2oo47HEGF1CINPolUS45F8MFNJuT1lKitT6plN3B jVVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hAK0Do5s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The definition of INDEX_op_dupi_vec is that it operates on units of tcg_target_ulong -- in this case 32 bits. It does not work to use this for a uint64_t value that happens to be small enough to fit in tcg_target_ulong. Fixes: d2fd745fe8b Fixes: db432672dc5 Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index ed6fb55fe1..cdbf11c573 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -252,10 +252,10 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m) void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a) { - if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) { - do_dupi_vec(r, MO_32, a); - } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) { + if (TCG_TARGET_REG_BITS == 64) { do_dupi_vec(r, MO_64, a); + } else if (a == dup_const(MO_32, a)) { + do_dupi_vec(r, MO_32, a); } else { TCGv_i64 c = tcg_const_i64(a); tcg_gen_dup_i64_vec(MO_64, r, c); @@ -280,7 +280,11 @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a) void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a) { - do_dupi_vec(r, MO_REG, dup_const(vece, a)); + if (vece == MO_64) { + tcg_gen_dup64i_vec(r, a); + } else { + do_dupi_vec(r, MO_REG, dup_const(vece, a)); + } } void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a) From patchwork Wed Sep 9 00:16:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249406 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5016320ilg; Tue, 8 Sep 2020 17:24:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJySVhTzawnw5frNGWItsa/lSeWNooYWyeTO5r8UaeeUA4TQ6qlh2I8y1FDofnS6/Xh+mpCT X-Received: by 2002:a25:2d59:: with SMTP id s25mr2357120ybe.86.1599611077942; Tue, 08 Sep 2020 17:24:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611077; cv=none; d=google.com; s=arc-20160816; b=Qa7P4RnZOBc3LXBuVIxHVPanlgSIKXE3LSFEHJezTlyVbizuSuwiOlrxixUEoXwPOk +iMNm2Ow+ksOBXDq3H2qTVc2YowTrBPw6/lPEirBfZf1zSNqAh8u1FrW5cD44m06SW4A pJjKDACJeuWjmXtb/l1/tJg/JNFuN+dZUGvy8t/CcxRXshrbtOJ5Z03HMQQ79uhhUq6v F91qWB8FFng9fm3kgqNtQRjZ4leDhe7pI61ulRCfy4oeZW1rpyVROn+nM8jWUwa69y6h 8LqxcgcdEb9a2DTnPwym0FN79bmiTMBqCoVqhKaHAvVojvT13mthJurJ4D08ReFfzeDF JNmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WANLQRCpycKiqrfSXuwWnjHW6iUlbU2o8NExmAhiBGo=; b=O+qH6P+GhEelbIhBsZnUs64T+8NQ57Bc7iWdBN3yZoyLqOogv3+lF9cnoaM4JZBP3I ajNLNhJ+2u9unvCDqnq4f7NCubkDJ1KNPRY8/hiZQzZfJi0OZ3VBnHq+3IL7S8Mqatwk kSG5xteppSYsqxVG+wTijx84JHooftq/1sMoLNXgr6eWaa4YQ9cso6ThnFV8eMSC2UpC rafUVUoUScUNW/FXbSdSnDZTTZMke84wF7lsudTNEdSdM8CmMABtj3/dyE6QQrq9FCEm WtCdszvLWyt7BdegkBf/uiHqhdZ5alw2bv6ao4yz6TS3j+rSQ2FjeDcGtX2STvWOoqHX fglg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zFHxOBUA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e8si945697ybb.412.2020.09.08.17.24.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:24:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zFHxOBUA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnuf-000804-Cd for patch@linaro.org; Tue, 08 Sep 2020 20:24:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnL-0007qE-TS for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:03 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:33741) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnK-0002Cg-7f for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:03 -0400 Received: by mail-pg1-x542.google.com with SMTP id e33so752995pgm.0 for ; Tue, 08 Sep 2020 17:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WANLQRCpycKiqrfSXuwWnjHW6iUlbU2o8NExmAhiBGo=; b=zFHxOBUA4THZW2VM6gUFeAzETtdF+vMSsfacwfh/LzcRiMNc29ttwk42Zr6h8l5NdI 6ZcpPAd//DiOvCVR9KFR9P0A1i1kBNykb6sEDJrifpKPLUPx5SPkKCqFjyplQJkENL8Y hG0qp1MQRpynDkWfFTG0NlFEYiwkFwjtrplx/e7x6PArWQxvUSASrETx9UxGVkXtfrAO OY+0yFQYN7eQE/p3/Ft0lBkQgxu2fP7H5JCoWRLakpacRlgmbuSmBmW2TKwRWfWojZ4+ Va5mJRnyjeOu4SJU6aInmE1QfiGF5WddstnhLdRLdWQKR+U2p40JYJ2YoFi6tvDZCATb x3KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WANLQRCpycKiqrfSXuwWnjHW6iUlbU2o8NExmAhiBGo=; b=W4M1wugTtiKWhI/+jefe/epPat92dL3h8/WeQW/FEFBby5+zbYoUNd368nUw4zKpaB vebzxAsjoB54FHttU5tGfOwbMEIL/oYEs5Hygc+Vfy0UofDCAuQfjRHmBkpQkqCu6u2f Jc5tqxLNOea7SRcYzMMu9kh3tRGPQgaUkyWbOsI3lrdEEHWG8U1wToGWKJNTKDvnloGJ DKJcbhhbn3ZCntel5+Uk1dOdUrTSQsQmQ1grR5oFpJb027x/R/960eDqC9HG8rUpuRaH Pk9I45J9gMWg8EyVH2mVIx+Nz+0qsYAQvL2b7YuZelMqvQUwiCo2sXrn9u3PkhbRVitL svQA== X-Gm-Message-State: AOAM533baiw65+ZKGJLCJ1eQzIOQlanNLwjTrUgLViyGQFOg4E+NkJ+k NVxDmnlnMPSKF2CUSdEEZt+rTzVgwH5m/w== X-Received: by 2002:a63:5d66:: with SMTP id o38mr949965pgm.366.1599610620688; Tue, 08 Sep 2020 17:17:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.16.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/43] tcg/optimize: Fold dup2_vec Date: Tue, 8 Sep 2020 17:16:13 -0700 Message-Id: <20200909001647.532249-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When the two arguments are identical, this can be reduced to dup_vec or to mov_vec from a tcg_constant_vec. Signed-off-by: Richard Henderson --- tcg/optimize.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 53aa8e5329..220f4601d5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1109,6 +1109,21 @@ void tcg_optimize(TCGContext *s) } goto do_default; + case INDEX_op_dup2_vec: + assert(TCG_TARGET_REG_BITS == 32); + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + tmp = arg_info(op->args[1])->val; + if (tmp == arg_info(op->args[2])->val) { + tcg_opt_gen_movi(s, op, op->args[0], tmp); + break; + } + } else if (args_are_copies(op->args[1], op->args[2])) { + op->opc = INDEX_op_dup_vec; + TCGOP_VECE(op) = MO_32; + nb_iargs = 1; + } + goto do_default; + CASE_OP_32_64(not): CASE_OP_32_64(neg): CASE_OP_32_64(ext8s): From patchwork Wed Sep 9 00:16:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249389 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5014155ilg; Tue, 8 Sep 2020 17:20:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzkOu9GBRUK9mim1sQ+b8hf8Hp4b7f10hK1Wa3KtUXKE76mqygPkWOePqsGVha3M+dxahkG X-Received: by 2002:a25:d2cf:: with SMTP id j198mr2135153ybg.418.1599610818304; Tue, 08 Sep 2020 17:20:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610818; cv=none; d=google.com; s=arc-20160816; b=OBsJJDOtzvrKh1T1WUfDbWVmxKJoFAvx6LU03tJWWxbJ/wELgcB44m5q+9zLyLUxTQ /1BCFaF4tNl4JAhz83tKv0KZ8mM3DvnsB7KYHgBVKi41alEB11EOsmTLn7tN8UuabMxr wj8IKMsCtRN+Y9WIaOcxCnSc5+i6qVTk3yeIZHv6xtX6R1n2/DI7Gz4Y6+rhG0TxqSql c37klgNIa4mxhlpPUieBa2LxWoUXcjeAwvDqnGlgylOOhPA66syeJVdozaaChvyU38pc ukeZtvk6DKbXbiXszp5UDSEHTgfj6E21mGLfXSQiitmJf+pJxrjNotI/DLaFxKutL9hT //wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fodn9EwyCn1urQvTDcZN29eMc/3x0mPfT2ar5TaBOAc=; b=k/kPqF4pXWW5VAbTBmILF2v/xG70oh7f18WVnomzoEprv9PDyWsGmXSmVrEQxP+uIy Hckj+jb9yBp1aKX2mkWcEjpVPdUEws1tqIaVRBQ73CLJWz0AS5R9gs/GlWSyTTFdG569 5gSmduCn2E4f1GxQ2eY9LSR9cM9O7hP3zsqBrZDnPxGUaPRVTRArxdJjzeXcSbW32F9n 2Jape1MHPb7voqcW5MDzL9rT7+pJGjLXTxTkpKk/zjnV1Y0rGoAhjOSMEBDOR+U7+bGo GyU9IqfxekgMlNsg2RPrG7cSGkrkT9tAyNR3JzPerobsLbLvF2asd+VKcn1ImleRTAJ2 SzZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="V/axuwLt"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g6si849015ybk.4.2020.09.08.17.20.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:20:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="V/axuwLt"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnqT-0006Zy-Ow for patch@linaro.org; Tue, 08 Sep 2020 20:20:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnN-0007uA-7Z for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:05 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:43497) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnL-0002DB-HY for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:04 -0400 Received: by mail-pf1-x42b.google.com with SMTP id f18so539901pfa.10 for ; Tue, 08 Sep 2020 17:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fodn9EwyCn1urQvTDcZN29eMc/3x0mPfT2ar5TaBOAc=; b=V/axuwLtpU8Hwu68PCUmsDnACAxXINotlIj46fvpKd/RplKFeB1pBl9zKz7KLjB364 WEsXKk2i9isMI4XzjuYsqDs7CCt13Ul/aeMM82eJXvX+CV2ZMKUdW3M4lMdulaG0m6WN U3FX7LmvlfsqI7aTQOP+Z6d4Qlvs7GFlKlXvp0A+sfdKuJ18qlQwJ84QLir1VmuBL0ga CRQxCpC2GBXsKBEOIZA6IpQdiJ215mBNH342S8/iw9bYLp2BxwsbDTFxp8+kMutD3D2j t+leaQRWGNsuz/7Wl0+yopZjCFNCMM66VnsDEr8+JwPRpW6vn7opjkFwcPI/oyI5pJPL u6cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fodn9EwyCn1urQvTDcZN29eMc/3x0mPfT2ar5TaBOAc=; b=QuZTA3JtVeiTHW/Zp3tSPT7ippBBoiCzzrjXea1FWxEKv5r9tV0xLSHTAFUQ02qTi7 tI4WmUzl/3APmc+pWWkeRbLVir49nPJ97PstpG187GIal1WAU4TNCguJHFLqalbtMbjj agNTEhLMjvbqS6PNPAvzSz7z63ic9Sacy0WT+H7JC49uNfvD5wocd5K2Al4OxLa7yLp7 i7khNR3SqFwcF90pxfU+8lcmbbieXSuqZGvs94OLXTX1dHzugO9231LjqKag8IuW4jXq xSHkMSH5UDGTaAu8SqZxO+ZgNerzmOgcSEi/0N9WYUk2eEtmG4RUfzTurIusYejUh8ck MvSw== X-Gm-Message-State: AOAM530swCmKfia2R2zfrjNLntKHlbU5sR1D2nI+JXfqirnoQafpG1gq /oSdR8XX5jl5QrUYAMP71BJaNSMT2pBrLw== X-Received: by 2002:a63:29c7:: with SMTP id p190mr975523pgp.292.1599610621672; Tue, 08 Sep 2020 17:17:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec Date: Tue, 8 Sep 2020 17:16:14 -0700 Message-Id: <20200909001647.532249-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The cmp_vec opcode is mandatory; this symbol is unused. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - 3 files changed, 3 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 9bc2a5ecbe..663dd0b95e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -139,7 +139,6 @@ typedef enum { #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 -#define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 99ac1e3958..1f6dd8f45d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -189,7 +189,6 @@ extern bool have_avx2; #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 -#define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index aee38157a2..be10363956 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -169,7 +169,6 @@ extern bool have_vsx; #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 -#define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 From patchwork Wed Sep 9 00:16:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249388 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5013507ilg; Tue, 8 Sep 2020 17:19:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyDTObRlCGzmjeTItLFH6T3BOkDTBYm5Em0EIBwhIdYIgsjs7iQNBJraYVDAeLu1XZhk8Lt X-Received: by 2002:a25:abf0:: with SMTP id v103mr2101872ybi.203.1599610747765; Tue, 08 Sep 2020 17:19:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610747; cv=none; d=google.com; s=arc-20160816; b=Y+ELypm4SjMGSXJWi1IjJK6X16oGNHRDU/NQ/FRwpTKmzu6vw6KelyTon7S3NDyLWw Q6TI6Z8K9a/fiffj9djQgN5aEFdTPxS0mX5k6dNvOeteo7WJl6YWaX68OpokThO37bfY er+6C1keVF4NHZLMYHDnNjlOzY7KsIwrZnCaiUtZc2Rx9ggxi9Z8WYy4H6xWvBXbCR2k 9dF6CidEs5n1r0fCZISRNpZqThX7UHaErtVOXXz7OF9/qoPWdeHAskwgKDipcc5/JBBF FejLKMs+YII3wv/X4yOPTXW/0fYJgzqdKzuQjyIv5m9ZKLPvpQaXygwvN9oRdOOnQ2It v/Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1eE3lAmyrdjuzVxb1U2PcBVqu2mO9eS/d8wE+vhl4dk=; b=XpX7W8S71WcVza6fZzwhdijobj+scAnQk35mX2/a1+D08mfQyMvIiq1PJubV11WlRb EO4CqOEL1nizdzc/nxq8DqvxOHhtBOLWbu+n/rx2TZGiwMfvsxw4fA7uXjTZSjuPRAkX 1oHJl9SBAcmROPSe9k1g2k+hPm9sQuLssDnFms9nzV+u4rX8m9gwQ36Lx3OubAs/T2cM HNSP+yow5DRdnhE3RHg/fz2YoJwil8GR36A4ZeBJvA7FpK1m9krw0nUCtxCf/BZN6Gq6 wdjWRmHUyozvSQjKJuoDqKiu/xgqIWOe3u8CWOjcLTzygGp3yH8VZDGO79D5JEp3rqzO 0hCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CIOceMSb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x15si887045ybk.301.2020.09.08.17.19.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:19:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CIOceMSb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnpL-0002tl-4x for patch@linaro.org; Tue, 08 Sep 2020 20:19:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnO-0007xU-D6 for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:06 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:41714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnM-0002DL-Gv for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:06 -0400 Received: by mail-pf1-x444.google.com with SMTP id z19so548958pfn.8 for ; Tue, 08 Sep 2020 17:17:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1eE3lAmyrdjuzVxb1U2PcBVqu2mO9eS/d8wE+vhl4dk=; b=CIOceMSbz6q5hVVYR8y/JyXR9F/6OZRg3aj94I0bIMta8PVatNahlpYokct61Xek5N 7Naq0OyTWHOOCByBdzHS0edv0QIKzxA1kNXwLNLSuS6L30qHiizJsPlRWm+P1kJED4ad hFUsEIYLBMp6SnwkPPhGvODoH7Ic0WcI/S3s6F4PNge6xc5IPuBSfbTgvgNkrUWLDYrk 2jYzRHn3XC3S5kXYRuLjWn+ff1v80xz3rgKF2T6+Z8xwUCA3rEWJJkUOISopcRQjLsTN qQ1yr0nfevxYkncVT6MuL87ysmLYorHTNFjflakfSHra+croKkBZFE/fGgt4vO0YFoPa nlVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1eE3lAmyrdjuzVxb1U2PcBVqu2mO9eS/d8wE+vhl4dk=; b=WjD19U9RUSY5IorU82Xp2/gdNq7ZVimZr7wxtcuxi6k/mPzXuXv5t/NF1MfbaCEaVn nv2bckXteQuWWW2b7M3J09EEAOGkN9D6uv4YZ1hDuCBhYBacoql/JmBkL9JPmU5smxAE crBxwaBdsZb6QV6koupy44e6s5Lv0hx0AWHII3yJ7Od3Op/LnjbzgdUrNKsqrrtFMlyL oKkXsZdp6+ZH/a4rWx76mtGtkAr8y5FyYpEyCQ6e0ECspsM/dZk74SHhYuV//RmyqJA0 i24uBUAuXG5LRfhgk8CmYpO9QhtLPBqDb1LlaS7/FISYZ5ZmK/UgOVkbgfOVjAl6gDV0 Sblg== X-Gm-Message-State: AOAM532pi+5GWYrKhj8ti/U8PxJCuqtwmSJiCVnvdfQ1f/wdzeLI5jOw 7T4WzJeET9U32/CV2mMCAp7Vig8UuErd9g== X-Received: by 2002:a63:4e5e:: with SMTP id o30mr948390pgl.324.1599610622907; Tue, 08 Sep 2020 17:17:02 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/43] tcg: Use tcg_out_dupi_vec from temp_load Date: Tue, 8 Sep 2020 17:16:15 -0700 Message-Id: <20200909001647.532249-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Having dupi pass though movi is confusing and arguably wrong. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 6 +++- tcg/aarch64/tcg-target.c.inc | 7 ---- tcg/i386/tcg-target.c.inc | 63 ++++++++++++++++++++++++------------ tcg/ppc/tcg-target.c.inc | 6 ---- 4 files changed, 47 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index ad4b7fb90f..84bdcc6537 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3305,7 +3305,11 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, case TEMP_VAL_CONST: reg = tcg_reg_alloc(s, desired_regs, allocated_regs, preferred_regs, ts->indirect_base); - tcg_out_movi(s, ts->type, reg, ts->val); + if (ts->type <= TCG_TYPE_I64) { + tcg_out_movi(s, ts->type, reg, ts->val); + } else { + tcg_out_dupi_vec(s, ts->type, reg, ts->val); + } ts->mem_coherent = 0; break; case TEMP_VAL_MEM: diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 479a9d26be..72c4d25fdb 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1007,13 +1007,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, case TCG_TYPE_I64: tcg_debug_assert(rd < 32); break; - - case TCG_TYPE_V64: - case TCG_TYPE_V128: - tcg_debug_assert(rd >= 32); - tcg_out_dupi_vec(s, type, rd, value); - return; - default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d8797ed398..e2852cbb09 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -966,30 +966,32 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, } } -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_movi_vec(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + if (arg == 0) { + tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); + return; + } + if (arg == -1) { + tcg_out_vex_modrm(s, OPC_PCMPEQB, ret, ret, ret); + return; + } + + int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); + tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret); + if (TCG_TARGET_REG_BITS == 64) { + new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); + } else { + new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); + } +} + +static void tcg_out_movi_int(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) { tcg_target_long diff; - switch (type) { - case TCG_TYPE_I32: -#if TCG_TARGET_REG_BITS == 64 - case TCG_TYPE_I64: -#endif - if (ret < 16) { - break; - } - /* fallthru */ - case TCG_TYPE_V64: - case TCG_TYPE_V128: - case TCG_TYPE_V256: - tcg_debug_assert(ret >= 16); - tcg_out_dupi_vec(s, type, ret, arg); - return; - default: - g_assert_not_reached(); - } - if (arg == 0) { tgen_arithr(s, ARITH_XOR, ret, ret); return; @@ -1018,6 +1020,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out64(s, arg); } +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + switch (type) { + case TCG_TYPE_I32: +#if TCG_TARGET_REG_BITS == 64 + case TCG_TYPE_I64: +#endif + if (ret < 16) { + tcg_out_movi_int(s, type, ret, arg); + } else { + tcg_out_movi_vec(s, type, ret, arg); + } + break; + default: + g_assert_not_reached(); + } +} + static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) { if (val == (int8_t)val) { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 7a5760bb23..bc6fb09adb 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -983,12 +983,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_out_movi_int(s, type, ret, arg, false); break; - case TCG_TYPE_V64: - case TCG_TYPE_V128: - tcg_debug_assert(ret >= TCG_REG_V0); - tcg_out_dupi_vec(s, type, ret, arg); - break; - default: g_assert_not_reached(); } From patchwork Wed Sep 9 00:16:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249392 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5014628ilg; Tue, 8 Sep 2020 17:21:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZpdHTYU6U7zKfOHczIG54CqFgd9aHAVQk834w1Qh7lu+5V6pG4wMoicCiG8DUL1+kAWSI X-Received: by 2002:a25:b19f:: with SMTP id h31mr2473959ybj.420.1599610879068; Tue, 08 Sep 2020 17:21:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610879; cv=none; d=google.com; s=arc-20160816; b=Fx70Evvws036yGKmyKR60m/kAOlxo0IGq3wvQcNaCDE6TwzDL9RDA3CpNBw47EtZVd gUdo/n/JAXc/N7Y6Ma8OoQqP3g7WeYmWxoqfmHa+SnspUvguO3Pf2XwEL5y42bk84wsY n/rftDl3IbmsTFs/Ewdp9Agw76W/z8rrVI1v/p7q/q7xuxtGq+Z/dgIDbAH2NcHrKD3N Zsa4Lp/SAR2GfIMekONvpJdnMSkV5A6PHKLcRzbdGpH2k8pEpc+yyWktytHP+YCmArdD UN6DByGYIvJTm/xT6TFvETilcum4FuO4DLoERzs7mQoSwPHMtMhtxR8DTUvnNG9ZGHrn 9PWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=W2Y3ZHQJCdZHuqmnkSlt2vnfygEUmtT0oY/lhiXUYbI=; b=gfNGxIdOlcjf1X9xGwBgkZBQA5G6zJE5h8l4/ypY4dN7HUZSucd7RkgorklR9EhVuS 0iGuvkG2BKW/ZcxaaALhj10pVY0WajEmIVwtblOv+9/Xoin2gSOCLh5hfm0A8+pxzMlV eFao3TT4QgdLYbKxRVxNwZk/Lx6KRpt/QrNupUL9sjPRekqQ6pBXxuraa0Jx3wboDCTp 6ZO4EhnC2odkpCoJz7ssR0z9uRwhIpVkd8rWWPHJzwntKSDet+X8PK41Xh94cRms19lt BLicOk7XCGC6ZJh+TbyO05vPzVr43vcUUuyGuqnMcWy1roE5mxBORNxbEEO4dZjAuqTl XcUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y6XGhVWU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v66si993237ybb.411.2020.09.08.17.21.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:21:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y6XGhVWU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnrS-0007VS-HX for patch@linaro.org; Tue, 08 Sep 2020 20:21:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnQ-00082M-4M for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:08 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:33171) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnO-0002Db-0v for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:07 -0400 Received: by mail-pj1-x1029.google.com with SMTP id md22so473180pjb.0 for ; Tue, 08 Sep 2020 17:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=W2Y3ZHQJCdZHuqmnkSlt2vnfygEUmtT0oY/lhiXUYbI=; b=y6XGhVWUJhO/ZRRjICQprkVRKJksalYNbdPWalE+iW94gKTVGlTSwbsGfQEw/HznCM b3oMYBgDiiHgc8gWi0BBAMXTxrYrkUFpmWkUfCqE6Q8tdpd9hMKFw5nmFaUfC0cJLSm4 nE/bkCb61wzh/r6nUnYANAq9nQHSdj3WCNLlkFrvg8s2UNnlSkr6mhnTu1aX4vYj2CVz YXiipk1mMgigOBAnaG4B14r3U9Ozd1lj7LJ98QoZ0lzTic+XYiNVn6gVvYwyAsyad0Cn WFScv0OghMmVFs2TjJQn0GxkdpLkOUQ/pyR3lu22jR4ajkxOjvGuXG7AVodOMdu8M5bu kycA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W2Y3ZHQJCdZHuqmnkSlt2vnfygEUmtT0oY/lhiXUYbI=; b=fKN4KoiXvlS1/5awRvFYG++SaMhhOu4yxDuRvzpEb3naXltZzP0ravzEc3WgITywbQ a5neh2FIpAdZW78tN9en3NAwOQdaTddeMLKrG6mMp0+nP/lBzOMJMqtqXa6Fd4YNdkw+ 9nfaYcHQ1vZfQEk8oP4JeX3K32YgtnjKD07fasoi3coLSN/ozYFg8cxaDKxCnfbMZR6K +m5SVf1MnlJGnmbL391GusuAazCowE3dEGkT3zWrSAngZb68bIvoPAzC8kYMGRmBcgjL mfQ3BWa8IhRpsr0W8BGa7nOLOs9romhnEs20BhPEMOpmLyYZN8NQnx13fOYQ9l4qLMO2 pddA== X-Gm-Message-State: AOAM5311HG4vOo0xNekwiuv4+ynO5ATSMfQkuXJkrjj9dkYuAna3xAkD GwZDbtNkc+Sd3bMFMFuxPgnn2vkkJW95vw== X-Received: by 2002:a17:90a:af84:: with SMTP id w4mr1185258pjq.94.1599610624125; Tue, 08 Sep 2020 17:17:04 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/43] tcg: Increase tcg_out_dupi_vec immediate to int64_t Date: Tue, 8 Sep 2020 17:16:16 -0700 Message-Id: <20200909001647.532249-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While we don't store more than tcg_target_long in TCGTemp, we shouldn't be limited to that for code generation. We will be able to use this for INDEX_op_dup2_vec with 2 constants. Also pass along the minimal vece that may be said to apply to the constant. This allows some simplification in the various backends. Signed-off-by: Richard Henderson --- tcg/tcg.c | 31 +++++++++++++++++++++++++----- tcg/aarch64/tcg-target.c.inc | 12 ++++++------ tcg/i386/tcg-target.c.inc | 22 ++++++++++++--------- tcg/ppc/tcg-target.c.inc | 37 +++++++++++++++++++++++------------- 4 files changed, 69 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 84bdcc6537..6474a695f2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -116,8 +116,8 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src); static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset); -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg dst, tcg_target_long arg); +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, int64_t arg); static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args); @@ -132,8 +132,8 @@ static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, { g_assert_not_reached(); } -static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg dst, tcg_target_long arg) +static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, int64_t arg) { g_assert_not_reached(); } @@ -3308,7 +3308,28 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, if (ts->type <= TCG_TYPE_I64) { tcg_out_movi(s, ts->type, reg, ts->val); } else { - tcg_out_dupi_vec(s, ts->type, reg, ts->val); + uint64_t val = ts->val; + MemOp vece = MO_64; + + /* + * Find the minimal vector element that matches the constant. + * The targets will, in general, have to do this search anyway, + * do this generically. + */ + if (TCG_TARGET_REG_BITS == 32) { + val = dup_const(MO_32, val); + vece = MO_32; + } + if (val == dup_const(MO_8, val)) { + vece = MO_8; + } else if (val == dup_const(MO_16, val)) { + vece = MO_16; + } else if (TCG_TARGET_REG_BITS == 64 && + val == dup_const(MO_32, val)) { + vece = MO_32; + } + + tcg_out_dupi_vec(s, ts->type, vece, reg, ts->val); } ts->mem_coherent = 0; break; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 72c4d25fdb..5692607087 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -853,14 +853,14 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c); } -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg rd, tcg_target_long v64) +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg rd, int64_t v64) { bool q = type == TCG_TYPE_V128; int cmode, imm8, i; /* Test all bytes equal first. */ - if (v64 == dup_const(MO_8, v64)) { + if (vece == MO_8) { imm8 = (uint8_t)v64; tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8); return; @@ -887,7 +887,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, * cannot find an expansion there's no point checking a larger * width because we already know by replication it cannot match. */ - if (v64 == dup_const(MO_16, v64)) { + if (vece == MO_16) { uint16_t v16 = v64; if (is_shimm16(v16, &cmode, &imm8)) { @@ -906,7 +906,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff); tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8); return; - } else if (v64 == dup_const(MO_32, v64)) { + } else if (vece == MO_32) { uint32_t v32 = v64; uint32_t n32 = ~v32; @@ -2430,7 +2430,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); break; } - tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0); + tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); a2 = TCG_VEC_TMP; } insn = cmp_insn[cond]; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index e2852cbb09..6b7cbaa47a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -933,8 +933,8 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, return true; } -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg ret, int64_t arg) { int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); @@ -947,7 +947,14 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, return; } - if (TCG_TARGET_REG_BITS == 64) { + if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) { + if (have_avx2) { + tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); + } else { + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); + } + new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); + } else { if (type == TCG_TYPE_V64) { tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); } else if (have_avx2) { @@ -955,14 +962,11 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, } else { tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); } - new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); - } else { - if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); + if (TCG_TARGET_REG_BITS == 64) { + new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); } else { - tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); + new_pool_l2(s, R_386_32, s->code_ptr - 4, 0, arg, arg >> 32); } - new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); } } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index bc6fb09adb..ff56f1971f 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -908,31 +908,41 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } } -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long val) +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg ret, int64_t val) { uint32_t load_insn; int rel, low; intptr_t add; - low = (int8_t)val; - if (low >= -16 && low < 16) { - if (val == (tcg_target_long)dup_const(MO_8, low)) { + switch (vece) { + case MO_8: + low = (int8_t)val; + if (low >= -16 && low < 16) { tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); return; } - if (val == (tcg_target_long)dup_const(MO_16, low)) { + if (have_isa_3_00) { + tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); + return; + } + break; + + case MO_16: + low = (int16_t)val; + if (low >= -16 && low < 16) { tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); return; } - if (val == (tcg_target_long)dup_const(MO_32, low)) { + break; + + case MO_32: + low = (int32_t)val; + if (low >= -16 && low < 16) { tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); return; } - } - if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) { - tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); - return; + break; } /* @@ -952,14 +962,15 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, if (TCG_TARGET_REG_BITS == 64) { new_pool_label(s, val, rel, s->code_ptr, add); } else { - new_pool_l2(s, rel, s->code_ptr, add, val, val); + new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); } } else { load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); if (TCG_TARGET_REG_BITS == 64) { new_pool_l2(s, rel, s->code_ptr, add, val, val); } else { - new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val); + new_pool_l4(s, rel, s->code_ptr, add, + val >> 32, val, val >> 32, val); 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The temp_fixed, temp_global, temp_local bits are all related. Combine them into a single enumeration. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 20 +++++--- tcg/optimize.c | 8 +-- tcg/tcg.c | 122 ++++++++++++++++++++++++++++------------------ 3 files changed, 90 insertions(+), 60 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 8804a8c4a2..f157092b51 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -483,23 +483,27 @@ typedef enum TCGTempVal { TEMP_VAL_CONST, } TCGTempVal; +typedef enum TCGTempKind { + /* Temp is dead at the end of all basic blocks. */ + TEMP_NORMAL, + /* Temp is saved across basic blocks but dead at the end of TBs. */ + TEMP_LOCAL, + /* Temp is saved across both basic blocks and translation blocks. */ + TEMP_GLOBAL, + /* Temp is in a fixed register. */ + TEMP_FIXED, +} TCGTempKind; + typedef struct TCGTemp { TCGReg reg:8; TCGTempVal val_type:8; TCGType base_type:8; TCGType type:8; - unsigned int fixed_reg:1; + TCGTempKind kind:3; unsigned int indirect_reg:1; unsigned int indirect_base:1; unsigned int mem_coherent:1; unsigned int mem_allocated:1; - /* If true, the temp is saved across both basic blocks and - translation blocks. */ - unsigned int temp_global:1; - /* If true, the temp is saved across basic blocks but dead - at the end of translation blocks. If false, the temp is - dead at the end of basic blocks. */ - unsigned int temp_local:1; unsigned int temp_allocated:1; tcg_target_long val; diff --git a/tcg/optimize.c b/tcg/optimize.c index 220f4601d5..3cffd941bd 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -116,21 +116,21 @@ static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) TCGTemp *i; /* If this is already a global, we can't do better. */ - if (ts->temp_global) { + if (ts->kind >= TEMP_GLOBAL) { return ts; } /* Search for a global first. */ for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { - if (i->temp_global) { + if (i->kind >= TEMP_GLOBAL) { return i; } } /* If it is a temp, search for a temp local. */ - if (!ts->temp_local) { + if (ts->kind == TEMP_NORMAL) { for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { - if (ts->temp_local) { + if (i->kind >= TEMP_LOCAL) { return i; } } diff --git a/tcg/tcg.c b/tcg/tcg.c index 6474a695f2..67e122527b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1160,7 +1160,7 @@ static inline TCGTemp *tcg_global_alloc(TCGContext *s) tcg_debug_assert(s->nb_globals == s->nb_temps); s->nb_globals++; ts = tcg_temp_alloc(s); - ts->temp_global = 1; + ts->kind = TEMP_GLOBAL; return ts; } @@ -1177,7 +1177,7 @@ static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, ts = tcg_global_alloc(s); ts->base_type = type; ts->type = type; - ts->fixed_reg = 1; + ts->kind = TEMP_FIXED; ts->reg = reg; ts->name = name; tcg_regset_set_reg(s->reserved_regs, reg); @@ -1204,7 +1204,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, bigendian = 1; #endif - if (!base_ts->fixed_reg) { + if (base_ts->kind != TEMP_FIXED) { /* We do not support double-indirect registers. */ tcg_debug_assert(!base_ts->indirect_reg); base_ts->indirect_base = 1; @@ -1252,6 +1252,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) { TCGContext *s = tcg_ctx; + TCGTempKind kind = temp_local ? TEMP_LOCAL : TEMP_NORMAL; TCGTemp *ts; int idx, k; @@ -1264,7 +1265,7 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) ts = &s->temps[idx]; ts->temp_allocated = 1; tcg_debug_assert(ts->base_type == type); - tcg_debug_assert(ts->temp_local == temp_local); + tcg_debug_assert(ts->kind == kind); } else { ts = tcg_temp_alloc(s); if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { @@ -1273,18 +1274,18 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) ts->base_type = type; ts->type = TCG_TYPE_I32; ts->temp_allocated = 1; - ts->temp_local = temp_local; + ts->kind = kind; tcg_debug_assert(ts2 == ts + 1); ts2->base_type = TCG_TYPE_I64; ts2->type = TCG_TYPE_I32; ts2->temp_allocated = 1; - ts2->temp_local = temp_local; + ts2->kind = kind; } else { ts->base_type = type; ts->type = type; ts->temp_allocated = 1; - ts->temp_local = temp_local; + ts->kind = kind; } } @@ -1341,12 +1342,12 @@ void tcg_temp_free_internal(TCGTemp *ts) } #endif - tcg_debug_assert(ts->temp_global == 0); + tcg_debug_assert(ts->kind < TEMP_GLOBAL); tcg_debug_assert(ts->temp_allocated != 0); ts->temp_allocated = 0; idx = temp_idx(ts); - k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0); + k = ts->base_type + (ts->kind == TEMP_NORMAL ? 0 : TCG_TYPE_COUNT); set_bit(idx, s->free_temps[k].l); } @@ -1876,17 +1877,27 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) static void tcg_reg_alloc_start(TCGContext *s) { int i, n; - TCGTemp *ts; - for (i = 0, n = s->nb_globals; i < n; i++) { - ts = &s->temps[i]; - ts->val_type = (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM); - } - for (n = s->nb_temps; i < n; i++) { - ts = &s->temps[i]; - ts->val_type = (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD); - ts->mem_allocated = 0; - ts->fixed_reg = 0; + for (i = 0, n = s->nb_temps; i < n; i++) { + TCGTemp *ts = &s->temps[i]; + TCGTempVal val = TEMP_VAL_MEM; + + switch (ts->kind) { + case TEMP_FIXED: + val = TEMP_VAL_REG; + break; + case TEMP_GLOBAL: + break; + case TEMP_NORMAL: + val = TEMP_VAL_DEAD; + /* fall through */ + case TEMP_LOCAL: + ts->mem_allocated = 0; + break; + default: + g_assert_not_reached(); + } + ts->val_type = val; } memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); @@ -1897,12 +1908,17 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, { int idx = temp_idx(ts); - if (ts->temp_global) { + switch (ts->kind) { + case TEMP_FIXED: + case TEMP_GLOBAL: pstrcpy(buf, buf_size, ts->name); - } else if (ts->temp_local) { + break; + case TEMP_LOCAL: snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); - } else { + break; + case TEMP_NORMAL: snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); + break; } return buf; } @@ -2492,15 +2508,24 @@ static void la_bb_end(TCGContext *s, int ng, int nt) { int i; - for (i = 0; i < ng; ++i) { - s->temps[i].state = TS_DEAD | TS_MEM; - la_reset_pref(&s->temps[i]); - } - for (i = ng; i < nt; ++i) { - s->temps[i].state = (s->temps[i].temp_local - ? TS_DEAD | TS_MEM - : TS_DEAD); - la_reset_pref(&s->temps[i]); + for (i = 0; i < nt; ++i) { + TCGTemp *ts = &s->temps[i]; + int state; + + switch (ts->kind) { + case TEMP_FIXED: + case TEMP_GLOBAL: + case TEMP_LOCAL: + state = TS_DEAD | TS_MEM; + break; + case TEMP_NORMAL: + state = TS_DEAD; + break; + default: + g_assert_not_reached(); + } + ts->state = state; + la_reset_pref(ts); } } @@ -3109,7 +3134,8 @@ static void check_regs(TCGContext *s) } for (k = 0; k < s->nb_temps; k++) { ts = &s->temps[k]; - if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg + if (ts->val_type == TEMP_VAL_REG + && ts->kind != TEMP_FIXED && s->reg_to_temp[ts->reg] != ts) { printf("Inconsistency for temp %s:\n", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); @@ -3146,15 +3172,14 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); mark it free; otherwise mark it dead. */ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) { - if (ts->fixed_reg) { + if (ts->kind == TEMP_FIXED) { return; } if (ts->val_type == TEMP_VAL_REG) { s->reg_to_temp[ts->reg] = NULL; } ts->val_type = (free_or_dead < 0 - || ts->temp_local - || ts->temp_global + || ts->kind != TEMP_NORMAL ? TEMP_VAL_MEM : TEMP_VAL_DEAD); } @@ -3171,7 +3196,7 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, TCGRegSet preferred_regs, int free_or_dead) { - if (ts->fixed_reg) { + if (ts->kind == TEMP_FIXED) { return; } if (!ts->mem_coherent) { @@ -3354,7 +3379,8 @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) { /* The liveness analysis already ensures that globals are back in memory. Keep an tcg_debug_assert for safety. */ - tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg); + tcg_debug_assert(ts->val_type == TEMP_VAL_MEM + || ts->kind == TEMP_FIXED); } /* save globals to their canonical location and assume they can be @@ -3379,7 +3405,7 @@ static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) for (i = 0, n = s->nb_globals; i < n; i++) { TCGTemp *ts = &s->temps[i]; tcg_debug_assert(ts->val_type != TEMP_VAL_REG - || ts->fixed_reg + || ts->kind == TEMP_FIXED || ts->mem_coherent); } } @@ -3392,7 +3418,7 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) for (i = s->nb_globals; i < s->nb_temps; i++) { TCGTemp *ts = &s->temps[i]; - if (ts->temp_local) { + if (ts->kind == TEMP_LOCAL) { temp_save(s, ts, allocated_regs); } else { /* The liveness analysis already ensures that temps are dead. @@ -3412,7 +3438,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, TCGRegSet preferred_regs) { /* ENV should not be modified. */ - tcg_debug_assert(!ots->fixed_reg); + tcg_debug_assert(ots->kind != TEMP_FIXED); /* The movi is not explicitly generated here. */ if (ots->val_type == TEMP_VAL_REG) { @@ -3452,7 +3478,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) ts = arg_temp(op->args[1]); /* ENV should not be modified. */ - tcg_debug_assert(!ots->fixed_reg); + tcg_debug_assert(ots->kind != TEMP_FIXED); /* Note that otype != itype for no-op truncation. */ otype = ots->type; @@ -3491,7 +3517,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) } temp_dead(s, ots); } else { - if (IS_DEAD_ARG(1) && !ts->fixed_reg) { + if (IS_DEAD_ARG(1) && ts->kind != TEMP_FIXED) { /* the mov can be suppressed */ if (ots->val_type == TEMP_VAL_REG) { s->reg_to_temp[ots->reg] = NULL; @@ -3513,7 +3539,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) * Store the source register into the destination slot * and leave the destination temp as TEMP_VAL_MEM. */ - assert(!ots->fixed_reg); + assert(ots->kind != TEMP_FIXED); if (!ts->mem_allocated) { temp_allocate_frame(s, ots); } @@ -3550,7 +3576,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) its = arg_temp(op->args[1]); /* ENV should not be modified. */ - tcg_debug_assert(!ots->fixed_reg); + tcg_debug_assert(ots->kind != TEMP_FIXED); itype = its->type; vece = TCGOP_VECE(op); @@ -3690,7 +3716,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) i_preferred_regs = o_preferred_regs = 0; if (arg_ct->ialias) { o_preferred_regs = op->output_pref[arg_ct->alias_index]; - if (ts->fixed_reg) { + if (ts->kind == TEMP_FIXED) { /* if fixed register, we must allocate a new register if the alias is not the same register */ if (arg != op->args[arg_ct->alias_index]) { @@ -3780,7 +3806,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) ts = arg_temp(arg); /* ENV should not be modified. */ - tcg_debug_assert(!ts->fixed_reg); + tcg_debug_assert(ts->kind != TEMP_FIXED); if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { reg = new_args[arg_ct->alias_index]; @@ -3821,7 +3847,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) ts = arg_temp(op->args[i]); /* ENV should not be modified. */ - tcg_debug_assert(!ts->fixed_reg); + tcg_debug_assert(ts->kind != TEMP_FIXED); if (NEED_SYNC_ARG(i)) { temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); @@ -3953,7 +3979,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) ts = arg_temp(arg); /* ENV should not be modified. */ - tcg_debug_assert(!ts->fixed_reg); + tcg_debug_assert(ts->kind != TEMP_FIXED); reg = tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] == NULL); From patchwork Wed Sep 9 00:16:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249398 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5015159ilg; Tue, 8 Sep 2020 17:22:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxgvrv4eNMymFtkmeiWfi7spJL1F36bK+yQEtReP8cv6yd/DtwAXiunY3n3DM2iIx6cWf+p X-Received: by 2002:a25:acd0:: with SMTP id x16mr2142536ybd.268.1599610943239; Tue, 08 Sep 2020 17:22:23 -0700 (PDT) ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In most, but not all, places that we check for TEMP_FIXED, we are really testing that we do not modify the temporary. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 5 +++++ tcg/tcg.c | 21 ++++++++++----------- 2 files changed, 15 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index f157092b51..44ca8845cf 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -681,6 +681,11 @@ struct TCGContext { target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; }; +static inline bool temp_readonly(TCGTemp *ts) +{ + return ts->kind == TEMP_FIXED; +} + extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; extern TCGv_env cpu_env; diff --git a/tcg/tcg.c b/tcg/tcg.c index 67e122527b..577bfec202 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3172,7 +3172,7 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); mark it free; otherwise mark it dead. */ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) { - if (ts->kind == TEMP_FIXED) { + if (temp_readonly(ts)) { return; } if (ts->val_type == TEMP_VAL_REG) { @@ -3196,7 +3196,7 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, TCGRegSet preferred_regs, int free_or_dead) { - if (ts->kind == TEMP_FIXED) { + if (temp_readonly(ts)) { return; } if (!ts->mem_coherent) { @@ -3379,8 +3379,7 @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) { /* The liveness analysis already ensures that globals are back in memory. Keep an tcg_debug_assert for safety. */ - tcg_debug_assert(ts->val_type == TEMP_VAL_MEM - || ts->kind == TEMP_FIXED); + tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || temp_readonly(ts)); } /* save globals to their canonical location and assume they can be @@ -3438,7 +3437,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, TCGRegSet preferred_regs) { /* ENV should not be modified. */ - tcg_debug_assert(ots->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ots)); /* The movi is not explicitly generated here. */ if (ots->val_type == TEMP_VAL_REG) { @@ -3478,7 +3477,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) ts = arg_temp(op->args[1]); /* ENV should not be modified. */ - tcg_debug_assert(ots->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ots)); /* Note that otype != itype for no-op truncation. */ otype = ots->type; @@ -3539,7 +3538,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) * Store the source register into the destination slot * and leave the destination temp as TEMP_VAL_MEM. */ - assert(ots->kind != TEMP_FIXED); + assert(!temp_readonly(ots)); if (!ts->mem_allocated) { temp_allocate_frame(s, ots); } @@ -3576,7 +3575,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) its = arg_temp(op->args[1]); /* ENV should not be modified. */ - tcg_debug_assert(ots->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ots)); itype = its->type; vece = TCGOP_VECE(op); @@ -3806,7 +3805,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) ts = arg_temp(arg); /* ENV should not be modified. */ - tcg_debug_assert(ts->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ts)); if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { reg = new_args[arg_ct->alias_index]; @@ -3847,7 +3846,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) ts = arg_temp(op->args[i]); /* ENV should not be modified. */ - tcg_debug_assert(ts->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ts)); if (NEED_SYNC_ARG(i)) { temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); @@ -3979,7 +3978,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) ts = arg_temp(arg); /* ENV should not be modified. */ - tcg_debug_assert(ts->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ts)); reg = tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] == NULL); From patchwork Wed Sep 9 00:16:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249387 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5013449ilg; Tue, 8 Sep 2020 17:18:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKllEPGV7hYQv6sli2mejk9bn9UJxNAdIrkGHLv9wzIyh7gmDS3TVvIE9FkGhDvuXaEEQy X-Received: by 2002:a25:d18d:: with SMTP id i135mr2492210ybg.71.1599610739429; Tue, 08 Sep 2020 17:18:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610739; cv=none; d=google.com; s=arc-20160816; b=WYQbqRXC5PPRbq56AYVPc3KTH96Wr3rkMvZmM+88RIFdSCSpS3bc0FSAKTjK+nlHQd SyDxMBmNU70jD7JZNZxqC+Y/WtLxuOHTfUi416qttQJDcNjrOZxoRl2/o8VYCFxendLm 1nJLTdvvJjinIWOuTUJMBHZ1Kg6EXGl7UAJJQhLLH2RjrQcokzGbCt/rV2X63+qvJnbw NjcRya2PQKXRRrMngy7VmdkS5/tg0e5T04pJJ15StRiN2VrS5VlC/RIJG3O0tziptpn1 9KQ9KRD1oSKooYxt+qigJx3lRK5aO+8Imx6vGbuOPyC/P9/pE+Je9NEmbw5nPi11v4Il CZvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oNAn0opw3juAzKtNOLvu3FWPGR8vu8k8ubiNRQeOiqo=; b=P7vsrVsyBHn3N1eCszWVhVn6LZKdWRMFWJKPMGYiaj5bE8UUBMAoU72tecbhbCdvGq mzeXgwf1K0CC2JIsw3dKYIVo88hIU4r/zgwlOC+MECKjkcyeJ2n2LnzjcQAY48tc6+9y Z9pgHEavltEGWeXHRGHr6mEpqOMNmDLeW2DqUn6M3rgnMMhCXJQTTWI8uzaJH3f7RLCx NoZXjDfmAi8fyyLwmmpO4CC5i2V/RA6XL2paPYewDu4lOtrxMW46w1f6oeDXaqmhrqmS IY8kI3MIqHj49YLwu52YLxSBtkjJXeor8MmaP9OIKkm3cvYPSoGej0g/3nwUvVOtjrYb nfxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eSx3WBEm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will reduce the differences between 32-bit and 64-bit hosts, allowing full 64-bit constants to be created with the same interface. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 44ca8845cf..f3eca6feb0 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -506,7 +506,7 @@ typedef struct TCGTemp { unsigned int mem_allocated:1; unsigned int temp_allocated:1; - tcg_target_long val; + int64_t val; struct TCGTemp *mem_base; intptr_t mem_offset; const char *name; diff --git a/tcg/tcg.c b/tcg/tcg.c index 577bfec202..1650c5a9db 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3094,7 +3094,7 @@ static void dump_regs(TCGContext *s) tcg_target_reg_names[ts->mem_base->reg]); break; case TEMP_VAL_CONST: - printf("$0x%" TCG_PRIlx, ts->val); + printf("$0x%" PRIx64, ts->val); break; case TEMP_VAL_DEAD: printf("D"); From patchwork Wed Sep 9 00:16:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249405 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5015863ilg; Tue, 8 Sep 2020 17:23:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwA9xmtTxwRPfxuqPN3g4F+PO7GqVHXX8l6K9PMAn5VvYfGVnz1KF1hDA3RB+fWtr6r77R7 X-Received: by 2002:a25:3258:: with SMTP id y85mr2342232yby.473.1599611025432; Tue, 08 Sep 2020 17:23:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611025; cv=none; d=google.com; s=arc-20160816; b=pGqRP6/AXzmlxm1ozMnVeNRVKVXyCZj7PTTkB2ggNufznHCAnWpgfiYrwDRODKn0Rj L+7NnpMJBDLsTBYRP7nCZ807tKEbP4aaYjCOVLLKEAHT9renLGhAF9ZYEopAglT1lOhB Y+1ZmZLkqctjaoXpfl8bYE1w+DgOTmA8Vbvqhk8KfaR+R5dOWRN+sYrQsivkCzKGcGDZ 8kLR72eZ4BRQPE9HtSOexRPW5RmE5CtUAmUYZRn3K3mSOmbDWJjxJc1YZYWtSjfLOlbN V2gm+Ec9seaiIifGqT3E8/323HaM/RZU2XcHb1f0yY7QC6KqroNBCkEGOx5h/cyI9tIb 8HTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bBAAD2EsIW/155GIjaU48r4O2esHCcXs+AbT7vfXmho=; b=FLybiwyNEbFuNZEtIyrH7NIFx4I1SmdJ9ILJ1tYhfS/b8plqXkMDYcrCX2sigf4FEB eLHD6/i78TTx7UZhb0MmjVGnEIEbwwwVRGc4DHL5VZBpruc/ZRlyc4KCfgv/6Cgndxfx E4ClyCJuYj5qj0PO693rr6QiSDU4ccZkAVpPKwzBWGLP6vuaOeAVtWeyYzZVhCGy/W9c hDKaRy+RnGmaYzCbV/FJ8LfVB0BzhakjnT+gr5Xx6ZhLkAcqGvW3O6+hHn35NZu3ewNm 75umuLwYOSkMadkusT2CUR1pV2n19y6dSa3ix4rJLPWmVFcsxWIZ+it+apCJRrBsJwvS CG+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dcHQ9efW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fix this name vs our coding style. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 3cffd941bd..81faf7cf10 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -35,20 +35,20 @@ glue(glue(case INDEX_op_, x), _i64): \ glue(glue(case INDEX_op_, x), _vec) -struct tcg_temp_info { +typedef struct TempOptInfo { bool is_const; TCGTemp *prev_copy; TCGTemp *next_copy; tcg_target_ulong val; tcg_target_ulong mask; -}; +} TempOptInfo; -static inline struct tcg_temp_info *ts_info(TCGTemp *ts) +static inline TempOptInfo *ts_info(TCGTemp *ts) { return ts->state_ptr; } -static inline struct tcg_temp_info *arg_info(TCGArg arg) +static inline TempOptInfo *arg_info(TCGArg arg) { return ts_info(arg_temp(arg)); } @@ -71,9 +71,9 @@ static inline bool ts_is_copy(TCGTemp *ts) /* Reset TEMP's state, possibly removing the temp for the list of copies. */ static void reset_ts(TCGTemp *ts) { - struct tcg_temp_info *ti = ts_info(ts); - struct tcg_temp_info *pi = ts_info(ti->prev_copy); - struct tcg_temp_info *ni = ts_info(ti->next_copy); + TempOptInfo *ti = ts_info(ts); + TempOptInfo *pi = ts_info(ti->prev_copy); + TempOptInfo *ni = ts_info(ti->next_copy); ni->prev_copy = ti->prev_copy; pi->next_copy = ti->next_copy; @@ -89,12 +89,12 @@ static void reset_temp(TCGArg arg) } /* Initialize and activate a temporary. */ -static void init_ts_info(struct tcg_temp_info *infos, +static void init_ts_info(TempOptInfo *infos, TCGTempSet *temps_used, TCGTemp *ts) { size_t idx = temp_idx(ts); if (!test_bit(idx, temps_used->l)) { - struct tcg_temp_info *ti = &infos[idx]; + TempOptInfo *ti = &infos[idx]; ts->state_ptr = ti; ti->next_copy = ts; @@ -105,7 +105,7 @@ static void init_ts_info(struct tcg_temp_info *infos, } } -static void init_arg_info(struct tcg_temp_info *infos, +static void init_arg_info(TempOptInfo *infos, TCGTempSet *temps_used, TCGArg arg) { init_ts_info(infos, temps_used, arg_temp(arg)); @@ -171,7 +171,7 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) const TCGOpDef *def; TCGOpcode new_op; tcg_target_ulong mask; - struct tcg_temp_info *di = arg_info(dst); + TempOptInfo *di = arg_info(dst); def = &tcg_op_defs[op->opc]; if (def->flags & TCG_OPF_VECTOR) { @@ -202,8 +202,8 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) TCGTemp *dst_ts = arg_temp(dst); TCGTemp *src_ts = arg_temp(src); const TCGOpDef *def; - struct tcg_temp_info *di; - struct tcg_temp_info *si; + TempOptInfo *di; + TempOptInfo *si; tcg_target_ulong mask; TCGOpcode new_op; @@ -236,7 +236,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) di->mask = mask; if (src_ts->type == dst_ts->type) { - struct tcg_temp_info *ni = ts_info(si->next_copy); + TempOptInfo *ni = ts_info(si->next_copy); di->next_copy = si->next_copy; di->prev_copy = src_ts; @@ -599,7 +599,7 @@ void tcg_optimize(TCGContext *s) { int nb_temps, nb_globals; TCGOp *op, *op_next, *prev_mb = NULL; - struct tcg_temp_info *infos; + TempOptInfo *infos; TCGTempSet temps_used; /* Array VALS has an element for each temp. @@ -610,7 +610,7 @@ void tcg_optimize(TCGContext *s) nb_temps = s->nb_temps; nb_globals = s->nb_globals; bitmap_zero(temps_used.l, nb_temps); - infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps); + infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps); QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { tcg_target_ulong mask, partmask, affected; From patchwork Wed Sep 9 00:16:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249414 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5017576ilg; Tue, 8 Sep 2020 17:27:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzY2DwFhgCmbxpEaNZrdxOI2wwZT9ZFQ51kBV/OiZvXIu7QSMCfci3TQXvkX4F36Fpe2ah0 X-Received: by 2002:a05:6902:725:: with SMTP id l5mr2102851ybt.430.1599611229792; Tue, 08 Sep 2020 17:27:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611229; cv=none; d=google.com; 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[209.51.188.17]) by mx.google.com with ESMTPS id f93si1044040ybi.316.2020.09.08.17.27.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:27:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="b/P7kCuS"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnx7-0005zE-A4 for patch@linaro.org; Tue, 08 Sep 2020 20:27:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37478) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnV-0008Hq-Ty for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:13 -0400 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:39474) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnU-0002Er-67 for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:13 -0400 Received: by mail-pj1-x1041.google.com with SMTP id s2so425989pjr.4 for ; Tue, 08 Sep 2020 17:17:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KysIP4SxxPHUzbaJQ7kkTPCy9I7LKQnOtelCJefhblY=; b=b/P7kCuSh9/H8RhlUz9a78L1IC69pDlYZWiEE+l0xBf1cH9SaWTney3lVRJvu9Ryjk TwKwFqj2v31+NsdwLW6iviAY1TwybGJenVfYNWASVK9mwlh5p64EgtPAMW/H4+iHAD9E DTUQnPFMECMxevhIy7ulftsDPebrPTinJlCD7p1Mjnp4i0Z1WdOpZ0uDNWKajp7ua868 2p9S1a2n8lRh1HsCPtrUpH06d4Bg5X+nRkRQWMcwDHpKCCt1kk20DF7rMpN7iF1dz8MB Lfx6iMLBXV4CwjmZdOKuX16IdvDSi99H0IcbFYKYoyvEGBYLTNepmBtI+EuB+tTPOalV Vbsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KysIP4SxxPHUzbaJQ7kkTPCy9I7LKQnOtelCJefhblY=; b=rstfZ1/GIdMYS4v8vugWWPQHqvoJ1e+J65jsLsQp16gN24JAzckEl5KZuDpsb8vot4 tJ+U15/pHdraUcfRByETBYA5IY4/DZEgSnA0fZAbVucvQFP193Bf8imlDKIki/1SHkHg IR0s99wsoi9j+f2k+pUm6OsboukO8L5Lg3BHYxNb4L+2bLBKs2Z32h3PFUekcxVaBEuG 1qU0tRvQ2kzR9oNc3Vyp4EgMc48DGp6A3A12sRV+scl5Q2F6JnTHUx4UfD5+dN46luPN f7x6Fyu8ehnRSbTBqQgi038z5gUoLn8U+uqy1XYOwiepkgLOpz1Ocqv1dgjc6Q6u17Oq mubg== X-Gm-Message-State: AOAM531NPSVvE+klQRnq3Q9EUflxujMwrcFk4+n1iZG+xGqvSW19qOXP 8WltSWdXSpq00Jp7fKnKyIW4UDSnEP8AdQ== X-Received: by 2002:a17:90a:c907:: with SMTP id v7mr1192959pjt.204.1599610630489; Tue, 08 Sep 2020 17:17:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/43] tcg: Expand TempOptInfo to 64-bits Date: Tue, 8 Sep 2020 17:16:21 -0700 Message-Id: <20200909001647.532249-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This propagates the extended value of TCGTemp.val that we did before. In addition, it will be required for vector constants. Signed-off-by: Richard Henderson --- tcg/optimize.c | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 81faf7cf10..33d1fc8f87 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -39,8 +39,8 @@ typedef struct TempOptInfo { bool is_const; TCGTemp *prev_copy; TCGTemp *next_copy; - tcg_target_ulong val; - tcg_target_ulong mask; + uint64_t val; + uint64_t mask; } TempOptInfo; static inline TempOptInfo *ts_info(TCGTemp *ts) @@ -166,11 +166,11 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2) return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); } -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) +static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, uint64_t val) { const TCGOpDef *def; TCGOpcode new_op; - tcg_target_ulong mask; + uint64_t mask; TempOptInfo *di = arg_info(dst); def = &tcg_op_defs[op->opc]; @@ -204,7 +204,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) const TCGOpDef *def; TempOptInfo *di; TempOptInfo *si; - tcg_target_ulong mask; + uint64_t mask; TCGOpcode new_op; if (ts_are_copies(dst_ts, src_ts)) { @@ -247,7 +247,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) } } -static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) +static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) { uint64_t l64, h64; @@ -410,10 +410,10 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) } } -static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y) +static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y) { const TCGOpDef *def = &tcg_op_defs[op]; - TCGArg res = do_constant_folding_2(op, x, y); + uint64_t res = do_constant_folding_2(op, x, y); if (!(def->flags & TCG_OPF_64BIT)) { res = (int32_t)res; } @@ -501,8 +501,9 @@ static bool do_constant_folding_cond_eq(TCGCond c) static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, TCGArg y, TCGCond c) { - tcg_target_ulong xv = arg_info(x)->val; - tcg_target_ulong yv = arg_info(y)->val; + uint64_t xv = arg_info(x)->val; + uint64_t yv = arg_info(y)->val; + if (arg_is_const(x) && arg_is_const(y)) { const TCGOpDef *def = &tcg_op_defs[op]; tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR)); @@ -613,9 +614,8 @@ void tcg_optimize(TCGContext *s) infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps); QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { - tcg_target_ulong mask, partmask, affected; + uint64_t mask, partmask, affected, tmp; int nb_oargs, nb_iargs, i; - TCGArg tmp; TCGOpcode opc = op->opc; const TCGOpDef *def = &tcg_op_defs[opc]; @@ -1221,14 +1221,15 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(extract2): if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - TCGArg v1 = arg_info(op->args[1])->val; - TCGArg v2 = arg_info(op->args[2])->val; + uint64_t v1 = arg_info(op->args[1])->val; + uint64_t v2 = arg_info(op->args[2])->val; + int shr = op->args[3]; if (opc == INDEX_op_extract2_i64) { - tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3])); + tmp = (v1 >> shr) | (v2 << (64 - shr)); } else { - tmp = (int32_t)(((uint32_t)v1 >> op->args[3]) | - ((uint32_t)v2 << (32 - op->args[3]))); + tmp = (int32_t)(((uint32_t)v1 >> shr) | + ((uint32_t)v2 << (32 - shr))); } tcg_opt_gen_movi(s, op, op->args[0], tmp); break; @@ -1267,9 +1268,10 @@ void tcg_optimize(TCGContext *s) break; } if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { - tcg_target_ulong tv = arg_info(op->args[3])->val; - tcg_target_ulong fv = arg_info(op->args[4])->val; + uint64_t tv = arg_info(op->args[3])->val; + uint64_t fv = arg_info(op->args[4])->val; TCGCond cond = op->args[5]; + if (fv == 1 && tv == 0) { cond = tcg_invert_cond(cond); } else if (!(tv == 1 && fv == 0)) { From patchwork Wed Sep 9 00:16:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249391 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5014499ilg; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These will hold a single constant for the duration of the TB. They are hashed, so that each value has one temp across the TB. Not used yet, this is all infrastructure. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 24 +++++- tcg/optimize.c | 13 +++- tcg/tcg.c | 195 ++++++++++++++++++++++++++++++++++++---------- 3 files changed, 188 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index f3eca6feb0..aa7b0ba163 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -492,6 +492,8 @@ typedef enum TCGTempKind { TEMP_GLOBAL, /* Temp is in a fixed register. */ TEMP_FIXED, + /* Temp is a fixed constant. */ + TEMP_CONST, } TCGTempKind; typedef struct TCGTemp { @@ -667,6 +669,7 @@ struct TCGContext { QSIMPLEQ_HEAD(, TCGOp) plugin_ops; #endif + GHashTable *const_table[TCG_TYPE_COUNT]; TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ @@ -683,7 +686,7 @@ struct TCGContext { static inline bool temp_readonly(TCGTemp *ts) { - return ts->kind == TEMP_FIXED; + return ts->kind >= TEMP_FIXED; } extern TCGContext tcg_init_ctx; @@ -1051,6 +1054,7 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc); void tcg_optimize(TCGContext *s); +/* Allocate a new temporary and initialize it with a constant. */ TCGv_i32 tcg_const_i32(int32_t val); TCGv_i64 tcg_const_i64(int64_t val); TCGv_i32 tcg_const_local_i32(int32_t val); @@ -1060,6 +1064,24 @@ TCGv_vec tcg_const_ones_vec(TCGType); TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); +/* + * Locate or create a read-only temporary that is a constant. + * This kind of temporary need not and should not be freed. + */ +TCGTemp *tcg_constant_internal(TCGType type, int64_t val); + +static inline TCGv_i32 tcg_constant_i32(int32_t val) +{ + return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); +} + +static inline TCGv_i64 tcg_constant_i64(int64_t val) +{ + return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); +} + +TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); + #if UINTPTR_MAX == UINT32_MAX # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) diff --git a/tcg/optimize.c b/tcg/optimize.c index 33d1fc8f87..c0fd65d2e4 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -99,8 +99,17 @@ static void init_ts_info(TempOptInfo *infos, ts->state_ptr = ti; ti->next_copy = ts; ti->prev_copy = ts; - ti->is_const = false; - ti->mask = -1; + if (ts->kind == TEMP_CONST) { + ti->is_const = true; + ti->val = ti->mask = ts->val; + if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { + /* High bits of a 32-bit quantity are garbage. */ + ti->mask |= ~0xffffffffull; + } + } else { + ti->is_const = false; + ti->mask = -1; + } set_bit(idx, temps_used->l); } } diff --git a/tcg/tcg.c b/tcg/tcg.c index 1650c5a9db..e413bf70d4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1204,13 +1204,19 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, bigendian = 1; #endif - if (base_ts->kind != TEMP_FIXED) { + switch (base_ts->kind) { + case TEMP_FIXED: + break; + case TEMP_GLOBAL: /* We do not support double-indirect registers. */ tcg_debug_assert(!base_ts->indirect_reg); base_ts->indirect_base = 1; s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 ? 2 : 1); indirect_reg = 1; + break; + default: + g_assert_not_reached(); } if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { @@ -1335,6 +1341,11 @@ void tcg_temp_free_internal(TCGTemp *ts) TCGContext *s = tcg_ctx; int k, idx; + /* In order to simplify users of tcg_constant_*, silently ignore free. */ + if (ts->kind == TEMP_CONST) { + return; + } + #if defined(CONFIG_DEBUG_TCG) s->temps_in_use--; if (s->temps_in_use < 0) { @@ -1351,6 +1362,60 @@ void tcg_temp_free_internal(TCGTemp *ts) set_bit(idx, s->free_temps[k].l); } +TCGTemp *tcg_constant_internal(TCGType type, int64_t val) +{ + TCGContext *s = tcg_ctx; + GHashTable *h = s->const_table[type]; + TCGTemp *ts; + + if (h == NULL) { + h = g_hash_table_new(g_int64_hash, g_int64_equal); + s->const_table[type] = h; + } + + ts = g_hash_table_lookup(h, &val); + if (ts == NULL) { + ts = tcg_temp_alloc(s); + + if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { + TCGTemp *ts2 = tcg_temp_alloc(s); + + ts->base_type = TCG_TYPE_I64; + ts->type = TCG_TYPE_I32; + ts->kind = TEMP_CONST; + ts->temp_allocated = 1; + /* + * Retain the full value of the 64-bit constant in the low + * part, so that the hash table works. Actual uses will + * truncate the value to the low part. + */ + ts->val = val; + + tcg_debug_assert(ts2 == ts + 1); + ts2->base_type = TCG_TYPE_I64; + ts2->type = TCG_TYPE_I32; + ts2->kind = TEMP_CONST; + ts2->temp_allocated = 1; + ts2->val = val >> 32; + } else { + ts->base_type = type; + ts->type = type; + ts->kind = TEMP_CONST; + ts->temp_allocated = 1; + ts->val = val; + } + g_hash_table_insert(h, &ts->val, ts); + } + + return ts; +} + +TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) +{ + val = dup_const(vece, val); + return temp_tcgv_vec(tcg_constant_internal(type, val)); +} + TCGv_i32 tcg_const_i32(int32_t val) { TCGv_i32 t0; @@ -1883,6 +1948,9 @@ static void tcg_reg_alloc_start(TCGContext *s) TCGTempVal val = TEMP_VAL_MEM; switch (ts->kind) { + case TEMP_CONST: + val = TEMP_VAL_CONST; + break; case TEMP_FIXED: val = TEMP_VAL_REG; break; @@ -1919,6 +1987,26 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, case TEMP_NORMAL: snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); break; + case TEMP_CONST: + switch (ts->type) { + case TCG_TYPE_I32: + snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val); + break; +#if TCG_TARGET_REG_BITS > 32 + case TCG_TYPE_I64: + snprintf(buf, buf_size, "$0x%" PRIx64, ts->val); + break; +#endif + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + snprintf(buf, buf_size, "v%d$0x%" PRIx64, + 64 << (ts->type - TCG_TYPE_V64), ts->val); + break; + default: + g_assert_not_reached(); + } + break; } return buf; } @@ -2519,6 +2607,7 @@ static void la_bb_end(TCGContext *s, int ng, int nt) state = TS_DEAD | TS_MEM; break; case TEMP_NORMAL: + case TEMP_CONST: state = TS_DEAD; break; default: @@ -3172,15 +3261,28 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); mark it free; otherwise mark it dead. */ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) { - if (temp_readonly(ts)) { + TCGTempVal new_type; + + switch (ts->kind) { + case TEMP_FIXED: return; + case TEMP_GLOBAL: + case TEMP_LOCAL: + new_type = TEMP_VAL_MEM; + break; + case TEMP_NORMAL: + new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD; + break; + case TEMP_CONST: + new_type = TEMP_VAL_CONST; + break; + default: + g_assert_not_reached(); } if (ts->val_type == TEMP_VAL_REG) { s->reg_to_temp[ts->reg] = NULL; } - ts->val_type = (free_or_dead < 0 - || ts->kind != TEMP_NORMAL - ? TEMP_VAL_MEM : TEMP_VAL_DEAD); + ts->val_type = new_type; } /* Mark a temporary as dead. */ @@ -3196,10 +3298,7 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, TCGRegSet preferred_regs, int free_or_dead) { - if (temp_readonly(ts)) { - return; - } - if (!ts->mem_coherent) { + if (!temp_readonly(ts) && !ts->mem_coherent) { if (!ts->mem_allocated) { temp_allocate_frame(s, ts); } @@ -3417,12 +3516,22 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) for (i = s->nb_globals; i < s->nb_temps; i++) { TCGTemp *ts = &s->temps[i]; - if (ts->kind == TEMP_LOCAL) { + + switch (ts->kind) { + case TEMP_LOCAL: temp_save(s, ts, allocated_regs); - } else { + break; + case TEMP_NORMAL: /* The liveness analysis already ensures that temps are dead. Keep an tcg_debug_assert for safety. */ tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); + break; + case TEMP_CONST: + /* Similarly, we should have freed any allocated register. */ + tcg_debug_assert(ts->val_type == TEMP_VAL_CONST); + break; + default: + g_assert_not_reached(); } } @@ -3715,45 +3824,42 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) i_preferred_regs = o_preferred_regs = 0; if (arg_ct->ialias) { o_preferred_regs = op->output_pref[arg_ct->alias_index]; - if (ts->kind == TEMP_FIXED) { - /* if fixed register, we must allocate a new register - if the alias is not the same register */ - if (arg != op->args[arg_ct->alias_index]) { - goto allocate_in_reg; - } - } else { - /* if the input is aliased to an output and if it is - not dead after the instruction, we must allocate - a new register and move it */ - if (!IS_DEAD_ARG(i)) { - goto allocate_in_reg; - } - /* check if the current register has already been allocated - for another input aliased to an output */ - if (ts->val_type == TEMP_VAL_REG) { - int k2, i2; - reg = ts->reg; - for (k2 = 0 ; k2 < k ; k2++) { - i2 = def->args_ct[nb_oargs + k2].sort_index; - if (def->args_ct[i2].ialias && reg == new_args[i2]) { - goto allocate_in_reg; - } + /* + * If the input is readonly, then it cannot also be an + * output and aliased to itself. If the input is not + * dead after the instruction, we must allocate a new + * register and move it. + */ + if (temp_readonly(ts) || !IS_DEAD_ARG(i)) { + goto allocate_in_reg; + } + + /* + * Check if the current register has already been allocated + * for another input aliased to an output. + */ + if (ts->val_type == TEMP_VAL_REG) { + reg = ts->reg; + for (int k2 = 0; k2 < k; k2++) { + int i2 = def->args_ct[nb_oargs + k2].sort_index; + if (def->args_ct[i2].ialias && reg == new_args[i2]) { + goto allocate_in_reg; } } - i_preferred_regs = o_preferred_regs; } + i_preferred_regs = o_preferred_regs; } temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs); reg = ts->reg; - if (tcg_regset_test_reg(arg_ct->regs, reg)) { - /* nothing to do : the constraint is satisfied */ - } else { - allocate_in_reg: - /* allocate a new register matching the constraint - and move the temporary register into it */ + if (!tcg_regset_test_reg(arg_ct->regs, reg)) { + allocate_in_reg: + /* + * Allocate a new register matching the constraint + * and move the temporary register into it. + */ temp_load(s, ts, tcg_target_available_regs[ts->type], i_allocated_regs, 0); reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs, @@ -4211,6 +4317,13 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) } #endif + for (i = 0; i < TCG_TYPE_COUNT; ++i) { + if (s->const_table[i]) { + g_hash_table_destroy(s->const_table[i]); + s->const_table[i] = NULL; + } + } + tcg_reg_alloc_start(s); s->code_buf = tb->tc.ptr; From patchwork Wed Sep 9 00:16:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249408 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5016558ilg; Tue, 8 Sep 2020 17:25:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzcJufslqKV4phm1ajYVq3gX0J1XEBVb0DdGDdBahTpxjgT8dlTGe0UdalWeUk3Wk2oAKws X-Received: by 2002:a25:6a88:: with SMTP id f130mr2160789ybc.411.1599611104936; Tue, 08 Sep 2020 17:25:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611104; cv=none; d=google.com; s=arc-20160816; b=c2w0G1+q3zyTt1Nwz1pRph20qQ4BHzUr9+Uwv5jOBzrpxkgqfYt/Ww08AqO4MmnAaV odTU0EFlh26PCQ3mfXPelfcg5n7tGBScvcbIgXDVm1g23979gWL86KIFvBkXFYxDXUC2 AMcQiSyxllfhDz22PJYiIY2kzpT7bnz9y+hUzDbs42/rYy90dRBXFiIS6CefyqfJSFaq Zt2lBh+XazamfmqLaModnpyF1McoibPH5xk8LAESc6e5NztU5+IV0oqDxLoxcj63m0fy 89ygy+PE+kw7BeNCD8U3eNAZRVuTRVm+6XXzt7ubYYwoijKOliYMkjKv0GhzPca3KlOg ta2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=x+s9W4S8X9df0AJnC/pFDE7SPPgT3/tOf2XSzgDEzSo=; b=NCT3DkIuflO6OULdUI658rGOqi3YpOS7WF7ez1GAw0CqQNIhFLAGDA9R3KcHbnzzaG 1cf0rI5j+qFUxLOhNkIS6lE8KNONjegGiT8pzhb0VGm5w+WQ2lNdWbIeraoA+mjlR4mN zhicBrTBrG/gvasPxb7JTSNNZRKVDBwivVL/sBMGVp4nuKixGTEi5BKwdmxTE2hPUn86 zUsE7uEDuMQpVdm/Ei7VXuvesegGpR2cvULj8qp+HDfmShp4YUZdpeszW97SSzb571Pc X8l7tW/f+ZU187AP8oz4ESsqhxEOAu3tldLLPrVJN9PyEUYaoFLPBV6k2s9IuRYHpn94 1B4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LWrer79b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u15si1128409ybc.228.2020.09.08.17.25.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:25:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LWrer79b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnv6-0008CI-Bo for patch@linaro.org; Tue, 08 Sep 2020 20:25:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnY-0008ON-AY for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:16 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:37377) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnW-0002FW-MK for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:15 -0400 Received: by mail-pf1-x441.google.com with SMTP id w7so565013pfi.4 for ; Tue, 08 Sep 2020 17:17:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=x+s9W4S8X9df0AJnC/pFDE7SPPgT3/tOf2XSzgDEzSo=; b=LWrer79bKyuhjmzyncNJWLXkxJGTeDtW71v/dXDkZejqc3re+JH+4+kTrvE4k5vHgs K0Ze/HspxaLKlK9o5Miz/ba11e1YHZQxy6+Fs0p0Row87q9Zuq7Gw/sTVCCPC+yFSZiK UYeBsgdzspNa21PpUTz6Edu6y9ZuR5Jpl8bOosxV3+eNfvRd+pqdOewlW9WXOZ+EWkPU cnfT9tVDZQeqLaMbLbB3Sn9CVS86Wrd1ja6YeU63VJrNoGpKySdiF9bgXDeTWtw6PkWr F7YFWLmtsvfog8NB61c7G48vLCzyihC9bonQ9145xeuaE1GlcJ/6QQGlNDdy62w9+OvH bbQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x+s9W4S8X9df0AJnC/pFDE7SPPgT3/tOf2XSzgDEzSo=; b=QSndHHKjonAZUOXCwWzd4GAF782xgi4y5vpJgFMOQa+C7oFQct3/JJdbib1x6NO/Nk PrduiQLVuP8o6YlKYs9iYI1Onq28ytpdXEjr/CZUeTEzP5mZPjpQ5WFr89pcxvujjiQT PxiKoyRLxpHqzRIhBDzMz6fy0GM7OTIHaNO/5QvGInHuZdQRcaFfog4U5gB1dS3wocTx K3XovagLSrx6/aXgfMSQmVxeSfErbHF8wazrgLzvI+nw0N5BnDSSTyA5PML+TJ0APh+G kKEaEZhOc2smgkqyjqWSWIERwYClJqUtEt8ytO5jig9BhRpQinEvBXOMD9yUABCBYMAE 56rA== X-Gm-Message-State: AOAM530M1BMpZT0i28kBrKYfgacIN2TUje6MYnfgddaeoFAgqvsMh/l5 Wn9ErujL3pb7fzCD5980ePTx4keQJJ1JxQ== X-Received: by 2002:a17:902:788e:: with SMTP id q14mr1097753pll.140.1599610633108; Tue, 08 Sep 2020 17:17:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 19/43] tcg/optimize: Improve find_better_copy Date: Tue, 8 Sep 2020 17:16:23 -0700 Message-Id: <20200909001647.532249-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Prefer TEMP_CONST over anything else. Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index c0fd65d2e4..bf2c2a3ce5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -122,31 +122,28 @@ static void init_arg_info(TempOptInfo *infos, static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) { - TCGTemp *i; + TCGTemp *i, *g, *l; - /* If this is already a global, we can't do better. */ - if (ts->kind >= TEMP_GLOBAL) { + /* If this is already readonly, we can't do better. */ + if (temp_readonly(ts)) { return ts; } - /* Search for a global first. */ + g = l = NULL; for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { - if (i->kind >= TEMP_GLOBAL) { + if (temp_readonly(i)) { return i; - } - } - - /* If it is a temp, search for a temp local. */ - if (ts->kind == TEMP_NORMAL) { - for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { - if (i->kind >= TEMP_LOCAL) { - return i; + } else if (i->kind > ts->kind) { + if (i->kind == TEMP_GLOBAL) { + g = i; + } else if (i->kind == TEMP_LOCAL) { + l = i; } } } - /* Failure to find a better representation, return the same temp. */ - return ts; + /* If we didn't find a better representation, return the same temp. */ + return g ? g : l ? l : ts; } static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) From patchwork Wed Sep 9 00:16:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249412 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5017039ilg; Tue, 8 Sep 2020 17:26:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy+VwNCKn1/3ixKDCSGFZKJqooAic1Hp89sPvH+iHHvzaOhzJtJo+u8SEs8imcdvJmYUpI5 X-Received: by 2002:a25:c07:: with SMTP id 7mr2120179ybm.200.1599611163191; Tue, 08 Sep 2020 17:26:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611163; cv=none; d=google.com; s=arc-20160816; b=t7lzMHpfJb9KMfKZ9F2xN0MKvzauhaql3rxcjZzn+8JU4Opo/Y+JsPXAEtJ4AbqnIu ADnTIdkoMT1YsE7/OHngWuMHwTW0rcx9Yz/5KL1HOHgOxPJbVFIB/PvZo5md6KMZYge+ SHXaYJsQhjs63GCcBbhDshnSalwPYHBFjtoE9A0F4gERblqxzWKa678sIXQltOouU3wl +uFG1UPEAGNjp9IrAgznm7H6p4286qmyjemEhVPvn1UxsyPPD3GtFgyMUKZqDcCWLqyZ ePuQLI+/ARB58noy9oGVlz+qupmWUHaVl3XrxrYhkjpQ6pX10qgV0GsDiCxb/dKXdpU8 ChVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1NhNPEIDsGzd2+XZQVnWFC0k3zKAB+Awk5/hTm4NEwE=; b=MAaQxqRrv0XEufX9Bhlu49mG+GoJAa0lxg3BB+FDVKi8vzxvXZvC7iwUO4eygnKHN4 +75fRN3lSsWdYueta4hbdQMoSbGhA6xRYx5iIVT/eViDpe9fPBVVI60tacq8i+OyTTYe uFOVzJ+BwQkTdd3CfWm8urNMVStbbFZ7qpy8TQFc3nK/0zrVcNSdOPBBdXDXuQaWa/Yb IyJbKGjHMo5Sye/y5K5sqC+P/uLTze/ZAp6VHv3GFQNAKQZJlXTzCByVPvRXMbJkE1ZQ 7WmN0RwAM4FaiWlDGf0rl3PAU5uWqU5WDeJ+hiAHZr7o20Ug93zxtnKQTqv8FHhcc+oC gEvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fV1LqSRE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not allocate a large block for indexing. Instead, allocate for each temporary as they are seen. In general, this will use less memory, if we consider that most TBs do not touch every target register. This also allows us to allocate TempOptInfo for new temps created during optimization. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/optimize.c | 60 ++++++++++++++++++++++++++++---------------------- 1 file changed, 34 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index bf2c2a3ce5..e269962932 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -89,35 +89,41 @@ static void reset_temp(TCGArg arg) } /* Initialize and activate a temporary. */ -static void init_ts_info(TempOptInfo *infos, - TCGTempSet *temps_used, TCGTemp *ts) +static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts) { size_t idx = temp_idx(ts); - if (!test_bit(idx, temps_used->l)) { - TempOptInfo *ti = &infos[idx]; + TempOptInfo *ti; + if (test_bit(idx, temps_used->l)) { + return; + } + set_bit(idx, temps_used->l); + + ti = ts->state_ptr; + if (ti == NULL) { + ti = tcg_malloc(sizeof(TempOptInfo)); ts->state_ptr = ti; - ti->next_copy = ts; - ti->prev_copy = ts; - if (ts->kind == TEMP_CONST) { - ti->is_const = true; - ti->val = ti->mask = ts->val; - if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { - /* High bits of a 32-bit quantity are garbage. */ - ti->mask |= ~0xffffffffull; - } - } else { - ti->is_const = false; - ti->mask = -1; + } + + ti->next_copy = ts; + ti->prev_copy = ts; + if (ts->kind == TEMP_CONST) { + ti->is_const = true; + ti->val = ts->val; + ti->mask = ts->val; + if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { + /* High bits of a 32-bit quantity are garbage. */ + ti->mask |= ~0xffffffffull; } - set_bit(idx, temps_used->l); + } else { + ti->is_const = false; + ti->mask = -1; } } -static void init_arg_info(TempOptInfo *infos, - TCGTempSet *temps_used, TCGArg arg) +static void init_arg_info(TCGTempSet *temps_used, TCGArg arg) { - init_ts_info(infos, temps_used, arg_temp(arg)); + init_ts_info(temps_used, arg_temp(arg)); } static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) @@ -604,9 +610,8 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { - int nb_temps, nb_globals; + int nb_temps, nb_globals, i; TCGOp *op, *op_next, *prev_mb = NULL; - TempOptInfo *infos; TCGTempSet temps_used; /* Array VALS has an element for each temp. @@ -616,12 +621,15 @@ void tcg_optimize(TCGContext *s) nb_temps = s->nb_temps; nb_globals = s->nb_globals; + bitmap_zero(temps_used.l, nb_temps); - infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps); + for (i = 0; i < nb_temps; ++i) { + s->temps[i].state_ptr = NULL; + } QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { uint64_t mask, partmask, affected, tmp; - int nb_oargs, nb_iargs, i; + int nb_oargs, nb_iargs; TCGOpcode opc = op->opc; const TCGOpDef *def = &tcg_op_defs[opc]; @@ -633,14 +641,14 @@ void tcg_optimize(TCGContext *s) for (i = 0; i < nb_oargs + nb_iargs; i++) { TCGTemp *ts = arg_temp(op->args[i]); if (ts) { - init_ts_info(infos, &temps_used, ts); + init_ts_info(&temps_used, ts); } } } else { nb_oargs = def->nb_oargs; nb_iargs = def->nb_iargs; for (i = 0; i < nb_oargs + nb_iargs; i++) { - init_arg_info(infos, &temps_used, op->args[i]); + init_arg_info(&temps_used, op->args[i]); } } From patchwork Wed Sep 9 00:16:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249402 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5015322ilg; Tue, 8 Sep 2020 17:22:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxyzaxrYc7ihNrY+gGeBjpFn8aaF20cQV1zkLdF+3wYXERt0kk+q6We9BpgSuMf5enLQk6O X-Received: by 2002:a25:d348:: with SMTP id e69mr2237509ybf.273.1599610964245; Tue, 08 Sep 2020 17:22:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610964; cv=none; d=google.com; s=arc-20160816; b=hjVsBQ2zKO07i2kDdZBbG05GwfeeI6/1/vDoSxT6lXoCoLCY/L+LnCb+fzTQiYmM6U d3FiMRqCWHhtRvC1h1B7y8H5kEDiUqoJzu7OkIwx6BSrwGv9DdoLS4NgaKxgpj7gvASs tvrRACU9WmzmyGRZtUoWJ0hWmqZbJli7vFKlyFZlQXP+KIITlr+de+IspPyc2Gwzeeul /9vR+ieQg7Tz7lqnJt+77iRpp9ehUVL+pr4z4ox6T37CqhohsXC8zximt32Z7D/1LxQS 57TCcSrUFW8FjR55XB2okaFOFtVPhrLeV/XBlTEoWoj48DRVQp2QMMvTWMXoFAga53my cn6g== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/optimize.c | 108 ++++++++++++++++++++++--------------------------- 1 file changed, 49 insertions(+), 59 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index e269962932..1eda7dc419 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -178,37 +178,6 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2) return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); } -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, uint64_t val) -{ - const TCGOpDef *def; - TCGOpcode new_op; - uint64_t mask; - TempOptInfo *di = arg_info(dst); - - def = &tcg_op_defs[op->opc]; - if (def->flags & TCG_OPF_VECTOR) { - new_op = INDEX_op_dupi_vec; - } else if (def->flags & TCG_OPF_64BIT) { - new_op = INDEX_op_movi_i64; - } else { - new_op = INDEX_op_movi_i32; - } - op->opc = new_op; - /* TCGOP_VECL and TCGOP_VECE remain unchanged. */ - op->args[0] = dst; - op->args[1] = val; - - reset_temp(dst); - di->is_const = true; - di->val = val; - mask = val; - if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) { - /* High bits of the destination are now garbage. */ - mask |= ~0xffffffffull; - } - di->mask = mask; -} - static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) { TCGTemp *dst_ts = arg_temp(dst); @@ -259,6 +228,27 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) } } +static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used, + TCGOp *op, TCGArg dst, uint64_t val) +{ + const TCGOpDef *def = &tcg_op_defs[op->opc]; + TCGType type; + TCGTemp *tv; + + if (def->flags & TCG_OPF_VECTOR) { + type = TCGOP_VECL(op) + TCG_TYPE_V64; + } else if (def->flags & TCG_OPF_64BIT) { + type = TCG_TYPE_I64; + } else { + type = TCG_TYPE_I32; + } + + /* Convert movi to mov with constant temp. */ + tv = tcg_constant_internal(type, val); + init_ts_info(temps_used, tv); + tcg_opt_gen_mov(s, op, dst, temp_arg(tv)); +} + static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) { uint64_t l64, h64; @@ -622,7 +612,7 @@ void tcg_optimize(TCGContext *s) nb_temps = s->nb_temps; nb_globals = s->nb_globals; - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); for (i = 0; i < nb_temps; ++i) { s->temps[i].state_ptr = NULL; } @@ -727,7 +717,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(rotr): if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == 0) { - tcg_opt_gen_movi(s, op, op->args[0], 0); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); continue; } break; @@ -1050,7 +1040,7 @@ void tcg_optimize(TCGContext *s) if (partmask == 0) { tcg_debug_assert(nb_oargs == 1); - tcg_opt_gen_movi(s, op, op->args[0], 0); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); continue; } if (affected == 0) { @@ -1067,7 +1057,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(mulsh): if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0) { - tcg_opt_gen_movi(s, op, op->args[0], 0); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); continue; } break; @@ -1094,7 +1084,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(sub): CASE_OP_32_64_VEC(xor): if (args_are_copies(op->args[1], op->args[2])) { - tcg_opt_gen_movi(s, op, op->args[0], 0); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); continue; } break; @@ -1111,14 +1101,14 @@ void tcg_optimize(TCGContext *s) break; CASE_OP_32_64(movi): case INDEX_op_dupi_vec: - tcg_opt_gen_movi(s, op, op->args[0], op->args[1]); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], op->args[1]); break; case INDEX_op_dup_vec: if (arg_is_const(op->args[1])) { tmp = arg_info(op->args[1])->val; tmp = dup_const(TCGOP_VECE(op), tmp); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1128,7 +1118,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { tmp = arg_info(op->args[1])->val; if (tmp == arg_info(op->args[2])->val) { - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } } else if (args_are_copies(op->args[1], op->args[2])) { @@ -1156,7 +1146,7 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extrh_i64_i32: if (arg_is_const(op->args[1])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1186,7 +1176,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1197,7 +1187,7 @@ void tcg_optimize(TCGContext *s) TCGArg v = arg_info(op->args[1])->val; if (v != 0) { tmp = do_constant_folding(opc, v, 0); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); } else { tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); } @@ -1210,7 +1200,7 @@ void tcg_optimize(TCGContext *s) tmp = deposit64(arg_info(op->args[1])->val, op->args[3], op->args[4], arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1219,7 +1209,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = extract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1228,7 +1218,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = sextract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1245,7 +1235,7 @@ void tcg_optimize(TCGContext *s) tmp = (int32_t)(((uint32_t)v1 >> shr) | ((uint32_t)v2 << (32 - shr))); } - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1254,7 +1244,7 @@ void tcg_optimize(TCGContext *s) tmp = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[3]); if (tmp != 2) { - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1264,7 +1254,7 @@ void tcg_optimize(TCGContext *s) op->args[1], op->args[2]); if (tmp != 2) { if (tmp) { - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); op->opc = INDEX_op_br; op->args[0] = op->args[3]; } else { @@ -1310,7 +1300,7 @@ void tcg_optimize(TCGContext *s) uint64_t a = ((uint64_t)ah << 32) | al; uint64_t b = ((uint64_t)bh << 32) | bl; TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); if (opc == INDEX_op_add2_i32) { a += b; @@ -1320,8 +1310,8 @@ void tcg_optimize(TCGContext *s) rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(s, op, rl, (int32_t)a); - tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32)); + tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)a); + tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(a >> 32)); break; } goto do_default; @@ -1332,12 +1322,12 @@ void tcg_optimize(TCGContext *s) uint32_t b = arg_info(op->args[3])->val; uint64_t r = (uint64_t)a * b; TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(s, op, rl, (int32_t)r); - tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32)); + tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)r); + tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(r >> 32)); break; } goto do_default; @@ -1348,7 +1338,7 @@ void tcg_optimize(TCGContext *s) if (tmp != 2) { if (tmp) { do_brcond_true: - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); op->opc = INDEX_op_br; op->args[0] = op->args[5]; } else { @@ -1364,7 +1354,7 @@ void tcg_optimize(TCGContext *s) /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); op->opc = INDEX_op_brcond_i32; op->args[0] = op->args[1]; op->args[1] = op->args[3]; @@ -1390,7 +1380,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_brcond_low: - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); op->opc = INDEX_op_brcond_i32; op->args[1] = op->args[2]; op->args[2] = op->args[4]; @@ -1425,7 +1415,7 @@ void tcg_optimize(TCGContext *s) op->args[5]); if (tmp != 2) { do_setcond_const: - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); } else if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) && arg_is_const(op->args[3]) @@ -1510,7 +1500,7 @@ void tcg_optimize(TCGContext *s) block, otherwise we only trash the output args. "mask" is the non-zero bits mask for the first output arg. */ if (def->flags & TCG_OPF_BB_END) { - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); } else { do_reset_output: for (i = 0; i < nb_oargs; i++) { From patchwork Wed Sep 9 00:16:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249415 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5017742ilg; Tue, 8 Sep 2020 17:27:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyutx0NP4hI/MXN39PoXMkSug09dOgFyxPfkUqdR8l5pSd5C/ztIBZo9H880HoIYYZ1CANu X-Received: by 2002:a25:25cd:: with SMTP id l196mr2315858ybl.160.1599611249957; Tue, 08 Sep 2020 17:27:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611249; cv=none; d=google.com; s=arc-20160816; b=RahNpKAbdUvk1caKq5FGHm6oU4OB88nmctwR5h0h/oq8N/+DAvFaT3dRIpHGoczimT EYFJdS6gD4kf9dk1JPSptKcRsnROWTSr/hM6MSEgSQsmOi5dDTPuurhQeu8acJFhlla6 4eQu7Xcs1t+FGY70QmU5zjSdKk4u4eTMo/xSTcdZ1/Xr3eRQQlVNZlzMNIVH3M+Hp5fy 3Y8PBjadzdzrWNGT4KNX5ebHV3OFHBM26nR9CVbV8PlESfyvmlF72bfVkPaU/vVAIloD dEqzPvIsO3I4kbJ8LHvE/kMDuHVW9v6GLh//RQ24Q5bgMEeVGu4ya1r/MTDHjxSxdNGb R3tA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DrWwc7nhYkhyIWgVLuU+D0JRjvYc9QKHe5GHoGABUmU=; b=h0eO5skf+SqF6nLsc6VZCqrvCrG2zw37Kd9bIIp2clA8oOfMQrmhMVouZMgUW4udaS id+erXJW+MeohsGVqXOhq/GbFv78gQcz2w/1/zKhPXuNs5v5pAmMAGBZW/8uLmc5tF7p L9mmtTiSWDPsXfZ4qyZUhNVcpCv6GUr81D+4ATv9/lCH4+HlqGdWXl4OXA8iCo+sQ/tO HZ6tSYoNQZI5/irgnk+wAiZy3ldwMjTZCdM7sLEoXUE68unMfeVcDchx0ODUgri9govt oVUEy/y/dUjcoCO+0QPab3wsU14+qTWEQSka8qjzC+ox5pRn/xC/o3oo90hPabythe/m MwqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PYXUrzx7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because we now store uint64_t in TCGTemp, we can now always store the full 64-bit duplicate immediate. So remove the difference between 32- and 64-bit hosts. Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 ++++----- tcg/tcg-op-vec.c | 39 ++++++++++----------------------------- tcg/tcg.c | 7 +------ 3 files changed, 15 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 1eda7dc419..af07c6f628 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1116,11 +1116,10 @@ void tcg_optimize(TCGContext *s) case INDEX_op_dup2_vec: assert(TCG_TARGET_REG_BITS == 32); if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tmp = arg_info(op->args[1])->val; - if (tmp == arg_info(op->args[2])->val) { - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); - break; - } + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], + deposit64(arg_info(op->args[1])->val, 32, 32, + arg_info(op->args[2])->val)); + break; } else if (args_are_copies(op->args[1], op->args[2])) { op->opc = INDEX_op_dup_vec; TCGOP_VECE(op) = MO_32; diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index cdbf11c573..9fbed1366c 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -216,25 +216,17 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a) } } -#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32) - -static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a) -{ - TCGTemp *rt = tcgv_vec_temp(r); - vec_gen_2(INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a); -} - TCGv_vec tcg_const_zeros_vec(TCGType type) { TCGv_vec ret = tcg_temp_new_vec(type); - do_dupi_vec(ret, MO_REG, 0); + tcg_gen_dupi_vec(MO_64, ret, 0); return ret; } TCGv_vec tcg_const_ones_vec(TCGType type) { TCGv_vec ret = tcg_temp_new_vec(type); - do_dupi_vec(ret, MO_REG, -1); + tcg_gen_dupi_vec(MO_64, ret, -1); return ret; } @@ -252,39 +244,28 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m) void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a) { - if (TCG_TARGET_REG_BITS == 64) { - do_dupi_vec(r, MO_64, a); - } else if (a == dup_const(MO_32, a)) { - do_dupi_vec(r, MO_32, a); - } else { - TCGv_i64 c = tcg_const_i64(a); - tcg_gen_dup_i64_vec(MO_64, r, c); - tcg_temp_free_i64(c); - } + tcg_gen_dupi_vec(MO_64, r, a); } void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a) { - do_dupi_vec(r, MO_REG, dup_const(MO_32, a)); + tcg_gen_dupi_vec(MO_32, r, a); } void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a) { - do_dupi_vec(r, MO_REG, dup_const(MO_16, a)); + tcg_gen_dupi_vec(MO_16, r, a); } void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a) { - do_dupi_vec(r, MO_REG, dup_const(MO_8, a)); + tcg_gen_dupi_vec(MO_8, r, a); } void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a) { - if (vece == MO_64) { - tcg_gen_dup64i_vec(r, a); - } else { - do_dupi_vec(r, MO_REG, dup_const(vece, a)); - } + TCGTemp *rt = tcgv_vec_temp(r); + tcg_gen_mov_vec(r, tcg_constant_vec(rt->base_type, vece, a)); } void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a) @@ -489,8 +470,8 @@ void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a) if (tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0) { tcg_gen_sari_vec(vece, t, a, (8 << vece) - 1); } else { - do_dupi_vec(t, MO_REG, 0); - tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, t); + tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, + tcg_constant_vec(type, vece, 0)); } tcg_gen_xor_vec(vece, r, a, t); tcg_gen_sub_vec(vece, r, r, t); diff --git a/tcg/tcg.c b/tcg/tcg.c index e413bf70d4..0ce45fd123 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3440,16 +3440,11 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, * The targets will, in general, have to do this search anyway, * do this generically. */ - if (TCG_TARGET_REG_BITS == 32) { - val = dup_const(MO_32, val); - vece = MO_32; - } if (val == dup_const(MO_8, val)) { vece = MO_8; } else if (val == dup_const(MO_16, val)) { vece = MO_16; - } else if (TCG_TARGET_REG_BITS == 64 && - val == dup_const(MO_32, val)) { + } else if (val == dup_const(MO_32, val)) { vece = MO_32; } From patchwork Wed Sep 9 00:16:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249416 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5018140ilg; Tue, 8 Sep 2020 17:28:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyp9wBxonOfzNe8cTJZdD4q8q/FcVLhMV5IfTSxk3gbZOLORB+Xiq1nCzYXrF+MdPZOvE9c X-Received: by 2002:a25:ad22:: with SMTP id y34mr2191517ybi.52.1599611297436; Tue, 08 Sep 2020 17:28:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611297; cv=none; d=google.com; s=arc-20160816; b=sZA/kvVDw/Npss1N1k6VeuVRviAMu53IDohY5d8A/g6TFJUZ6nF2PKCk5K0fD1lrMZ vO1iu9woK+Pi0T/JUxqFZTEbW0BhQqXnk9c1d46vcOu6rgPMYfxxQ5BdT4L7JoBHwxTA 91PrGYPMVuo7AUB81aKbP5ZgH75FE2hdmEPAPRSkkdrhEjTDYUWppN2DUoRIXzxaSNS1 WicuDHJ38hXYuDWYBPJIHd883Dy4yTsWrn7+fLzpxeFusuqkl+iDDgo7gfAfMhdaD45Y z87oGU6SmQCf4DlsX8y0YayXSNqCjqvNnuDJbO8I6JDNp5VwAhuM4pMr400hikx56rOQ YpPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mEMZJyAsz2pya7wCS7q3Y/mkN8EK0RWNbiEA9tVJa2o=; b=uEIPMS6XjlPIWO8s0thYXjt1Gf/vukEOR0n/uGaDYs62KJb239MmPCzyDyAnSFj9Qf 0QlC9H8hLybeGcpUhRpgt4n79Ba1gHnS+KwirkZJHZvWhqf++oX8KB0YIDfUFkXR2V2+ ksN7x7TSX0ViKQvEiVHnAtl8xKLRA0MVc9K6OTa2QyZdhQ/II31Qkhlbz0S17Ox+r9Q0 IEAYCF9GWnJSJv+QUXRgL8sidmTNl2Y3uuhHF5ZSJomn06ae5YaracAu1D2x5ftyDu7Z 5hlAe0RSvmLAGm6JBeFPR6PQe3mQDwfZf4Vs8wdQ4oXblEEwoIYxOmi+sY1c6Uk2V8+P x9jA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hDMoKmOZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e14si1048915ybq.296.2020.09.08.17.28.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:28:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hDMoKmOZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnyC-0000ji-TP for patch@linaro.org; Tue, 08 Sep 2020 20:28:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnne-00004v-1e for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:22 -0400 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:35442) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnc-0002GQ-4Y for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:21 -0400 Received: by mail-pj1-x1041.google.com with SMTP id jw11so439080pjb.0 for ; Tue, 08 Sep 2020 17:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mEMZJyAsz2pya7wCS7q3Y/mkN8EK0RWNbiEA9tVJa2o=; b=hDMoKmOZUUGjVln1k5ny28MW96Qbh1XTQSp25eRLt+a78DImCkAPiJQgIN2hcVVDfv xmcvps+GOLKl1faGvT4WTqnivlv2yBgxbFSmf5rTj1BS5hKosDSI2wn0JyUaQE63yRB9 cw8Ot+FYm1klluQTT31LqBYNdNBbzaRQzJ92Po23qva4Z1VZ5RIRohmn4s2Q7wppnXf7 td7oKvhzO9bq38+AzDJDWFOexMDf1KCaoQQnsmvtMPVilWybzKxKa0AXbD0K7c9k5iha iULI1fhNgAZp9CKyBePgcudI6R0rrDM0/qTzGRpPfc7DKkNgrINFG42w0SGVk0yTPkBs +GXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mEMZJyAsz2pya7wCS7q3Y/mkN8EK0RWNbiEA9tVJa2o=; b=MSlQkxwda2HqwzKkQ87r7FyYQ/WxMCAox2V3870geRrDubRVQOzS6xryXPu54+icKt AT+0HngjIkcSxbKyNXG6Mr4MGUPGHQdXIQiW/Uxp0xBUS9OpRf5Zy0KfRLQtdYIb697Z OK1AM2mC0i6WxpjlEGEgzc4Yo4c+6i1RtuGBkvNrq6IOmdwegX5N0WGKApADBDSY6MvW y2DM7MwIZbm7OhoNo0BVmHlsh0BErDkiRHD2/CfScfOMKzzBh1iBNg/28PkKd75Db7eI axdG7ElfHZoQ4z/FY+vhvlSSVHSPmlOgWtmp9MM8MTGD2n82xDsUVp/+U1UmrIgKGuin Xh3Q== X-Gm-Message-State: AOAM533iYMN5s1N2Y5gyg/xcG67KfCl5TYiXOEJ7kfMenHa5PCHeOeNP Io0KbLam/USAhbMVJ0hBlxB/HpWl616ysg== X-Received: by 2002:a17:90b:715:: with SMTP id s21mr1128445pjz.113.1599610638255; Tue, 08 Sep 2020 17:17:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 23/43] tcg: Use tcg_constant_i32 with icount expander Date: Tue, 8 Sep 2020 17:16:27 -0700 Message-Id: <20200909001647.532249-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must do this before we adjust tcg_out_movi_i32, lest the under-the-hood poking that we do for icount be broken. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 822c43cfd3..404732518a 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -34,7 +34,7 @@ static inline void gen_io_end(void) static inline void gen_tb_start(TranslationBlock *tb) { - TCGv_i32 count, imm; + TCGv_i32 count; tcg_ctx->exitreq_label = gen_new_label(); if (tb_cflags(tb) & CF_USE_ICOUNT) { @@ -48,15 +48,13 @@ static inline void gen_tb_start(TranslationBlock *tb) offsetof(ArchCPU, env)); if (tb_cflags(tb) & CF_USE_ICOUNT) { - imm = tcg_temp_new_i32(); - /* We emit a movi with a dummy immediate argument. Keep the insn index - * of the movi so that we later (when we know the actual insn count) - * can update the immediate argument with the actual insn count. */ - tcg_gen_movi_i32(imm, 0xdeadbeef); + /* + * We emit a sub with a dummy immediate argument. Keep the insn index + * of the sub so that we later (when we know the actual insn count) + * can update the argument with the actual insn count. + */ + tcg_gen_sub_i32(count, count, tcg_constant_i32(0)); icount_start_insn = tcg_last_op(); - - tcg_gen_sub_i32(count, count, imm); - tcg_temp_free_i32(imm); } tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); @@ -74,9 +72,12 @@ static inline void gen_tb_start(TranslationBlock *tb) static inline void gen_tb_end(TranslationBlock *tb, int num_insns) { if (tb_cflags(tb) & CF_USE_ICOUNT) { - /* Update the num_insn immediate parameter now that we know - * the actual insn count. */ - tcg_set_insn_param(icount_start_insn, 1, num_insns); + /* + * Update the num_insn immediate parameter now that we know + * the actual insn count. + */ + tcg_set_insn_param(icount_start_insn, 2, + tcgv_i32_arg(tcg_constant_i32(num_insns))); } gen_set_label(tcg_ctx->exitreq_label); From patchwork Wed Sep 9 00:16:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249396 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5015046ilg; Tue, 8 Sep 2020 17:22:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJynzhwyqTiQBZxkTTGMImLVZWQoEAEksDrrP5A0mdEDkWWDv6SVaOtZr7ABQ8wcUKAEKzn4 X-Received: by 2002:a25:d347:: with SMTP id e68mr2248898ybf.462.1599610928419; Tue, 08 Sep 2020 17:22:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599610928; cv=none; d=google.com; s=arc-20160816; b=kn1sAmTJPnTLJFRrrY/z3HtHz6A3ZO5qHAK6RSpcEU2716+mZGDRV35j1HqdHTLrGM bYlGqAm2AMzTp6IldVLdnNL6bJ2BeBKWTBV1bMOJAD7DAoqnIDiFocxOSd/l30bpSkbs pdIdwVCmPwvY5FN22x2txt3cGzIGACxUHqOAD3qAKTgYzuHk3yTmefgO9aB5rrjJKpRV 6F4PgMWpyFw9yLrvkH82cFQaNiNUrF0+uS6JWU6VStUkBHqiiWjGjRNNt9kxqSTOelDP krc8KJaQBXFS3khxumWt0lOE7zHG65CnNTzu499amXT7vPUwq2RTJENVtBhy1Ej9xYFE hqtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aEQok0/L5FX5jAQIApgNcuA+gqvYfIDMod+uDV+LrZA=; b=nUh70+g4Wz1TvStl4rP9kPEidN9kPrrKi4sFjHxqDLmrQWMAWtuNcqc5xmg2ji9ZIB /0+8+jBHGKEKB80CPjx+tQe87M7bDtNDoLzbsaQK4XjGILKtfUhr7MeBGEIJFYo62U3b gCG8bpJeFMW7pn43u8u5TSOywVSI8ucHHydUx7j+mgMmPZaSpNNpag8FvIvhe5Q2vNE9 PKLYn1xEM+nUDbhKhmcWO899OOvUsir0+MSjvV16g8OdQYWTHo8D2XRRiWIq4SPiSsd8 wS02hc1Affu0hMjtUgThSF43Ph4GXpKq4mF3T+u/lui3CTvtfO5aGbDeZooWx4U2WdV7 37Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="kObbtB/n"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 13 +-- tcg/tcg-op.c | 227 ++++++++++++++++++++----------------------- 2 files changed, 109 insertions(+), 131 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 5abf17fecc..b4fba35e87 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -271,6 +271,7 @@ void tcg_gen_mb(TCGBar); /* 32 bit ops */ +void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -349,11 +350,6 @@ static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) } } -static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) -{ - tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); -} - static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { @@ -467,6 +463,7 @@ static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) /* 64 bit ops */ +void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); @@ -550,11 +547,6 @@ static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) } } -static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) -{ - tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); -} - static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { @@ -698,7 +690,6 @@ static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) void tcg_gen_discard_i64(TCGv_i64 arg); void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 4b8a473fad..e2d8ae3234 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -104,15 +104,18 @@ void tcg_gen_mb(TCGBar mb_type) /* 32 bit ops */ +void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) +{ + tcg_gen_mov_i32(ret, tcg_constant_i32(arg)); +} + void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_add_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_add_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -122,9 +125,7 @@ void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) /* Don't recurse with tcg_gen_neg_i32. */ tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg2); } else { - TCGv_i32 t0 = tcg_const_i32(arg1); - tcg_gen_sub_i32(ret, t0, arg2); - tcg_temp_free_i32(t0); + tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2); } } @@ -134,15 +135,12 @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_sub_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_sub_i32(ret, arg1, tcg_constant_i32(arg2)); } } void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { - TCGv_i32 t0; /* Some cases can be optimized here. */ switch (arg2) { case 0: @@ -165,9 +163,8 @@ void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } break; } - t0 = tcg_const_i32(arg2); - tcg_gen_and_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + + tcg_gen_and_i32(ret, arg1, tcg_constant_i32(arg2)); } void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) @@ -178,9 +175,7 @@ void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_or_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_or_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -193,9 +188,7 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) /* Don't recurse with tcg_gen_not_i32. */ tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_xor_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_xor_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -205,9 +198,7 @@ void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_shl_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_shl_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -217,9 +208,7 @@ void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_shr_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_shr_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -229,9 +218,7 @@ void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_sar_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_sar_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -250,9 +237,7 @@ void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l) if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_brcond_i32(cond, arg1, t0, l); - tcg_temp_free_i32(t0); + tcg_gen_brcond_i32(cond, arg1, tcg_constant_i32(arg2), l); } } @@ -271,9 +256,7 @@ void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_setcond_i32(cond, ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) @@ -283,9 +266,7 @@ void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } else if (is_power_of_2(arg2)) { tcg_gen_shli_i32(ret, arg1, ctz32(arg2)); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_mul_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_mul_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -433,9 +414,7 @@ void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) { - TCGv_i32 t = tcg_const_i32(arg2); - tcg_gen_clz_i32(ret, arg1, t); - tcg_temp_free_i32(t); + tcg_gen_clz_i32(ret, arg1, tcg_constant_i32(arg2)); } void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) @@ -468,10 +447,9 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) tcg_gen_clzi_i32(t, t, 32); tcg_gen_xori_i32(t, t, 31); } - z = tcg_const_i32(0); + z = tcg_constant_i32(0); tcg_gen_movcond_i32(TCG_COND_EQ, ret, arg1, z, arg2, t); tcg_temp_free_i32(t); - tcg_temp_free_i32(z); } else { gen_helper_ctz_i32(ret, arg1, arg2); } @@ -487,9 +465,7 @@ void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) tcg_gen_ctpop_i32(ret, t); tcg_temp_free_i32(t); } else { - TCGv_i32 t = tcg_const_i32(arg2); - tcg_gen_ctz_i32(ret, arg1, t); - tcg_temp_free_i32(t); + tcg_gen_ctz_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -547,9 +523,7 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else if (TCG_TARGET_HAS_rot_i32) { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_rotl_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_rotl_i32(ret, arg1, tcg_constant_i32(arg2)); } else { TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); @@ -653,9 +627,8 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_gen_andi_i32(ret, arg, (1u << len) - 1); } else if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { - TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 zero = tcg_constant_i32(0); tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len); - tcg_temp_free_i32(zero); } else { /* To help two-operand hosts we prefer to zero-extend first, which allows ARG to stay live. */ @@ -1052,7 +1025,7 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) } else { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_const_i32(0x00ff00ff); + TCGv_i32 t2 = tcg_constant_i32(0x00ff00ff); /* arg = abcd */ tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */ @@ -1067,7 +1040,6 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); } } @@ -1114,8 +1086,15 @@ void tcg_gen_discard_i64(TCGv_i64 arg) void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) { - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); + TCGTemp *ts = tcgv_i64_temp(arg); + + /* Canonicalize TCGv_i64 TEMP_CONST into TCGv_i32 TEMP_CONST. */ + if (ts->kind == TEMP_CONST) { + tcg_gen_movi_i64(ret, ts->val); + } else { + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); + } } void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) @@ -1237,6 +1216,14 @@ void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t0); tcg_temp_free_i32(t1); } + +#else + +void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) +{ + tcg_gen_mov_i64(ret, tcg_constant_i64(arg)); +} + #endif /* TCG_TARGET_REG_SIZE == 32 */ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) @@ -1244,10 +1231,12 @@ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); + } else if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2)); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_add_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), + tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32)); } } @@ -1256,10 +1245,12 @@ void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) if (arg1 == 0 && TCG_TARGET_HAS_neg_i64) { /* Don't recurse with tcg_gen_neg_i64. */ tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg2); + } else if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2); } else { - TCGv_i64 t0 = tcg_const_i64(arg1); - tcg_gen_sub_i64(ret, t0, arg2); - tcg_temp_free_i64(t0); + tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), + tcg_constant_i32(arg1), tcg_constant_i32(arg1 >> 32), + TCGV_LOW(arg2), TCGV_HIGH(arg2)); } } @@ -1268,17 +1259,17 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); + } else if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_sub_i64(ret, arg1, tcg_constant_i64(arg2)); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_sub_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), + tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32)); } } void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - TCGv_i64 t0; - if (TCG_TARGET_REG_BITS == 32) { tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); @@ -1313,9 +1304,8 @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } break; } - t0 = tcg_const_i64(arg2); - tcg_gen_and_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + + tcg_gen_and_i64(ret, arg1, tcg_constant_i64(arg2)); } void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) @@ -1331,9 +1321,7 @@ void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_or_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_or_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1351,9 +1339,7 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) /* Don't recurse with tcg_gen_not_i64. */ tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_xor_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_xor_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1415,9 +1401,7 @@ void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_shl_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_shl_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1429,9 +1413,7 @@ void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_shr_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_shr_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1443,9 +1425,7 @@ void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_sar_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_sar_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1468,12 +1448,17 @@ void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l) void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l) { - if (cond == TCG_COND_ALWAYS) { + if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l); + } else if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_brcond_i64(cond, arg1, t0, l); - tcg_temp_free_i64(t0); + l->refs++; + tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, + TCGV_LOW(arg1), TCGV_HIGH(arg1), + tcg_constant_i32(arg2), + tcg_constant_i32(arg2 >> 32), + cond, label_arg(l)); } } @@ -1499,9 +1484,19 @@ void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_setcond_i64(cond, ret, arg1, t0); - tcg_temp_free_i64(t0); + if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_setcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); + } else if (cond == TCG_COND_ALWAYS) { + tcg_gen_movi_i64(ret, 1); + } else if (cond == TCG_COND_NEVER) { + tcg_gen_movi_i64(ret, 0); + } else { + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), + tcg_constant_i32(arg2), + tcg_constant_i32(arg2 >> 32), cond); + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); + } } void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) @@ -1690,7 +1685,7 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) } else { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_const_i64(0x00ff00ff); + TCGv_i64 t2 = tcg_constant_i64(0x00ff00ff); /* arg = ....abcd */ tcg_gen_shri_i64(t0, arg, 8); /* t0 = .....abc */ @@ -1706,7 +1701,6 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } } @@ -1850,16 +1844,16 @@ void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_clz_i32 && arg2 <= 0xffffffffu) { - TCGv_i32 t = tcg_const_i32((uint32_t)arg2 - 32); - tcg_gen_clz_i32(t, TCGV_LOW(arg1), t); + TCGv_i32 t = tcg_temp_new_i32(); + tcg_gen_clzi_i32(t, TCGV_LOW(arg1), arg2 - 32); tcg_gen_addi_i32(t, t, 32); tcg_gen_clz_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), t); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); tcg_temp_free_i32(t); } else { - TCGv_i64 t = tcg_const_i64(arg2); - tcg_gen_clz_i64(ret, arg1, t); - tcg_temp_free_i64(t); + TCGv_i64 t0 = tcg_const_i64(arg2); + tcg_gen_clz_i64(ret, arg1, t0); + tcg_temp_free_i64(t0); } } @@ -1881,7 +1875,7 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) tcg_gen_clzi_i64(t, t, 64); tcg_gen_xori_i64(t, t, 63); } - z = tcg_const_i64(0); + z = tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_EQ, ret, arg1, z, arg2, t); tcg_temp_free_i64(t); tcg_temp_free_i64(z); @@ -1895,8 +1889,8 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_ctz_i32 && arg2 <= 0xffffffffu) { - TCGv_i32 t32 = tcg_const_i32((uint32_t)arg2 - 32); - tcg_gen_ctz_i32(t32, TCGV_HIGH(arg1), t32); + TCGv_i32 t32 = tcg_temp_new_i32(); + tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32); tcg_gen_addi_i32(t32, t32, 32); tcg_gen_ctz_i32(TCGV_LOW(ret), TCGV_LOW(arg1), t32); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); @@ -1911,9 +1905,9 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) tcg_gen_ctpop_i64(ret, t); tcg_temp_free_i64(t); } else { - TCGv_i64 t64 = tcg_const_i64(arg2); - tcg_gen_ctz_i64(ret, arg1, t64); - tcg_temp_free_i64(t64); + TCGv_i64 t0 = tcg_const_i64(arg2); + tcg_gen_ctz_i64(ret, arg1, t0); + tcg_temp_free_i64(t0); } } @@ -1969,9 +1963,7 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else if (TCG_TARGET_HAS_rot_i64) { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_rotl_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_rotl_i64(ret, arg1, tcg_constant_i64(arg2)); } else { TCGv_i64 t0, t1; t0 = tcg_temp_new_i64(); @@ -2089,9 +2081,8 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); } else if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len); - tcg_temp_free_i64(zero); } else { if (TCG_TARGET_REG_BITS == 32) { if (ofs >= 32) { @@ -3102,9 +3093,8 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, #ifdef CONFIG_SOFTMMU { - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(retv, cpu_env, addr, cmpv, newv, oi); - tcg_temp_free_i32(oi); + TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); } #else gen(retv, cpu_env, addr, cmpv, newv); @@ -3147,9 +3137,8 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, #ifdef CONFIG_SOFTMMU { - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop, idx)); - gen(retv, cpu_env, addr, cmpv, newv, oi); - tcg_temp_free_i32(oi); + TCGMemOpIdx oi = make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); } #else gen(retv, cpu_env, addr, cmpv, newv); @@ -3211,9 +3200,8 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, #ifdef CONFIG_SOFTMMU { - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(ret, cpu_env, addr, val, oi); - tcg_temp_free_i32(oi); + TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); } #else gen(ret, cpu_env, addr, val); @@ -3257,9 +3245,8 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, #ifdef CONFIG_SOFTMMU { - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(ret, cpu_env, addr, val, oi); - tcg_temp_free_i32(oi); + TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); } #else gen(ret, cpu_env, addr, val); From patchwork Wed Sep 9 00:16:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249407 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5016339ilg; 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[209.51.188.17]) by mx.google.com with ESMTPS id q126si1272277ybc.245.2020.09.08.17.24.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:24:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xoKMSKGB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnuh-000776-II for patch@linaro.org; Tue, 08 Sep 2020 20:24:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnh-0000Bg-GV for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:25 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:36389) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnne-0002H5-Ed for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:25 -0400 Received: by mail-pg1-x544.google.com with SMTP id m8so742300pgi.3 for ; Tue, 08 Sep 2020 17:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HakP3QzMMgoP+5PWHWKQnZl86G7xrmBYKlGdyeWSyq0=; b=xoKMSKGBBrzkocv2yaAhmwCE0q6iGgV8X8NY+ks19Y4gWDeLEgo+uZa6Hh7UPuU56x 0xdxFFgvlR/vgAe6FRijyA/EmqCmy0VfZ3N937GlSjzsk1FvGK3ZCQFae6bUoqdWWpYM DeDH/OIJ7JCGUARvE9KP9mWADfCwtb+ugNyq5RyE83dwcnhp1R2naNOn3OD8pThk0CXq zD0u1RHqvawY50fVKEGam6o6pDd3la5uj8fUgAz8XxJokdOVQr0N1umBGvqP9xRx+xmO NQSpWyz+0+4IMPmcLIfw9iqjhsgCmDscXZI2x/pn36DWcgj5nICQ8V7mk/eY3Mj8vINA w4ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HakP3QzMMgoP+5PWHWKQnZl86G7xrmBYKlGdyeWSyq0=; b=oblKJoE/efxoUIM2hpRHJaksffXRB0Zo+Ki2cu9z6iMDrKe6nC2e4TMvK7T2lo7XRX +uCBRNZCAvoKvrwO89LQYmagjGdsn+aPzBuFZef/lDCnA0r1OW5DtXVcCd+jvNmBNyQf cEvRzCvHw0LJPztxf5tOwO1RSDD1OIreGLtp/dbmeAnblBF+V18lBX75H6F/8aGfv9bs xs61NGfUC+qxfzjtJ+iJXJwb5uKqGuUoP9H/VRR49L3CZ5ITMnLbw7fcsByLuJTtmpQj NYk2r5hHDo5sEYqmEbtEsBSnaye7FKQOEwlGo0AXRJ0WbPn1Lxncydt+I/TVUI5NECwP Mc8g== X-Gm-Message-State: AOAM531D0khTq6TVOWWc6n1Kp2xhE3pNSoc/BUYoUrrqA3V9D6OtYMdi P6NbBvoiFYoasvO78ezVHuhruDyKV9W0tQ== X-Received: by 2002:a63:413:: with SMTP id 19mr983735pge.310.1599610640740; Tue, 08 Sep 2020 17:17:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 25/43] tcg: Use tcg_constant_{i32,i64} with tcg plugins Date: Tue, 8 Sep 2020 17:16:29 -0700 Message-Id: <20200909001647.532249-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 49 +++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 51580d51a0..e5dc9d0ca9 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -284,8 +284,8 @@ static TCGOp *copy_extu_i32_i64(TCGOp **begin_op, TCGOp *op) if (TCG_TARGET_REG_BITS == 32) { /* mov_i32 */ op = copy_op(begin_op, op, INDEX_op_mov_i32); - /* movi_i32 */ - op = copy_op(begin_op, op, INDEX_op_movi_i32); + /* mov_i32 w/ $0 */ + op = copy_op(begin_op, op, INDEX_op_mov_i32); } else { /* extu_i32_i64 */ op = copy_op(begin_op, op, INDEX_op_extu_i32_i64); @@ -306,39 +306,34 @@ static TCGOp *copy_mov_i64(TCGOp **begin_op, TCGOp *op) return op; } -static TCGOp *copy_movi_i64(TCGOp **begin_op, TCGOp *op, uint64_t v) -{ - if (TCG_TARGET_REG_BITS == 32) { - /* 2x movi_i32 */ - op = copy_op(begin_op, op, INDEX_op_movi_i32); - op->args[1] = v; - - op = copy_op(begin_op, op, INDEX_op_movi_i32); - op->args[1] = v >> 32; - } else { - /* movi_i64 */ - op = copy_op(begin_op, op, INDEX_op_movi_i64); - op->args[1] = v; - } - return op; -} - static TCGOp *copy_const_ptr(TCGOp **begin_op, TCGOp *op, void *ptr) { if (UINTPTR_MAX == UINT32_MAX) { - /* movi_i32 */ - op = copy_op(begin_op, op, INDEX_op_movi_i32); - op->args[1] = (uintptr_t)ptr; + /* mov_i32 */ + op = copy_op(begin_op, op, INDEX_op_mov_i32); + op->args[1] = tcgv_i32_arg(tcg_constant_i32((uintptr_t)ptr)); } else { - /* movi_i64 */ - op = copy_movi_i64(begin_op, op, (uint64_t)(uintptr_t)ptr); + /* mov_i64 */ + op = copy_op(begin_op, op, INDEX_op_mov_i64); + op->args[1] = tcgv_i64_arg(tcg_constant_i64((uintptr_t)ptr)); } return op; } static TCGOp *copy_const_i64(TCGOp **begin_op, TCGOp *op, uint64_t v) { - return copy_movi_i64(begin_op, op, v); + if (TCG_TARGET_REG_BITS == 32) { + /* 2x mov_i32 */ + op = copy_op(begin_op, op, INDEX_op_mov_i32); + op->args[1] = tcgv_i32_arg(tcg_constant_i32(v)); + op = copy_op(begin_op, op, INDEX_op_mov_i32); + op->args[1] = tcgv_i32_arg(tcg_constant_i32(v >> 32)); + } else { + /* mov_i64 */ + op = copy_op(begin_op, op, INDEX_op_mov_i64); + op->args[1] = tcgv_i64_arg(tcg_constant_i64(v)); + } + return op; } static TCGOp *copy_extu_tl_i64(TCGOp **begin_op, TCGOp *op) @@ -486,8 +481,8 @@ static TCGOp *append_mem_cb(const struct qemu_plugin_dyn_cb *cb, tcg_debug_assert(type == PLUGIN_GEN_CB_MEM); - /* const_i32 == movi_i32 ("info", so it remains as is) */ - op = copy_op(&begin_op, op, INDEX_op_movi_i32); + /* const_i32 == mov_i32 ("info", so it remains as is) */ + op = copy_op(&begin_op, op, INDEX_op_mov_i32); /* const_ptr */ op = copy_const_ptr(&begin_op, op, cb->userp); From patchwork Wed Sep 9 00:16:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249410 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5016824ilg; Tue, 8 Sep 2020 17:25:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyDOmI958GCITNHu6DcMQdRoQlsJoX+lMbMaV6tZLc2/RqKmwzN6q4wGXtZn195R8M2xQSj X-Received: by 2002:a25:c2c7:: with SMTP id s190mr2186635ybf.161.1599611136335; Tue, 08 Sep 2020 17:25:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611136; cv=none; d=google.com; s=arc-20160816; b=qRBHar1IdZp/jzakjVkGC488fiuxR4ccQ2j6kb0chahJQ06O0cj5aVDnMbIpblwITA qGDbpMuLkIui9yPmGqCZ8O+3uUEEgtMulk5cBV7tlHziFRuTveZJgLaU+fP10zQsg51u vx/NbFiqvPYeerQfibwK4CA0md1XveyhlwfcFbONzh4qbPpkZ5cBH3yuLXVGKw+n7YC1 JOfLyIjXj1p4vAWev1Fw5lIZR0ms80ZhNLvQve+7ri12xGdmg1+oGtwAzRi8EMo1EHQX HCyV5xniPDqXEK3Y1FIsq6J0vx/Q5ucX4Z6KPNWb82WQw0mt4HfsAv22Pk0mVCCuOy6e ygbA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id w67si901281ybc.303.2020.09.08.17.25.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:25:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GKMbpIoX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnvb-00024i-Ld for patch@linaro.org; Tue, 08 Sep 2020 20:25:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnni-0000Es-M7 for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:26 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:42160) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnf-0002HQ-OH for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:26 -0400 Received: by mail-pf1-x442.google.com with SMTP id d6so545294pfn.9 for ; Tue, 08 Sep 2020 17:17:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=y5irF3zqN04rzNfXKfW0upIicpgvBlypjvXV8hRJtkM=; b=GKMbpIoXHXNi8Fd6F7Px4I7XGXG/X6wAMFFIuo8l/pi4g0FKNsFmQ8hPMOY5gNFq/Z DenQJEqqHBmUf9xmHFoB9yBxLddMdkhn3l2uD4TUq2hnmR38qm3Fnuy+K5N276FstmFD iVruyd3Df1DEvWWPw1DvkU2/0Kem0Ov6Av1dQg9T5cfni6UMXwvzu6O5yo68qjKTEP0N tDpRPO5H7YF2Y5scE32Z1CtNAdjfRVt/YJOY24gOP1PAj84TVHQw6OUPVJgJ8pHx16MK +ZPWjZjdnrU4aHaRyhoQyj95Q6LYSAAtk4e0MpXrRTz/vwwZm4IVw4TGEmuIjvpWh5ea vatA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y5irF3zqN04rzNfXKfW0upIicpgvBlypjvXV8hRJtkM=; b=BtWMdfrX/fGHtHKnCiKqa/e6egAbTWgxrbHR7Sj48yAKQTL4Ja9XtTv5pqSqp9Z2R4 0UXoYSb7W9BpbWMxPgpGzvh3OrDSjel4EhZe3+xTqhQzbg9BLoV4lLbPNHm4vdPeu/xw LK4xh9S16V/N8+SLrsPZCDD75r8ZZLdQfz7jr3EVVBLn6iFWweV2aBjdtsLrew8YXc1e zqnRoq1tXgsQE1D/jVO5gmzlMuQGbCW/pxSSQktwq+SUIjfjCPCCVl2fllmrsFHiHhOT 2IQBOt0wXqRMCe+OVXjtDpQBzM2i+Yj8u2KE8JVEDcA5DOdh/3wAkV3nqXakELK+4CBy WRrQ== X-Gm-Message-State: AOAM5316nRJCD0SBZAtvjzhaE8PoV/e59kbDYJ0D0tBelqqF8IBqOiLu onMxcXJvu8lQGqFKj4O7MlYHwgyjCwtStQ== X-Received: by 2002:a65:64cc:: with SMTP id t12mr1008704pgv.106.1599610641777; Tue, 08 Sep 2020 17:17:21 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 26/43] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders Date: Tue, 8 Sep 2020 17:16:30 -0700 Message-Id: <20200909001647.532249-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + tcg/tcg-op-gvec.c | 125 ++++++++++++++++++---------------------------- tcg/tcg.c | 8 +++ 3 files changed, 58 insertions(+), 76 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index aa7b0ba163..309460704a 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1081,6 +1081,7 @@ static inline TCGv_i64 tcg_constant_i64(int64_t val) } TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); +TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); #if UINTPTR_MAX == UINT32_MAX # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index ddbe06b71a..80eb53c770 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -115,7 +115,7 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, gen_helper_gvec_2 *fn) { TCGv_ptr a0, a1; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -127,7 +127,6 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with two vector operands @@ -137,7 +136,7 @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, gen_helper_gvec_2i *fn) { TCGv_ptr a0, a1; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -149,7 +148,6 @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with three vector operands. */ @@ -158,7 +156,7 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, gen_helper_gvec_3 *fn) { TCGv_ptr a0, a1, a2; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -173,7 +171,6 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); tcg_temp_free_ptr(a2); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with four vector operands. */ @@ -182,7 +179,7 @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, int32_t data, gen_helper_gvec_4 *fn) { TCGv_ptr a0, a1, a2, a3; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -200,7 +197,6 @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a1); tcg_temp_free_ptr(a2); tcg_temp_free_ptr(a3); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with five vector operands. */ @@ -209,7 +205,7 @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn) { TCGv_ptr a0, a1, a2, a3, a4; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -230,7 +226,6 @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a2); tcg_temp_free_ptr(a3); tcg_temp_free_ptr(a4); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with three vector operands @@ -240,7 +235,7 @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, int32_t data, gen_helper_gvec_2_ptr *fn) { TCGv_ptr a0, a1; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -252,7 +247,6 @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with three vector operands @@ -262,7 +256,7 @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, int32_t data, gen_helper_gvec_3_ptr *fn) { TCGv_ptr a0, a1, a2; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -277,7 +271,6 @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); tcg_temp_free_ptr(a2); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with four vector operands @@ -288,7 +281,7 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, gen_helper_gvec_4_ptr *fn) { TCGv_ptr a0, a1, a2, a3; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -306,7 +299,6 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a1); tcg_temp_free_ptr(a2); tcg_temp_free_ptr(a3); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with five vector operands @@ -317,7 +309,7 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, gen_helper_gvec_5_ptr *fn) { TCGv_ptr a0, a1, a2, a3, a4; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -338,7 +330,6 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a2); tcg_temp_free_ptr(a3); tcg_temp_free_ptr(a4); - tcg_temp_free_i32(desc); } /* Return true if we want to implement something of OPRSZ bytes @@ -602,9 +593,9 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, || (TCG_TARGET_REG_BITS == 64 && (in_c == 0 || in_c == -1 || !check_size_impl(oprsz, 4)))) { - t_64 = tcg_const_i64(in_c); + t_64 = tcg_constant_i64(in_c); } else { - t_32 = tcg_const_i32(in_c); + t_32 = tcg_constant_i32(in_c); } } @@ -628,15 +619,14 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, /* Otherwise implement out of line. */ t_ptr = tcg_temp_new_ptr(); tcg_gen_addi_ptr(t_ptr, cpu_env, dofs); - t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0)); + t_desc = tcg_constant_i32(simd_desc(oprsz, maxsz, 0)); if (vece == MO_64) { if (in_64) { gen_helper_gvec_dup64(t_ptr, t_desc, in_64); } else { - t_64 = tcg_const_i64(in_c); + t_64 = tcg_constant_i64(in_c); gen_helper_gvec_dup64(t_ptr, t_desc, t_64); - tcg_temp_free_i64(t_64); } } else { typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32); @@ -648,24 +638,23 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, if (in_32) { fns[vece](t_ptr, t_desc, in_32); - } else { + } else if (in_64) { t_32 = tcg_temp_new_i32(); - if (in_64) { - tcg_gen_extrl_i64_i32(t_32, in_64); - } else if (vece == MO_8) { - tcg_gen_movi_i32(t_32, in_c & 0xff); - } else if (vece == MO_16) { - tcg_gen_movi_i32(t_32, in_c & 0xffff); - } else { - tcg_gen_movi_i32(t_32, in_c); - } + tcg_gen_extrl_i64_i32(t_32, in_64); fns[vece](t_ptr, t_desc, t_32); tcg_temp_free_i32(t_32); + } else { + if (vece == MO_8) { + in_c &= 0xff; + } else if (vece == MO_16) { + in_c &= 0xffff; + } + t_32 = tcg_constant_i32(in_c); + fns[vece](t_ptr, t_desc, t_32); } } tcg_temp_free_ptr(t_ptr); - tcg_temp_free_i32(t_desc); return; done: @@ -1215,10 +1204,9 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, if (g->fno) { tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno); } else { - TCGv_i64 tcg_c = tcg_const_i64(c); + TCGv_i64 tcg_c = tcg_constant_i64(c); tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz, maxsz, c, g->fnoi); - tcg_temp_free_i64(tcg_c); } oprsz = maxsz; } @@ -1712,16 +1700,14 @@ static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); gen_addv_mask(d, a, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); gen_addv_mask(d, a, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1805,9 +1791,8 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(c); + TCGv_i64 tmp = tcg_constant_i64(c); tcg_gen_gvec_adds(vece, dofs, aofs, tmp, oprsz, maxsz); - tcg_temp_free_i64(tmp); } static const TCGOpcode vecop_list_sub[] = { INDEX_op_sub_vec, 0 }; @@ -1865,16 +1850,14 @@ static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); gen_subv_mask(d, a, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); gen_subv_mask(d, a, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1985,9 +1968,8 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(c); + TCGv_i64 tmp = tcg_constant_i64(c); tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz); - tcg_temp_free_i64(tmp); } void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -2044,18 +2026,16 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { - TCGv_i32 max = tcg_const_i32(-1); + TCGv_i32 max = tcg_constant_i32(-1); tcg_gen_add_i32(d, a, b); tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d); - tcg_temp_free_i32(max); } static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 max = tcg_const_i64(-1); + TCGv_i64 max = tcg_constant_i64(-1); tcg_gen_add_i64(d, a, b); tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d); - tcg_temp_free_i64(max); } void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -2088,18 +2068,16 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { - TCGv_i32 min = tcg_const_i32(0); + TCGv_i32 min = tcg_constant_i32(0); tcg_gen_sub_i32(d, a, b); tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); - tcg_temp_free_i32(min); } static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 min = tcg_const_i64(0); + TCGv_i64 min = tcg_constant_i64(0); tcg_gen_sub_i64(d, a, b); tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d); - tcg_temp_free_i64(min); } void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -2260,16 +2238,14 @@ static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m) void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); gen_negv_mask(d, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); gen_negv_mask(d, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b) @@ -2538,9 +2514,8 @@ void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c)); + TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); - tcg_temp_free_i64(tmp); } static const GVecGen2s gop_xors = { @@ -2563,9 +2538,8 @@ void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c)); + TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors); - tcg_temp_free_i64(tmp); } static const GVecGen2s gop_ors = { @@ -2588,9 +2562,8 @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c)); + TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors); - tcg_temp_free_i64(tmp); } void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) @@ -3078,9 +3051,9 @@ static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_shlv_vec(vece, d, a, t); tcg_temp_free_vec(t); } @@ -3141,9 +3114,9 @@ static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_shrv_vec(vece, d, a, t); tcg_temp_free_vec(t); } @@ -3204,9 +3177,9 @@ static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_sarv_vec(vece, d, a, t); tcg_temp_free_vec(t); } @@ -3267,9 +3240,9 @@ static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_rotlv_vec(vece, d, a, t); tcg_temp_free_vec(t); } @@ -3326,9 +3299,9 @@ static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_rotrv_vec(vece, d, a, t); tcg_temp_free_vec(t); } diff --git a/tcg/tcg.c b/tcg/tcg.c index 0ce45fd123..b63da0b603 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1416,6 +1416,14 @@ TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) return temp_tcgv_vec(tcg_constant_internal(type, val)); } +TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val) +{ + TCGTemp *t = tcgv_vec_temp(match); + + tcg_debug_assert(t->temp_allocated != 0); + return tcg_constant_vec(t->base_type, vece, val); +} + TCGv_i32 tcg_const_i32(int32_t val) { TCGv_i32 t0; From patchwork Wed Sep 9 00:16:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249413 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5017460ilg; Tue, 8 Sep 2020 17:26:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxlAOd6N3QDdCzokOIu7CiF/aEO3KsT+hc+1KLwaYZN97wHSGpYpNYDc7p1l57aSQEvJRtp X-Received: by 2002:a25:660a:: with SMTP id a10mr2078257ybc.327.1599611212120; Tue, 08 Sep 2020 17:26:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611212; cv=none; d=google.com; s=arc-20160816; b=OnIVBypD4dx9JMsxx3y7NQPA2/Co3wsbsvAHqK2+BI5GywU9smw+fcdhfIRQP/3iPC g3mkVGy05x81m8kbUTgOV2CC1FWtL+cweG2NeY1zJg2lEMQZCiyVkrVVmunR3M1nPdN4 tFAfDc8UVBKicifkaqw1zelqakoQO3MFR69jDbL2DPQzyI7TSSaeNIxVEN6L1KIOhcOy dcCPPcHEnu/UVBRUPgjmRdSJl/Vj8MpJ5xPDKoYMAUagWVqT3YTepgE3SAS3AYMs8kLq hbUCxoxTwP2KGDm+/tj5rxdnf8RgFyga9wTZyZE4QToqVSucGR7EtwSqM6OyBfE01HWP LQUQ== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id y5si965308ybk.174.2020.09.08.17.26.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:26:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ae6bfskK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnwp-0005Cp-J1 for patch@linaro.org; Tue, 08 Sep 2020 20:26:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnj-0000GI-92 for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:27 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:41718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnh-0002Ho-9T for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:26 -0400 Received: by mail-pf1-x442.google.com with SMTP id z19so549531pfn.8 for ; Tue, 08 Sep 2020 17:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tgLoS46T1HySALWu2osFoRUIKmh8CryJe2qEASNX6h0=; b=Ae6bfskK8CTck2/VLO4ujMWf/b6tNFlk2D0//KMpInnVPX33FPH/HrAG53VFxOFVhI 2xCFsBGbDGhhVwyFtbCi1XzuNryfQ349/nbrrUpT0oZEitDgzXDWI+49I1iPIzOMnCFq bD2lrqrOmbnwD1ikxPVAm9syaETdxe5RySsdh2NVYmj/EorHKyvnrn36MlRdOcZnPVuG +VijV250hDZt2XbxXnRuJKA4/NfD7tDmf7QKfvDqo+ORR4LjOF5yzfzeWlIyCBD6+hlr KRp+Dg2jVexq7r2dTnMafoCD0cUDtOXXpn/a9lqEglKTYqeWGIEbV6FSYFeYup8KJJq5 c0NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tgLoS46T1HySALWu2osFoRUIKmh8CryJe2qEASNX6h0=; b=f0lMG2hFsjNEh77xfpeabENY9aNHo6XiNH1/abqIH7EMp+mQyH9G8x1WuePALTxa3P Zh3mF0Md/GSie4jFEHYRNLB6amY6tVyI0A4LbY0/0hp/UkXhA4SMiPLbsxdGlEkwoYM+ wKvkd2F7lyyYWPmARDMvwylkGMifL9ug5SfBwSMdJrNftmwL7tF6t1N7U8zMlQDapwxA gtMKm+pr+VtKOa5FjENu0jCNd9Lsqhu6W4PaLDygROkzexYZH0VgJeaG8A3WMAe0syLA pJUPem5/BF+NGIDql1BI8nqKc8YRU1KOGd3XuPmaqRgoowGhGM3ZWgK8ORkUvNZy9R6l TGRw== X-Gm-Message-State: AOAM532StWu5T1mhjl/KmHP9faZZO5Kwl43+uVF4+jkZNs+Wf/2cNH5u khYniAjyJxh6QDGA4SxvaW1+gYBoMsm70g== X-Received: by 2002:a63:4902:: with SMTP id w2mr953967pga.311.1599610643634; Tue, 08 Sep 2020 17:17:23 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 27/43] tcg/tci: Add special tci_movi_{i32,i64} opcodes Date: Tue, 8 Sep 2020 17:16:31 -0700 Message-Id: <20200909001647.532249-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The normal movi opcodes are going away. We need something for TCI to use internally. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 8 ++++++++ tcg/tci.c | 4 ++-- tcg/tci/tcg-target.c.inc | 4 ++-- 3 files changed, 12 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index e3929b80d2..5a941eaa07 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -272,6 +272,14 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #include "tcg-target.opc.h" #endif +#ifdef TCG_TARGET_INTERPRETER +/* These opcodes are only for use between the tci generator and interpreter. */ +DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) +#if TCG_TARGET_REG_BITS == 64 +DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) +#endif +#endif + #undef TLADDR_ARGS #undef DATA64_ARGS #undef IMPL diff --git a/tcg/tci.c b/tcg/tci.c index 46fe9ce63f..a6c1aaf5af 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -576,7 +576,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t1 = tci_read_r32(regs, &tb_ptr); tci_write_reg32(regs, t0, t1); break; - case INDEX_op_movi_i32: + case INDEX_op_tci_movi_i32: t0 = *tb_ptr++; t1 = tci_read_i32(&tb_ptr); tci_write_reg32(regs, t0, t1); @@ -847,7 +847,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t1 = tci_read_r64(regs, &tb_ptr); tci_write_reg64(regs, t0, t1); break; - case INDEX_op_movi_i64: + case INDEX_op_tci_movi_i64: t0 = *tb_ptr++; t1 = tci_read_i64(&tb_ptr); tci_write_reg64(regs, t0, t1); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 231b9b1775..c8c8386a72 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -529,13 +529,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, uint8_t *old_code_ptr = s->code_ptr; uint32_t arg32 = arg; if (type == TCG_TYPE_I32 || arg == arg32) { - tcg_out_op_t(s, INDEX_op_movi_i32); + tcg_out_op_t(s, INDEX_op_tci_movi_i32); tcg_out_r(s, t0); tcg_out32(s, arg32); } else { tcg_debug_assert(type == TCG_TYPE_I64); #if TCG_TARGET_REG_BITS == 64 - tcg_out_op_t(s, INDEX_op_movi_i64); + tcg_out_op_t(s, INDEX_op_tci_movi_i64); tcg_out_r(s, t0); tcg_out64(s, arg); #else From patchwork Wed Sep 9 00:16:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249403 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5015714ilg; Tue, 8 Sep 2020 17:23:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgc6jqB6n2XmzJZPJgf7+utE+nLMTnYspmgYiLNmmNCbXhvIgvQjhZxztMAE7++/zlleqe X-Received: by 2002:a25:19d5:: with SMTP id 204mr2242826ybz.48.1599611007446; Tue, 08 Sep 2020 17:23:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611007; cv=none; d=google.com; s=arc-20160816; b=nX8wBtYI+Xvy2mmndaIkKX1mYdi8ssfOE0cSGbYQzsjeRRM7LYIuS9+iSVkdn+VJ7F GgTSYPWgELEJ5ghPgXjtGN3nqklNtan1om7JAxlM5Sn6NJ9Vg332F4H8bHmi9YocCdhO GK9wB+6mMwEzuVompF0J5QXQCi1g+bAUQzZnMep4W/GD7VK5jDKSQjTJpUWgS7Vt7WfC VnSG/bhZdo4W+pTHbYCSEzcmZCqc1K/0q2QWONNVS1dRxxj5zA1US5ky0pnUX8xCBi5s wKvv/QPd1r4uV9x6pqo/f4i+TduX7Y1VoiKjZYVXWwfvLYYOmv35r3EMJAziSmZIgaAS UrQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bN4BQE3WpGmWjjSI/j/g7Y1hlfWuKsaOhnClW7UwbZc=; b=YtGKNmM6kJkua7eRTvafLTXocIWqDa7lMYTGgpgSvmi1iO5WevvFuEMnGlB8JJs13O 4l+sNjSQnaqjbQT41CWTBS3By1XIlWY2sX1Hj5M+evEI+4dTrqM2i6ZwWlhIuXt7ilDq 4UnsAOQ3lxDpxO99G0vX4qG9u2Vs5c2SvmPgYSXdprBCTx/oKHn1fOF0NJ0G9cgqOvUN O0MUuHnkgdsiRK++8sQjTzAQF97hI9wn5SO5GZu7tNMedbrxVHzNjfqw4vZ/7Ti2lWsh I2Oju2cWHN0wRRdeqhaBqlonpRBFszzxWynGSto1I8rTKMM1AfMt6iR2M+aIYL59+EIz CEgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yGgEsYYv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Markovic , =?utf-8?q?Alex_?= =?utf-8?q?Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are now completely covered by mov from a TYPE_CONST temporary. Reviewed-by: Alex Bennée Reviewed-by: Aleksandar Markovic Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 --- tcg/optimize.c | 4 ---- tcg/tcg-op-vec.c | 1 - tcg/tcg.c | 18 +----------------- tcg/aarch64/tcg-target.c.inc | 3 --- tcg/arm/tcg-target.c.inc | 1 - tcg/i386/tcg-target.c.inc | 3 --- tcg/mips/tcg-target.c.inc | 2 -- tcg/ppc/tcg-target.c.inc | 3 --- tcg/riscv/tcg-target.c.inc | 2 -- tcg/s390/tcg-target.c.inc | 2 -- tcg/sparc/tcg-target.c.inc | 2 -- tcg/tci/tcg-target.c.inc | 2 -- 13 files changed, 1 insertion(+), 45 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 5a941eaa07..d63c6bcb3d 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -45,7 +45,6 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) DEF(mb, 0, 0, 1, 0) DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) -DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) /* load/store */ @@ -110,7 +109,6 @@ DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32)) DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) -DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) DEF(setcond_i64, 1, 2, 1, IMPL64) DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) /* load/store */ @@ -215,7 +213,6 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) -DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) DEF(dup_vec, 1, 1, 0, IMPLVEC) DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) diff --git a/tcg/optimize.c b/tcg/optimize.c index af07c6f628..1a94e9a41b 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1099,10 +1099,6 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(mov): tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); break; - CASE_OP_32_64(movi): - case INDEX_op_dupi_vec: - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], op->args[1]); - break; case INDEX_op_dup_vec: if (arg_is_const(op->args[1])) { diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 9fbed1366c..ce0d2f6e0e 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -83,7 +83,6 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_xor_vec: case INDEX_op_mov_vec: case INDEX_op_dup_vec: - case INDEX_op_dupi_vec: case INDEX_op_dup2_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: diff --git a/tcg/tcg.c b/tcg/tcg.c index b63da0b603..f9c6450837 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1503,7 +1503,6 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_HAS_goto_ptr; case INDEX_op_mov_i32: - case INDEX_op_movi_i32: case INDEX_op_setcond_i32: case INDEX_op_brcond_i32: case INDEX_op_ld8u_i32: @@ -1597,7 +1596,6 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_REG_BITS == 32; case INDEX_op_mov_i64: - case INDEX_op_movi_i64: case INDEX_op_setcond_i64: case INDEX_op_brcond_i64: case INDEX_op_ld8u_i64: @@ -1703,7 +1701,6 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_mov_vec: case INDEX_op_dup_vec: - case INDEX_op_dupi_vec: case INDEX_op_dupm_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: @@ -3542,7 +3539,7 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) } /* - * Specialized code generation for INDEX_op_movi_*. + * Specialized code generation for INDEX_op_mov_* with a constant. */ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, tcg_target_ulong val, TCGLifeData arg_life, @@ -3565,14 +3562,6 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, } } -static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) -{ - TCGTemp *ots = arg_temp(op->args[0]); - tcg_target_ulong val = op->args[1]; - - tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]); -} - /* * Specialized code generation for INDEX_op_mov_*. */ @@ -4353,11 +4342,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) case INDEX_op_mov_vec: tcg_reg_alloc_mov(s, op); break; - case INDEX_op_movi_i32: - case INDEX_op_movi_i64: - case INDEX_op_dupi_vec: - tcg_reg_alloc_movi(s, op); - break; case INDEX_op_dup_vec: tcg_reg_alloc_dup(s, op); break; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 5692607087..fdc118391c 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2252,8 +2252,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: g_assert_not_reached(); @@ -2461,7 +2459,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 62c37a954b..30d30874c7 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2065,7 +2065,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6b7cbaa47a..819ee25cff 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2692,8 +2692,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); @@ -2979,7 +2977,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 98c6a41caf..3e282c1bde 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2152,8 +2152,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index ff56f1971f..3d23a6b226 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2973,8 +2973,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); @@ -3322,7 +3320,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, return; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d536f3ccc1..aaef1c5eed 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1602,8 +1602,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: g_assert_not_reached(); diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index c5e096449b..824a07aa7a 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2306,8 +2306,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 44373d742b..af480115c5 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1586,8 +1586,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c8c8386a72..25ed868505 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -814,8 +814,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson --- tcg/tcg.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index f9c6450837..507c95cd39 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3954,6 +3954,100 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } } +static void tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) +{ + const TCGLifeData arg_life = op->life; + TCGTemp *ots, *itsl, *itsh; + TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64; + + /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ + tcg_debug_assert(TCG_TARGET_REG_BITS == 32); + tcg_debug_assert(TCGOP_VECE(op) == MO_64); + + ots = arg_temp(op->args[0]); + itsl = arg_temp(op->args[1]); + itsh = arg_temp(op->args[2]); + + /* ENV should not be modified. */ + tcg_debug_assert(!temp_readonly(ots)); + + /* Allocate the output register now. */ + if (ots->val_type != TEMP_VAL_REG) { + TCGRegSet allocated_regs = s->reserved_regs; + TCGRegSet dup_out_regs = + tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; + + /* Make sure to not spill the input registers. */ + if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) { + tcg_regset_set_reg(allocated_regs, itsl->reg); + } + if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) { + tcg_regset_set_reg(allocated_regs, itsh->reg); + } + + ots->reg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, + op->output_pref[0], ots->indirect_base); + ots->val_type = TEMP_VAL_REG; + ots->mem_coherent = 0; + s->reg_to_temp[ots->reg] = ots; + } + + /* Promote dup2 of immediates to dupi_vec. */ + if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) { + uint64_t val = deposit64(itsl->val, 32, 32, itsh->val); + MemOp vece = MO_64; + + if (val == dup_const(MO_8, val)) { + vece = MO_8; + } else if (val == dup_const(MO_16, val)) { + vece = MO_16; + } else if (val == dup_const(MO_32, val)) { + vece = MO_32; + } + + tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); + goto done; + } + + /* If the two inputs form one 64-bit value, try dupm_vec. */ + if (itsl + 1 == itsh && + itsl->base_type == TCG_TYPE_I64 && + itsh->base_type == TCG_TYPE_I64) { + if (!itsl->mem_coherent) { + temp_sync(s, itsl, s->reserved_regs, 0, 0); + } + if (!itsl->mem_coherent) { + temp_sync(s, itsl, s->reserved_regs, 0, 0); + } +#ifdef HOST_WORDS_BIGENDIAN + TCGTemp *its = itsh; +#else + TCGTemp *its = itsl; +#endif + if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, + its->mem_base->reg, its->mem_offset)) { + goto done; + } + } + + /* Fall back to generic expansion. */ + tcg_reg_alloc_op(s, op); + return; + + done: + if (IS_DEAD_ARG(1)) { + temp_dead(s, itsl); + } + if (IS_DEAD_ARG(2)) { + temp_dead(s, itsh); + } + if (NEED_SYNC_ARG(0)) { + temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); + } else if (IS_DEAD_ARG(0)) { + temp_dead(s, ots); + } +} + #ifdef TCG_TARGET_STACK_GROWSUP #define STACK_DIR(x) (-(x)) #else @@ -4345,6 +4439,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) case INDEX_op_dup_vec: tcg_reg_alloc_dup(s, op); break; + case INDEX_op_dup2_vec: + tcg_reg_alloc_dup2(s, op); + break; case INDEX_op_insn_start: if (num_insns >= 0) { size_t off = tcg_current_code_size(s); From patchwork Wed Sep 9 00:16:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249420 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5018754ilg; Tue, 8 Sep 2020 17:29:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyMYwP6QS1Mw/9ahzOYxrwpYRWf6El5NySP5Yn/fJKiIVgeBOEGv+YRMxHS0OFKqtPu7vyR X-Received: by 2002:a25:d0c8:: with SMTP id h191mr2144992ybg.368.1599611369788; Tue, 08 Sep 2020 17:29:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611369; cv=none; d=google.com; s=arc-20160816; b=r9Crivxgl8R/74arEmMf9INnqrrG5WXkV9MR3dLH1DtKuZV6YsVtvJwueHVpFi9Nso L9vjCbgLen8lFhjoKstk3xKycge3lDPnGGmbXa+Vor0xCl0wa9Iq2082JRDn1xYzDrT6 zqNF8HNEVEEQ+IJ4OkdStWZLBnRLsmUDoIBdUJ9zmqkHCBzeeQCjOrh4eMOUO7QuaGEH T1ONzDczPgen98ol1bcRxcMZlW3OlmOq3O5bAbFT4vE284takWtXg9wk0AFS2pLkQkqh mn67XbYtC+32jVRRr+BTmKCm8DxamoQ1+f2CMqtSFNKQjKxuJsTI3cqakizj2aqirdFW YRsQ== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 819ee25cff..36a90e7ef3 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3508,7 +3508,7 @@ static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) { - TCGv_vec t1, t2, t3, t4; + TCGv_vec t1, t2, t3, t4, zero; tcg_debug_assert(vece == MO_8); @@ -3526,11 +3526,11 @@ static void expand_vec_mul(TCGType type, unsigned vece, case TCG_TYPE_V64: t1 = tcg_temp_new_vec(TCG_TYPE_V128); t2 = tcg_temp_new_vec(TCG_TYPE_V128); - tcg_gen_dup16i_vec(t2, 0); + zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2)); + tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); tcg_gen_mul_vec(MO_16, t1, t1, t2); tcg_gen_shri_vec(MO_16, t1, t1, 8); vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, @@ -3545,15 +3545,15 @@ static void expand_vec_mul(TCGType type, unsigned vece, t2 = tcg_temp_new_vec(type); t3 = tcg_temp_new_vec(type); t4 = tcg_temp_new_vec(type); - tcg_gen_dup16i_vec(t4, 0); + zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); + tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); + tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); + tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); tcg_gen_mul_vec(MO_16, t1, t1, t2); tcg_gen_mul_vec(MO_16, t3, t3, t4); tcg_gen_shri_vec(MO_16, t1, t1, 8); @@ -3581,7 +3581,7 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, NEED_UMIN = 8, NEED_UMAX = 16, }; - TCGv_vec t1, t2; + TCGv_vec t1, t2, t3; uint8_t fixup; switch (cond) { @@ -3652,9 +3652,9 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, } else if (fixup & NEED_BIAS) { t1 = tcg_temp_new_vec(type); t2 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1)); - tcg_gen_sub_vec(vece, t1, v1, t2); - tcg_gen_sub_vec(vece, t2, v2, t2); + t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1)); + tcg_gen_sub_vec(vece, t1, v1, t3); + tcg_gen_sub_vec(vece, t2, v2, t3); v1 = t1; v2 = t2; cond = tcg_signed_cond(cond); From patchwork Wed Sep 9 00:16:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249423 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5019667ilg; Tue, 8 Sep 2020 17:31:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJRPqM9U5tylAMf3g5FIr+G5Ar/ohCvNlykMjHkk2MPWbZrynaIDJjMQ0sAGf9vgBvLTkL X-Received: by 2002:a25:ec11:: with SMTP id j17mr2116429ybh.509.1599611464639; Tue, 08 Sep 2020 17:31:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611464; cv=none; d=google.com; s=arc-20160816; b=h2SOkYrqaltCwdWZxmncL7G0I8zzSzCXv/XuhsKxzRwrtMtQWfX+8sOO7T7i/rjHyf Bri7aHehpMi/Cy21DSe13N4s7ZjJODP2FmTPlD2dXPO4+utewJpHw4z2CovJsBFwKVpa MfGFI2+6Pe5exJU3qQF06Xt+suqfOO6CHwp6Ha6WWH4ga6AaoywkXnKgTIt2ErBne2P8 37nYhDifzePh+RSswRhybg2qHlYQGZocdhUqaO0j696xURbCU0zUPW2nsiTYaXo/nDd8 eWh97gEVgVYon0w39RucK8l5jkqz0Kluef44nTmx0PBbcK02gtao/5Kt2wl0nK6SSSa+ YX1g== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These interfaces have been replaced by tcg_gen_dupi_vec and tcg_constant_vec. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 ---- tcg/tcg-op-vec.c | 20 -------------------- 2 files changed, 24 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index b4fba35e87..d0319692ec 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -959,10 +959,6 @@ void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long); -void tcg_gen_dup8i_vec(TCGv_vec, uint32_t); -void tcg_gen_dup16i_vec(TCGv_vec, uint32_t); -void tcg_gen_dup32i_vec(TCGv_vec, uint32_t); -void tcg_gen_dup64i_vec(TCGv_vec, uint64_t); void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index ce0d2f6e0e..d19aa7373e 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -241,26 +241,6 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m) return tcg_const_ones_vec(t->base_type); } -void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a) -{ - tcg_gen_dupi_vec(MO_64, r, a); -} - -void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a) -{ - tcg_gen_dupi_vec(MO_32, r, a); -} - -void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a) -{ - tcg_gen_dupi_vec(MO_16, r, a); -} - -void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a) -{ - tcg_gen_dupi_vec(MO_8, r, a); -} - void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a) { TCGTemp *rt = tcgv_vec_temp(r); From patchwork Wed Sep 9 00:16:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249417 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5018146ilg; Tue, 8 Sep 2020 17:28:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyMnUqTsnOZXXTYtmfJbv2yMG2D6fcup5eblTMTvTSVs0ww9po2vbtd9CD6ZxtLiilw7O1v X-Received: by 2002:a25:d7c5:: with SMTP id o188mr2306693ybg.72.1599611298201; Tue, 08 Sep 2020 17:28:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611298; cv=none; d=google.com; s=arc-20160816; b=SVXe1ed4JEkizC8hObME3f/Znyockvy7fgQV7l3oSpG6NW+L3nKizmid5K6cQXPvgE Mp/1C/D8ZABR0ohdNIW6KhktlI+HkLR+9YUIdXFkPJlXWQDbsCIHCY3VJeHqMl08HuGg f8pHkuEQD9FVbr41uKOadby2GgyThBJ9BxeNzAPq7dpDzF0N+we4xce0gBQYqtH1LETE q5fJGl6FoayzZTOmd0XCqEM0umETTrDi8Mc7akpCXf+C37A+0JmDTnsszH2l8mOO36pW g4OQkbvuLtnCG8FOHFpHtJVKGGalisqNw5XLGd3i24wehXsRIp/IwXct9p2BdC7uE4D4 VoCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BMREvoHjj8f1EBfCvu7SAC5TIkS0aPkGQG5Rh07Q5oA=; b=UA4W5O8iuToFYqt4zfCi1qfzp3DjS2y/JYKb74H+I57kRlQUEuZOP9waNTJOwLEFoa 5gudTFZY7PyoQsY6GY5YTcBqsi8oEDcLCuBkqJQAv+PZ4Iu9es88+93mKhNjI7oL5TYJ 9LhUVmFgk+rsh1Hj6RoOcrT3Kh+N+7b+zPSx/IEoNOzO/t92dBSHDq7xVbYtZTrhsOWO doadYP+auGeoUZLR6c0QM6XBuidI8AOhwf9Osn/RufQ0LHqqjgZChfMnqLXy20GcNWT4 2Xjy5hJRZqmV94XldpIRdBjB9pajcqjfr+G9RMly1yu59PPtyf7n6KKCW5Q6Jf59F9ub pEIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZpxMCaG8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e194si953168yba.368.2020.09.08.17.28.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:28:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZpxMCaG8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnyD-0008JT-Ln for patch@linaro.org; Tue, 08 Sep 2020 20:28:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnp-0000X3-1k for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:33 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:33747) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnn-0002Ja-8B for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:32 -0400 Received: by mail-pg1-x544.google.com with SMTP id e33so753711pgm.0 for ; Tue, 08 Sep 2020 17:17:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BMREvoHjj8f1EBfCvu7SAC5TIkS0aPkGQG5Rh07Q5oA=; b=ZpxMCaG8wjJxmbdxj4VeD3QaUkzX+KW0qxu1LMlSbD2JcdGP+DSF76g4gMu6HQHRUd 8F9mL2HayGWWc5QoYvzjj03biCnPylKdX0byO+2lnORkqcEuBVGZozwtCR8CdEi5I3UR 5hsP6q+KDi/ducnvYgPQzLHt5cAbsccGFd3cMdg8IWhu832Ho9+KVpueHA8P+Q7AHQhn VCKc+P8QdGKINzs6uTjhgJzJ3+wswWioQOjOJ9HuaS2P6xBwjEfcPQkK20r2uVx3vHpU GQy8S5/uHkqxXWWwy+iY/8nJi7lwH6CHMfp3XKqBxSdt4yfQ3gfd9wCx81UIZsed2Shv FOKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BMREvoHjj8f1EBfCvu7SAC5TIkS0aPkGQG5Rh07Q5oA=; b=UFASN2Gir06Flbzr5IRyaw43hNdBKmjnGehOJIxXboo9iCbryc8xloOT3v256mCf/O 0O6PiMumt9cTw06k/FFlngdoBk80KpvJsoyZuRbgr7g4ovcHlbS00SbbWvzFplLIKK7j Zpc6vTwxufsmLB34XM/poKrwtv9lll8bWRiVGVdJ3S4EmxTmyUzwNf4M5Co/LfzZ2+Bo G2qx2ybgMqOmPqna4TUuD5GiD8iunSydSRADvLIKf/e7Nid60SxgwASYwLHzwrSbvCi3 AJ/C3hs96EqyG7bQ7Z9xmjtADGB5kVZ5h/biRx40uifdilrk0Dz8iCt99RDeQclpdCHa rwRQ== X-Gm-Message-State: AOAM532abnHYIjtxnH2JG7PlV3yzgL0g5xQW1mx/EVJS7DLFZrlVmErA lDBTSUSleeJOxkF9rN0y4Cj2+q3Pb5No4Q== X-Received: by 2002:a63:fe06:: with SMTP id p6mr926551pgh.337.1599610649495; Tue, 08 Sep 2020 17:17:29 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 32/43] tcg/ppc: Use tcg_constant_vec with tcg vec expanders Date: Tue, 8 Sep 2020 17:16:36 -0700 Message-Id: <20200909001647.532249-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Improve expand_vec_shi to use sign-extraction for MO_32. This allows a single VSPLTISB instruction to load all of the valid shift constants. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 44 ++++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3d23a6b226..155c42ed24 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3332,13 +3332,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGArg imm, TCGOpcode opci) { - TCGv_vec t1 = tcg_temp_new_vec(type); + TCGv_vec t1; - /* Splat w/bytes for xxspltib. */ - tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); + if (vece == MO_32) { + /* + * Only 5 bits are significant, and VSPLTISB can represent -16..15. + * So using negative numbers gets us the 4th bit easily. + */ + imm = sextract32(imm, 0, 5); + } else { + imm &= (8 << vece) - 1; + } + + /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */ + t1 = tcg_constant_vec(type, MO_8, imm); vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(t1)); - tcg_temp_free_vec(t1); } static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, @@ -3396,7 +3405,7 @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, { TCGv_vec t1 = tcg_temp_new_vec(type); TCGv_vec t2 = tcg_temp_new_vec(type); - TCGv_vec t3, t4; + TCGv_vec c0, c16; switch (vece) { case MO_8: @@ -3415,21 +3424,22 @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, case MO_32: tcg_debug_assert(!have_isa_2_07); - t3 = tcg_temp_new_vec(type); - t4 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(MO_8, t4, -16); + /* + * Only 5 bits are significant, and VSPLTISB can represent -16..15. + * So using -16 is a quick way to represent 16. + */ + c16 = tcg_constant_vec(type, MO_8, -16); + c0 = tcg_constant_vec(type, MO_8, 0); + vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), - tcgv_vec_arg(v2), tcgv_vec_arg(t4)); + tcgv_vec_arg(v2), tcgv_vec_arg(c16)); vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v2)); - tcg_gen_dupi_vec(MO_8, t3, 0); - vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3), - tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); - vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3), - tcgv_vec_arg(t3), tcgv_vec_arg(t4)); - tcg_gen_add_vec(MO_32, v0, t2, t3); - tcg_temp_free_vec(t3); - tcg_temp_free_vec(t4); + vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0)); + vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1), + tcgv_vec_arg(t1), tcgv_vec_arg(c16)); + tcg_gen_add_vec(MO_32, v0, t1, t2); break; default: From patchwork Wed Sep 9 00:16:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249419 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5018740ilg; Tue, 8 Sep 2020 17:29:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwq21AUgmchie6SF4FepITPtqqK+2OEJFiUdwIwForuUl6LCax/u56xdvuw/wj7QPuFMmh/ X-Received: by 2002:a25:874d:: with SMTP id e13mr2434382ybn.68.1599611368834; Tue, 08 Sep 2020 17:29:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611368; cv=none; d=google.com; s=arc-20160816; b=wCdtS7Os+dRHshFv8o7FsLUalxal6wl6HqC+nJS4/zt3JA7BCMXT5OPUigXFN95/h0 WuT1xX/orc78RlgfoCVGZMitGwOXwj3kiW0C6v2lmlu/+c9rhh+zPuU1gOEvE9nieq1x Jp1sPc3stupy4ExTsIWopwlXMbKuidOXLt0rY3dvtY8lcP3yfolBMNHwts57eqzjfvlJ jeQCNICyM6sI+JI2NP0KiF4qRIH50alJrvofRN5UiWNJJ9yO5oH9tEoDe/Ran06Ui5e6 B8wG4oAz7wwVv/D9yM7weYX9zO503f69CY3maqg59ueezoVjvpwolJ8jwahxDMLyAIto CMGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5oTHhTIpHsSvQvico3TP/px05iIcGlpWqa7T/U3dIqI=; b=sOS19t8VjrkYf1qEdEOAQD1H/QmdcHIekJQCVXquYG45RhL7fX+aPHthiWphDaym/I siRq4+MwlgboYqV+botnTE7KKgsNci9DJN4AG4oYFZsHeTjzvmSUGujsZUR6EQJnmhn7 aMGK/uZQQABSNW873PoBKyuHQ5UZkCR/7UhFsFAd2+uok52nlvWUivNuXlUG2XA/6tRW VS3PVK41g+R8GBE4gR9aFhbptX8j7Nh0d8fDT934ZucvmCwBVq33ufmIE494nm1K/tay WueVjFT7Go3SfPOAve9YQXdUIsXFQnJhAkdZZ9AEq9bgay53jeLoainzsTh9TxK7JRGJ OTDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ed5ei2Zu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 80si1093066ybd.186.2020.09.08.17.29.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:29:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ed5ei2Zu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38270 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnzM-0003Eo-BJ for patch@linaro.org; Tue, 08 Sep 2020 20:29:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37854) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnq-0000Zt-4R for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:34 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:34384) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnno-0002Jl-Bi for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:33 -0400 Received: by mail-pj1-x1044.google.com with SMTP id n3so471079pjq.1 for ; Tue, 08 Sep 2020 17:17:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5oTHhTIpHsSvQvico3TP/px05iIcGlpWqa7T/U3dIqI=; b=ed5ei2Zu3tRgX6uO1MfYoHHYNYfXG566IYYOg4vagiST50dBZ8qJrA3Hhga3Iop7ws kwK+4fwXNuUtDDMleYZwbvRRVxf5dzKekwRi/7DLUDJ6unB4G1pqNS0OM2oqeiNJQuSO mlxhOEdWkdBcFT7LbjgPWdR700KUjdlQRPItvgUaNQYciXLIMxIQDD6aNb/FJ398vm6E YpdO3pk2g6Knlw7Cv1czagf5aSeZsUe4ooy4iwbSVxfj9Uwq3m06arQrr26AaYP8OX9y wfUjdAw81nLA3yOUHQzQ1Q6F2m2aIiTKhQkEBRVBITRLsnLzof4ciIGMc0jN8ToAVFiD M9rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5oTHhTIpHsSvQvico3TP/px05iIcGlpWqa7T/U3dIqI=; b=sfx//6+s17dvSqtOO3IKTqCo42lWq8X2Ru9CDJ9DgcBibJS5TsCdcBPwc/xtFlDzmr Ia+QVXkKMS5Y7m13mj2rUxNy8K8vHjTZ5WkXe615uH8TihiOiwg1j7Ec4X48rQ7M6G+K 0hE2w51nFe9bjSeCiK4YYd/JKji0hr3Bs4zYfR83FcEibitJGlURaVzjyeyj9NHxp7Fn 7J7q+qb3Hg2bI9+V+V0Z5KELu3KSCliVm+ZdFhSeMzpFlzEXehJMdPoN8xOnMCFWWKww X0tTC4o1izqzxuvqfEPywT0TP7cf/Xjy+ZyeOxwHu9RInKFHk8QBYJod7vBqcFBX2mzl sw7w== X-Gm-Message-State: AOAM530j39NhC39k/2kVg/whvmoTenm7wB+kpaV9sl1B+y8SpyB9e8AH 1pPbdJfTc5K75OCRMsp4B/CDbz3aKT3suw== X-Received: by 2002:a17:90b:4c0f:: with SMTP id na15mr1160808pjb.119.1599610650603; Tue, 08 Sep 2020 17:17:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 33/43] tcg/aarch64: Use tcg_constant_vec with tcg vec expanders Date: Tue, 8 Sep 2020 17:16:37 -0700 Message-Id: <20200909001647.532249-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to "t1 = -v, t2 = c - v2". This avoids a serial dependency between t1 and t2. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index fdc118391c..d9d397075a 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2511,7 +2511,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t1, t2; + TCGv_vec v0, v1, v2, t1, t2, c1; TCGArg a2; va_start(va, a0); @@ -2543,8 +2543,8 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_rotlv_vec: t1 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(vece, t1, 8 << vece); - tcg_gen_sub_vec(vece, t1, v2, t1); + c1 = tcg_constant_vec(type, vece, 8 << vece); + tcg_gen_sub_vec(vece, t1, v2, c1); /* Right shifts are negative left shifts for AArch64. */ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t1)); @@ -2557,9 +2557,9 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_rotrv_vec: t1 = tcg_temp_new_vec(type); t2 = tcg_temp_new_vec(type); + c1 = tcg_constant_vec(type, vece, 8 << vece); tcg_gen_neg_vec(vece, t1, v2); - tcg_gen_dupi_vec(vece, t2, 8 << vece); - tcg_gen_add_vec(vece, t2, t1, t2); + tcg_gen_sub_vec(vece, t2, c1, v2); /* Right shifts are negative left shifts for AArch64. */ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t1)); From patchwork Wed Sep 9 00:16:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249409 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5016661ilg; Tue, 8 Sep 2020 17:25:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwRfrC0mz8oBHIJY/5B/iL/QuIPxZfmGGpCczz4/TF2wuP8sXL8qi2ZDDFfOPdRmwmCYGYS X-Received: by 2002:a25:8448:: with SMTP id r8mr2050993ybm.119.1599611117672; Tue, 08 Sep 2020 17:25:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611117; cv=none; d=google.com; s=arc-20160816; b=veBd5mcjcuW+H2hypTIP9vU2VIKnzDNdq4siunstLAhtdqhrHIxcnpjBLp5Od13u5O O9hGah7YKdpx2bk35euy/aC2QLzLINUGQfMBXIM9P0Xv3/JH9c1ltCunqegC+LPdjCkn rrTOqBEar37qPjrKv92bovLyreqJMOBBDQUs0PccIqI0WKt+RF+hA6zcF2K4mC2J2m7o nGF3RcaOFQMUmmc3VK0X2N5FyTP6ePNkAUT2tR7xkATYVsqC3yevXZ1tnkRNugjB46Ut pgOkyQE6WgK+oH7WbKtKh9pBIxO+p1yUYO89mXEonGQF2BfkrGOjLMKNFwUOitPKAhs+ EJ4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CeNByq4xJzQ0NQWVpC7UobWtIj47eNKfcOoWhkzYyh0=; b=VgPIjMwiQ6ZTtHkObJCVS8C6d7qM8OuNHWrGFdBIQNuePta9lwXNgMYhso6C5dU2Pf 4zF+uDs+p/ZIxnaTFNjvKanRPL/2nsX39g1F/wFkhMGgVui//gJqRLVFAYH2BsGOzQNv aEqEo9w+lNYLYa/AHnH67TvPFef6poaA2d/7Tzh+Q6dYRFS9RL+fCMIJ7Dq7NtuaccIu Aa8Np4T+JA4WQrCBJM/QT5hsx8bMlb1wno/qrD0iJk4SYk8y8zWmhNxp4yCmEPxZI/FZ 0SRBsmW0EnRx7C+kgHjnxS/chY2Rm16E/sUy/rPq7pLLFX4npHk5iTSZ4jblyO7f0XqU xvjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O3ylNEe1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n84si928799yba.7.2020.09.08.17.25.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:25:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O3ylNEe1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFnvI-0000En-Vp for patch@linaro.org; Tue, 08 Sep 2020 20:25:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnr-0000dx-HP for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:35 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:34059) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnp-0002Ju-Iz for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:35 -0400 Received: by mail-pj1-x102e.google.com with SMTP id n3so471097pjq.1 for ; Tue, 08 Sep 2020 17:17:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CeNByq4xJzQ0NQWVpC7UobWtIj47eNKfcOoWhkzYyh0=; b=O3ylNEe1Caq/KsHJZOKy5eBk8NP1kzYrWXNDxCXiA4glzGsRPpI6g7tX/xEjPwiACh 3UIt2zn/xZPr1gye0c+dqqduk7bYiAsZJBWI8HL3Bq704OCpKo5kWeG3I6kV3PnAg4ud HlZ2S+Su7PGfH77N1KxMXpMSntfQJT6mC1gtfTcm3sKNw+GoiLnS431QuimYV3zB0+nR 9UP6RgGE5UV6YinbwzXn0W/VaGDJ2VgjXir1qQ2UChkbEU+cPbuImonjlS24b1zWrclP LvEVFOak4mKle/efTvOBY1JsJrLCzUlznNuWnSA/Alfxiihdj0YDV+QOSmHLN0fn0UYy iEaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CeNByq4xJzQ0NQWVpC7UobWtIj47eNKfcOoWhkzYyh0=; b=Kl5voGHqgnZwyuwwZqNe1GBa3UdSwL5P1tqx6q+WfSq5HnoST8iq4RmZiLIH4IfZ9r LujpoYB9CsGvEOT/8S0TDpOv0nkC5vdwllShFmCUbMWBEjK48pWCwdnLL+e3ZZDtmp3M tyf6PI/YI3XRvceDIzRRoiqTuYnOXNSH8yQT/kqSQ98cRDE6qIq0iEQp6d4asH6Jiead 47Gc3J/tqt9uz76ScAA1fgWrbGnI2P4Amk7DLAHvI0MANavkstx2LCxMNNzlOz+zAe/r FMOhE0a5zpPGT/9puJpcDkQtYFrOhw5PkKf9niCgQnCLKgZrizOIuEVI/Ue98sqdVy5n S2YQ== X-Gm-Message-State: AOAM5329LyWdTcPyuG/mecazkgjIJ4a+zNzqJ8TRc4D4AmcDi0XD+gEr sVmDBc6b/7JA4vNeotgFjjFy3eBBVnRduA== X-Received: by 2002:a17:90a:e609:: with SMTP id j9mr1108258pjy.129.1599610651826; Tue, 08 Sep 2020 17:17:31 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 34/43] tcg: Add tcg-constr.c.inc Date: Tue, 8 Sep 2020 17:16:38 -0700 Message-Id: <20200909001647.532249-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin conversion of constraints to pre-validated, read-only entities. To begin, create a simple method by which sets of TCGTargetOpDef structures may be declared and used. This simplifies each host's tcg_target_op_def function and ensures that we have a collected set of constraints. Signed-off-by: Richard Henderson --- tcg/tcg-constr.c.inc | 108 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 tcg/tcg-constr.c.inc -- 2.25.1 diff --git a/tcg/tcg-constr.c.inc b/tcg/tcg-constr.c.inc new file mode 100644 index 0000000000..f7490a096e --- /dev/null +++ b/tcg/tcg-constr.c.inc @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * TCG backend data: operand constaints. + * Copyright (c) 2020 Linaro + */ + +/* + * Define structures for each set of constraints. + */ + +#define C_PFX1(P, A) P##A +#define C_PFX2(P, A, B) P##A##_##B +#define C_PFX3(P, A, B, C) P##A##_##B##_##C +#define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D +#define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E +#define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F + +#define C_O0_I1(I1) \ + static const TCGTargetOpDef C_PFX1(c_o0_i1_, I1) \ + = { .args_ct_str = { #I1 } }; + +#define C_O0_I2(I1, I2) \ + static const TCGTargetOpDef C_PFX2(c_o0_i2_, I1, I2) \ + = { .args_ct_str = { #I1, #I2 } }; + +#define C_O0_I3(I1, I2, I3) \ + static const TCGTargetOpDef C_PFX3(c_o0_i3_, I1, I2, I3) \ + = { .args_ct_str = { #I1, #I2, #I3 } }; + +#define C_O0_I4(I1, I2, I3, I4) \ + static const TCGTargetOpDef C_PFX4(c_o0_i4_, I1, I2, I3, I4) \ + = { .args_ct_str = { #I1, #I2, #I3, #I4 } }; + +#define C_O1_I1(O1, I1) \ + static const TCGTargetOpDef C_PFX2(c_o1_i1_, O1, I1) \ + = { .args_ct_str = { #O1, #I1 } }; + +#define C_O1_I2(O1, I1, I2) \ + static const TCGTargetOpDef C_PFX3(c_o1_i2_, O1, I1, I2) \ + = { .args_ct_str = { #O1, #I1, #I2 } }; + +#define C_O1_I3(O1, I1, I2, I3) \ + static const TCGTargetOpDef C_PFX4(c_o1_i3_, O1, I1, I2, I3) \ + = { .args_ct_str = { #O1, #I1, #I2, #I3 } }; + +#define C_O1_I4(O1, I1, I2, I3, I4) \ + static const TCGTargetOpDef C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) \ + = { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } }; + +#define C_N1_I2(O1, I1, I2) \ + static const TCGTargetOpDef C_PFX3(c_n1_i2_, O1, I1, I2) \ + = { .args_ct_str = { "&" #O1, #I1, #I2 } }; + +#define C_O2_I1(O1, O2, I1) \ + static const TCGTargetOpDef C_PFX3(c_o2_i1_, O1, O2, I1) \ + = { .args_ct_str = { #O1, #O2, #I1 } }; + +#define C_O2_I2(O1, O2, I1, I2) \ + static const TCGTargetOpDef C_PFX4(c_o2_i2_, O1, O2, I1, I2) \ + = { .args_ct_str = { #O1, #O2, #I1, #I2 } }; + +#define C_O2_I3(O1, O2, I1, I2, I3) \ + static const TCGTargetOpDef C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3) \ + = { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } }; + +#define C_O2_I4(O1, O2, I1, I2, I3, I4) \ + static const TCGTargetOpDef C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) \ + = { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } }; + +#include "tcg-target-constr.h" + + +/* + * Redefine the macros so that they now reference those structures. + * These values should be returned from tcg_target_op_def(). + */ + +#undef C_O0_I1 +#undef C_O0_I2 +#undef C_O0_I3 +#undef C_O0_I4 +#undef C_O1_I1 +#undef C_O1_I2 +#undef C_O1_I3 +#undef C_O1_I4 +#undef C_N1_I2 +#undef C_O2_I1 +#undef C_O2_I2 +#undef C_O2_I3 +#undef C_O2_I4 + +#define C_O0_I1(I1) &C_PFX1(c_o0_i1_, I1) +#define C_O0_I2(I1, I2) &C_PFX2(c_o0_i2_, I1, I2) +#define C_O0_I3(I1, I2, I3) &C_PFX3(c_o0_i3_, I1, I2, I3) +#define C_O0_I4(I1, I2, I3, I4) &C_PFX4(c_o0_i4_, I1, I2, I3, I4) + +#define C_O1_I1(O1, I1) &C_PFX2(c_o1_i1_, O1, I1) +#define C_O1_I2(O1, I1, I2) &C_PFX3(c_o1_i2_, O1, I1, I2) +#define C_O1_I3(O1, I1, I2, I3) &C_PFX4(c_o1_i3_, O1, I1, I2, I3) +#define C_O1_I4(O1, I1, I2, I3, I4) &C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) + +#define C_N1_I2(O1, I1, I2) &C_PFX3(c_n1_i2_, O1, I1, I2) + +#define C_O2_I1(O1, O2, I1) &C_PFX3(c_o2_i1_, O1, O2, I1) +#define C_O2_I2(O1, O2, I1, I2) &C_PFX4(c_o2_i2_, O1, O2, I1, I2) +#define C_O2_I3(O1, O2, I1, I2, I3) &C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3) +#define C_O2_I4(O1, O2, I1, I2, I3, I4) \ + &C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) From patchwork Wed Sep 9 00:16:39 2020 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id a11si1128592ybg.167.2020.09.08.17.31.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:31:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PHf57HCZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFo0r-0005rx-Rt for patch@linaro.org; Tue, 08 Sep 2020 20:31:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFnnt-0000iz-Bk for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:37 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:53160) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnq-0002K5-SP for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:37 -0400 Received: by mail-pj1-x102b.google.com with SMTP id o16so432835pjr.2 for ; Tue, 08 Sep 2020 17:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KiiHEmXlGV1VcjJy5syvlceWZPJvv12U3Hn3dF6mLHE=; b=PHf57HCZvvsXe2dBpbfUQsdf/47TJXnzpGrxd3zmK0ICZlyOQNH45IPalrOpIIktO5 EOn+xz4jLbuV0pyePpCBiIBDEYqRT67KFBBHGEQczcf4LcJxtEOfuGQ2DvIoHlf9LiEI jmsRhFqH2g4fQWIXw71iTvFn03ZtOJsl9dBe3VhPf4je4mY9k+AXY3xeS4F3u3AVPJr6 +KVo0v8UX8t72TI643472Cs9Y02fwNCoOYrjUYMGbkpn1k9vCWCI+o0InoL3i5I39StE y8zOcPmDdTf7ovwsEIAHiREWW3kNA3bbxiuD4e/8RKuc4CHFdtcDXZAg3r8k5huk35Gq OBmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KiiHEmXlGV1VcjJy5syvlceWZPJvv12U3Hn3dF6mLHE=; b=uKIgWkZIyPd72DbSYClEoPUisvTsYHW7OihtsXeQBPLsqIpRnyPMz15hukciRKZfXG 2aHMXWDdEhMbib6cd6gmh4vHdCvL9xT/+yKm6oQ17h4zVg9Rsou9g4BOKeEb4oZNvn0Q sn5KKFoKfSV8exMSea3PGbaMuMer7tCuyWw5eLsTW0RdYqlf0W51XIih9jQspH9Tgqow yEFJVe/9GqU0osB1ekaRwckfOfeWg2HCtXpS1ZLrri0Hc7bQZtaSu86cukqbBWmDnoXk TNX/Zb+4yNUVED3YETdbVMbGdEQ37c6bfu0LGwx90gA3VU5C/A8uVs5JGC4VzXcgFVmZ enlg== X-Gm-Message-State: AOAM531/eVVoaDwhazF1KVlfMMlliA6wHLu7odTmD+IXe+0vK+mUy20l ETKBdrMnzClwg/TGXzmNS28jyCDnW4Jkgw== X-Received: by 2002:a17:90a:297:: with SMTP id w23mr1183047pja.44.1599610653020; Tue, 08 Sep 2020 17:17:33 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 35/43] tcg/i386: Convert to tcg-constr.c.inc Date: Tue, 8 Sep 2020 17:16:39 -0700 Message-Id: <20200909001647.532249-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-constr.h | 55 +++++++++++ tcg/i386/tcg-target.c.inc | 187 +++++++++++++---------------------- 2 files changed, 121 insertions(+), 121 deletions(-) create mode 100644 tcg/i386/tcg-target-constr.h -- 2.25.1 diff --git a/tcg/i386/tcg-target-constr.h b/tcg/i386/tcg-target-constr.h new file mode 100644 index 0000000000..91d394612e --- /dev/null +++ b/tcg/i386/tcg-target-constr.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * i386 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) + +C_O0_I2(qi, r) +C_O0_I2(ri, r) +C_O0_I2(re, r) +C_O0_I2(r, re) +C_O0_I2(L, L) +C_O0_I2(x, r) + +C_O0_I3(L, L, L) + +C_O0_I4(L, L, L, L) +C_O0_I4(r, r, ri, ri) + +C_O1_I1(r, 0) +C_O1_I1(r, q) +C_O1_I1(r, r) +C_O1_I1(r, L) +C_O1_I1(x, r) +C_O1_I1(x, x) + +C_O1_I2(r, r, re) +C_O1_I2(r, 0, r) +C_O1_I2(r, 0, re) +C_O1_I2(r, 0, reZ) +C_O1_I2(r, 0, rI) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, ci) +C_O1_I2(r, r, ri) +C_O1_I2(Q, 0, Q) +C_O1_I2(q, r, re) +C_O1_I2(r, L, L) +C_O1_I2(x, x, x) +C_N1_I2(r, r, r) +C_N1_I2(r, r, rW) + +C_O1_I3(x, x, x, x) + +C_O1_I4(r, r, re, r, 0) +C_O1_I4(r, r, r, ri, ri) + +C_O2_I1(r, r, L) + +C_O2_I2(r, r, L, L) +C_O2_I2(a, d, a, r) + +C_O2_I3(a, d, 0, 1, r) + +C_O2_I4(r, r, 0, 1, re, re) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 36a90e7ef3..1dac1b33d1 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2983,39 +2983,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, } } +/* Define all constraint sets. */ +#include "../tcg-constr.c.inc" + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } }; - static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } }; - static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } }; - static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } }; - static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } }; - static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } }; - static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } }; - static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L_L - = { .args_ct_str = { "L", "L", "L", "L" } }; - static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } }; - static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } }; - static const TCGTargetOpDef x_x_x_x - = { .args_ct_str = { "x", "x", "x", "x" } }; - static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -3029,22 +3004,25 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st8_i64: - return &qi_r; + return C_O0_I2(qi, r); + case INDEX_op_st16_i32: case INDEX_op_st16_i64: case INDEX_op_st_i32: case INDEX_op_st32_i64: - return &ri_r; + return C_O0_I2(ri, r); + case INDEX_op_st_i64: - return &re_r; + return C_O0_I2(re, r); case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_re; + return C_O1_I2(r, r, re); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_mul_i32: @@ -3053,24 +3031,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return &r_0_re; + return C_O1_I2(r, 0, re); case INDEX_op_and_i32: case INDEX_op_and_i64: - { - static const TCGTargetOpDef and - = { .args_ct_str = { "r", "0", "reZ" } }; - return ∧ - } - break; + return C_O1_I2(r, 0, reZ); + case INDEX_op_andc_i32: case INDEX_op_andc_i64: - { - static const TCGTargetOpDef andc - = { .args_ct_str = { "r", "r", "rI" } }; - return &andc; - } - break; + return C_O1_I2(r, 0, rI); case INDEX_op_shl_i32: case INDEX_op_shl_i64: @@ -3078,16 +3047,17 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shr_i64: case INDEX_op_sar_i32: case INDEX_op_sar_i64: - return have_bmi2 ? &r_r_ri : &r_0_ci; + return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci); + case INDEX_op_rotl_i32: case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - return &r_0_ci; + return C_O1_I2(r, 0, ci); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_re; + return C_O0_I2(r, re); case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -3099,13 +3069,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_not_i32: case INDEX_op_not_i64: case INDEX_op_extrh_i64_i32: - return &r_0; + return C_O1_I1(r, 0); case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: - return &r_q; + return C_O1_I1(r, q); + case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: @@ -3120,108 +3091,80 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sextract_i32: case INDEX_op_ctpop_i32: case INDEX_op_ctpop_i64: - return &r_r; + return C_O1_I1(r, r); + case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &r_0_r; + return C_O1_I2(r, 0, r); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - = { .args_ct_str = { "Q", "0", "Q" } }; - return &dep; - } + return C_O1_I2(Q, 0, Q); + case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - { - static const TCGTargetOpDef setc - = { .args_ct_str = { "q", "r", "re" } }; - return &setc; - } + return C_O1_I2(q, r, re); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "re", "r", "0" } }; - return &movc; - } + return C_O1_I4(r, r, re, r, 0); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - = { .args_ct_str = { "a", "d", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(a, d, 0, 1, r); + case INDEX_op_mulu2_i32: case INDEX_op_mulu2_i64: case INDEX_op_muls2_i32: case INDEX_op_muls2_i64: - { - static const TCGTargetOpDef mul2 - = { .args_ct_str = { "a", "d", "a", "r" } }; - return &mul2; - } + return C_O2_I2(a, d, a, r); + case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - { - static const TCGTargetOpDef arith2 - = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } }; - return &arith2; - } + return C_O2_I4(r, r, 0, 1, re, re); + case INDEX_op_ctz_i32: case INDEX_op_ctz_i64: - { - static const TCGTargetOpDef ctz[2] = { - { .args_ct_str = { "&r", "r", "r" } }, - { .args_ct_str = { "&r", "r", "rW" } }, - }; - return &ctz[have_bmi1]; - } + return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); + case INDEX_op_clz_i32: case INDEX_op_clz_i64: - { - static const TCGTargetOpDef clz[2] = { - { .args_ct_str = { "&r", "r", "r" } }, - { .args_ct_str = { "&r", "r", "rW" } }, - }; - return &clz[have_lzcnt]; - } + return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O0_I2(L, L) : C_O0_I3(L, L, L)); + case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L); + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); + case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &L_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L - : &L_L_L_L); + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(L, L, L) + : C_O0_I4(L, L, L, L)); case INDEX_op_brcond2_i32: - { - static const TCGTargetOpDef b2 - = { .args_ct_str = { "r", "r", "ri", "ri" } }; - return &b2; - } + return C_O0_I4(r, r, ri, ri); + case INDEX_op_setcond2_i32: - { - static const TCGTargetOpDef s2 - = { .args_ct_str = { "r", "r", "r", "ri", "ri" } }; - return &s2; - } + return C_O1_I4(r, r, r, ri, ri); case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &x_r; + return C_O1_I1(x, r); + + case INDEX_op_st_vec: + return C_O0_I2(x, r); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3256,16 +3199,18 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) #if TCG_TARGET_REG_BITS == 32 case INDEX_op_dup2_vec: #endif - return &x_x_x; + return C_O1_I2(x, x, x); + case INDEX_op_abs_vec: case INDEX_op_dup_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: case INDEX_op_x86_psrldq_vec: - return &x_x; + return C_O1_I1(x, x); + case INDEX_op_x86_vpblendvb_vec: - return &x_x_x_x; + return C_O1_I3(x, x, x, x); default: break; From patchwork Wed Sep 9 00:16:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249425 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5020359ilg; Tue, 8 Sep 2020 17:32:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzNLurSOjgwMbdLCU36Q/BQPa2hnq7z4cs4FsXgvjybwsVJc7s/oKuxwIcx0sHeX6rM+LdS X-Received: by 2002:a25:3619:: with SMTP id d25mr2231805yba.414.1599611536520; Tue, 08 Sep 2020 17:32:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611536; cv=none; d=google.com; s=arc-20160816; b=nI+hoqPh9XlMST6HrJpEIU6X2Dk46/zAHBeUZBsjJ6o8N8wjkycyV7gsNKWOBstysX J58Lddtx0umq0ala0rk/+Up+5QdT+GQwS43qDgGk6ty0pN+ezpccol9n1PgEazym33j/ uXfDwqLcNUd30rcHm6+qI16lYmYpEDrwIEL5he+fQ1BkXm+Zwt+f+9wJEMw26vnXXQzb r+EYPTjnSvxccFAyiES7NFDNYAjY1GybuYYoP3TuxUTGxlyG9JIA5iblVZrFOSjdKAM/ aoRMZBJqnhKRZV/IPUAfR8ZJWVFXBr7xsQ1d6454KGUWc8WidE0vLdr7qNvS1HvwXasL +TJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5e04R8fqhgLE3g8fvUJRt06a4TS6ucpOGpQQp2jgtQI=; b=0c3/IO2ST7DqzRpI8g/MB4H1fBhz6FW7hQCy9gAK3kdsMiDOHYjaUALGjJQu9h/f9H BaiOrw/Lj0GRHF95DZMqIdN+IgKMQdbGZmYp/wpa8i3Ga5stgy2sUVx4QKkEB8nXLQPE 89nhUTxrEbnB1fipChemRGsKGfD2FwrI0zkmFzh0CvChxfmw+Wz4dLAadrvL0idjGen/ WYFFwvrStl7uftvnpiJT4EQqqCPCPjrl5V1nLEbwCUv8ksGSXQrT4sQaNc2eKO7U6v1v WArxJFGiGc9XBHR+drBJig7XIz6g72wRRA/8VpccvUafaWmP0XTTUFqVGDPkx72dZ99O hAWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TM37lqVs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-constr.h | 31 ++++++++++++ tcg/aarch64/tcg-target.c.inc | 85 +++++++++++---------------------- 2 files changed, 60 insertions(+), 56 deletions(-) create mode 100644 tcg/aarch64/tcg-target-constr.h -- 2.25.1 diff --git a/tcg/aarch64/tcg-target-constr.h b/tcg/aarch64/tcg-target-constr.h new file mode 100644 index 0000000000..dcf46a7457 --- /dev/null +++ b/tcg/aarch64/tcg-target-constr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * AArch64 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(lZ, l) +C_O0_I2(r, rA) +C_O0_I2(rZ, r) +C_O0_I2(w, r) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I1(w, r) +C_O1_I1(w, w) +C_O1_I1(w, wr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rA) +C_O1_I2(r, r, rAL) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rL) +C_O1_I2(r, rZ, rZ) +C_O1_I2(w, 0, w) +C_O1_I2(w, w, w) +C_O1_I2(w, w, wN) +C_O1_I2(w, w, wO) +C_O1_I2(w, w, wZ) +C_O1_I3(w, w, w, w) +C_O1_I4(r, r, rA, rZ, rZ) +C_O2_I4(r, r, rZ, rZ, rA, rMZ) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d9d397075a..e352f7f56b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2577,42 +2577,14 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, va_end(va); } +/* Define all constraint sets. */ +#include "../tcg-constr.c.inc" + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } }; - static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } }; - static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } }; - static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; - static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } }; - static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } }; - static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } }; - static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } }; - static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } }; - static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } }; - static const TCGTargetOpDef r_r_rAL - = { .args_ct_str = { "r", "r", "rAL" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef ext2 - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; - static const TCGTargetOpDef w_w_w_w - = { .args_ct_str = { "w", "w", "w", "w" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2651,7 +2623,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2660,7 +2632,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_add_i64: @@ -2668,7 +2640,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return &r_r_rA; + return C_O1_I2(r, r, rA); case INDEX_op_mul_i32: case INDEX_op_mul_i64: @@ -2682,7 +2654,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_remu_i64: case INDEX_op_muluh_i64: case INDEX_op_mulsh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); case INDEX_op_and_i32: case INDEX_op_and_i64: @@ -2696,7 +2668,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_orc_i64: case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return &r_r_rL; + return C_O1_I2(r, r, rL); case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -2708,42 +2680,42 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sar_i64: case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rAL; + return C_O1_I2(r, r, rAL); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_rA; + return C_O0_I2(r, rA); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, rA, rZ, rZ); case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_l; + return C_O1_I1(r, l); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return &lZ_l; + return C_O0_I2(lZ, l); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &ext2; + return C_O1_I2(r, rZ, rZ); case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rA, rMZ); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2761,32 +2733,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: case INDEX_op_aa64_sshl_vec: - return &w_w_w; + return C_O1_I2(w, w, w); case INDEX_op_not_vec: case INDEX_op_neg_vec: case INDEX_op_abs_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: - return &w_w; + return C_O1_I1(w, w); case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &w_r; + return C_O1_I1(w, r); + case INDEX_op_st_vec: + return C_O0_I2(w, r); case INDEX_op_dup_vec: - return &w_wr; + return C_O1_I1(w, wr); case INDEX_op_or_vec: case INDEX_op_andc_vec: - return &w_w_wO; + return C_O1_I2(w, w, wO); case INDEX_op_and_vec: case INDEX_op_orc_vec: - return &w_w_wN; + return C_O1_I2(w, w, wN); case INDEX_op_cmp_vec: - return &w_w_wZ; + return C_O1_I2(w, w, wZ); case INDEX_op_bitsel_vec: - return &w_w_w_w; + return C_O1_I3(w, w, w, w); case INDEX_op_aa64_sli_vec: - return &w_0_w; + return C_O1_I2(w, 0, w); default: return NULL; From patchwork Wed Sep 9 00:16:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249428 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5021038ilg; Tue, 8 Sep 2020 17:33:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxABxnC+bnN45bwkQHHvDQXQ850WXLna9o9ViqLgi10eQCMY0T93pa0ewkRFb4wz05W3EDQ X-Received: by 2002:a25:cfc7:: with SMTP id f190mr2210463ybg.82.1599611613681; Tue, 08 Sep 2020 17:33:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611613; cv=none; d=google.com; s=arc-20160816; b=e4HgfYZKW3Ie5xwadwNl9pGaaSYOutMj2iYDrgy7jhgwfZJd7EP84tedIFuFaFGPWz FL9wHUQMH6h3tmhL1WN65bPmm25H1ql9xomMVA2E6aEukUz4Qs3D96HxC2sXw3q9sCeC Obz6EhCsl3jrZ4YXFUTpbRmwsWyb++tVsZtczdLxBjNj6O09lyXr73mIxqJcQvHgbf6h REDrU/MJkditQCHKI6ckIqDNCaFwVcQadDaGymu78kn6ICTpzTyXXOLHnObEVOjDJ51f oUljYDaIhRkkWAqx7ur9dUK9mdOL02+GXupzPpLn3aaj28HHe4fDvHc29IA9+xMUpubz AzLA== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-constr.h | 30 ++++++++++++ tcg/arm/tcg-target.c.inc | 93 +++++++++++++------------------------ 2 files changed, 63 insertions(+), 60 deletions(-) create mode 100644 tcg/arm/tcg-target-constr.h -- 2.25.1 diff --git a/tcg/arm/tcg-target-constr.h b/tcg/arm/tcg-target-constr.h new file mode 100644 index 0000000000..c59be2da11 --- /dev/null +++ b/tcg/arm/tcg-target-constr.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM32 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, rIN) +C_O0_I2(s, s) +C_O0_I3(s, s, s) +C_O0_I4(r, r, rI, rI) +C_O0_I4(s, s, s, s) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, l, l) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rIN) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, r, r, rI, rI) +C_O1_I4(r, r, rIN, rIK, 0) +C_O2_I1(r, r, l) +C_O2_I2(r, r, l, l) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, r, r, rIN, rIK) +C_O2_I4(r, r, rI, rI, rIN, rIK) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 30d30874c7..70a9e798e3 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2071,57 +2071,20 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } +/* Define all constraint sets. */ +#include "../tcg-constr.c.inc" + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } }; - static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } }; - static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rIN - = { .args_ct_str = { "r", "r", "rIN" } }; - static const TCGTargetOpDef r_r_rIK - = { .args_ct_str = { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_r_r - = { .args_ct_str = { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l_l - = { .args_ct_str = { "r", "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s_s - = { .args_ct_str = { "s", "s", "s", "s" } }; - static const TCGTargetOpDef br - = { .args_ct_str = { "r", "rIN" } }; - static const TCGTargetOpDef ext2 - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } }; - static const TCGTargetOpDef sub2 - = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "r", "r", "rI", "rI" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "r", "r", "rI", "rI" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: case INDEX_op_bswap16_i32: @@ -2131,59 +2094,69 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ext16u_i32: case INDEX_op_extract_i32: case INDEX_op_sextract_i32: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + return C_O0_I2(r, r); case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_setcond_i32: - return &r_r_rIN; + return C_O1_I2(r, r, rIN); + case INDEX_op_and_i32: case INDEX_op_andc_i32: case INDEX_op_clz_i32: case INDEX_op_ctz_i32: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); + case INDEX_op_mul_i32: case INDEX_op_div_i32: case INDEX_op_divu_i32: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); + case INDEX_op_or_i32: case INDEX_op_xor_i32: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_rotl_i32: case INDEX_op_rotr_i32: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_brcond_i32: - return &br; + return C_O0_I2(r, rIN); case INDEX_op_deposit_i32: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_extract2_i32: - return &ext2; + return C_O1_I2(r, rZ, rZ); case INDEX_op_movcond_i32: - return &movc; + return C_O1_I4(r, r, rIN, rIK, 0); case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rIN, rIK); case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rI, rIN, rIK); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, rI, rI); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, rI, rI); case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l; + return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l); case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l; + return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s; + return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s); case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s; + return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s); default: return NULL; From patchwork Wed Sep 9 00:16:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249429 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5021468ilg; Tue, 8 Sep 2020 17:34:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxGsw5MB8+WQo73qX5nGHVPALrPpfyO+0VfTv7XzzkXeElTsiMKDHoAXcgVK+knVfaqpl19 X-Received: by 2002:a25:8404:: with SMTP id u4mr2380618ybk.176.1599611656231; Tue, 08 Sep 2020 17:34:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611656; cv=none; d=google.com; s=arc-20160816; b=WOWlK5yjxbnbxO66Q/ayHwykFNMLcqJCYzkEhaeDSuo4JL6uc+S7Op70ojhOY7ZVf3 /u9SuZjS/LCPw+qWjsXXqS9d5Uz4iYy4R8nSBCFOXTQqaMvo04hQLoYDWHRgUVOLKIMi B1dURjPC7CeECRz8avBf8uf+ppDxIS7+nTzum4pZoihHqX7jgdfmpZmwg7wtiBYtq8lg dKLXvVxHAN23toP/n+HujtTNe8iq1l/jUwcgyzgQfNTEc1Qksjv+kQKEDJqIIFUcBW4l cJDZK1zP4hiKuKlWUfW/ySdwYJKrB3y/AiS7YUXu4DlZmq6ILIhZ5sN2RERqogElmei1 1GzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VHMzWfhySbeDoxJTEYjQPiFuY5RLIdMHbneN2NIax7E=; b=TgFQg1WvWmUdHBnFexMOx+nZcEmCaBDTp6Et2sEj0JZxtNz+yB8ZelCXLZjEAei98B btcVG91R49W6920FGRRBUpqXT36L78T60PKKFglafvdHOKsnA0y4mn0VdvMksPf5iWLM EaoCHujOcM8/L24kxYWR41Ej5CPBoWKmGQk/7+XOMnTPwJht1rAcCmYTeQ2IQiONNdMl 5E7NqsXtrDYI3HfIvxEHyuqTxao2alMIYslwyzTCiuLHRD6gf4blgXWRq+SZR5datOvR 7LTeEIVY0EtmlsBGCozFok1nJITxWqt4ucNL69HAPJPfZF+is3jj9yWuFCL/FWHRmgmd OcSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xtGZHGVH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-constr.h | 31 ++++++++++++ tcg/mips/tcg-target.c.inc | 95 ++++++++++++------------------------ 2 files changed, 61 insertions(+), 65 deletions(-) create mode 100644 tcg/mips/tcg-target-constr.h -- 2.25.1 diff --git a/tcg/mips/tcg-target-constr.h b/tcg/mips/tcg-target-constr.h new file mode 100644 index 0000000000..831e2d8a01 --- /dev/null +++ b/tcg/mips/tcg-target-constr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * MIPS target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I2(SZ, S) +C_O0_I3(SZ, S, S) +C_O0_I3(SZ, SZ, S) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O0_I4(SZ, SZ, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rJ) +C_O1_I2(r, r, rWZ) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, 0) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 3e282c1bde..9e78a79eb6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2158,52 +2158,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } +/* Define all constraint sets. */ +#include "../tcg-constr.c.inc" + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } }; - static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } }; - static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } }; - static const TCGTargetOpDef SZ_SZ_S - = { .args_ct_str = { "SZ", "SZ", "S" } }; - static const TCGTargetOpDef SZ_SZ_S_S - = { .args_ct_str = { "SZ", "SZ", "S", "S" } }; - static const TCGTargetOpDef r_rZ_rN - = { .args_ct_str = { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_rIK - = { .args_ct_str = { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_rWZ - = { .args_ct_str = { "r", "r", "rWZ" } }; - static const TCGTargetOpDef r_r_r_r - = { .args_ct_str = { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } }; - static const TCGTargetOpDef movc_r6 - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2236,7 +2198,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2245,14 +2207,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_rJ; + return C_O1_I2(r, r, rJ); case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: case INDEX_op_muluh_i32: @@ -2271,20 +2233,20 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_remu_i64: case INDEX_op_nor_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); case INDEX_op_muls2_i32: case INDEX_op_mulu2_i32: case INDEX_op_muls2_i64: case INDEX_op_mulu2_i64: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); case INDEX_op_and_i32: case INDEX_op_and_i64: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); case INDEX_op_or_i32: case INDEX_op_xor_i32: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: @@ -2295,41 +2257,44 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sar_i64: case INDEX_op_rotr_i64: case INDEX_op_rotl_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_clz_i32: case INDEX_op_clz_i64: - return &r_r_rWZ; + return C_O1_I2(r, r, rWZ); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return use_mips32r6_instructions ? &movc_r6 : &movc; - + return (use_mips32r6_instructions + ? C_O1_I4(r, rZ, rZ, rZ, rZ) + : C_O1_I4(r, rZ, rZ, rZ, 0)); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rN, rN); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, rZ, rZ, rZ, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(rZ, rZ, rZ, rZ); case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &SZ_S : &SZ_S_S); + ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L); + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &SZ_S - : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S); + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S) + : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S) + : C_O0_I4(SZ, SZ, S, S)); default: return NULL; From patchwork Wed Sep 9 00:16:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249430 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5021954ilg; Tue, 8 Sep 2020 17:35:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8ethZ8vMNgzju+MvtRK7SSVOHH5UonsOJi3iD+nLtV9ORD7nI1jAMN4JaaUgzF7tvKQrw X-Received: by 2002:a25:db88:: with SMTP id g130mr2341758ybf.193.1599611705961; Tue, 08 Sep 2020 17:35:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611705; cv=none; d=google.com; s=arc-20160816; b=Kck3roqv5u94Na//GkC574COUFZqHKF1rGQRerbuuT1Wx1W+a6J190/cSevFf3W16w /yk8IDhU7F9woPPKj64sNmpAarfc1C97qN1nyVTufwJZhehBYJrr5jiy++AM13N2hb6g u3K8GwMGXFHfM+xLDXUNQereefgnWw2xHIUtlwjS1Xjswvk7lYOjfZC8BR5zEBmD2vjL EJJeSrKeWXAxJyQTDkT8z/TYb0XR15w7rRME8f060sdzf/8z5AxxstPp+NTz9CWkm2x0 lIRv52d0MMSF47J+lz4bFJaEhiK+VVY0f35Zct9asXPrIt+Uv5CyJNqwcbz1vTlc6s5H yctg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7BiS9+5sMvbJcaQD+6Dpdr+95svEiwirFL2XKd2vVDQ=; b=Yu4RzFfVApmnHObMrpfFh3UznPfi08GLC9+m5FzSdkdpDbtV/aVE3WTQMQpPqEY2HP 4yAvgdGAob0YVoeuo4GtyKe3te2mE+RbgtNbAm24xuTbi7QmRciBSrB0JNK/eK7foXwC HC8nd+g1ua5D64ruEG1JFIUS23FhpyscsHq7rEO55h222FSOabFQU7Oxvv5srUJrMeWC CrV8y5j4oE4Lye3xEe92CFFZuxbmlPAxLfW8iBRz4x+rKnPP36KUr/BYLE6lyz+qNgkt S4GaAh8rweqApoC0sReTzdI3DHdV9L9XghoedEUiafN1kEMLgFZhDlrtCGJzjEMXAx5G 9hiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IPzfUrC+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-constr.h | 37 ++++++++++ tcg/ppc/tcg-target.c.inc | 135 +++++++++++++++--------------------- 2 files changed, 94 insertions(+), 78 deletions(-) create mode 100644 tcg/ppc/tcg-target-constr.h -- 2.25.1 diff --git a/tcg/ppc/tcg-target-constr.h b/tcg/ppc/tcg-target-constr.h new file mode 100644 index 0000000000..9a38f8ed89 --- /dev/null +++ b/tcg/ppc/tcg-target-constr.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * PowerPC target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O0_I2(S, S) +C_O0_I2(v, r) +C_O0_I3(S, S, S) +C_O0_I4(r, r, ri, ri) +C_O0_I4(S, S, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I1(v, r) +C_O1_I1(v, v) +C_O1_I1(v, vr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, rI, ri) +C_O1_I2(r, rI, rT) +C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rT) +C_O1_I2(r, r, rU) +C_O1_I2(r, r, rZW) +C_O1_I2(v, v, v) +C_O1_I3(v, v, v, v) +C_O1_I4(r, r, ri, rZ, rZ) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(L, L, L) +C_O2_I2(L, L, L, L) +C_O2_I4(r, r, rI, rZM, r, r) +C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 155c42ed24..e34a02ee04 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3495,62 +3495,20 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, va_end(va); } +/* Define all constraint sets. */ +#include "../tcg-constr.c.inc" + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } }; - static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } }; - static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } }; - static const TCGTargetOpDef r_rI_ri - = { .args_ct_str = { "r", "rI", "ri" } }; - static const TCGTargetOpDef r_rI_rT - = { .args_ct_str = { "r", "rI", "rT" } }; - static const TCGTargetOpDef r_r_rZW - = { .args_ct_str = { "r", "r", "rZW" } }; - static const TCGTargetOpDef L_L_L_L - = { .args_ct_str = { "L", "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S_S - = { .args_ct_str = { "S", "S", "S", "S" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } }; - static const TCGTargetOpDef sub2 - = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } }; - static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } }; - static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } }; - static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } }; - static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } }; - static const TCGTargetOpDef v_v_v_v - = { .args_ct_str = { "v", "v", "v", "v" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_ctpop_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: @@ -3566,10 +3524,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: case INDEX_op_ctpop_i64: case INDEX_op_neg_i64: case INDEX_op_not_i64: @@ -3582,7 +3536,16 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return C_O0_I2(r, r); case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -3605,10 +3568,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); + case INDEX_op_mul_i32: case INDEX_op_mul_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_div_i32: case INDEX_op_divu_i32: case INDEX_op_nand_i32: @@ -3623,55 +3588,63 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_divu_i64: case INDEX_op_mulsh_i64: case INDEX_op_muluh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_sub_i32: - return &r_rI_ri; + return C_O1_I2(r, rI, ri); case INDEX_op_add_i64: - return &r_r_rT; + return C_O1_I2(r, r, rT); case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rU; + return C_O1_I2(r, r, rU); case INDEX_op_sub_i64: - return &r_rI_rT; + return C_O1_I2(r, rI, rT); case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rZW; + return C_O1_I2(r, r, rZW); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, ri, rZ, rZ); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, ri, ri); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, ri, ri); case INDEX_op_add2_i64: case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rI, rZM); case INDEX_op_sub2_i64: case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rZM, r, r); case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) + : C_O1_I2(r, L, L)); + case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &S_S : &S_S_S); + ? C_O0_I2(S, S) + : C_O0_I3(S, S, S)); + case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L); + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L) + : C_O2_I2(L, L, L, L)); + case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &S_S - : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S); + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S) + : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S) + : C_O0_I4(S, S, S, S)); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3701,19 +3674,25 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: case INDEX_op_dup2_vec: - return &v_v_v; + return C_O1_I2(v, v, v); + case INDEX_op_not_vec: case INDEX_op_neg_vec: - return &v_v; + return C_O1_I1(v, v); + case INDEX_op_dup_vec: - return have_isa_3_00 ? &v_vr : &v_v; + return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); + case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &v_r; + return C_O1_I1(v, r); + + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_bitsel_vec: case INDEX_op_ppc_msum_vec: - return &v_v_v_v; + return C_O1_I3(v, v, v, v); default: return NULL; From patchwork Wed Sep 9 00:16:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249421 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5018814ilg; Tue, 8 Sep 2020 17:29:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJydD8RXm6QpHlZIAQ9WyZ9uAiBogN6IEBCuBYF5WtJuayxJQmp8Xu2vvrc9uZTYVv1UQ99e X-Received: by 2002:a25:ca57:: with SMTP id a84mr2313092ybg.313.1599611376004; Tue, 08 Sep 2020 17:29:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611376; cv=none; d=google.com; s=arc-20160816; b=ujKCqQhwWFBKA+K5EUq9x/lshKhBEkLkOJtyBBliERW+UeFl+FdljyBFoxDOWphJ2v MeM8w/7659hEC/hPtXTDBxlnYGYNtoCILKwjNDGuJAt0WYdYCcWOhk6kxRfEWZeAB/tP P0UM0PLuOg6LeFFV8Hx4blklS60GCte4WUNPHPVgDkRIJGYv0M6qHat/JMgnipyiiIcM mr8t3KXU5IvHfNGClrKyGazajNCssL2HCusGRj24rL9TkhG4CGQPBTbgLcGhEMA6Gsps vAskgWyQ3buJHtb5M9wttwHEwzcYZNM9JJvU9TRmuGUJWRvSolLJ5hP4AfnufDRFFK1q t4yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hCBX2cyLM5KyoJd9ZdINXW9/beVmBc7hH0uzic/OGPU=; b=ZXRellrGbeOesjyN2IoTOJoCFVCruRGdITAshuA+pE1ria4xmYkhSZlRIJxyrqYcsD B5DFfq+oLQoZi/focJQnpC6ScKDf7U6916c4+L5NGa5JEIv/DZBspvFE2WCatSHEwF3n bRNmCdmQDHd187W+4bZMZ1tiKJGrpOO4xxIUkKqCqqGs6i/fHMtBfbnbbGVEJx8jPtQd 4k5SxQQKfDwxPDQe1ehOJ7npF6xCVRad5WoaJVtp/ETl7fqg23k2Smreabe0cM3kSiwu mTSmGeJ6TRZLF3+Fv79vfs4LT5rUDI279rmElb78Fcx288BGzuX9VW9u7BJ+ThMdM2UE brSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tRqWUiD6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-constr.h | 25 +++++++++++ tcg/riscv/tcg-target.c.inc | 82 ++++++++++------------------------- 2 files changed, 49 insertions(+), 58 deletions(-) create mode 100644 tcg/riscv/tcg-target-constr.h -- 2.25.1 diff --git a/tcg/riscv/tcg-target-constr.h b/tcg/riscv/tcg-target-constr.h new file mode 100644 index 0000000000..aeff74034c --- /dev/null +++ b/tcg/riscv/tcg-target-constr.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * RISC-V target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(LZ, L) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I3(LZ, L, L) +C_O0_I3(LZ, LZ, L) +C_O0_I4(LZ, LZ, L, L) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index aaef1c5eed..042a41e1f4 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1608,50 +1608,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } +/* Define all constraint sets. */ +#include "../tcg-constr.c.inc" + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r - = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r - = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef rZ_r - = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef rZ_rZ - = { .args_ct_str = { "rZ", "rZ" } }; - static const TCGTargetOpDef rZ_rZ_rZ_rZ - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_ri - = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI - = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_rZ_rN - = { .args_ct_str = { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_L - = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef r_r_L - = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L - = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef LZ_L - = { .args_ct_str = { "LZ", "L" } }; - static const TCGTargetOpDef LZ_L_L - = { .args_ct_str = { "LZ", "L", "L" } }; - static const TCGTargetOpDef LZ_LZ_L - = { .args_ct_str = { "LZ", "LZ", "L" } }; - static const TCGTargetOpDef LZ_LZ_L_L - = { .args_ct_str = { "LZ", "LZ", "L", "L" } }; - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1683,7 +1647,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -1692,7 +1656,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -1702,11 +1666,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_and_i64: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: @@ -1724,7 +1688,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_rem_i64: case INDEX_op_remu_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -1732,36 +1696,38 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &r_r_rZ_rZ_rM_rM; + return C_O2_I4(r, r, rZ, rZ, rM, rM); case INDEX_op_brcond2_i32: - return &rZ_rZ_rZ_rZ; + return C_O0_I4(rZ, rZ, rZ, rZ); case INDEX_op_setcond2_i32: - return &r_rZ_rZ_rZ_rZ; + return C_O1_I4(r, rZ, rZ, rZ, rZ); case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L; + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return TCG_TARGET_REG_BITS == 64 ? &LZ_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L - : &LZ_LZ_L_L; + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L) + : C_O0_I4(LZ, LZ, L, L)); default: return NULL; From patchwork Wed Sep 9 00:16:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249424 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5019745ilg; Tue, 8 Sep 2020 17:31:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzW4UZxL9r7q3O93aneR+uUTktfkbE9Mq6LZlBsf/uN9pGTS88lC+qGYSbupEaQLJnJPWIk X-Received: by 2002:a25:cfc7:: with SMTP id f190mr2199873ybg.82.1599611471638; Tue, 08 Sep 2020 17:31:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611471; cv=none; d=google.com; s=arc-20160816; b=mO4Bh9Z0yMqlxPfQnz+2LZbcz2znIOaKvxU5N3C+3JUUNrfbqu+jSnYzXwZVJbt3c/ NNNLBq25YisyyuQUM3iXU4XvEl365aMvvdFHN7v+QB2geu3qaiY3ANfpwhVZL0Mi4jW/ p/8DdJ++IPwPRrMny2AsK+awis4n0eMCRHLVOQ6tnCCGGlgV4rS017pADnJX3jGLO6pu LzHOaqTv5u18P17CegXXEYAPqqgoXZPUyjQjSBANhDWSss3c4/j/zynRUtkeom0Ms7uj tK2Ma4eb6ymWoBJyqS+q3VJWmWPCJNXPYCfssAllAMlGKABcuQtHZPkrz3Boijz6xgM+ 4Kxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E/+IbLkuc88o8W2y0bJXVmWsi6CUPEMwbQDPjSqv7So=; b=OVLIGSWdRcQUpDDhi/O4/RN+Z/rUDqSZ761+F3GFAKHPalhBx0vxIrY8FSP5+CA/J6 C06TW2alZT9xvGX574opZ44SwJdPAN6YVAH21hx8SvNJ0RRB/U/WnIl18PEp0Bsf0GS9 OCO+/jgZoLbWB25UJT0a1oni0ldhmQQc+zDDGcLaxBkt9ZHT7FXXBtnHsVAN/q7Xh3Zf 8Ti9LdgP0xARy9cAGWJOr0yTNyKMqPXq2NntsGQYL3shzy/BU+Xjck1F1vgpZW4E9/7q yDnwK5dkgWbdGN645wZ1WVmSrMQW7efbfT8ikFBJ+HLmIyJARQme4UNZOQ/wKKrTLmw8 cUHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Iap+ptFI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b65si1027515ybb.72.2020.09.08.17.31.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:31:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Iap+ptFI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFo11-00069P-3c for patch@linaro.org; Tue, 08 Sep 2020 20:31:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFno0-00012p-Bb for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:44 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:53977) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnny-0002M2-Cd for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:44 -0400 Received: by mail-pj1-x1035.google.com with SMTP id t7so429341pjd.3 for ; Tue, 08 Sep 2020 17:17:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=E/+IbLkuc88o8W2y0bJXVmWsi6CUPEMwbQDPjSqv7So=; b=Iap+ptFIl1CDEjjohXB+PEi7PSbcCFYOhS5YRYGdltd4W/WUbn8AawP8p9Aiz1mdz8 1fsjJO/VZFWGZTvYm1mYga5ryRCdbzYIyt+mN7A/UoDifzEjvYop8+03re5/DGk7qIZl wxfQO4qgVphmoBTdrimg6tlQJ7D/XMxcoYQ8lET6R9W/IP5jJ0DOdrPEMm4tw2ElgGXk KCp501QsfIbO53L8x6q2hu6sVpGsWrozoMzBY5a+KTH9K9UOxqkK/gZEY86PMd0jKL8X u41T7N8JZ+86kg7vOpUzvQ/b99wpkXOebT9IzwXmINDmmZvArK39ZtKHH/T+nuVhTIgG lURg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E/+IbLkuc88o8W2y0bJXVmWsi6CUPEMwbQDPjSqv7So=; b=SO23C3XbNIvZ4uS8tdIq62jTloR9Bce0nZv6Ky6qmPxExtJVQgkKRnpDS2pucObE7g N/48tTeu2IISlSvxfqrZ8rwMZaDr7ZutYEM1Sn5nJsKadzxqtwLYKNwmmXsozmCY3Akg TDg2i+bfWml847LZoxtNfx6sla2CW2rrLsO6ijwnNuyFBxVldCM9lskU+yZHPXKN9r87 wuUh+0wj6iPf0LLiLlMOwNL/zUZZ3Z6f98wfpd5bJoVNX971j2ijpzVOqufWq6ntPeB3 5Xn7zmhQB/x7Cz0w0/3gb+frsXfSbYOAtc7aCSIGkBSsp/Fh2VnirR6E6z1KXgV+e+1E GIpA== X-Gm-Message-State: AOAM532AFtoXuHNZJdRbcEo0poTDSDN9lO1O6Ylbp80fejtKCg/c3yys s1v0SIeqvJoVvTkq3arhVZo4Wtq8pzy+Hw== X-Received: by 2002:a17:90a:c907:: with SMTP id v7mr1194438pjt.204.1599610660596; Tue, 08 Sep 2020 17:17:40 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 41/43] tcg/s390: Convert to tcg-constr.c.inc Date: Tue, 8 Sep 2020 17:16:45 -0700 Message-Id: <20200909001647.532249-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target-constr.h | 24 +++++++ tcg/s390/tcg-target.c.inc | 119 +++++++++++++++-------------------- 2 files changed, 76 insertions(+), 67 deletions(-) create mode 100644 tcg/s390/tcg-target-constr.h -- 2.25.1 diff --git a/tcg/s390/tcg-target-constr.h b/tcg/s390/tcg-target-constr.h new file mode 100644 index 0000000000..06c1f4a944 --- /dev/null +++ b/tcg/s390/tcg-target-constr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * S390 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(L, L) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, rI) +C_O1_I2(r, 0, rJ) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, r) +C_O1_I4(r, r, ri, r, 0) +C_O1_I4(r, r, ri, rI, 0) +C_O2_I2(b, a, 0, r) +C_O2_I3(b, a, 0, 1, r) +C_O2_I4(r, r, 0, 1, rA, r) +C_O2_I4(r, r, 0, 1, ri, r) +C_O2_I4(r, r, 0, 1, r, r) diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 824a07aa7a..c628194421 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2312,27 +2312,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } +/* Define all constraint sets. */ +#include "../tcg-constr.c.inc" + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; - static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; - static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; - static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; - static const TCGTargetOpDef a2_r - = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; - static const TCGTargetOpDef a2_ri - = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } }; - static const TCGTargetOpDef a2_rA - = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -2346,6 +2333,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: + return C_O1_I1(r, r); + case INDEX_op_st8_i32: case INDEX_op_st8_i64: case INDEX_op_st16_i32: @@ -2353,11 +2342,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st_i32: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &r_r; + return C_O0_I2(r, r); case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_ri; + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_and_i32: @@ -2366,35 +2366,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, ri) + : C_O1_I2(r, 0, rI)); + case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, rJ) + : C_O1_I2(r, 0, rI)); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); - - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - return &r_r_ri; - - case INDEX_op_rotl_i32: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i32: - case INDEX_op_rotr_i64: - return &r_r_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2417,58 +2415,45 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extu_i32_i64: case INDEX_op_extract_i32: case INDEX_op_extract_i64: - return &r_r; - - case INDEX_op_clz_i64: - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I1(r, r); case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_L; + return C_O1_I1(r, L); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return &L_L; + return C_O0_I2(L, L); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "rZ", "r" } }; - return &dep; - } + return C_O1_I2(r, rZ, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "ri", "r", "0" } }; - static const TCGTargetOpDef movc_l - = { .args_ct_str = { "r", "r", "ri", "rI", "0" } }; - return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc); - } + return (s390_facilities & FACILITY_LOAD_ON_COND2 + ? C_O1_I4(r, r, ri, rI, 0) + : C_O1_I4(r, r, ri, r, 0)); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - = { .args_ct_str = { "b", "a", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(b, a, 0, 1, r); + case INDEX_op_mulu2_i64: - { - static const TCGTargetOpDef mul2 - = { .args_ct_str = { "b", "a", "0", "r" } }; - return &mul2; - } + return C_O2_I2(b, a, 0, r); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, ri, r) + : C_O2_I4(r, r, 0, 1, r, r)); + case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, rA, r) + : C_O2_I4(r, r, 0, 1, r, r)); default: break; From patchwork Wed Sep 9 00:16:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249426 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5020421ilg; Tue, 8 Sep 2020 17:32:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxgadJqWlONvCZ2OJJSVlORXw+WCofsASIxeB6FwDrGoVixpxlfSQbbyrIeSxO1fDMm9Fs9 X-Received: by 2002:a25:ec12:: with SMTP id j18mr2285642ybh.121.1599611542526; Tue, 08 Sep 2020 17:32:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599611542; cv=none; d=google.com; s=arc-20160816; b=VmBGHQK7KG6vlN/0M5MDZ4QXtD+NPBP8iU663vdfZpAaI2dyy9gwYIuaxETmqNURuP Q7+TpsRzuQdPPfsgKMZz9793gMMrVF8WpX7Ez21smJjhmV74HZawzITkcB3CRlZYCHFx TSBUFZXW2nqlcuyAEBDbQe28vUdYSV8nEpc3mYSePQF02E9cOhtq/2Dl6b8xNkBiBoun aFpxEPPzw34YBHbzbaJvxOJFi2ga3vPU12aSkECmleaZwya2XB4okGX1KUQdKsekh5k3 e2gQa0PYPr/FYSz08C48NwxACw6uD/mHKI5sF6xzSYzvs9/SyG9Dx/d59CFw5NsvltpJ BBFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Uou06gf/IRn+bzfObWOTsvklHo4+rp/muN9749mhiKU=; b=e7BZXGYr6FfnLikdkA93KT3CzWGEiENXxXaUJNITB5qhdUOWJRMc1rHDnsqTdW1eYs KNH5DqgQU362RhCHg+N892Y2+/vmO8kRoJ7Hg/FTFyt1MaMWs2CMpHWux9lQ70BvhYeL W2fHl9+Quob4r7/FTe72cbOkJcydVYIRmzUi00EDZSnE7UMXje8EJo/te/0LQBXv3w0f 1pOS+JDYpMTdsXrd0AV2On+niB/xbH1zD1kR0suP/unU/Np/5SQkvUpQgcS7qX3dcAh6 bUXf2wukE6UeL4155FnfYfCiU1nZCyK01qzyv4qyc2GKAuXgRhDbQPXdo4bmn5QLWXaY rSIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N0FvhHcq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x10si883079ybr.453.2020.09.08.17.32.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Sep 2020 17:32:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N0FvhHcq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFo2A-0000Dk-0o for patch@linaro.org; Tue, 08 Sep 2020 20:32:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38066) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFno1-00015b-BH for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:45 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:34063) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFnnz-0002MA-Dv for qemu-devel@nongnu.org; Tue, 08 Sep 2020 20:17:45 -0400 Received: by mail-pj1-x1032.google.com with SMTP id n3so471258pjq.1 for ; Tue, 08 Sep 2020 17:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Uou06gf/IRn+bzfObWOTsvklHo4+rp/muN9749mhiKU=; b=N0FvhHcq4yJNnx+FK2kzubQa6Dk0g63AJphJPE1Hq9820NiJSN/7+zeHtL+HqfgiKJ LiTNkRxt1JH+YjWB57h3YkwGs3scC9qExFjU9azta3bBOmgtP/WNtl2fhzA9JdNF30gU pv4j5MTnjS8cvzPNo8EauSM73YXUJAj4qRfrW6a83+Y6V5Sal8FKcI09rOH44XKIRoSD kDo1yGBoPCAp8EYvClhqDwsYluPxoYWJJMWMXOoU+9lV+2rIkiauEVuDNbbEcTdGhqqn jE7Znpi2Jw/nYK8IZSK1BVS0ICpkxmT2qL0e0jroVtVzLaiIAF2gOtPXV0aLyfkWO448 PppQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Uou06gf/IRn+bzfObWOTsvklHo4+rp/muN9749mhiKU=; b=XQbmTaBAzg2T3p3MDcE2hu2fXqrYbLPbt7/sCV7vXxk23mWFzdLgnIXH3GdpdrTaei T8q6Q2K9GrCF7VjlTAoa9qSQtxtfbq1/i1UdadREl3yNC89az9C4fwnUu+1WYpRk50DT hkwBoWg+SWyMBN1qQGYgeaeyKW0RA88Gf4+6IZKBADEhdwxgwD81OEMzZCdCEN3A/AFe YQWvAyufFkIsYH4poApDrdZLJ5MAe54djYifQk2COqznBWM8E7j0WYUH+Q942IDwz/KZ 5uHrvwBC9BEyWmNcaNQtXDlEaqDmG9QGdJdDAO4TTL6nrrO9DLPJvh5yghBLcX99nWHj DYCQ== X-Gm-Message-State: AOAM5307ST4+dWn8Vc8w/wbi/EQHvrFq0iBTqQtYjMjGV424Vmq4Orih xS683SJmJkbokRvJbAAw46HULY0dsofKhw== X-Received: by 2002:a17:90a:7f93:: with SMTP id m19mr1249399pjl.194.1599610661719; Tue, 08 Sep 2020 17:17:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id 137sm505437pfu.149.2020.09.08.17.17.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 17:17:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 42/43] tcg/sparc: Convert to tcg-constr.c.inc Date: Tue, 8 Sep 2020 17:16:46 -0700 Message-Id: <20200909001647.532249-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target-constr.h | 27 +++++++++++++ tcg/sparc/tcg-target.c.inc | 74 ++++++++++++----------------------- 2 files changed, 51 insertions(+), 50 deletions(-) create mode 100644 tcg/sparc/tcg-target-constr.h -- 2.25.1 diff --git a/tcg/sparc/tcg-target-constr.h b/tcg/sparc/tcg-target-constr.h new file mode 100644 index 0000000000..28aec2ae0f --- /dev/null +++ b/tcg/sparc/tcg-target-constr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Sparc target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(rZ, r) +C_O0_I2(RZ, r) +C_O0_I2(rZ, rJ) +C_O0_I2(RZ, RJ) +C_O0_I2(sZ, A) +C_O0_I2(SZ, A) +C_O1_I1(r, A) +C_O1_I1(R, A) +C_O1_I1(r, r) +C_O1_I1(r, R) +C_O1_I1(R, r) +C_O1_I1(R, R) +C_O1_I2(R, R, R) +C_O1_I2(r, rZ, rJ) +C_O1_I2(R, RZ, RJ) +C_O1_I4(r, rZ, rJ, rI, 0) +C_O1_I4(R, RZ, RJ, RI, 0) +C_O2_I2(r, r, rZ, rJ) +C_O2_I4(R, R, RZ, RZ, RJ, RI) +C_O2_I4(r, r, rZ, rZ, rJ, rJ) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index af480115c5..aa426a1c90 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1592,40 +1592,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } +/* Define all constraint sets. */ +#include "../tcg-constr.c.inc" + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } }; - static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } }; - static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } }; - static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } }; - static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } }; - static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } }; - static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } }; - static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } }; - static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } }; - static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } }; - static const TCGTargetOpDef r_rZ_rJ - = { .args_ct_str = { "r", "rZ", "rJ" } }; - static const TCGTargetOpDef R_RZ_RJ - = { .args_ct_str = { "R", "RZ", "RJ" } }; - static const TCGTargetOpDef r_r_rZ_rJ - = { .args_ct_str = { "r", "r", "rZ", "rJ" } }; - static const TCGTargetOpDef movc_32 - = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } }; - static const TCGTargetOpDef movc_64 - = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } }; - static const TCGTargetOpDef add2_32 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } }; - static const TCGTargetOpDef add2_64 - = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1634,12 +1608,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: case INDEX_op_st_i32: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_mul_i32: @@ -1655,18 +1629,18 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_setcond_i32: - return &r_rZ_rJ; + return C_O1_I2(r, rZ, rJ); case INDEX_op_brcond_i32: - return &rZ_rJ; + return C_O0_I2(rZ, rJ); case INDEX_op_movcond_i32: - return &movc_32; + return C_O1_I4(r, rZ, rJ, rI, 0); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return &add2_32; + return C_O2_I4(r, r, rZ, rZ, rJ, rJ); case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: - return &r_r_rZ_rJ; + return C_O2_I2(r, r, rZ, rJ); case INDEX_op_ld8u_i64: case INDEX_op_ld8s_i64: @@ -1677,13 +1651,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: - return &R_r; + return C_O1_I1(R, r); case INDEX_op_st8_i64: case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &RZ_r; + return C_O0_I2(RZ, r); case INDEX_op_add_i64: case INDEX_op_mul_i64: @@ -1699,36 +1673,36 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shr_i64: case INDEX_op_sar_i64: case INDEX_op_setcond_i64: - return &R_RZ_RJ; + return C_O1_I2(R, RZ, RJ); case INDEX_op_neg_i64: case INDEX_op_not_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: - return &R_R; + return C_O1_I1(R, R); case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - return &r_R; + return C_O1_I1(r, R); case INDEX_op_brcond_i64: - return &RZ_RJ; + return C_O0_I2(RZ, RJ); case INDEX_op_movcond_i64: - return &movc_64; + return C_O1_I4(R, RZ, RJ, RI, 0); case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return &add2_64; + return C_O2_I4(R, R, RZ, RZ, RJ, RI); case INDEX_op_muluh_i64: - return &R_R_R; + return C_O1_I2(R, R, R); case INDEX_op_qemu_ld_i32: - return &r_A; + return C_O1_I1(r, A); case INDEX_op_qemu_ld_i64: - return &R_A; + return C_O1_I1(R, A); case INDEX_op_qemu_st_i32: - return &sZ_A; + return C_O0_I2(sZ, A); case INDEX_op_qemu_st_i64: - return &SZ_A; + return C_O0_I2(SZ, A); default: return NULL; From patchwork Wed Sep 9 00:16:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249427 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp5020919ilg; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This does require finishing the conversion to tcg_target_op_def. Remove quite a lot of ifdefs, since we can reference opcodes even if they are not implemented. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-constr.h | 28 +++ tcg/tci/tcg-target.c.inc | 360 ++++++++++++++---------------------- 2 files changed, 163 insertions(+), 225 deletions(-) create mode 100644 tcg/tci/tcg-target-constr.h -- 2.25.1 diff --git a/tcg/tci/tcg-target-constr.h b/tcg/tci/tcg-target-constr.h new file mode 100644 index 0000000000..6658e905e6 --- /dev/null +++ b/tcg/tci/tcg-target-constr.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * TCI target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O0_I2(r, S) +C_O0_I3(r, r, S) +C_O0_I3(r, S, S) +C_O0_I4(r, r, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, r) +C_O1_I2(r, L, L) +C_O1_I2(r, ri, ri) +C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) + +#if TCG_TARGET_REG_BITS == 32 +C_O0_I4(r, r, ri, ri) +C_O1_I4(r, r, r, ri, ri) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, r, r, r, r) +#endif diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 25ed868505..350cb498d7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -37,236 +37,146 @@ /* Bitfield n...m (in 32 bit value). */ #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) -/* Macros used in tcg_target_op_defs. */ -#define R "r" -#define RI "ri" -#if TCG_TARGET_REG_BITS == 32 -# define R64 "r", "r" -#else -# define R64 "r" -#endif -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -# define L "L", "L" -# define S "S", "S" -#else -# define L "L" -# define S "S" -#endif - -/* TODO: documentation. */ -static const TCGTargetOpDef tcg_target_op_defs[] = { - { INDEX_op_exit_tb, { NULL } }, - { INDEX_op_goto_tb, { NULL } }, - { INDEX_op_br, { NULL } }, - - { INDEX_op_ld8u_i32, { R, R } }, - { INDEX_op_ld8s_i32, { R, R } }, - { INDEX_op_ld16u_i32, { R, R } }, - { INDEX_op_ld16s_i32, { R, R } }, - { INDEX_op_ld_i32, { R, R } }, - { INDEX_op_st8_i32, { R, R } }, - { INDEX_op_st16_i32, { R, R } }, - { INDEX_op_st_i32, { R, R } }, - - { INDEX_op_add_i32, { R, RI, RI } }, - { INDEX_op_sub_i32, { R, RI, RI } }, - { INDEX_op_mul_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i32 - { INDEX_op_div_i32, { R, R, R } }, - { INDEX_op_divu_i32, { R, R, R } }, - { INDEX_op_rem_i32, { R, R, R } }, - { INDEX_op_remu_i32, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i32 - { INDEX_op_div2_i32, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i32, { R, R, "0", "1", R } }, -#endif - /* TODO: Does R, RI, RI result in faster code than R, R, RI? - If both operands are constants, we can optimize. */ - { INDEX_op_and_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i32 - { INDEX_op_andc_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i32 - { INDEX_op_eqv_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i32 - { INDEX_op_nand_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i32 - { INDEX_op_nor_i32, { R, RI, RI } }, -#endif - { INDEX_op_or_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i32 - { INDEX_op_orc_i32, { R, RI, RI } }, -#endif - { INDEX_op_xor_i32, { R, RI, RI } }, - { INDEX_op_shl_i32, { R, RI, RI } }, - { INDEX_op_shr_i32, { R, RI, RI } }, - { INDEX_op_sar_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i32 - { INDEX_op_rotl_i32, { R, RI, RI } }, - { INDEX_op_rotr_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i32 - { INDEX_op_deposit_i32, { R, "0", R } }, -#endif - - { INDEX_op_brcond_i32, { R, RI } }, - - { INDEX_op_setcond_i32, { R, R, RI } }, -#if TCG_TARGET_REG_BITS == 64 - { INDEX_op_setcond_i64, { R, R, RI } }, -#endif /* TCG_TARGET_REG_BITS == 64 */ - -#if TCG_TARGET_REG_BITS == 32 - /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ - { INDEX_op_add2_i32, { R, R, R, R, R, R } }, - { INDEX_op_sub2_i32, { R, R, R, R, R, R } }, - { INDEX_op_brcond2_i32, { R, R, RI, RI } }, - { INDEX_op_mulu2_i32, { R, R, R, R } }, - { INDEX_op_setcond2_i32, { R, R, R, RI, RI } }, -#endif - -#if TCG_TARGET_HAS_not_i32 - { INDEX_op_not_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i32 - { INDEX_op_neg_i32, { R, R } }, -#endif - -#if TCG_TARGET_REG_BITS == 64 - { INDEX_op_ld8u_i64, { R, R } }, - { INDEX_op_ld8s_i64, { R, R } }, - { INDEX_op_ld16u_i64, { R, R } }, - { INDEX_op_ld16s_i64, { R, R } }, - { INDEX_op_ld32u_i64, { R, R } }, - { INDEX_op_ld32s_i64, { R, R } }, - { INDEX_op_ld_i64, { R, R } }, - - { INDEX_op_st8_i64, { R, R } }, - { INDEX_op_st16_i64, { R, R } }, - { INDEX_op_st32_i64, { R, R } }, - { INDEX_op_st_i64, { R, R } }, - - { INDEX_op_add_i64, { R, RI, RI } }, - { INDEX_op_sub_i64, { R, RI, RI } }, - { INDEX_op_mul_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i64 - { INDEX_op_div_i64, { R, R, R } }, - { INDEX_op_divu_i64, { R, R, R } }, - { INDEX_op_rem_i64, { R, R, R } }, - { INDEX_op_remu_i64, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i64 - { INDEX_op_div2_i64, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i64, { R, R, "0", "1", R } }, -#endif - { INDEX_op_and_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i64 - { INDEX_op_andc_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i64 - { INDEX_op_eqv_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i64 - { INDEX_op_nand_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i64 - { INDEX_op_nor_i64, { R, RI, RI } }, -#endif - { INDEX_op_or_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i64 - { INDEX_op_orc_i64, { R, RI, RI } }, -#endif - { INDEX_op_xor_i64, { R, RI, RI } }, - { INDEX_op_shl_i64, { R, RI, RI } }, - { INDEX_op_shr_i64, { R, RI, RI } }, - { INDEX_op_sar_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i64 - { INDEX_op_rotl_i64, { R, RI, RI } }, - { INDEX_op_rotr_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i64 - { INDEX_op_deposit_i64, { R, "0", R } }, -#endif - { INDEX_op_brcond_i64, { R, RI } }, - -#if TCG_TARGET_HAS_ext8s_i64 - { INDEX_op_ext8s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i64 - { INDEX_op_ext16s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32s_i64 - { INDEX_op_ext32s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i64 - { INDEX_op_ext8u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i64 - { INDEX_op_ext16u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32u_i64 - { INDEX_op_ext32u_i64, { R, R } }, -#endif - { INDEX_op_ext_i32_i64, { R, R } }, - { INDEX_op_extu_i32_i64, { R, R } }, -#if TCG_TARGET_HAS_bswap16_i64 - { INDEX_op_bswap16_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i64 - { INDEX_op_bswap32_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap64_i64 - { INDEX_op_bswap64_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_not_i64 - { INDEX_op_not_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i64 - { INDEX_op_neg_i64, { R, R } }, -#endif -#endif /* TCG_TARGET_REG_BITS == 64 */ - - { INDEX_op_qemu_ld_i32, { R, L } }, - { INDEX_op_qemu_ld_i64, { R64, L } }, - - { INDEX_op_qemu_st_i32, { R, S } }, - { INDEX_op_qemu_st_i64, { R64, S } }, - -#if TCG_TARGET_HAS_ext8s_i32 - { INDEX_op_ext8s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i32 - { INDEX_op_ext16s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i32 - { INDEX_op_ext8u_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i32 - { INDEX_op_ext16u_i32, { R, R } }, -#endif - -#if TCG_TARGET_HAS_bswap16_i32 - { INDEX_op_bswap16_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i32 - { INDEX_op_bswap32_i32, { R, R } }, -#endif - - { INDEX_op_mb, { } }, - { -1 }, -}; +/* Define all constraint sets. */ +#include "../tcg-constr.c.inc" static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - int i, n = ARRAY_SIZE(tcg_target_op_defs); + switch (op) { + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + return C_O1_I1(r, r); - for (i = 0; i < n; ++i) { - if (tcg_target_op_defs[i].op == op) { - return &tcg_target_op_defs[i]; - } + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return C_O0_I2(r, r); + + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + return C_O1_I2(r, r, r); + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + /* TODO: Does R, RI, RI result in faster code than R, R, RI? */ + return C_O1_I2(r, ri, ri); + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + return C_O1_I2(r, 0, r); + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return C_O0_I2(r, ri); + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); + +#if TCG_TARGET_REG_BITS == 32 + /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + return C_O2_I4(r, r, r, r, r, r); + case INDEX_op_brcond2_i32: + return C_O0_I4(r, r, ri, ri); + case INDEX_op_mulu2_i32: + return C_O2_I2(r, r, r, r); + case INDEX_op_setcond2_i32 + return C_O1_I4(r, r, r, ri, ri); +#endif + + case INDEX_op_qemu_ld_i32: + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) + : C_O1_I2(r, L, L)); + case INDEX_op_qemu_ld_i64: + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); + case INDEX_op_qemu_st_i32: + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O0_I2(r, S) + : C_O0_I3(r, S, S)); + case INDEX_op_qemu_st_i64: + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, S) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, S) + : C_O0_I4(r, r, S, S)); + + default: + return NULL; } - return NULL; } static const int tcg_target_reg_alloc_order[] = {