From patchwork Tue Sep 8 07:11:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249275 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp4304016ilg; Tue, 8 Sep 2020 00:12:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzq6unjcxqbTkKpcLBawFbQ60LKmZWHd0+eU4M5JACp1pECaGAu3PhJAgqULA6BMOUam2JC X-Received: by 2002:a17:906:6b95:: with SMTP id l21mr23786940ejr.317.1599549176170; Tue, 08 Sep 2020 00:12:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599549176; cv=none; d=google.com; s=arc-20160816; b=fslSLtp7oMC9GTRi7Vm1ryNXKfmpd6Q8aZunVbLRixdn+7s1rUAHK3sIMrB/XR+HTZ fAq4NldXnP8po8145ezxndQcWv8JqI2qzO+hF7jd3Y/Timg3jGGEuRLeKQJ6+qVHdNTj Y0ifa4maFIY+mMrPElaj3fTvfRoll9C7ATYvgZlLREQ7n2kmAW2l6hkJN3Ai0dIO+G6v D8tAj4rz6gKYWQ+xwhABOv5KqkeKx3w94zcpIOKkrOsr/1hgQO3w20vdZbRiX8Au+1vb iu9DBmnAPG5QuIBJWANF+wGHCOh31jVoe9AYSlCm+ZsOtFc7zT66oM/+hg67ywG8Uueq f9+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=CFDC7RzHxiN0xIogkZtoggiPp+jBQhpBqjC/KuNUryk=; b=DeoLVmN4LXxKzJLTWd3Luj8/KRZe7o8IH5BqRSNJRAmqCmV7oAMeb/GKUHMzcU7lac htpmEysxaIFyHgB3Ez1RXGjiuVQbk4/JlXfGG2QmGr+mCnblL2RYen6fYvVnK6KooO6a H/oMNzxp+TJYU6suIprIaXNg5tP1Az9BNFEQoZvKz1C6JDQ94nNVcQLGic2Jbd1L/mds VysAQ22MnIkD7XiXMDiOuihE1AXvoIrm9FhSjpnd8J6wbJAZgClUQfbplWNYgu2DHV1W G1rszVPH0F1sTUu67EKarYse70twOet5CpoGWzcl2t5Ith3LcUN0oTEr6zXsGJvl/tH4 9DSw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x15si11076770eje.180.2020.09.08.00.12.56; Tue, 08 Sep 2020 00:12:56 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729246AbgIHHMs (ORCPT + 6 others); Tue, 8 Sep 2020 03:12:48 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:57896 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728137AbgIHHMk (ORCPT ); Tue, 8 Sep 2020 03:12:40 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 7A2061CFE44A83F966DD; Tue, 8 Sep 2020 15:12:36 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Tue, 8 Sep 2020 15:12:27 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang Subject: [PATCH v2 1/3] irqchip: dw-apb-ictl: prepare for support hierarchy irq domain Date: Tue, 8 Sep 2020 15:11:32 +0800 Message-ID: <20200908071134.2578-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200908071134.2578-1-thunder.leizhen@huawei.com> References: <20200908071134.2578-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename some functions and variables in advance, to make the next patch looks more clear. The details are as follows: 1. rename dw_apb_ictl_handler() to dw_apb_ictl_handle_irq_cascaded(). In function dw_apb_ictl_init(): 1. rename local variable irq to parent_irq. 2. add "const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops", then replace &irq_generic_chip_ops in other places with domain_ops. 3. add "irq_flow_handler_t flow_handler = handle_level_irq", then replace handle_level_irq in other places with flow_handler. No functional change. Signed-off-by: Zhen Lei Tested-by: Haoyu Lv --- drivers/irqchip/irq-dw-apb-ictl.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) -- 2.26.0.106.g9fadedd diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index e4550e9c810b..aa6214da0b1f 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -26,7 +26,7 @@ #define APB_INT_FINALSTATUS_H 0x34 #define APB_INT_BASE_OFFSET 0x04 -static void dw_apb_ictl_handler(struct irq_desc *desc) +static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); @@ -73,12 +73,14 @@ static int __init dw_apb_ictl_init(struct device_node *np, struct irq_domain *domain; struct irq_chip_generic *gc; void __iomem *iobase; - int ret, nrirqs, irq, i; + int ret, nrirqs, parent_irq, i; u32 reg; + const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops; + irq_flow_handler_t flow_handler = handle_level_irq; /* Map the parent interrupt for the chained handler */ - irq = irq_of_parse_and_map(np, 0); - if (irq <= 0) { + parent_irq = irq_of_parse_and_map(np, 0); + if (parent_irq <= 0) { pr_err("%pOF: unable to parse irq\n", np); return -EINVAL; } @@ -120,8 +122,7 @@ static int __init dw_apb_ictl_init(struct device_node *np, else nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L)); - domain = irq_domain_add_linear(np, nrirqs, - &irq_generic_chip_ops, NULL); + domain = irq_domain_add_linear(np, nrirqs, domain_ops, NULL); if (!domain) { pr_err("%pOF: unable to add irq domain\n", np); ret = -ENOMEM; @@ -129,7 +130,7 @@ static int __init dw_apb_ictl_init(struct device_node *np, } ret = irq_alloc_domain_generic_chips(domain, 32, 1, np->name, - handle_level_irq, clr, 0, + flow_handler, clr, 0, IRQ_GC_INIT_MASK_CACHE); if (ret) { pr_err("%pOF: unable to alloc irq domain gc\n", np); @@ -146,7 +147,8 @@ static int __init dw_apb_ictl_init(struct device_node *np, gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; } - irq_set_chained_handler_and_data(irq, dw_apb_ictl_handler, domain); + irq_set_chained_handler_and_data(parent_irq, + dw_apb_ictl_handle_irq_cascaded, domain); return 0; From patchwork Tue Sep 8 07:11:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249274 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp4303923ilg; Tue, 8 Sep 2020 00:12:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzE/9Laz82dqiijfg8u6hsb6F0I8ofJV68Ydfb7N782Z/uMdkhwfNKzQqxE77tSiCYCP6YL X-Received: by 2002:a17:906:bb06:: with SMTP id jz6mr23811669ejb.275.1599549164919; Tue, 08 Sep 2020 00:12:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599549164; cv=none; d=google.com; s=arc-20160816; b=ZcbtKs1pJ/R3NKpWqNGfF5IKDSKPKMIhViSxNLYkSnD+8tvJ6NdabPPXx9RO6aT1Gm yrChbkx6cY5ULF9l2Omn9chxGsR5FYTemF/dFYm/GShwG09kp1ouLvXfb0ZKNM3HTCRJ u+l1Nn28huIHCFM1xYtDTAukTn69l4ADvk8h9wLhbf5XuFPOtNoUdnHKaRhP1Q8U4bPE 0W7t7vvf60/o1jf/uWUVgLhS35+ah3cqFh/JfcL0Kap4MX01rw/gzFNPv3+3FQk5+OoK /CHVEMunoms3R3n/Xandex6uWzGX6ISSVfwpl/Ul2+PCZqnr58hQq3v3u+0zQaUSE8NF t/sA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=CWhoMsW8J0+16Lzyn/33T6fKq7LZVEilSnSmqflUIDo=; b=iz/7IORsPDzg4o2JuzUcGGEMJ8lYcgCYly+PdT1u5z+59VrWGlOz0BkTwbV5hg+N/o Irfy/AQ1/KGvFF8BwGlx33jux/fTjITi1GGZR7g24Th+x5qNG6q7h0xJTBT5vNuS+tKq Po2/eimdSwZjfF4RRoQ2glaLglAyBy5Dj5rlMiceyNgUl2gMvaythlgQjnfjv4lx6mbn +P+2d8H+Nr+ckPldMGqvxjopF7tK2I4zgZZdEMpOlHvbb11DjRlIIsCoLeBSTFdhpW8M mNu7o21NBSA99gqrbdPs8Tpn98H8Bs9ucxKRoVilCk70NM9wK4bUqfKFbLcn3QQXvYRa JDjg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id s11si11420113eju.295.2020.09.08.00.12.44; Tue, 08 Sep 2020 00:12:44 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729230AbgIHHMk (ORCPT + 6 others); Tue, 8 Sep 2020 03:12:40 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:57898 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728562AbgIHHMj (ORCPT ); Tue, 8 Sep 2020 03:12:39 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 6F34C10494B93BEF3F5A; Tue, 8 Sep 2020 15:12:36 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Tue, 8 Sep 2020 15:12:28 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang Subject: [PATCH v2 2/3] irqchip: dw-apb-ictl: support hierarchy irq domain Date: Tue, 8 Sep 2020 15:11:33 +0800 Message-ID: <20200908071134.2578-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200908071134.2578-1-thunder.leizhen@huawei.com> References: <20200908071134.2578-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to use dw-apb-ictl as primary interrupt controller. Suggested-by: Marc Zyngier Signed-off-by: Zhen Lei Tested-by: Haoyu Lv --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-dw-apb-ictl.c | 75 +++++++++++++++++++++++++++++-- 2 files changed, 73 insertions(+), 4 deletions(-) -- 2.26.0.106.g9fadedd Reported-by: kernel test robot diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bfc9719dbcdc..7c2d1c8fa551 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -148,7 +148,7 @@ config DAVINCI_CP_INTC config DW_APB_ICTL bool select GENERIC_IRQ_CHIP - select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY config FARADAY_FTINTC010 bool diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index aa6214da0b1f..405861322596 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -17,6 +17,7 @@ #include #include #include +#include #define APB_INT_ENABLE_L 0x00 #define APB_INT_ENABLE_H 0x04 @@ -26,6 +27,30 @@ #define APB_INT_FINALSTATUS_H 0x34 #define APB_INT_BASE_OFFSET 0x04 +/* + * irq domain of the primary interrupt controller. Currently, only one is + * supported. + */ +static struct irq_domain *dw_apb_ictl_irq_domain; + +static void __exception_irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs) +{ + struct irq_domain *d = dw_apb_ictl_irq_domain; + int n; + + for (n = 0; n < d->revmap_size; n += 32) { + struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n); + u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); + + while (stat) { + u32 hwirq = ffs(stat) - 1; + + handle_domain_irq(d, hwirq, regs); + stat &= ~(1 << hwirq); + } + } +} + static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); @@ -50,6 +75,30 @@ static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + irq_map_generic_chip(domain, virq + i, hwirq + i); + + return 0; +} + +static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = { + .translate = irq_domain_translate_onecell, + .alloc = dw_apb_ictl_irq_domain_alloc, + .free = irq_domain_free_irqs_top, +}; + #ifdef CONFIG_PM static void dw_apb_ictl_resume(struct irq_data *d) { @@ -78,11 +127,24 @@ static int __init dw_apb_ictl_init(struct device_node *np, const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops; irq_flow_handler_t flow_handler = handle_level_irq; + if (dw_apb_ictl_irq_domain) { + pr_err("%pOF: a hierarchy irq domain is already exist.\n", np); + return -EBUSY; + } + /* Map the parent interrupt for the chained handler */ parent_irq = irq_of_parse_and_map(np, 0); if (parent_irq <= 0) { - pr_err("%pOF: unable to parse irq\n", np); - return -EINVAL; + /* It's used as secondary interrupt controller */ + if (of_find_property(np, "interrupts", NULL)) { + pr_err("%pOF: unable to parse irq\n", np); + return -EINVAL; + } + + /* It's used as the primary interrupt controller */ + parent_irq = 0; + domain_ops = &dw_apb_ictl_irq_domain_ops; + flow_handler = handle_fasteoi_irq; } ret = of_address_to_resource(np, 0, &r); @@ -145,10 +207,17 @@ static int __init dw_apb_ictl_init(struct device_node *np, gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; + if (!parent_irq) + gc->chip_types[0].chip.irq_eoi = irq_gc_noop; } - irq_set_chained_handler_and_data(parent_irq, + if (parent_irq) { + irq_set_chained_handler_and_data(parent_irq, dw_apb_ictl_handle_irq_cascaded, domain); + } else { + dw_apb_ictl_irq_domain = domain; + set_handle_irq(dw_apb_ictl_handle_irq); + } return 0; From patchwork Tue Sep 8 07:11:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249276 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp4304021ilg; Tue, 8 Sep 2020 00:12:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjADHEmVABRKv0eFF3FDXwCBrN627Ya8QBvxONROPfmlqT9E5V9P8Ay1/+Kibp6aUv1/su X-Received: by 2002:a50:fd19:: with SMTP id i25mr25882293eds.142.1599549176773; Tue, 08 Sep 2020 00:12:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599549176; cv=none; d=google.com; s=arc-20160816; b=bpGOtLu3oCPcghHvXBiLhh90sy8wc49xfwila2Z5J1p6rTxegWLIv/16fzDBdDI6BT OtJbOv2HSQKR7bZzZI/jTHqDN8zRGYNDg/l94MdN3ulwuvjk+SPgTYxDXdEjGj/QIVzM y47/vGWfTP7dqNmX/czVzW6RZWpwMg/A4SKP2QIqTpkSunWOsJ/dQCGGknMkdi7T751s BLo2LExYxhJYSLTLxSumbzNTnKv0yGVcP1SFN6HZRHih3same3F10xOvVNg+TeOCRV4E 6pLqvk/CbkWgrv6WaVqq7qHBGkM18w8u6i35Vmrkgk0+A0gPnBSQAb86s07pUT9d1k6o WqVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=iUstKOcRXWvctkwm7cmQ8UcU2WOqTT8VxzBSfwidEoc=; b=awyp/pkSEdbR9PTIGJoVhrx5nfKB4DQqluZKJkbNCkYDO3qXNZr98TcXqXlVgrxhh7 yNpWuzB1xLd9WHirUAr0YUfPlaohFpH2EV21JaOSDTHAD2+ITDRFPUSBx/+K1E0PRhhN BCUOgX0qRcbj395Z5SiHElox3jFG9+FpaOL3j1g1I/1Me0jjjwPEdE99ZTxfabT8NAn1 eqs8iBHS6VUoeF5K4iM5niVbgtf4kfPIw5IfM+wYOenRKW4GywYRtRgS7UzeqgMrzuBq wPccd0YmSZ28KtooSyDZoX8vTXKyaAh46BGCuOYpv7FIZLaIBhqr6IXrdOg4m0q5rLMz FQ4w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x15si11076770eje.180.2020.09.08.00.12.56; Tue, 08 Sep 2020 00:12:56 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728562AbgIHHMs (ORCPT + 6 others); Tue, 8 Sep 2020 03:12:48 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:57894 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729028AbgIHHMk (ORCPT ); Tue, 8 Sep 2020 03:12:40 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 69EFF89B22D7942ADF0F; Tue, 8 Sep 2020 15:12:36 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Tue, 8 Sep 2020 15:12:29 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang Subject: [PATCH v2 3/3] dt-bindings: dw-apb-ictl: support hierarchy irq domain Date: Tue, 8 Sep 2020 15:11:34 +0800 Message-ID: <20200908071134.2578-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200908071134.2578-1-thunder.leizhen@huawei.com> References: <20200908071134.2578-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to use dw-apb-ictl as primary interrupt controller. Signed-off-by: Zhen Lei --- .../interrupt-controller/snps,dw-apb-ictl.txt | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.26.0.106.g9fadedd diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt index 086ff08322db..2db59df9408f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt @@ -2,7 +2,8 @@ Synopsys DesignWare APB interrupt controller (dw_apb_ictl) Synopsys DesignWare provides interrupt controller IP for APB known as dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with -APB bus, e.g. Marvell Armada 1500. +APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt +controller in some SoCs, e.g. Hisilicon SD5203. Required properties: - compatible: shall be "snps,dw-apb-ictl" @@ -10,6 +11,8 @@ Required properties: region starting with ENABLE_LOW register - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 + +Additional required property when it's used as secondary interrupt controller: - interrupts: interrupt reference to primary interrupt controller The interrupt sources map to the corresponding bits in the interrupt @@ -21,6 +24,7 @@ registers, i.e. - (optional) fast interrupts start at 64. Example: + /* dw_apb_ictl is used as secondary interrupt controller */ aic: interrupt-controller@3000 { compatible = "snps,dw-apb-ictl"; reg = <0x3000 0xc00>; @@ -29,3 +33,11 @@ Example: interrupt-parent = <&gic>; interrupts = ; }; + + /* dw_apb_ictl is used as primary interrupt controller */ + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + };