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[209.51.188.17]) by mx.google.com with ESMTPS id s12si12511923ybq.79.2020.09.07.10.51.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Sep 2020 10:51:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LV9zaVyX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFLIX-0004j8-Mf for patch@linaro.org; Mon, 07 Sep 2020 13:51:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFLIM-0004gN-Ea for qemu-devel@nongnu.org; Mon, 07 Sep 2020 13:51:10 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:41269) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFLIK-0000kg-Kp for qemu-devel@nongnu.org; Mon, 07 Sep 2020 13:51:10 -0400 Received: by mail-pl1-x636.google.com with SMTP id m15so3629984pls.8 for ; Mon, 07 Sep 2020 10:51:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NuEz6+kQZUq9cGZGZ8oi5i58Pnr2fh1fXAdy37NU5ys=; b=LV9zaVyXYmWOFcrXW8qLRPjefXaUPDgRXYfR6LkdmJjQKTWb3+JnCnEVvrVEPrGqnR vaKF1BN6hQsBVFLlDTJeYbqr2e7fxBJWyixmf0I2RIlk46KfKt8d1sLw2J8xGD7HOSiP 393pqmux0y3BG87L8AK4+RTV4SOWu7qdqIgTAm89u5Y8JA+rQ8V4AU9wePuCZ+tN/OMh mEQlirpLEWEb6dAVUxVW5qP04QQ+xPQqwmwec0f/qVSdTE46OAZgt6A8yV0vVwkrtd2q fY90OE/7P+q6gW92WxPjd0Rt4LVzIU6UrqfqTAyHGQBM84ciK5V1gWNZtRBZ/FzMpyxR eYzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NuEz6+kQZUq9cGZGZ8oi5i58Pnr2fh1fXAdy37NU5ys=; b=XuzxoAUOT9pTVa9amxiudqD5k6bvQFGeY0Kmy53KBWa9wRIabPZiMXKxR6s8bapxnF yJksNkITB9Vyj6TknGYC7kISH59/BHgiEzf+fJ3ySP/waRZHwyi3IlvWlkAKmlrlUo9m O4gqTkgwwmO+tU4h8+OUdulBqf9ClFab6OgFK0imY8YaVDe3UTFYhiWBnnOhpuFeL4lH 3JRx+JyKW9ixCcwFyWkndPM1OtcXnhPGBSLMNJzh1A7CAcUjoYRyOUa/r3q/E1i2Ugsu xT/G29ZZwrRGG1BesLu4CNevquA8/gcYLIsRcFiZs1aYX6zcxfEEk/+BuztpYyHlxn2l bmDQ== X-Gm-Message-State: AOAM532W+9B6oI59hf/6qqH1FKNce3FNQmbctqz73jUFubPd+lEvQPmb 7IC8zFnkDb5YpyVW/Mnx2r1Huj2ZT8OKJA== X-Received: by 2002:a17:90a:4481:: with SMTP id t1mr328460pjg.167.1599501066779; Mon, 07 Sep 2020 10:51:06 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id ga3sm1651496pjb.18.2020.09.07.10.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2020 10:51:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/19] target/microblaze: Collected fixes for env->iflags Date: Mon, 7 Sep 2020 10:50:44 -0700 Message-Id: <20200907175102.28027-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200907175102.28027-1-richard.henderson@linaro.org> References: <20200907175102.28027-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org, Thomas Huth Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are several problems here that can result in soft lockup, depending on exactly where an interrupt or exception is delivered: Include BIMM_FLAG in IFLAGS_TB_MASK, since it needs to follow D_FLAG. Ensure that iflags is 0 when entering an interrupt/exception handler. Add mb_cpu_synchronize_from_tb to restore iflags from tb->flags. The change to t_sync_flags is cosmetic, but makes the code clearer. This fixes the reported regression in acceptance/replay_kernel.py. Fixes: 683a247ed7a4 ("target/microblaze: Store "current" iflags in insn_start") Reported-by: Thomas Huth Tested-by: Thomas Huth Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 ++- target/microblaze/cpu.c | 11 +++++++++++ target/microblaze/helper.c | 17 +++++++++++------ target/microblaze/translate.c | 4 ++-- 4 files changed, 26 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d11b6fa995..a25a2b427f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -270,7 +270,8 @@ struct CPUMBState { #define D_FLAG (1 << 19) /* Bit in ESR. */ /* TB dependent CPUMBState. */ -#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) +#define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \ + DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) #define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE) uint32_t iflags; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 67017ecc33..6392524135 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -80,6 +80,16 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); cpu->env.pc = value; + /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */ + cpu->env.iflags = 0; +} + +static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + + cpu->env.pc = tb->pc; + cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; } static bool mb_cpu_has_work(CPUState *cs) @@ -321,6 +331,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; + cc->synchronize_from_tb = mb_cpu_synchronize_from_tb; cc->gdb_read_register = mb_cpu_gdb_read_register; cc->gdb_write_register = mb_cpu_gdb_write_register; cc->tlb_fill = mb_cpu_tlb_fill; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 48547385b0..00090526da 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -113,7 +113,10 @@ void mb_cpu_do_interrupt(CPUState *cs) uint32_t t, msr = mb_cpu_read_msr(env); /* IMM flag cannot propagate across a branch and into the dslot. */ - assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); + assert((env->iflags & (D_FLAG | IMM_FLAG)) != (D_FLAG | IMM_FLAG)); + /* BIMM flag cannot be set without D_FLAG. */ + assert((env->iflags & (D_FLAG | BIMM_FLAG)) != BIMM_FLAG); + /* RTI flags are private to translate. */ assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); env->res_addr = RES_ADDR_NONE; switch (cs->exception_index) { @@ -146,7 +149,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->pc, env->ear, env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags &= ~(IMM_FLAG | D_FLAG); + env->iflags = 0; env->pc = cpu->cfg.base_vectors + 0x20; break; @@ -186,14 +189,14 @@ void mb_cpu_do_interrupt(CPUState *cs) "exception at pc=%x ear=%" PRIx64 " iflags=%x\n", env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags &= ~(IMM_FLAG | D_FLAG); + env->iflags = 0; env->pc = cpu->cfg.base_vectors + 0x20; break; case EXCP_IRQ: assert(!(msr & (MSR_EIP | MSR_BIP))); assert(msr & MSR_IE); - assert(!(env->iflags & D_FLAG)); + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); t = (msr & (MSR_VM | MSR_UM)) << 1; @@ -226,13 +229,14 @@ void mb_cpu_do_interrupt(CPUState *cs) mb_cpu_write_msr(env, msr); env->regs[14] = env->pc; + env->iflags = 0; env->pc = cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; case EXCP_HW_BREAK: - assert(!(env->iflags & IMM_FLAG)); - assert(!(env->iflags & D_FLAG)); + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); + t = (msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=%x msr=%x %x iflags=%x\n", @@ -242,6 +246,7 @@ void mb_cpu_do_interrupt(CPUState *cs) msr |= t; msr |= MSR_BIP; env->regs[16] = env->pc; + env->iflags = 0; env->pc = cpu->cfg.base_vectors + 0x18; mb_cpu_write_msr(env, msr); break; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a377818b5e..a8a3249185 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -91,8 +91,8 @@ static int typeb_imm(DisasContext *dc, int x) static void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ - if ((dc->tb_flags ^ dc->base.tb->flags) & ~MSR_TB_MASK) { - tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & ~MSR_TB_MASK); + if ((dc->tb_flags ^ dc->base.tb->flags) & IFLAGS_TB_MASK) { + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & IFLAGS_TB_MASK); } } From patchwork Mon Sep 7 17:50:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249244 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3882262ilg; Mon, 7 Sep 2020 10:53:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw54VhXRWhNu3ViW8wpe41JeXg4Uy9Z2EhjpCGLCEAbAK6xiHWIdakqQjGqqzQfi5Loxj/P X-Received: by 2002:a25:3802:: with SMTP id f2mr4647712yba.118.1599501196498; Mon, 07 Sep 2020 10:53:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599501196; cv=none; d=google.com; s=arc-20160816; b=iGC8SjhEYam4aLsSpAlArl+R1s/oCQF+sHDQoDFKMf/eVjEKxpUFheCSNPauLDUx5p mLZGyV5XJ4YjqhpHkARk8/bQM1JVL4bjq3S8NJoHEDTstwiJlnj4dG8dFSJp2XK8//4t iVMHsyos4P34iMoobAm+giJYK2WANmM4443KbaZYcXIkQPrk6L0Y/sqkgmWP1YR9ehvk gcpYz2dfGS585LaNuw8en/WS/8wzTE3vKCMl48bULY5yNCANkFavq+CQekU5yKXSepAN zYwpXHLzy+BNawOjdMn1ouHTURo4hPwAoQGiTjHuiaG1iBNOwrSX0pWiTNxiOFg6t+aK 6UsQ== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id k186si16432882yba.105.2020.09.07.10.53.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Sep 2020 10:53:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fGvT2kbK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFLKN-0007tD-SO for patch@linaro.org; Mon, 07 Sep 2020 13:53:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFLIN-0004iK-Js for qemu-devel@nongnu.org; Mon, 07 Sep 2020 13:51:11 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:38449) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFLIM-0000kr-1t for qemu-devel@nongnu.org; Mon, 07 Sep 2020 13:51:11 -0400 Received: by mail-pj1-x1044.google.com with SMTP id u3so3537125pjr.3 for ; Mon, 07 Sep 2020 10:51:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m0GTL/th73zAOOPhUOn5M7H75WJeN6n2LDCntpwQd3k=; b=fGvT2kbKCBaFQi2Rrgx/fsZPReKvG5KXhBI6xTxJLxqCFYSTapIKMnqawf0EnA39gz 2OKbTB1q2mFe21dxLrOT94EedmO24v95I7sAT98aRrbU4DYBtKRTb6w+LgXWqWoTZtTz vQyfmHeLSxLjA3huYrwqvysX8GLQu7zaNnXzejNzg7y78v4/1kthwUdSHjYPT4U5Zq26 lFpkBEwHP/L/S8UzksFR6iS81NKVzQuU+rJ6sKCwHfnRO+cVCG2oE6ILQrhABZ+UVpeC WELkmSsIHc7fvh+g7APGrxUJ4WozKAQ+snMKH/Mqf9AEL69rjGZr+ySS9URDHea5ujHN uOBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m0GTL/th73zAOOPhUOn5M7H75WJeN6n2LDCntpwQd3k=; b=Pf5kR62WGragOV4JijZ54zQdn8KVfY11T5QYOiP7PWZPvzMWbU4jkmaeJHJOGds9QV yaJy3L1EOT70HdOxTDYq0pQ6/5PqXP5Dram+dwAWMhYz3ju+ktg9fYIW+74lo+86E/1l j5wUOcLBVNUdjj31PPpiwCLSLUxpDeMw2B4GRoC0MO3D2ik8lH3naDzAvVCAVp0yJsVx IfyZjCHceEqvDDs066wmQ3UNoGB0dLAmu1TIdVOoAl1SvvEOwYra5dsKybJPBpDYm6iz 8BOvYVAatuCreoBMsETICJMMgW4bKtHU3Yw6a7yfHHPqJh+YB+TTNoUZDEU5T7Ug4gbl qY2A== X-Gm-Message-State: AOAM5338gcLOaarMhxj2JRpS4ql6vSz5fzD5F0zRVKT6hELKIiQipSZk HzFcINnLyf2XCfyawA2uIsuxKIPuBfmoHg== X-Received: by 2002:a17:90a:e391:: with SMTP id b17mr361934pjz.127.1599501067954; Mon, 07 Sep 2020 10:51:07 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id ga3sm1651496pjb.18.2020.09.07.10.51.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2020 10:51:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 02/19] target/microblaze: Renumber D_FLAG Date: Mon, 7 Sep 2020 10:50:45 -0700 Message-Id: <20200907175102.28027-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200907175102.28027-1-richard.henderson@linaro.org> References: <20200907175102.28027-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ESS[DS] is bit 19 in the manual, but the manual uses big-endian bit numbering. This corresponds to bit 12 in little-endian numbering. Let the comment about matching the ESR be true by renumbering it. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a25a2b427f..32811f773d 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -264,10 +264,10 @@ struct CPUMBState { /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ /* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */ +#define D_FLAG (1 << 12) /* Bit in ESR. */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) -#define D_FLAG (1 << 19) /* Bit in ESR. */ /* TB dependent CPUMBState. */ #define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \ From patchwork Mon Sep 7 17:50:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249245 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3882950ilg; Mon, 7 Sep 2020 10:54:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJ4qWDyySA1UwChF45023UKtuUx7oMGhEDnt9fxFJ9Gj2ujmAUYFlhXWAxR+Hb1AyYzwjq X-Received: by 2002:a25:d304:: with SMTP id e4mr28506633ybf.226.1599501261762; Mon, 07 Sep 2020 10:54:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599501261; cv=none; d=google.com; s=arc-20160816; b=0iUL9OYvc+90mmUE9c5v3pKs8s9lyJi61qIKxj/HjDzjY88rqTW5ItQy1i+3MC+/5U y/gzHB8krTWGutbjSalqTmC/Dsqm7QU3WQkd6FS5dMmNrwdTVzmsDCK0t+whWW2kRVEa jSL4Ig5x+H9tNFwWBmCdfGNTO8hP5ytguzPvP8GrWLuZ6mb2b1B+9ITeyqWHnXM1Wm5z m3IPM+wA+6fFis+qGJeGEJrGdnAxcm2GiEutHuRpL2figZ3WjREzFbXPb+L24t7bEmnH q3kv7DQkljFtLbL0uJjtlMIR+qhi6SbPBTtKCBNO1gWXy+FGaq9O4KDRBlpRoIwxyT59 j2HQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/yXJpGcM0pySBVNaBLwWnb+hh8s1YFgeVBC/jzYWhxA=; b=bM8U9RKOe5IfEsye9H1IK3TKzZvzyo7VEY2Hsy0O2eppbC4Q/+iUXBR8wDTv82uPbG kjopLDCop7Z6CcIsi7iHWO7axvUiT5Ek2ZDJ2Kc86uP32MB5qTIZOOzFMFZ6VvzpxPAY QMCusC9P5Y1SYNpYGHSkX7dJoGYFzBImbs0FbB5tOkx/3D5VcYxhUw68/1bPApk9hOd6 ZbuNhOBjNS/RQzWaaFv5gIV9ihx9zJtxRO5Lp8i5vAv5s+dEDRBHZYeqDZE4G5wVDX4I CTTellquj/ajDxchRc12mTVmUBHsU1yO4kT7Nn95QzfdDfEhB5bL3iiCHTo59nsQk5wj lfUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Y9LgytcN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reindent; remove dead/commented code. Use D_FLAG to set ESS[DS]. Sink MSR adjustment for kernel entry, iflags and res_addr clear. Improve CPU_LOG_INT formatting; report pc and msr before and after. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.c | 209 ++++++++++++++++--------------------- 1 file changed, 91 insertions(+), 118 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 00090526da..27a24bb99a 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -111,6 +111,7 @@ void mb_cpu_do_interrupt(CPUState *cs) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; uint32_t t, msr = mb_cpu_read_msr(env); + bool set_esr; /* IMM flag cannot propagate across a branch and into the dslot. */ assert((env->iflags & (D_FLAG | IMM_FLAG)) != (D_FLAG | IMM_FLAG)); @@ -118,142 +119,114 @@ void mb_cpu_do_interrupt(CPUState *cs) assert((env->iflags & (D_FLAG | BIMM_FLAG)) != BIMM_FLAG); /* RTI flags are private to translate. */ assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); - env->res_addr = RES_ADDR_NONE; + switch (cs->exception_index) { - case EXCP_HW_EXCP: - if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { - qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n"); - return; - } + case EXCP_HW_EXCP: + if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Exception raised on system without exceptions!\n"); + return; + } - env->regs[17] = env->pc + 4; - env->esr &= ~(1 << 12); + qemu_log_mask(CPU_LOG_INT, + "INT: HWE at pc=%08x msr=%08x iflags=%x\n", + env->pc, msr, env->iflags); - /* Exception breaks branch + dslot sequence? */ - if (env->iflags & D_FLAG) { - env->esr |= 1 << 12 ; - env->btr = env->btarget; - } + /* Exception breaks branch + dslot sequence? */ + set_esr = true; + env->esr &= ~D_FLAG; + if (env->iflags & D_FLAG) { + env->esr |= D_FLAG; + env->btr = env->btarget; + } - /* Disable the MMU. */ - t = (msr & (MSR_VM | MSR_UM)) << 1; - msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - msr |= t; - /* Exception in progress. */ - msr |= MSR_EIP; - mb_cpu_write_msr(env, msr); + /* Exception in progress. */ + msr |= MSR_EIP; + env->regs[17] = env->pc + 4; + env->pc = cpu->cfg.base_vectors + 0x20; + break; - qemu_log_mask(CPU_LOG_INT, - "hw exception at pc=%x ear=%" PRIx64 " " - "esr=%x iflags=%x\n", - env->pc, env->ear, - env->esr, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags = 0; - env->pc = cpu->cfg.base_vectors + 0x20; - break; + case EXCP_MMU: + qemu_log_mask(CPU_LOG_INT, + "INT: MMU at pc=%08x msr=%08x " + "ear=%" PRIx64 " iflags=%x\n", + env->pc, msr, env->ear, env->iflags); - case EXCP_MMU: + /* Exception breaks branch + dslot sequence? */ + set_esr = true; + env->esr &= ~D_FLAG; + if (env->iflags & D_FLAG) { + env->esr |= D_FLAG; + env->btr = env->btarget; + /* Reexecute the branch. */ + env->regs[17] = env->pc - (env->iflags & BIMM_FLAG ? 8 : 4); + } else if (env->iflags & IMM_FLAG) { + /* Reexecute the imm. */ + env->regs[17] = env->pc - 4; + } else { env->regs[17] = env->pc; + } - qemu_log_mask(CPU_LOG_INT, - "MMU exception at pc=%x iflags=%x ear=%" PRIx64 "\n", - env->pc, env->iflags, env->ear); + /* Exception in progress. */ + msr |= MSR_EIP; + env->pc = cpu->cfg.base_vectors + 0x20; + break; - env->esr &= ~(1 << 12); - /* Exception breaks branch + dslot sequence? */ - if (env->iflags & D_FLAG) { - env->esr |= 1 << 12 ; - env->btr = env->btarget; + case EXCP_IRQ: + assert(!(msr & (MSR_EIP | MSR_BIP))); + assert(msr & MSR_IE); + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); - /* Reexecute the branch. */ - env->regs[17] -= 4; - /* was the branch immprefixed?. */ - if (env->iflags & BIMM_FLAG) { - env->regs[17] -= 4; - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - } - } else if (env->iflags & IMM_FLAG) { - env->regs[17] -= 4; - } + qemu_log_mask(CPU_LOG_INT, + "INT: DEV at pc=%08x msr=%08x iflags=%x\n", + env->pc, msr, env->iflags); + set_esr = false; - /* Disable the MMU. */ - t = (msr & (MSR_VM | MSR_UM)) << 1; - msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - msr |= t; - /* Exception in progress. */ - msr |= MSR_EIP; - mb_cpu_write_msr(env, msr); + /* Disable interrupts. */ + msr &= ~MSR_IE; + env->regs[14] = env->pc; + env->pc = cpu->cfg.base_vectors + 0x10; + break; - qemu_log_mask(CPU_LOG_INT, - "exception at pc=%x ear=%" PRIx64 " iflags=%x\n", - env->pc, env->ear, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags = 0; - env->pc = cpu->cfg.base_vectors + 0x20; - break; + case EXCP_HW_BREAK: + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); - case EXCP_IRQ: - assert(!(msr & (MSR_EIP | MSR_BIP))); - assert(msr & MSR_IE); - assert(!(env->iflags & (D_FLAG | IMM_FLAG))); + qemu_log_mask(CPU_LOG_INT, + "INT: BRK at pc=%08x msr=%08x iflags=%x\n", + env->pc, msr, env->iflags); + set_esr = false; - t = (msr & (MSR_VM | MSR_UM)) << 1; + /* Break in progress. */ + msr |= MSR_BIP; + env->regs[16] = env->pc; + env->pc = cpu->cfg.base_vectors + 0x18; + break; -#if 0 -#include "disas/disas.h" + default: + cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); + /* not reached */ + } -/* Useful instrumentation when debugging interrupt issues in either - the models or in sw. */ - { - const char *sym; + /* Save previous mode, disable mmu, disable user-mode. */ + t = (msr & (MSR_VM | MSR_UM)) << 1; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; + mb_cpu_write_msr(env, msr); - sym = lookup_symbol(env->pc); - if (sym - && (!strcmp("netif_rx", sym) - || !strcmp("process_backlog", sym))) { + env->res_addr = RES_ADDR_NONE; + env->iflags = 0; - qemu_log("interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->pc, msr, t, env->iflags, sym); - - log_cpu_state(cs, 0); - } - } -#endif - qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%x msr=%x %x iflags=%x\n", - env->pc, msr, t, env->iflags); - - msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); - msr |= t; - mb_cpu_write_msr(env, msr); - - env->regs[14] = env->pc; - env->iflags = 0; - env->pc = cpu->cfg.base_vectors + 0x10; - //log_cpu_state_mask(CPU_LOG_INT, cs, 0); - break; - - case EXCP_HW_BREAK: - assert(!(env->iflags & (D_FLAG | IMM_FLAG))); - - t = (msr & (MSR_VM | MSR_UM)) << 1; - qemu_log_mask(CPU_LOG_INT, - "break at pc=%x msr=%x %x iflags=%x\n", - env->pc, msr, t, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - msr |= t; - msr |= MSR_BIP; - env->regs[16] = env->pc; - env->iflags = 0; - env->pc = cpu->cfg.base_vectors + 0x18; - mb_cpu_write_msr(env, msr); - break; - default: - cpu_abort(cs, "unhandled exception type=%d\n", - cs->exception_index); - break; + if (!set_esr) { + qemu_log_mask(CPU_LOG_INT, + " to pc=%08x msr=%08x\n", env->pc, msr); + } else if (env->esr & D_FLAG) { + qemu_log_mask(CPU_LOG_INT, + " to pc=%08x msr=%08x esr=%04x btr=%08x\n", + env->pc, msr, env->esr, env->btr); + } else { + qemu_log_mask(CPU_LOG_INT, + " to pc=%08x msr=%08x esr=%04x\n", + env->pc, msr, env->esr); } } From patchwork Mon Sep 7 17:50:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249243 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3882012ilg; Mon, 7 Sep 2020 10:52:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpWEgyf5BjQhxkCw7RzVu2rOYrtVCrfgaXfK3NB5omSI6BYmEduQjjhMj2MbvExsT4BRjb X-Received: by 2002:a25:250b:: with SMTP id l11mr21015708ybl.253.1599501169942; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Introduce typedefs and follow CODING_STYLE for naming. Rename struct microblaze_mmu to MicroBlazeMMU. Rename struct microblaze_mmu_lookup to MicroBlazeMMULookup. Tested-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/mmu.h | 15 ++++++--------- target/microblaze/helper.c | 4 ++-- target/microblaze/mmu.c | 11 +++++------ 4 files changed, 14 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 32811f773d..20c2979396 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -278,7 +278,7 @@ struct CPUMBState { #if !defined(CONFIG_USER_ONLY) /* Unified MMU. */ - struct microblaze_mmu mmu; + MicroBlazeMMU mmu; #endif /* Fields up to this point are cleared by a CPU reset */ diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 75e5301c79..c1feb811b9 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -63,8 +63,7 @@ #define TLB_ENTRIES 64 -struct microblaze_mmu -{ +typedef struct { /* Data and tag brams. */ uint64_t rams[2][TLB_ENTRIES]; /* We keep a separate ram for the tids to avoid the 48 bit tag width. */ @@ -76,10 +75,9 @@ struct microblaze_mmu int c_mmu_tlb_access; int c_mmu_zones; uint64_t c_addr_mask; /* Mask to apply to physical addresses. */ -}; +} MicroBlazeMMU; -struct microblaze_mmu_lookup -{ +typedef struct { uint32_t paddr; uint32_t vaddr; unsigned int size; @@ -88,13 +86,12 @@ struct microblaze_mmu_lookup enum { ERR_PROT, ERR_MISS, ERR_HIT } err; -}; +} MicroBlazeMMULookup; -unsigned int mmu_translate(struct microblaze_mmu *mmu, - struct microblaze_mmu_lookup *lu, +unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, target_ulong vaddr, int rw, int mmu_idx); uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v); -void mmu_init(struct microblaze_mmu *mmu); +void mmu_init(MicroBlazeMMU *mmu); #endif diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 27a24bb99a..3c2fd388fb 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -52,7 +52,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; - struct microblaze_mmu_lookup lu; + MicroBlazeMMULookup lu; unsigned int hit; int prot; @@ -235,7 +235,7 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; target_ulong vaddr, paddr = 0; - struct microblaze_mmu_lookup lu; + MicroBlazeMMULookup lu; int mmu_idx = cpu_mmu_index(env, false); unsigned int hit; diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 6e583d78d9..0546cfd0bc 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -35,7 +35,7 @@ static unsigned int tlb_decode_size(unsigned int f) static void mmu_flush_idx(CPUMBState *env, unsigned int idx) { CPUState *cs = env_cpu(env); - struct microblaze_mmu *mmu = &env->mmu; + MicroBlazeMMU *mmu = &env->mmu; unsigned int tlb_size; uint32_t tlb_tag, end, t; @@ -55,7 +55,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx) static void mmu_change_pid(CPUMBState *env, unsigned int newpid) { - struct microblaze_mmu *mmu = &env->mmu; + MicroBlazeMMU *mmu = &env->mmu; unsigned int i; uint32_t t; @@ -73,8 +73,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid) } /* rw - 0 = read, 1 = write, 2 = fetch. */ -unsigned int mmu_translate(struct microblaze_mmu *mmu, - struct microblaze_mmu_lookup *lu, +unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, target_ulong vaddr, int rw, int mmu_idx) { unsigned int i, hit = 0; @@ -290,7 +289,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) break; case MMU_R_TLBSX: { - struct microblaze_mmu_lookup lu; + MicroBlazeMMULookup lu; int hit; if (env->mmu.c_mmu_tlb_access <= 1) { @@ -314,7 +313,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) } } -void mmu_init(struct microblaze_mmu *mmu) +void mmu_init(MicroBlazeMMU *mmu) { int i; for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) { From patchwork Mon Sep 7 17:50:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249240 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3881113ilg; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The name "update" suggests that something needs updating, but this is not the case. Use "exit" to emphasize that nothing needs doing except to exit. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a8a3249185..8ceb04f4f0 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -37,7 +37,7 @@ /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ -#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_EXIT DISAS_TARGET_1 /* all cpu state modified dynamically */ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; @@ -1161,7 +1161,7 @@ static bool trans_brk(DisasContext *dc, arg_typea_br *arg) tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP); tcg_gen_movi_tl(cpu_res_addr, -1); - dc->base.is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_EXIT; return true; } @@ -1202,7 +1202,7 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM)); } tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set); - dc->base.is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_EXIT; #endif return true; @@ -1712,7 +1712,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) /* Force an exit if the per-tb cpu state has changed. */ if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) { - dc->base.is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_EXIT; tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); } } @@ -1733,7 +1733,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) gen_goto_tb(dc, 0, dc->base.pc_next); return; - case DISAS_UPDATE: + case DISAS_EXIT: if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { From patchwork Mon Sep 7 17:50:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249248 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3883711ilg; Mon, 7 Sep 2020 10:55:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxmzGmYcK64uYRiGYkEmhGPDl471/yNzzYqWXrTKw4IvexDbUAG8egpyhh1l0hB2ezf8hpj X-Received: by 2002:a25:8512:: with SMTP id w18mr4267432ybk.432.1599501349657; Mon, 07 Sep 2020 10:55:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599501349; cv=none; d=google.com; s=arc-20160816; b=oO+kX3jMyqDcJdIb0CRkXwLfB6u256FNRPlAIAurtLitZhjHXvFwsOh5d3sHL4F694 pydMTXE8i6uLYWzWrNKnhE1Nb9v6vXG8ogXzhIhSGEALd+DPFGrKsiizWbhzyjY3DMqM vsG2E+h1s8M8985iQtbfQzdMkjeZ677x+6AUcxcjzxWxcYnYv0ZauarKl2M2p1kuXrjz KpQpo5B1QvGQVoRggkL6gYMkM4IrqZm4GYx33HLgyJjU6fIkFcidUzkNs4P0o/aqmy5d SYxIJkv1DHK+yfZcdyyAVAWSAsb9fWSpyFAb+PFw5QmiHXS5OjMLa8nyN0lObL8NPlE0 JWUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qxvKwmePa50MKIg8eLv8VBXTLXGDs/q8gqEzTKISHeQ=; b=x/KF7Kkzm9ljwm/9tMBiAJwEp2jRPtUtssxWDZJMHQ4IB3S/TewnjSWBX381dzUVog UCdeGy51u89hPjVUGRJqLDCmBD9xdz9oosSHkkFxYwawdY6L451zH1B4EyJm20AUwMxP 8FkfsiTniImf4air+Rrx7zm8Wz6bxMZ+j++oahjbTZIcCugoljMJmgi4DjFD5tfAIJPE fh82+kc2lj+7A0FGOp8nC53h+Y0yG2p8NIG8MeSt+GtXt/8TKmSVZBx5D6QuVSkwFB5Y q2iyGe5FT/0ivEYUsDoeo5dYwzliZNke0VdvLlh1mTgbL5TM4GLlD/03tAMdOASdFqoH nF7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BH0RYrek; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Like DISAS_EXIT, except we need to update cpu_pc, either to pc_next or to btarget respectively. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8ceb04f4f0..2abef328a3 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -39,6 +39,11 @@ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_EXIT DISAS_TARGET_1 /* all cpu state modified dynamically */ +/* cpu state besides pc was modified dynamically; update pc to next */ +#define DISAS_EXIT_NEXT DISAS_TARGET_2 +/* cpu state besides pc was modified dynamically; update pc to btarget */ +#define DISAS_EXIT_JUMP DISAS_TARGET_3 + static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; @@ -1712,8 +1717,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) /* Force an exit if the per-tb cpu state has changed. */ if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) { - dc->base.is_jmp = DISAS_EXIT; - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + dc->base.is_jmp = DISAS_EXIT_NEXT; } } @@ -1734,12 +1738,14 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) return; case DISAS_EXIT: - if (unlikely(cs->singlestep_enabled)) { - gen_raise_exception(dc, EXCP_DEBUG); - } else { - tcg_gen_exit_tb(NULL, 0); - } - return; + break; + case DISAS_EXIT_NEXT: + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + break; + case DISAS_EXIT_JUMP: + tcg_gen_mov_i32(cpu_pc, cpu_btarget); + tcg_gen_discard_i32(cpu_btarget); + break; case DISAS_JUMP: if (dc->jmp_dest != -1 && !cs->singlestep_enabled) { @@ -1781,6 +1787,13 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) default: g_assert_not_reached(); } + + /* Finish DISAS_EXIT_* */ + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } } static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) From patchwork Mon Sep 7 17:50:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249246 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3883164ilg; Mon, 7 Sep 2020 10:54:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxkNkeeusz3KP88lFOzSouPLo6KKctCVNrVTshqynOq2m4P14d4uSDpRDOOHLtfzCMOAW0g X-Received: by 2002:a25:4fc2:: with SMTP id d185mr4079734ybb.108.1599501286481; Mon, 07 Sep 2020 10:54:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599501286; cv=none; d=google.com; s=arc-20160816; b=W4uiujUSNkQWwNucVusWulZqtWB1eQi2z3imHUOWylO/IbiPbj8KycC8qljxDYFngx gY0y2vQGRuMq7ujRb8t/pyj4mjnH3Nl8WAyFsR8fWg4UXdYhjx9KlJkGupsVLJuGF/ZS mMX4JcaOATDkFKFB5XNLvLzWJ/l6XnEgZ84/NOhhhro7HgL1CBxTb/i+hxyj98dG+nKg HPzyuW92sHSD9BBKCrjniXRjl7OwAWTXussHcllHGHwvboaz1uvzmQB/raDmY1NoFjmZ NtVrRg///CVRfyW2F6t3W34XlEjnWICPBPgYOod9rsITsjjXABM7Ixd25GWJw/45dMCy V6hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Lzoy3rQTW8RpzNKU3s0YRAjNrkjr7LKa4OsZvtm8Vk0=; b=mbEGs059St02wu7B+F+8JatnkPfdpMlDtbNPOcPwMIjqwyumjEO/UU1VBYHIkbpVjc KQ6FmsDa3fRf+JIWV/Pc49cKcBJC44F8ftv5lITt3w+np7cSIZB7RodsReRV2VGjmOqx qypgJrcvE/sY1awYVeD6euMehJxN4ncHiBReKdAqqWdyzJoZpJx4T+us3JRnIHgUSmvM CSHLUHAoXo7B3WP4LBy4mFrAuWvfNgeEUpHhgXchoWAHyxCxY7pM9OAS40CP5/dZ2EP8 cT8syxPaV2PPm7CSf9fvRWDDqQiCia07mrF9ZIfvbmcM1Js3FiitPQ3xHOa7GetApin+ 501A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FXKclDuR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p203si16956635ybg.152.2020.09.07.10.54.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Sep 2020 10:54:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FXKclDuR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFLLp-0002pA-V6 for patch@linaro.org; Mon, 07 Sep 2020 13:54:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFLIT-0004xc-Vn for qemu-devel@nongnu.org; Mon, 07 Sep 2020 13:51:18 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46806) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFLIR-0000lU-TX for qemu-devel@nongnu.org; Mon, 07 Sep 2020 13:51:17 -0400 Received: by mail-pg1-x541.google.com with SMTP id 31so8298286pgy.13 for ; Mon, 07 Sep 2020 10:51:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lzoy3rQTW8RpzNKU3s0YRAjNrkjr7LKa4OsZvtm8Vk0=; b=FXKclDuRErCsGJCxtLXBHvHIyRfpReqKcePsLnFqVbmRceh/K6EsEcD3OX7wbJ5Ns/ 6F5jD11Oze0ckYBxyNF+UuL0Ugw9plDynhLt1zFzjQxPiFWDp4Q1R6O1JuxlwLBWdC9P PNJZ9FmLymIPTL8wv27RVoAf7r/eRgkX5sC/hE8xkWA7Kbd8DZ0QX2//mpuCMqYrunXc Labq5tvhclb5lPBN7gMmPvxaP25lc1j+sWt0+ye+lH30TrN13Xx0/a9zylYPk2d4IfBc Q7uVDM3klUzvZVNmx9dO8QLn/ug0hEaqOEk/J7Q+bK4tY2DWl9PxsTYFjsW8ZZbukbrm d97w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lzoy3rQTW8RpzNKU3s0YRAjNrkjr7LKa4OsZvtm8Vk0=; b=DB7bA00NgyZTJxXle26PUxAdbFVBbpien71IJhQ2wlGzoXshpLi0aNL8FP0/G/0xgJ K0V1HpcqJcX1U6wt0cftSu970W1zT5niIxHwiAQ/zGUoRwEBsUbLEERoW+51GwW67SFq J2TyYdAcec7f75jU5TkkMYRVmvmNHqk3jiGRuXXUnQJDg9NzesQrgHmAP4VjI04uU2HX 7ewZvNoCMNuJAAS/n90/cwlzsHM+TJjYFobL4BLrxAz0xVzb+y4h2n4NwRRetQ+JmDby 6Kx9QOe5MnWpDOgUGB55mqiQ9iCUrm+U73c3ZuolnGkRsOkn63YGkVR+ITogt994J9/1 KRiw== X-Gm-Message-State: AOAM531HYiq2aBSFttnsTlwStJObTzywf6n1IKAbDsNyE1sjxo0t0Oo/ vmacdEnsgawyAaZPe9t335+/v3EIHJ5dJg== X-Received: by 2002:aa7:9574:: with SMTP id x20mr20661024pfq.191.1599501073966; Mon, 07 Sep 2020 10:51:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id ga3sm1651496pjb.18.2020.09.07.10.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2020 10:51:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/19] target/microblaze: Replace cpustate_changed with DISAS_EXIT_NEXT Date: Mon, 7 Sep 2020 10:50:50 -0700 Message-Id: <20200907175102.28027-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200907175102.28027-1-richard.henderson@linaro.org> References: <20200907175102.28027-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than look for the combination of DISAS_NEXT with a separate variable, go ahead and set is_jmp to the desired state. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 34 ++++++++++------------------------ 1 file changed, 10 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2abef328a3..6bf299a826 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -70,7 +70,6 @@ typedef struct DisasContext { /* Decoder. */ uint32_t ext_imm; - unsigned int cpustate_changed; unsigned int tb_flags; unsigned int tb_flags_to_set; int mem_index; @@ -1255,7 +1254,7 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg) * * Therefore, choose to end the TB always. */ - dc->cpustate_changed = 1; + dc->base.is_jmp = DISAS_EXIT_NEXT; return true; } @@ -1307,19 +1306,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d) tcg_temp_free_i32(t); } -#ifndef CONFIG_USER_ONLY -static void msr_write(DisasContext *dc, TCGv_i32 v) -{ - dc->cpustate_changed = 1; - - /* Install MSR_C. */ - tcg_gen_extract_i32(cpu_msr_c, v, 2, 1); - - /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */ - tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); -} -#endif - static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) { uint32_t imm = arg->imm; @@ -1352,7 +1338,7 @@ static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) } else { tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); } - dc->cpustate_changed = 1; + dc->base.is_jmp = DISAS_EXIT_NEXT; } return true; } @@ -1385,7 +1371,13 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg) TCGv_i32 src = reg_for_read(dc, arg->ra); switch (arg->rs) { case SR_MSR: - msr_write(dc, src); + /* Install MSR_C. */ + tcg_gen_extract_i32(cpu_msr_c, src, 2, 1); + /* + * Clear MSR_C and MSR_CC; + * MSR_PVR is not writable, and is always clear. + */ + tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR)); break; case SR_FSR: tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); @@ -1417,7 +1409,7 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg) qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs); return true; } - dc->cpustate_changed = 1; + dc->base.is_jmp = DISAS_EXIT_NEXT; return true; #endif } @@ -1629,7 +1621,6 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; - dc->cpustate_changed = 0; dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; @@ -1714,11 +1705,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) } dc->base.is_jmp = DISAS_JUMP; } - - /* Force an exit if the per-tb cpu state has changed. */ - if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) { - dc->base.is_jmp = DISAS_EXIT_NEXT; - } } static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) From patchwork Mon Sep 7 17:50:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249242 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3881993ilg; Mon, 7 Sep 2020 10:52:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwaLLQpbVvN2MqbaqZrqWW9z8H8qvt+uALLxPTy5n3ZG7Wkuci5dmv8YiN9lZ2C6+Uqd77l X-Received: by 2002:a25:b292:: with SMTP id k18mr29431228ybj.163.1599501168373; Mon, 07 Sep 2020 10:52:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599501168; cv=none; d=google.com; s=arc-20160816; b=W9BOO9WLctWLrYZvTCym7zPnmdsrX2DkSy3lXt95AWun5IJX1ytOujf5AbVLw6HQb2 irW+RgSyUJoIyBJgVN/06fkIkn2zM2OG3UZj8KeK5StTXm57bofolH4kNj8nMphAiBbd 6jAAg4l4RW2CyXAcQ1/qogtbSAUTDpZQOqxV7n41zJBdCP+QWKW8s/HsuIpFb2TNf5EQ 64z7uNezb5PejMj9Y/oIuqOhimUvfQbdQqcMzdpLZdPY1pFNOFLEuSR1ZyRdjDFaovvT KZwmUp+sHFcwjQkhKnSYDFlsl8g1eRXcwV1Fuj+q3Pl/A8F+Gt/OnO74OaIoYYyLNIZ4 9+Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=C+qOEnrO4mdVdydo87qRuF3WglkeUY/A8QOfETainjE=; b=PCq7TY99yKweeHA6Ub3+SrP2xMoIl2vtjQC/6v4TG5+DErCGKJd+AG10PvaoF98exL E/5kE1XcL1Q0RfktJ8ldGPAozp+ITI+TeL5XU3Iw1K2tnc1ThpMsh0AY1kfy9JtAjNdJ wu8OoX21PX3dt3NYR2yaRMZ7GLE09cGhhi8mCvVRZabwc/JMSGkP34y8v2YhxF2BUVsX CzulVNqijRcp1xCyPYrLLW4mNdjE9LN9ol1sN3Gzh0nuOI1rZrfK+qQ0T/Cav/9WyKw3 14/dSaeAlej9swOyPOepbZTxpl+k4BlravpK8t8ZGsHpkTd/C7UKjKPWs/yFvS96lkv2 Y6Ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tdLsvJqX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It is legal to put an mts instruction into a delay slot. We should continue to return to the main loop in that case so that we recognize any pending interrupts. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6bf299a826..608d413c83 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1696,6 +1696,10 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->base.pc_next += 4; if (dc->jmp_cond != TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { + /* + * Finish any return-from branch. + * TODO: Diagnose rtXd in delay slot of rtYd earlier. + */ if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); } else if (dc->tb_flags & DRTB_FLAG) { @@ -1703,7 +1707,35 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) } else if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } - dc->base.is_jmp = DISAS_JUMP; + + /* Complete the branch, ending the TB. */ + switch (dc->base.is_jmp) { + case DISAS_NORETURN: + /* + * E.g. illegal insn in a delay slot. We've already exited + * and will handle D_FLAG in mb_cpu_do_interrupt. + */ + break; + case DISAS_EXIT: + /* + * TODO: diagnose brk/brki in delay slot earlier. + * This would then fold into the illegal insn case above. + */ + break; + case DISAS_NEXT: + /* Normal insn a delay slot. */ + dc->base.is_jmp = DISAS_JUMP; + break; + case DISAS_EXIT_NEXT: + /* + * E.g. mts insn in a delay slot. Continue with btarget, + * but still return to the main loop. + */ + dc->base.is_jmp = DISAS_EXIT_JUMP; + break; + default: + g_assert_not_reached(); + } } } From patchwork Mon Sep 7 17:50:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249249 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3884724ilg; Mon, 7 Sep 2020 10:57:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFAUP1W1yNQ9+HUOaGPuLFWorMgP1NuDLsL+hgTcv/Rgd/x4L0B3nBQtC5zpmte2YHEH0C X-Received: by 2002:a25:e786:: with SMTP id e128mr26707068ybh.502.1599501446837; Mon, 07 Sep 2020 10:57:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599501446; cv=none; d=google.com; s=arc-20160816; b=Gkyy4xnKoGIs18Xbvy8s4gqbx4IuXFC2y9JFYphUxcvLGkE7hgqB+IlU+oi00AP9tK i1t6hx3PXWw0ufOkDsTz7KXerfGzJXpj9u7v6gz+tVVmYB48S6vh810TYcBNsW40dWCS T2GJOuhFZhucc7wG5jp8onsg+PlqZ89VH+E06nI99a08ORtu+Qw7s3FdImxl5+QIM8HX +giDCx4G2wmHF6DlJA82uusYA65J6F1IY5TzaIn8NCm/geARPz/rOidIIu1eEznnxeRO ttqTLzQGoGDBEFr1A7l/C4NCw5HhoIq7vrNn5UhdB0FzbwDtI7crvmKJQwAJyx6Et3j9 mNcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7UoRMIgCTJBIlKqoLjr+lb+MPy+eDOOMr1BDXkFiVtI=; b=iLpH8OUjrwPmRpAe6wz9qZXSzsV3kM8DXN+aH6dGTMD9pAwkLqHaAtltPqVOcJD61d s0KttSdfKwAN5dFwlvH0zTv6C0Fvu5XUhfceK30gb5/sG2tdRPI5XyPDLJB0NqUzoAKP iGPK0vD/ysHITvzCzV6svkdkbLhqj3LkUYnOZJKKdlMa/H8qWd2uh+ORc3Xo0aW29ytH D/R3P2Bi2xAymzxvWMYZdvsiI1jYmglHv0blsIytnzVWW4QymPzp2RpZyG1jNIxU9vNd 6xgpw/MvSE/b7nVA3+cCRYGrLYXSVLQsoYdkp58rExzMCBwf5aA4BbjE1RdvK0KNkfTF Sr4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zdJPIdMu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w2si2564979ybc.397.2020.09.07.10.57.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Sep 2020 10:57:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zdJPIdMu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36910 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFLOQ-0007sR-D1 for patch@linaro.org; Mon, 07 Sep 2020 13:57:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFLIV-00054Y-Q2 for qemu-devel@nongnu.org; Mon, 07 Sep 2020 13:51:19 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:42686) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFLIU-0000ln-4s for qemu-devel@nongnu.org; Mon, 07 Sep 2020 13:51:19 -0400 Received: by mail-pg1-x536.google.com with SMTP id m5so8318762pgj.9 for ; Mon, 07 Sep 2020 10:51:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7UoRMIgCTJBIlKqoLjr+lb+MPy+eDOOMr1BDXkFiVtI=; b=zdJPIdMuX6qycgq5VTtCWFBPhnGAQI4gYoafHhceH2zCXgrlN/uSJED7TP1zvzNP/y uvpzzDaoTD9uhkoMCbBhLofov/naPf0JPKZr1+LckdxnEhy6uTeWnI2CsRy1Lsl+KTQi BmEXT+vXjPv4j75fqRGrkNn32cYUnO0KLGKcNUWYz7No4kdRWJn/YUNpnJvFvFyYoN+g f7jNHGF5N1K2VOk/oJDC/PZZhr7+AD3BnbSsOPoeWW4BxkgM5o+T4qPYMieOdRw6yk57 uY0diH6Aml1/uj32dzaikUFgcfaP0PZFuuzuIvgIuDwtnUfA0PNOhfX/mft+2MRhzGT7 VsSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7UoRMIgCTJBIlKqoLjr+lb+MPy+eDOOMr1BDXkFiVtI=; b=pQXe782v+8KDG3jo+cpCzWlAOx7K+zATeoHkeCY0VS2ylVAUwDCSpKP9fwa0h+XlNP jqLbv68cR+IUtTCSab/w476jEwTWPzePlxDjPCQNrVxCdmdpgDV3nzzGCHpPFl9cjbxw Pp9zUGLbK/ujy6BPM1AWhrwD2en1ea5cl9nwVfY6ko8OcOXORBQDHoa+8tRQkl/GRaJR 2UDgkSwEKG2TzKamDpNXvRJ7pIEVaCYqkgdEVQ0fSHh+VYrfa7LmeMBcEYThwoYehuIB nMIJ2T/uP4bJyKAdLkTKB7venzfvjrCDV0Yv+9AqZYRNrqITX3nf1cgX3UKIXCvy0vI6 Mdeg== X-Gm-Message-State: AOAM531aZAvWprd5246qMrJgZt/xg+6SbBq33ISlzuxMJ3cuOdKddqEl OM4OwqlfCoBp0TjmuIVhUjqShgRdIVSd1A== X-Received: by 2002:a62:7cc3:: with SMTP id x186mr8161445pfc.229.1599501076365; Mon, 07 Sep 2020 10:51:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id ga3sm1651496pjb.18.2020.09.07.10.51.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2020 10:51:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/19] target/microblaze: Force rtid, rted, rtbd to exit Date: Mon, 7 Sep 2020 10:50:52 -0700 Message-Id: <20200907175102.28027-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200907175102.28027-1-richard.henderson@linaro.org> References: <20200907175102.28027-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These return-from-exception type instructions have modified MSR to re-enable various forms of interrupt. Force a return to the main loop. Consolidate the cleanup of tb_flags into mb_tr_translate_insn. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 608d413c83..da84fdb20b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1518,7 +1518,6 @@ static void do_rti(DisasContext *dc) tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); tcg_temp_free_i32(tmp); - dc->tb_flags &= ~DRTI_FLAG; } static void do_rtb(DisasContext *dc) @@ -1531,7 +1530,6 @@ static void do_rtb(DisasContext *dc) tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); tcg_temp_free_i32(tmp); - dc->tb_flags &= ~DRTB_FLAG; } static void do_rte(DisasContext *dc) @@ -1545,7 +1543,6 @@ static void do_rte(DisasContext *dc) tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); tcg_temp_free_i32(tmp); - dc->tb_flags &= ~DRTE_FLAG; } /* Insns connected to FSL or AXI stream attached devices. */ @@ -1700,12 +1697,16 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) * Finish any return-from branch. * TODO: Diagnose rtXd in delay slot of rtYd earlier. */ - if (dc->tb_flags & DRTI_FLAG) { - do_rti(dc); - } else if (dc->tb_flags & DRTB_FLAG) { - do_rtb(dc); - } else if (dc->tb_flags & DRTE_FLAG) { - do_rte(dc); + uint32_t rt_ibe = dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_FLAG); + if (unlikely(rt_ibe != 0)) { + dc->tb_flags &= ~(DRTI_FLAG | DRTB_FLAG | DRTE_FLAG); + if (rt_ibe & DRTI_FLAG) { + do_rti(dc); + } else if (rt_ibe & DRTB_FLAG) { + do_rtb(dc); + } else { + do_rte(dc); + } } /* Complete the branch, ending the TB. */ @@ -1723,8 +1724,12 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) */ break; case DISAS_NEXT: - /* Normal insn a delay slot. */ - dc->base.is_jmp = DISAS_JUMP; + /* + * Normal insn a delay slot. + * However, the return-from-exception type insns should + * return to the main loop, as they have adjusted MSR. + */ + dc->base.is_jmp = (rt_ibe ? DISAS_EXIT_JUMP : DISAS_JUMP); break; case DISAS_EXIT_NEXT: /* From patchwork Mon Sep 7 18:04:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249251 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3890580ilg; Mon, 7 Sep 2020 11:05:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwmv7vRRfdMUY7oBMlU7lsotWKifpyyJtVCROvY/MGZkUIUc5sIFfYJt2CAOgTUPUL8aaKQ X-Received: by 2002:a5b:990:: with SMTP id c16mr27446286ybq.303.1599501949819; Mon, 07 Sep 2020 11:05:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599501949; cv=none; d=google.com; s=arc-20160816; b=L3Zdc2L6wC5Y+bJ/ErQVxbC6I6xS6gzMumCyok0ZwYjRdy/jPY0ZmgHr2IejuxRKUh LmJ0R9tlWmmJy2jUTJ0aadMozL6DSuZz3sTCOHjHdAcMY3hUE2SB+VN+LALuEjR5i4ZA kmPGwLAVw++JokcLrCxPQk6FzAvELlApb+Y1pkJyn42j1cI5a0T4kYSHG+yGfh0Ysk76 AkPS2vXFSwb4CpGpd499UCew7koWNF/OpUxvU/4h5a6bYpDMz2j6g5v4+TDhxlKbXTeb YwdrlYzYn/VHA5dNYHMEBmpnT1yj9SQYnXoY9x2L0s4lb1xd6HKA8eCdBCXIaRJ1pb+t 0wIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hA0Q3ZvS9ZMt8mExwk35iB2Bwjpw4Nf408fgP9XSgOU=; b=J+rvWYIcl8Hvxs/t/dK31EzkxyI0LsbesPG8cfOz7IopJFZJdaq1i8EvwrFUefnON8 1M2xj9lX53WfcyZ9C/9ELKEsmF5HydqBdUZ5g9Pt6qK0V+wUrdoHBokERvHa8v4oN0fP 89pNrIZul3M9RhJHBfDcftPTk9H22dYtcU0lIXrt//nVC8zqrT0T+LDxeN2eUNK3MMr1 icUwNXpMxel4kknYJRyC1piwA4zRcZ9/rnPLLZo0yhRbgr8OQUGELFDNXWbRuwRsC75V 2S0NyGyu0+EC1p5aNyEAl5LoNH+2Nte6EUVsdn9pbUKlsB435VvVPKKO8OBQ9O4zKvD5 9UvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rPtdMp7e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Normal indirect jumps, or page-crossing direct jumps, can use tcg_gen_lookup_and_goto_ptr to avoid returning to the main loop simply to find an existing TB for the next pc. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index da84fdb20b..d98572fab9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -147,7 +147,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) tcg_gen_exit_tb(dc->base.tb, n); } else { tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } dc->base.is_jmp = DISAS_NORETURN; } @@ -1803,7 +1803,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } return; From patchwork Mon Sep 7 18:04:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249252 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3891380ilg; Mon, 7 Sep 2020 11:06:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9/bQHknMehrEOn7U2g24X1jMQ8I4DEDuR1NcAZa4T0rp2UZoisWC0/Xn+k3qoTvB5rJ/K X-Received: by 2002:a25:cb57:: with SMTP id b84mr29219330ybg.425.1599502018546; Mon, 07 Sep 2020 11:06:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599502018; cv=none; d=google.com; s=arc-20160816; b=c3wnqFEmI2B2YWINj6FqGuUQAOxIvN6ILcV4k1xoAT4HclUIYiXf8CX36NADEZAN/Z MGBos4ds2NVRPzLOraSX0dnTnETXUl4lDh1gG6TGMDsuznD7et4arWw/m2m7xP4sc3mD I6fwbteNUYdJRe9XVHTHRI/iW5Em6fJmz4b66AFynFv+Vayf0UTWH0zcR1TJzwexPNSb Kya8G5BsISYDStmf/9HKF3zxMPWPF31juVxNHFns+EKwpWpxTsgxLI2LIYMf5kSjo1/t 9P/+1yPl+xTJdrF3MFe2Y+78H4y2w3P1URug+GzJWRnQmuK16vT+oxd2N18wbuc3+wqO B9Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BKnI6SGaGA2YOpJ/qxM62G0O4ltDNID2ekxG+CDt900=; b=Xxctv9492uS+3AwIKpVG57cL0wGLSqcJI6ACCxUphoSUu3AczUkn+6EC3gWUQGzPU2 ObK04On7/dNMS1OCaRHIg0cTXjSCIHYYE0hq6d885kiGkCf+IrwRB1yJ6iyYdzW9nOCG uc+yWVWP1qIyoyA1vux9w/tDOyBlz1EQ4BXqlwmaSTa/DSoWFWIYCG8dYczgLdz77CYX nycHusbUG1RvTjyRfXt+b+N76uecai86T5Czpi0ECB//fW2mv8gBQGTrh83MnjXFt1JR VsaHnkxNWQIMVBBfM+TXUDhk0zQpcZ6o7564XmK4mPEYiPkn6x6fVOVVgVwgNCRCLxqC kmxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oP7O60eT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These cases result in undefined and undocumented behaviour but the behaviour is deterministic, i.e cores will not lock-up or expose security issues. However, RTL will not raise exceptions either. Therefore, log a GUEST_ERROR and treat these cases as nops, to avoid corner cases which could put qemu into an invalid state. Tested-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 48 ++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d98572fab9..ff0cb7dbb6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -179,6 +179,21 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } +/* + * Return true, and log an error, if the current insn is + * within a delay slot. + */ +static bool invalid_delay_slot(DisasContext *dc, const char *insn_type) +{ + if (dc->tb_flags & D_FLAG) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid insn in delay slot: %s at %08x\n", + insn_type, (uint32_t)dc->base.pc_next); + return true; + } + return false; +} + static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { if (likely(reg != 0)) { @@ -500,6 +515,9 @@ DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) static bool trans_imm(DisasContext *dc, arg_imm *arg) { + if (invalid_delay_slot(dc, "imm")) { + return true; + } dc->ext_imm = arg->imm << 16; tcg_gen_movi_i32(cpu_imm, dc->ext_imm); dc->tb_flags_to_set = IMM_FLAG; @@ -1067,6 +1085,9 @@ static bool do_branch(DisasContext *dc, int dest_rb, int dest_imm, { uint32_t add_pc; + if (invalid_delay_slot(dc, "branch")) { + return true; + } if (delay) { setup_dslot(dc, dest_rb < 0); } @@ -1106,6 +1127,9 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm, { TCGv_i32 zero, next; + if (invalid_delay_slot(dc, "bcc")) { + return true; + } if (delay) { setup_dslot(dc, dest_rb < 0); } @@ -1158,6 +1182,10 @@ static bool trans_brk(DisasContext *dc, arg_typea_br *arg) if (trap_userspace(dc, true)) { return true; } + if (invalid_delay_slot(dc, "brk")) { + return true; + } + tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb)); if (arg->rd) { tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); @@ -1176,6 +1204,10 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) if (trap_userspace(dc, imm != 0x8 && imm != 0x18)) { return true; } + if (invalid_delay_slot(dc, "brki")) { + return true; + } + tcg_gen_movi_i32(cpu_pc, imm); if (arg->rd) { tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); @@ -1216,6 +1248,11 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg) { int mbar_imm = arg->imm; + /* Note that mbar is a specialized branch instruction. */ + if (invalid_delay_slot(dc, "mbar")) { + return true; + } + /* Data access memory barrier. */ if ((mbar_imm & 2) == 0) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); @@ -1263,6 +1300,10 @@ static bool do_rts(DisasContext *dc, arg_typeb_bc *arg, int to_set) if (trap_userspace(dc, to_set)) { return true; } + if (invalid_delay_slot(dc, "rts")) { + return true; + } + dc->tb_flags_to_set |= to_set; setup_dslot(dc, true); @@ -1695,7 +1736,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) if (dc->jmp_cond != TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { /* * Finish any return-from branch. - * TODO: Diagnose rtXd in delay slot of rtYd earlier. */ uint32_t rt_ibe = dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_FLAG); if (unlikely(rt_ibe != 0)) { @@ -1717,12 +1757,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) * and will handle D_FLAG in mb_cpu_do_interrupt. */ break; - case DISAS_EXIT: - /* - * TODO: diagnose brk/brki in delay slot earlier. - * This would then fold into the illegal insn case above. - */ - break; case DISAS_NEXT: /* * Normal insn a delay slot. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This struct was previously unnamed, and defined in MicroBlazeCPU. Pull it out to its own typedef so that we can reuse it. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 55 ++++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 20c2979396..59d2a079c4 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -291,6 +291,34 @@ struct CPUMBState { } pvr; }; +/* + * Microblaze Configuration Settings + */ +typedef struct { + bool stackprot; + uint32_t base_vectors; + uint8_t addr_size; + uint8_t use_fpu; + uint8_t use_hw_mul; + bool use_barrel; + bool use_div; + bool use_msr_instr; + bool use_pcmp_instr; + bool use_mmu; + bool dcache_writeback; + bool endi; + bool dopb_bus_exception; + bool iopb_bus_exception; + bool illegal_opcode_exception; + bool opcode_0_illegal; + bool div_zero_exception; + bool unaligned_exceptions; + uint8_t pvr_user1; + uint32_t pvr_user2; + char *version; + uint8_t pvr; +} MicroBlazeCPUConfig; + /** * MicroBlazeCPU: * @env: #CPUMBState @@ -305,32 +333,7 @@ struct MicroBlazeCPU { CPUNegativeOffsetState neg; CPUMBState env; - - /* Microblaze Configuration Settings */ - struct { - bool stackprot; - uint32_t base_vectors; - uint8_t addr_size; - uint8_t use_fpu; - uint8_t use_hw_mul; - bool use_barrel; - bool use_div; - bool use_msr_instr; - bool use_pcmp_instr; - bool use_mmu; - bool dcache_writeback; - bool endi; - bool dopb_bus_exception; - bool iopb_bus_exception; - bool illegal_opcode_exception; - bool opcode_0_illegal; - bool div_zero_exception; - bool unaligned_exceptions; - uint8_t pvr_user1; - uint32_t pvr_user2; - char *version; - uint8_t pvr; - } cfg; + MicroBlazeCPUConfig cfg; }; From patchwork Mon Sep 7 18:04:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249250 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3890324ilg; Mon, 7 Sep 2020 11:05:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJye/lPa2O2DaF3GT31PpaxaACUFazrixgDmvUw/FU3vo3Rwuemm730v/VUg8KWp9OyNxXJV X-Received: by 2002:a25:d846:: with SMTP id p67mr13677054ybg.250.1599501929017; Mon, 07 Sep 2020 11:05:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599501929; cv=none; d=google.com; s=arc-20160816; b=D4NRSDeCImTFCNTD8w9pMCsnEh37BlK2tI4B02EZeDKarcSFNRlhR7nU8EOPPtr36K q+M3MVSBaAsmAPZEQES4Uk9I/d2X5y0Soh8M7X1aSig4G7yo9MEFweEtGqPwaoHtlp+x hKb0hb3YbcVVc/8hvu64QSEi8RpNWj2xn5XX7b+SZ3fJDGG7WtkzIiVNIBLs7/dDdDMZ qW45fHK54t/E+m0NdZMoP/E+DE5huntLeDDU63nSlIMV44UZetgXJr39nOviDWjEouAj 991jE9YiQoHpz/DGpS8Cnt4Lquj8pajzwJktFh/hEBgZizs2mDPal5hqsDiQNQqe1aBP tE0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lPpTfq2djWv2KtE9u88NEsXW+rPg4wV1NrdmvmqhTMc=; b=F9oq7GmB9xZ6ubp99YRk3PkSqXPGCJ4k3XI/oTIOc0WBgqvPmBBzkmSx+od+ftpYow IYLeBplQUmyax1eiNmuaCzr6opEsCCgXgBV0FgwBqPW+nO7tJTM0XOQ1IfLQ1ig6AU1f zeHvCXZ2om3fRVJ/qUymYKzWpBxcw/pAPFLTekVkzxYhJy8pfkHJ+soOoE1Qv7mZUkRH Pr9XDrzhQU06oQ+RUJXXBmALxhJ18iH/iQqKzymrMmya1wqUjRv6jkh9ytO1jZqShMy9 cd3PZQft/ld+/kVCQ0ucm8XYWMgafHeTceJ6rUbaIxL7ZvOVpizhlaDkZ3xBqy82vgeB G2RQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BQB1Zif9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Sort the elements by type and size, removing a number of holes and reducing the size of the entire struct. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 59d2a079c4..4d53345f23 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -293,13 +293,22 @@ struct CPUMBState { /* * Microblaze Configuration Settings + * + * Note that the structure is sorted by type and size to minimize holes. */ typedef struct { - bool stackprot; + char *version; + uint32_t base_vectors; + uint32_t pvr_user2; + uint8_t addr_size; uint8_t use_fpu; uint8_t use_hw_mul; + uint8_t pvr_user1; + uint8_t pvr; + + bool stackprot; bool use_barrel; bool use_div; bool use_msr_instr; @@ -313,10 +322,6 @@ typedef struct { bool opcode_0_illegal; bool div_zero_exception; bool unaligned_exceptions; - uint8_t pvr_user1; - uint32_t pvr_user2; - char *version; - uint8_t pvr; } MicroBlazeCPUConfig; /** From patchwork Mon Sep 7 18:04:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249256 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3893481ilg; Mon, 7 Sep 2020 11:10:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy+GE8Wice4BFR3ptVpUw+c3Gz/tLokWLlwShCZgMVKupwDLue/6ff5lZ6cS7Qgl/Pf+h65 X-Received: by 2002:a25:7502:: with SMTP id q2mr29217950ybc.285.1599502211086; Mon, 07 Sep 2020 11:10:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599502211; cv=none; d=google.com; s=arc-20160816; b=ZYogwuqwOHVXWidK0h2Q4O2fJvPREMMqtMefZZF8ylXqJ6rgjTJKEsl4pnrDb0kcTO hoORDr7sy6lUhY0WcLBPOZ+iLwQ7Ih88LaaaQqSBrmLtiqe4WWmMWIjMA4Zq/XbGo7OM k/cvrPOL4BvQuRkjoqUay7wcT2kcDqGFsaALwq6ire2VTmyAeF7Ge2byBDfGwWnV6UG5 9MpWuqYThJV8tdLA9j6TKcU77P6YUJoDKUs+leCLzYKpiaNY587ejH83ja7Xs6A1U8CE XnWgINzU8skoXfJJNe3FQKsIvFlL3JVkuYKtrxzAV+dukG0OyToOYLl5dpZqhI8z1uHC oWTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9hyROkW6SX1plBSlOICmkYSQa2gXJt88PJFbrx2To6c=; b=GsG1n05weCNnZ99238ySO+Uk3qSTnj3NvylOTv9biMfJcVGfwcW9CDp0pA5pppqalZ bfSFJDh/Y1NhgNoyEHECE2lqiBKzWk3FC6V580C9PHLN8KYPEHoL4TW5Frn5RrOzkrcu +7wgXopWxh4KDr3msKwCXmQ3aODtEEAPQSy0229WkzQ+DkSW+akmlA+RezG22gUXTnff +xzCg3+MJKo5eEBr/CtU9lvzs4TpX3vd2PnmxEsYbktMZd5qJm+QYFO+LfQ+t9nm9Fuj VSrcN6W0Xd6zM3OoG3GDQrIO8vKuRjxwGDIMaQlRMoh1m9vbchmFPxzpFAMbul2e1rI+ hcaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xX+hvrEu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These values are constant, and are derived from the other configuration knobs. Move them into MicroBlazeCPUConfig to emphasize that they are not variable. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 5 +- hw/microblaze/petalogix_ml605_mmu.c | 6 +- target/microblaze/cpu.c | 92 ++++++++++++++--------------- target/microblaze/gdbstub.c | 4 +- target/microblaze/helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 3 +- 7 files changed, 54 insertions(+), 60 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 4d53345f23..ef96f2fe02 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -285,10 +285,6 @@ struct CPUMBState { struct {} end_reset_fields; /* These fields are preserved on reset. */ - - struct { - uint32_t regs[13]; - } pvr; }; /* @@ -301,6 +297,7 @@ typedef struct { uint32_t base_vectors; uint32_t pvr_user2; + uint32_t pvr_regs[13]; uint8_t addr_size; uint8_t use_fpu; diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index e49fc86eb8..159db6cbe2 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -200,9 +200,9 @@ petalogix_ml605_init(MachineState *machine) } /* setup PVR to match kernel settings */ - cpu->env.pvr.regs[4] = 0xc56b8000; - cpu->env.pvr.regs[5] = 0xc56be000; - cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */ + cpu->cfg.pvr_regs[4] = 0xc56b8000; + cpu->cfg.pvr_regs[5] = 0xc56be000; + cpu->cfg.pvr_regs[10] = 0x0e000000; /* virtex 6 */ microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size, machine->initrd_filename, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6392524135..b9bb7f0cc7 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -153,7 +153,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) CPUState *cs = CPU(dev); MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; uint8_t version_code = 0; const char *version; int i = 0; @@ -173,16 +172,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_USE_EXC_MASK - | PVR0_USE_ICACHE_MASK - | PVR0_USE_DCACHE_MASK; - env->pvr.regs[2] = PVR2_D_OPB_MASK - | PVR2_D_LMB_MASK - | PVR2_I_OPB_MASK - | PVR2_I_LMB_MASK - | PVR2_FPU_EXC_MASK - | 0; - version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; for (i = 0; mb_cpu_lookup[i].name && version; i++) { if (strcmp(mb_cpu_lookup[i].name, version) == 0) { @@ -195,46 +184,53 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); } - env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | - (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | - (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | - (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | - (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | - (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | - (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | - (version_code << PVR0_VERSION_SHIFT) | - (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | - cpu->cfg.pvr_user1; + cpu->cfg.pvr_regs[0] = + (PVR0_USE_EXC_MASK | + PVR0_USE_ICACHE_MASK | + PVR0_USE_DCACHE_MASK | + (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | + (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | + (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | + (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | + (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | + (version_code << PVR0_VERSION_SHIFT) | + (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | + cpu->cfg.pvr_user1); - env->pvr.regs[1] = cpu->cfg.pvr_user2; - env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | - (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | - (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | - (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | - (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | - (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | - (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | - (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | - (cpu->cfg.dopb_bus_exception ? - PVR2_DOPB_BUS_EXC_MASK : 0) | - (cpu->cfg.iopb_bus_exception ? - PVR2_IOPB_BUS_EXC_MASK : 0) | - (cpu->cfg.div_zero_exception ? - PVR2_DIV_ZERO_EXC_MASK : 0) | - (cpu->cfg.illegal_opcode_exception ? - PVR2_ILL_OPCODE_EXC_MASK : 0) | - (cpu->cfg.unaligned_exceptions ? - PVR2_UNALIGNED_EXC_MASK : 0) | - (cpu->cfg.opcode_0_illegal ? - PVR2_OPCODE_0x0_ILL_MASK : 0); + cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2; - env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? - PVR5_DCACHE_WRITEBACK_MASK : 0; + cpu->cfg.pvr_regs[2] = + (PVR2_D_OPB_MASK | + PVR2_D_LMB_MASK | + PVR2_I_OPB_MASK | + PVR2_I_LMB_MASK | + PVR2_FPU_EXC_MASK | + (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | + (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | + (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | + (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | + (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | + (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | + (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) | + (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) | + (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) | + (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) | + (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) | + (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0)); - env->pvr.regs[10] = 0x0c000000 | /* Default to spartan 3a dsp family. */ - (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT; - env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | - 16 << 17; + cpu->cfg.pvr_regs[5] |= + cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; + + cpu->cfg.pvr_regs[10] = + (0x0c000000 | /* Default to spartan 3a dsp family. */ + (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT); + + cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | + 16 << 17); mcc->parent_realize(dev, errp); } diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 08d6a0e807..9e3b9ac824 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -78,7 +78,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - val = env->pvr.regs[n - GDB_PVR0]; + val = cpu->cfg.pvr_regs[n - GDB_PVR0]; break; case GDB_EDR: val = env->edr; @@ -134,7 +134,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - env->pvr.regs[n - GDB_PVR0] = tmp; + cpu->cfg.pvr_regs[n - GDB_PVR0] = tmp; break; case GDB_EDR: env->edr = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 3c2fd388fb..c9f236c897 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -122,7 +122,7 @@ void mb_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_HW_EXCP: - if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { + if (!(cpu->cfg.pvr_regs[0] & PVR0_USE_EXC_MASK)) { qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n"); return; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 4614e99db3..757f3ff04b 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -134,7 +134,7 @@ static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) raise = 1; } if (raise - && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) + && (env_archcpu(env)->cfg.pvr_regs[2] & PVR2_FPU_EXC_MASK) && (env->msr & MSR_EE)) { raise_fpu_exception(env, ra); } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ff0cb7dbb6..9e4551d99b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1539,7 +1539,8 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg) case 0x2000 ... 0x200c: tcg_gen_ld_i32(dest, cpu_env, - offsetof(CPUMBState, pvr.regs[arg->rs - 0x2000])); + offsetof(MicroBlazeCPU, cfg.pvr_regs[arg->rs - 0x2000]) + - offsetof(MicroBlazeCPU, env)); break; default: qemu_log_mask(LOG_GUEST_ERROR, "Invalid mfs reg 0x%x\n", arg->rs); From patchwork Mon Sep 7 18:04:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249255 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3892749ilg; Mon, 7 Sep 2020 11:09:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwSVoGU25i1OOjfyFWJVivGFKPK8SoICY59pcZuR5W1Gt+KawvRhS3yFGBEGtzlZsPFYlCM X-Received: by 2002:a25:cb97:: with SMTP id b145mr28938716ybg.393.1599502156010; Mon, 07 Sep 2020 11:09:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599502156; cv=none; d=google.com; s=arc-20160816; b=lcjpEsx0ftt+6VGeS5oCd+5aKK9MWZBAItUD2mxBb49ws1PS0gO4zqzKcNY4LbP16c ToxTSN0dfD6fwBlpXmSOMixOOQwkWUoABtBNEp/ci2iiuDkHP9nfkdEbcSzNgTiwE9GP rzk7xKms9zyj/ueqWBnjpmCeC1KIH+iHZeovRoSswxfvQqEq+yUyqBFpywC3uVTbmbyD p0La4AzVB5cgizj612yj5OuWgV/d0hM/HpKwEOourJJnvj4sd4n/+ZmXAgdqJ4vhszqF 1V0iKxKI8kKHnr52okGRA5FJIERLtRnTike4uPpqMfPn71jvzPH7ZqQc9/kASMwdV0bo uBWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=u9Y0vjaPuoAkxScaNqtUASpr1pIzL6DgrA0aESQcv0g=; b=DBNWSv0svHHOTiw8k8OnBusaWPFojJvq/30qiFhuR7G0zYstJ/xCo8PPv9Xe69zCQg Zl+ia7Pmvfd+EhbtyVR8NXu2ats+lt+16WPTZwku88cH0HZSYkQTI4qzGfskQxuptMWp 8bp4LzyWM3eeeeXz8ZbDjPTB3docJewSA6vp8AlEDp8v02bLhzpm6ah1NbGrV7sLj+n/ e4AQJkRsdQTuT/92cp21s+Hfrb3BtazjhyaPZz1M4RDYllObmzlmEFTiVtUNVOgqvQll 96/Sj03QZbqNRGxt30VQhiDAop4FL4kdIqIUsmOuSD1nTFuqoqsMRo8m/GW/Us2O5fvf L76g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YtqShFO1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not allow gdb to set the values, and don't bother dumping unchanging values with -d cpu. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/gdbstub.c | 4 ---- target/microblaze/translate.c | 5 ----- 2 files changed, 9 deletions(-) -- 2.25.1 diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 9e3b9ac824..be39fd4540 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -132,10 +132,6 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) case GDB_BTR: env->btr = tmp; break; - case GDB_PVR0 ... GDB_PVR11: - /* PVR12 is intentionally skipped */ - cpu->cfg.pvr_regs[n - GDB_PVR0] = tmp; - break; case GDB_EDR: env->edr = tmp; break; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9e4551d99b..eca422b3db 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1919,11 +1919,6 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) env->esr, env->fsr, env->btr, env->edr, env->ear, env->slr, env->shr); - for (i = 0; i < 12; i++) { - qemu_fprintf(f, "rpvr%-2d=%08x%c", - i, env->pvr.regs[i], i % 4 == 3 ? '\n' : ' '); - } - for (i = 0; i < 32; i++) { qemu_fprintf(f, "r%2.2d=%08x%c", i, env->regs[i], i % 4 == 3 ? '\n' : ' '); From patchwork Mon Sep 7 18:04:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249257 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3894449ilg; Mon, 7 Sep 2020 11:11:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHpw6ntFxm2X8OFCOrm9/RNIyji1eax+W4O8+EwiKA6oavaHIDRpAqgVXdEPb0o5TnAY+k X-Received: by 2002:a25:2057:: with SMTP id g84mr27171935ybg.169.1599502302548; Mon, 07 Sep 2020 11:11:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599502302; cv=none; d=google.com; s=arc-20160816; b=Gu9kcEKHbO9j7dhZU/SVx5FQd8KJZljSyjqQq4ay+jpklhO7Ect7RJhtdVRJRL7Z59 eBRSw85clPTgcG24X+EDJwK/FhryzPEwrOgpMMT7nDevh3HeYevo5dxIxWt6dTL8TVxq t6STx2cmzpyj2p88PXUa8MmUJcvXEyZCnWvIIWviuG8VBySXkdk8+TbNvhucXA/YFM44 TcL3cJCaotOZvX/NJ/ZV7/nFvo6GaPkBjiZwQvkbeEE/Guxemy2zqhXbmzwIQlDbqVvq EgoRE9ShunXUkZ1tZ28ywdyyLxFdLocbJ3j423f7WcaaY3a5fYwTtmmVAm+GhWUafY61 eeng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9SsoToSMEh6dKfrGI01LaB8qyEfZ2YCbynKlKreMREc=; b=bcnehvaSA1AjIMLI7+Zciae2kC2LVv+WKMn0WydApYJklpxYbuubawOWt2L8N+Ukb8 B/4bGhGyh+qM/Z/KV/LDOyVKIcmVxIe1TEOHfoiuWbf8Ybc2M8pGZWCu2x73Yqy1blJb YIhzHIW4uHv/dYSDXQFpNjkTDg4avmRanUwttfd7I2HwYQbuwyRAalVQsspdxIsRtkZo 7b9EZG5RIA2YiidZ3no4rqR31DPfwbqi2Vth1M1z+Giet9iWAfQbJFGzhTGAKn8qKt/k g8VX+ylfMRpEJ3ukiC/4lbSfn/slw1xsWMWRSRpWhBt1892X2iQ29o5886aJ2im9/EM6 r3HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vSMx1dUJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The final 4 fields in MicroBlazeMMU are configuration constants. Move them into MicroBlazeCPUConfig where they belong. Remove the leading "c_" from the member names, as that presumably implied "config", and that should not be explicit in the location. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 5 +++++ target/microblaze/mmu.h | 7 +------ target/microblaze/cpu.c | 9 +++++---- target/microblaze/helper.c | 4 ++-- target/microblaze/mmu.c | 30 +++++++++++++++++------------- 5 files changed, 30 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index ef96f2fe02..b54f99da61 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -295,6 +295,8 @@ struct CPUMBState { typedef struct { char *version; + uint64_t addr_mask; + uint32_t base_vectors; uint32_t pvr_user2; uint32_t pvr_regs[13]; @@ -304,6 +306,9 @@ typedef struct { uint8_t use_hw_mul; uint8_t pvr_user1; uint8_t pvr; + uint8_t mmu; + uint8_t mmu_tlb_access; + uint8_t mmu_zones; bool stackprot; bool use_barrel; diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index c1feb811b9..7d0fbb8341 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -70,11 +70,6 @@ typedef struct { uint8_t tids[TLB_ENTRIES]; /* Control flops. */ uint32_t regs[3]; - - int c_mmu; - int c_mmu_tlb_access; - int c_mmu_zones; - uint64_t c_addr_mask; /* Mask to apply to physical addresses. */ } MicroBlazeMMU; typedef struct { @@ -88,7 +83,7 @@ typedef struct { } err; } MicroBlazeMMULookup; -unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, +unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, target_ulong vaddr, int rw, int mmu_idx); uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index b9bb7f0cc7..fde646a7ad 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -135,10 +135,6 @@ static void mb_cpu_reset(DeviceState *dev) #else mb_cpu_write_msr(env, 0); mmu_init(&env->mmu); - env->mmu.c_mmu = 3; - env->mmu.c_mmu_tlb_access = 3; - env->mmu.c_mmu_zones = 16; - env->mmu.c_addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size); #endif } @@ -232,6 +228,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | 16 << 17); + cpu->cfg.mmu = 3; + cpu->cfg.mmu_tlb_access = 3; + cpu->cfg.mmu_zones = 16; + cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size); + mcc->parent_realize(dev, errp); } diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index c9f236c897..3d6ce1b31b 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -64,7 +64,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return true; } - hit = mmu_translate(&env->mmu, &lu, address, access_type, mmu_idx); + hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx); if (likely(hit)) { uint32_t vaddr = address & TARGET_PAGE_MASK; uint32_t paddr = lu.paddr + vaddr - lu.vaddr; @@ -240,7 +240,7 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) unsigned int hit; if (mmu_idx != MMU_NOMMU_IDX) { - hit = mmu_translate(&env->mmu, &lu, addr, 0, 0); + hit = mmu_translate(cpu, &lu, addr, 0, 0); if (hit) { vaddr = addr & TARGET_PAGE_MASK; paddr = lu.paddr + vaddr - lu.vaddr; diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 0546cfd0bc..1dbbb271c4 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -73,9 +73,10 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid) } /* rw - 0 = read, 1 = write, 2 = fetch. */ -unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, +unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, target_ulong vaddr, int rw, int mmu_idx) { + MicroBlazeMMU *mmu = &cpu->env.mmu; unsigned int i, hit = 0; unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel; uint64_t tlb_tag, tlb_rpn, mask; @@ -114,13 +115,13 @@ unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2)); t0 &= 0x3; - if (tlb_zsel > mmu->c_mmu_zones) { + if (tlb_zsel > cpu->cfg.mmu_zones) { qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of range! %d\n", tlb_zsel); t0 = 1; /* Ignore. */ } - if (mmu->c_mmu == 1) { + if (cpu->cfg.mmu == 1) { t0 = 1; /* Zones are disabled. */ } @@ -157,7 +158,7 @@ unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, tlb_rpn = d & TLB_RPN_MASK; lu->vaddr = tlb_tag; - lu->paddr = tlb_rpn & mmu->c_addr_mask; + lu->paddr = tlb_rpn & cpu->cfg.addr_mask; lu->size = tlb_size; lu->err = ERR_HIT; lu->idx = i; @@ -175,10 +176,11 @@ done: /* Writes/reads to the MMU's special regs end up here. */ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) { + MicroBlazeCPU *cpu = env_archcpu(env); unsigned int i; uint32_t r = 0; - if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { + if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) { qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); return 0; } @@ -191,7 +193,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) /* Reads to HI/LO trig reads from the mmu rams. */ case MMU_R_TLBLO: case MMU_R_TLBHI: - if (!(env->mmu.c_mmu_tlb_access & 1)) { + if (!(cpu->cfg.mmu_tlb_access & 1)) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); return 0; @@ -204,7 +206,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) break; case MMU_R_PID: case MMU_R_ZPR: - if (!(env->mmu.c_mmu_tlb_access & 1)) { + if (!(cpu->cfg.mmu_tlb_access & 1)) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); return 0; @@ -227,12 +229,14 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) { + MicroBlazeCPU *cpu = env_archcpu(env); uint64_t tmp64; unsigned int i; + qemu_log_mask(CPU_LOG_MMU, "%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]); - if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { + if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) { qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); return; } @@ -258,7 +262,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v); break; case MMU_R_ZPR: - if (env->mmu.c_mmu_tlb_access <= 1) { + if (cpu->cfg.mmu_tlb_access <= 1) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); return; @@ -272,7 +276,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) env->mmu.regs[rn] = v; break; case MMU_R_PID: - if (env->mmu.c_mmu_tlb_access <= 1) { + if (cpu->cfg.mmu_tlb_access <= 1) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); return; @@ -292,14 +296,14 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) MicroBlazeMMULookup lu; int hit; - if (env->mmu.c_mmu_tlb_access <= 1) { + if (cpu->cfg.mmu_tlb_access <= 1) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn); return; } - hit = mmu_translate(&env->mmu, &lu, - v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false)); + hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK, + 0, cpu_mmu_index(env, false)); if (hit) { env->mmu.regs[MMU_R_TLBX] = lu.idx; } else { From patchwork Mon Sep 7 18:04:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249254 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3892219ilg; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 ++ target/microblaze/cpu.c | 8 +-- target/microblaze/machine.c | 106 ++++++++++++++++++++++++++++++++++ target/microblaze/meson.build | 5 +- 4 files changed, 115 insertions(+), 8 deletions(-) create mode 100644 target/microblaze/machine.c -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b54f99da61..297b36879a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -429,4 +429,8 @@ static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) return MMU_KERNEL_IDX; } +#ifndef CONFIG_USER_ONLY +extern const VMStateDescription vmstate_mb_cpu; +#endif + #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index fde646a7ad..9b2482159d 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -26,7 +26,6 @@ #include "cpu.h" #include "qemu/module.h" #include "hw/qdev-properties.h" -#include "migration/vmstate.h" #include "exec/exec-all.h" #include "fpu/softfloat-helpers.h" @@ -251,11 +250,6 @@ static void mb_cpu_initfn(Object *obj) #endif } -static const VMStateDescription vmstate_mb_cpu = { - .name = "cpu", - .unmigratable = 1, -}; - static Property mb_properties[] = { DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, @@ -335,8 +329,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->do_transaction_failed = mb_cpu_transaction_failed; cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; -#endif dc->vmsd = &vmstate_mb_cpu; +#endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs = 32 + 27; diff --git a/target/microblaze/machine.c b/target/microblaze/machine.c new file mode 100644 index 0000000000..acdb8d0474 --- /dev/null +++ b/target/microblaze/machine.c @@ -0,0 +1,106 @@ +/* + * Microblaze VMState for qemu. + * + * Copyright (c) 2020 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "migration/cpu.h" + + +static VMStateField vmstate_mmu_fields[] = { + VMSTATE_UINT64_2DARRAY(rams, MicroBlazeMMU, 2, TLB_ENTRIES), + VMSTATE_UINT8_ARRAY(tids, MicroBlazeMMU, TLB_ENTRIES), + VMSTATE_UINT32_ARRAY(regs, MicroBlazeMMU, 3), + VMSTATE_END_OF_LIST() +}; + +static const VMStateDescription vmstate_mmu = { + .name = "mmu", + .version_id = 0, + .minimum_version_id = 0, + .fields = vmstate_mmu_fields, +}; + +static int get_msr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + CPUMBState *env = container_of(opaque, CPUMBState, msr); + + mb_cpu_write_msr(env, qemu_get_be32(f)); + return 0; +} + +static int put_msr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, QJSON *vmdesc) +{ + CPUMBState *env = container_of(opaque, CPUMBState, msr); + + qemu_put_be32(f, mb_cpu_read_msr(env)); + return 0; +} + +static const VMStateInfo vmstate_msr = { + .name = "msr", + .get = get_msr, + .put = put_msr, +}; + +static VMStateField vmstate_env_fields[] = { + VMSTATE_UINT32_ARRAY(regs, CPUMBState, 32), + + VMSTATE_UINT32(pc, CPUMBState), + VMSTATE_SINGLE(msr, CPUMBState, 0, vmstate_msr, uint32_t), + VMSTATE_UINT32(esr, CPUMBState), + VMSTATE_UINT32(fsr, CPUMBState), + VMSTATE_UINT32(btr, CPUMBState), + VMSTATE_UINT32(edr, CPUMBState), + VMSTATE_UINT32(slr, CPUMBState), + VMSTATE_UINT32(shr, CPUMBState), + VMSTATE_UINT64(ear, CPUMBState), + + VMSTATE_UINT32(btarget, CPUMBState), + VMSTATE_UINT32(imm, CPUMBState), + VMSTATE_UINT32(iflags, CPUMBState), + + VMSTATE_UINT32(res_val, CPUMBState), + VMSTATE_UINTTL(res_addr, CPUMBState), + + VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU), + + VMSTATE_END_OF_LIST() +}; + +static const VMStateDescription vmstate_env = { + .name = "env", + .version_id = 0, + .minimum_version_id = 0, + .fields = vmstate_env_fields, +}; + +static VMStateField vmstate_cpu_fields[] = { + VMSTATE_CPU(), + VMSTATE_STRUCT(env, MicroBlazeCPU, 1, vmstate_env, CPUMBState), + VMSTATE_END_OF_LIST() +}; + +const VMStateDescription vmstate_mb_cpu = { + .name = "cpu", + .version_id = 0, + .minimum_version_id = 0, + .fields = vmstate_cpu_fields, +}; diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index 639c3f73a8..05ee0ec163 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -11,7 +11,10 @@ microblaze_ss.add(files( )) microblaze_softmmu_ss = ss.source_set() -microblaze_softmmu_ss.add(files('mmu.c')) +microblaze_softmmu_ss.add(files( + 'mmu.c', + 'machine.c', +)) target_arch += {'microblaze': microblaze_ss} target_softmmu_arch += {'microblaze': microblaze_softmmu_ss} From patchwork Mon Sep 7 18:04:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249258 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3894831ilg; Mon, 7 Sep 2020 11:12:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRNAU31fyXBpuGlGmVoLDxp8Xh4DVymD4R2A1r4qJXmtdvIggS5u0rF/kwecBaagT8noDd X-Received: by 2002:a25:5808:: with SMTP id m8mr29764948ybb.246.1599502338340; Mon, 07 Sep 2020 11:12:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599502338; cv=none; d=google.com; s=arc-20160816; b=KSOIpx70ujVOV61VsXPJsg4acihp6jgGWyWuOnGnyWdtuEdhsLMJ09XG5o9R52SUOg FI03xIhQ6LjiRSgPjq54uof4SqSbg4C3EIde6CFO9W5zRrsT555d43L+AvuTTvWQXdBs 1GAip/tkQMxHU+j9k4ySGKAFnP31nRsi09qMKwbCFKBeNEQWQ6lKWerpYaufgS9JUtr1 ckEd+oh6N8rmrkcIKgQcHWzB1mAT4Wa0nPu3T9gnsqbCCDhJp6KHqERcuyR45o9eBFfD X63Yf85VVCqFtKQK1kWKFJHZzIMNti8DAI4cdwzd3+kAZS2z3VyLChBZJK278ncz0wvh 9wkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mCgjeXLmeN5hMfhXUcUPxa4AMIlfBZL76Mf1qDfxbvQ=; b=rAQs97favUIGTLckG/eCaGl49r8awvqIs98f1O5UDroHvxS/XPeAlqzLtIu/R9WT4I T4aVPKJCrNniaujuTNtiOGUbjs1tEteOhH83UomyjSRSLSU+1TYoeKGO+70wroVFaB+U 4QA0LYNxJz6GzH2BiZaFAkJY6ORfP8P7vr8YyMdbpUur2Vye3K44pGRpLWtRZnXpgHp9 c5dHCYqdLWi/8EiAB92JdrIT0N3QYHnVSPfDhr4VzAajlCY+iaa2K5xhxjPMG5PfK2Ef 0m3svH3TZKg37aLeezt0z2A1SGguncY533uQ7uPNAni9uddvE6+roSlsNzNK4zJkKWSb lqeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zMVbP3oL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The bulk of the translator should not have access to the complete cpu state, to avoid the temptation to examine bits that are in run time, but not translation time context. We do need access to the constant cpu configuration, and that is sufficient, so put that into DisasContext. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index eca422b3db..abfcc7e6c8 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -60,7 +60,7 @@ static TCGv_i32 cpu_res_val; /* This is the state at translation time. */ typedef struct DisasContext { DisasContextBase base; - MicroBlazeCPU *cpu; + const MicroBlazeCPUConfig *cfg; /* TCG op of the current insn_start. */ TCGOp *insn_start; @@ -159,7 +159,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE) - && dc->cpu->cfg.illegal_opcode_exception) { + && dc->cfg->illegal_opcode_exception) { gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); } return cond; @@ -291,7 +291,7 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, #define DO_TYPEA_CFG(NAME, CFG, SE, FN) \ static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ - { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } + { return dc->cfg->CFG && do_typea(dc, a, SE, FN); } #define DO_TYPEA0(NAME, SE, FN) \ static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ @@ -299,7 +299,7 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, #define DO_TYPEA0_CFG(NAME, CFG, SE, FN) \ static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ - { return dc->cpu->cfg.CFG && do_typea0(dc, a, SE, FN); } + { return dc->cfg->CFG && do_typea0(dc, a, SE, FN); } #define DO_TYPEBI(NAME, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ @@ -307,7 +307,7 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, #define DO_TYPEBI_CFG(NAME, CFG, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ - { return dc->cpu->cfg.CFG && do_typeb_imm(dc, a, SE, FNI); } + { return dc->cfg->CFG && do_typeb_imm(dc, a, SE, FNI); } #define DO_TYPEBV(NAME, SE, FN) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ @@ -683,7 +683,7 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) tcg_gen_movi_tl(ret, 0); } - if ((ra == 1 || rb == 1) && dc->cpu->cfg.stackprot) { + if ((ra == 1 || rb == 1) && dc->cfg->stackprot) { gen_helper_stackprot(cpu_env, ret); } return ret; @@ -703,7 +703,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) tcg_gen_movi_tl(ret, (uint32_t)imm); } - if (ra == 1 && dc->cpu->cfg.stackprot) { + if (ra == 1 && dc->cfg->stackprot) { gen_helper_stackprot(cpu_env, ret); } return ret; @@ -712,7 +712,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) #ifndef CONFIG_USER_ONLY static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) { - int addr_size = dc->cpu->cfg.addr_size; + int addr_size = dc->cfg->addr_size; TCGv ret = tcg_temp_new(); if (addr_size == 32 || ra == 0) { @@ -772,7 +772,7 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, if (size > MO_8 && (dc->tb_flags & MSR_EE) && - dc->cpu->cfg.unaligned_exceptions) { + dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, false); mop |= MO_ALIGN; } @@ -918,7 +918,7 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, if (size > MO_8 && (dc->tb_flags & MSR_EE) && - dc->cpu->cfg.unaligned_exceptions) { + dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, true); mop |= MO_ALIGN; } @@ -1325,7 +1325,7 @@ DO_RTS(rtsd, 0) static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ - if (dc->cpu->cfg.opcode_0_illegal) { + if (dc->cfg->opcode_0_illegal) { trap_illegal(dc, true); return true; } @@ -1658,7 +1658,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); int bound; - dc->cpu = cpu; + dc->cfg = &cpu->cfg; dc->tb_flags = dc->base.tb->flags; dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; From patchwork Mon Sep 7 18:04:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 249259 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3895843ilg; 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[209.51.188.17]) by mx.google.com with ESMTPS id e11si11571578ybr.229.2020.09.07.11.13.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Sep 2020 11:13:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=s8v1bztA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kFLeD-0006Pn-FB for patch@linaro.org; Mon, 07 Sep 2020 14:13:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kFLW0-0003yj-Qg for qemu-devel@nongnu.org; Mon, 07 Sep 2020 14:05:16 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:46182) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kFLVy-0002Q1-JM for qemu-devel@nongnu.org; Mon, 07 Sep 2020 14:05:16 -0400 Received: by mail-pl1-x634.google.com with SMTP id q3so2886622plr.13 for ; Mon, 07 Sep 2020 11:05:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R/+aDRJdVbA7mUdPidQK/w3cut6NOnimDPbWUZWCJxA=; b=s8v1bztAsYrkgNNmQdBmVYSm35EDEmahsrRlbIiZqwWf8TFOiSW0F+ps2O/ZPGyHJ5 XagUuMnTn/xXEsVHbFVFuryE+6TqX220upji3kd9CgGTBDS1xw1QEnGOBhs+wG+xREzz E9MAuayVP2Tq6NJ2exyQyjR2EVE5i1BAqSIRvuciu3BPdy89d5OBS7kiua3kZu3xIzEF akisB7K036khAIKLu8Z4ITeykvuE9m9dLxxs2KNCkUNtqaax+lC2TBuPB3WmmGC7kO9N PDDsg9et167KjjZN2al4updJ1zHOzvkZXYLqqEeiGXsFD4SXrT2q9TqF8QVoPB5giZKX eVtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R/+aDRJdVbA7mUdPidQK/w3cut6NOnimDPbWUZWCJxA=; b=MqRUayrdfApW1rVTwflrYLy/kXHSl0vwatlJUi6EZlfYNkFiE7qBFOBDe+hEXavu0Y ZE5TSMrmjFb1415WDWIIpwWwlBBtGN1PLoOFXUFk0pI3IdenpO/VOTKnB5hSfwny2tCJ y5YdrnSiGbbftLKVaAJ7YFtclk2T2d+5T2N+CXQK+y/Nk/usMjC25M8sgLZn5jldZceR 5X0AjCYfXzGKifh5Wu+vBBVc5i9aK/9A8gH30JpN22XgVynpLsd9+mwngJiLiIPCcB/C gsFZ9uFVi/ZnB3NUvxbuxh9cA2ZuNmeaZcrUE01FSkCUMuoAKF/hfINQaazBbHeX8ppw ZWOg== X-Gm-Message-State: AOAM532QSCdGkVWENCzlZG5qOIjiGABK+ioci+sRLXzJ/Y0WPDl83+nR L5sFFCsjYKUhiMKclOO1lqAoMBAjOMI2ng== X-Received: by 2002:a17:902:7405:: with SMTP id g5mr18579555pll.248.1599501912935; Mon, 07 Sep 2020 11:05:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id v6sm11367768pfi.38.2020.09.07.11.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2020 11:05:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 19/19] configure: Do not set TARGET_ABI32 for microblaze Date: Mon, 7 Sep 2020 11:04:59 -0700 Message-Id: <20200907180459.29025-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200907180459.29025-1-richard.henderson@linaro.org> References: <20200907175102.28027-1-richard.henderson@linaro.org> <20200907180459.29025-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In 19f27b6c2493 TARGET_ABI_LONG was reduced to 32 bits for CONFIG_USER_ONLY. There is no need to set this by hand; it will now be set automatically by include/exec/user/abitypes.h. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Reported-by: Peter Maydell Signed-off-by: Richard Henderson --- configure | 1 - 1 file changed, 1 deletion(-) -- 2.25.1 diff --git a/configure b/configure index 922adbc43a..83bdc91eed 100755 --- a/configure +++ b/configure @@ -7749,7 +7749,6 @@ case "$target_name" in TARGET_SYSTBL_ABI=common mttcg="yes" bflt="yes" - echo "TARGET_ABI32=y" >> $config_target_mak ;; mips|mipsel) mttcg="yes"