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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id r8sm754854lfm.42.2020.09.03.11.42.02 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 11:42:03 -0700 (PDT) From: Grzegorz Jaszczyk To: ssantosh@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, santosh.shilimkar@oracle.com, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, tony@atomide.com Subject: [PATCH 1/2] dt-bindings: soc: ti: Update TI PRUSS bindings regarding clock-muxes Date: Thu, 3 Sep 2020 20:41:40 +0200 Message-Id: <1599158501-8302-2-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599158501-8302-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1599158501-8302-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org ICSS/ICSSG modules have an IEP clock mux that allow selection of internal IEP clock from 2 clock sources. ICSSG module has a CORE clock mux that allows selection of internal CORE clock from 2 clock sources. Add binding information for these 2 clock muxes. Signed-off-by: Grzegorz Jaszczyk --- .../devicetree/bindings/soc/ti/ti,pruss.yaml | 121 ++++++++++++++++++++- 1 file changed, 120 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml index a13e4df..037c51b 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -132,10 +132,99 @@ patternProperties: - const: ti,pruss-cfg - const: syscon + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + reg: maxItems: 1 - additionalProperties: false + ranges: + maxItems: 1 + + clocks: + type: object + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + coreclk-mux@[a-f0-9]+$: + description: | + This is applicable only for ICSSG (K3 SoCs). The ICSSG modules + core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or + ICSSG_ICLK. This node models this clock mux and should have the + name "coreclk-mux". + + type: object + + properties: + '#clock-cells': + const: 0 + + clocks: + items: + - description: ICSSG_CORE Clock + - description: ICSSG_ICLK Clock + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + description: | + Standard assigned-clocks-parents definition used for selecting + mux parent (one of the mux input). + + reg: + maxItems: 1 + + required: + - clocks + + additionalProperties: false + + iepclk-mux@[a-f0-9]+$: + description: | + The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or + CORE_CLK (OCP_CLK in older SoCs). This node models this clock + mux and should have the name "iepclk-mux". + + type: object + + properties: + '#clock-cells': + const: 0 + + clocks: + items: + - description: ICSSG_IEP Clock + - description: Core Clock (OCP Clock in older SoCs) + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + description: | + Standard assigned-clocks-parents definition used for selecting + mux parent (one of the mux input). + + reg: + maxItems: 1 + + required: + - clocks + + additionalProperties: false + + additionalProperties: false iep@[a-f0-9]+$: description: | @@ -259,7 +348,22 @@ examples: pruss_cfg: cfg@26000 { compatible = "ti,pruss-cfg", "syscon"; + #address-cells = <1>; + #size-cells = <1>; reg = <0x26000 0x2000>; + ranges = <0x00 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&l3_gclk>, /* icss_iep */ + <&pruss_ocp_gclk>; /* icss_ocp */ + }; + }; }; pruss_mii_rt: mii-rt@32000 { @@ -298,7 +402,22 @@ examples: pruss1_cfg: cfg@26000 { compatible = "ti,pruss-cfg", "syscon"; + #address-cells = <1>; + #size-cells = <1>; reg = <0x26000 0x2000>; + ranges = <0x00 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss1_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&sysclk_div>, /* icss_iep */ + <&pruss_ocp_gclk>; /* icss_ocp */ + }; + }; }; pruss1_mii_rt: mii-rt@32000 { From patchwork Thu Sep 3 18:41:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 249037 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp717116ilg; Thu, 3 Sep 2020 11:42:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZWgc46PNmIiJuZhPDdWIEnStZs50dR+OynqYkzo2RUjB/fzryRyT7IAfFa1J5HHlLoMo+ X-Received: by 2002:a17:906:25d3:: with SMTP id n19mr3387431ejb.551.1599158535530; Thu, 03 Sep 2020 11:42:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599158535; cv=none; d=google.com; s=arc-20160816; b=kylomYpeUPcB4aMnYNShApyhkG0afoxZ40B7PQCZ0dswC13Yq5fx1UZl8KhAF4ug5r 95N9s4LOEWSEKYDiCvAxgs4cxHRE5sDHTX87oy3r7I+NXqExDHqMz+UvBQinItUR2o+Z NBZTQI3U3v54P9PavqJgyH3vgm1ugo4/Ybyw0CeoEwPvszZMoY0gh5MFmvQb9XsPLvCH HWfyc9ccTk0IGe/uYhgGSj5ZxAt+O+m2//VsH6AmIkRhv116okTx+oIJW4kER4cEwvEx vQWOGtMFC/XWB3sqMA+aXIgcyNO2ysPf5ldOwUsORRlycyGJo4TvcNESksJ78itQSPPp H06A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=EQQn6igoQHhSsSJgk3MRYdysLU2N7iqRMh2t7mrUk/Q=; b=vQWGNf/7+rM2PoGkogmJTNVV5Lcf8ueCZfS9ydPQCmQMPUcRhVhUVyK+fLUiH9He1w WXU2QuJJWSOtuTURN6mCR5weAeHhHunU/3HwQQ25UVbeTgT5S7OcnsroDi6Siek92H2+ ZFB3S+Pc/4JqXnY6x3kVQ1CycbnaEn+OkPUjTZi0PG9VGSVUtvk4eAWH4BYMf/poxZbg b5J22sOWHRh8Sjb95j2xLaKdetBS3hdPOWtVwxZeRMte9lJgkbaf2EtJPw1Pj/DtpcFb m2oX5T987z8JYF7soypcUQKl8IrwVEZInJgcf2XJUGkMTGLvf6aMYq0CbsiQ+81MLJAf DOvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UT95ePuD; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id r8sm754854lfm.42.2020.09.03.11.42.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 11:42:05 -0700 (PDT) From: Grzegorz Jaszczyk To: ssantosh@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, santosh.shilimkar@oracle.com, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, tony@atomide.com, Roger Quadros Subject: [PATCH 2/2] soc: ti: pruss: support CORECLK_MUX and IEPCLK_MUX Date: Thu, 3 Sep 2020 20:41:41 +0200 Message-Id: <1599158501-8302-3-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599158501-8302-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1599158501-8302-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The IEPCLK_MUX is present on all SoCs whereas the CORECLK_MUX is present only on AM65x SoCs and J721E. Add support for both these CLK muxes. This allows the clock rates and clock parents for these to be controlled through DT leveraging the clk infrastructure for configuring the default parents and rates. Signed-off-by: Roger Quadros Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- drivers/soc/ti/pruss.c | 184 +++++++++++++++++++++++++++++++++++++++++-- include/linux/pruss_driver.h | 6 ++ 2 files changed, 183 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 37df543..cc0b4ad 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -8,6 +8,7 @@ * Andrew F. Davis */ +#include #include #include #include @@ -16,13 +17,150 @@ #include #include #include +#include +#include /** * struct pruss_private_data - PRUSS driver private data * @has_no_sharedram: flag to indicate the absence of PRUSS Shared Data RAM + * @has_core_mux_clock: flag to indicate the presence of PRUSS core clock */ struct pruss_private_data { bool has_no_sharedram; + bool has_core_mux_clock; +}; + +static void pruss_of_free_clk_provider(void *data) +{ + struct device_node *clk_mux_np = data; + + of_clk_del_provider(clk_mux_np); + of_node_put(clk_mux_np); +} + +static int pruss_clk_mux_setup(struct pruss *pruss, struct clk *clk_mux, + char *mux_name, struct device_node *clks_np) +{ + struct device_node *clk_mux_np; + struct device *dev = pruss->dev; + char *clk_mux_name; + unsigned int num_parents; + const char **parent_names; + void __iomem *reg; + u32 reg_offset; + int ret; + + clk_mux_np = of_get_child_by_name(clks_np, mux_name); + if (!clk_mux_np) { + dev_err(dev, "%pOF is missing its '%s' node\n", clks_np, + mux_name); + return -ENODEV; + } + + num_parents = of_clk_get_parent_count(clk_mux_np); + if (num_parents < 1) { + dev_err(dev, "mux-clock %pOF must have parents\n", clk_mux_np); + ret = -EINVAL; + goto put_clk_mux_np; + } + + parent_names = devm_kcalloc(dev, sizeof(*parent_names), num_parents, + GFP_KERNEL); + if (!parent_names) { + ret = -ENOMEM; + goto put_clk_mux_np; + } + + of_clk_parent_fill(clk_mux_np, parent_names, num_parents); + + clk_mux_name = devm_kasprintf(dev, GFP_KERNEL, "%s.%pOFn", + dev_name(dev), clk_mux_np); + if (!clk_mux_name) { + ret = -ENOMEM; + goto put_clk_mux_np; + } + + ret = of_property_read_u32(clk_mux_np, "reg", ®_offset); + if (ret) + goto put_clk_mux_np; + + reg = pruss->cfg_base + reg_offset; + + clk_mux = clk_register_mux(NULL, clk_mux_name, parent_names, + num_parents, 0, reg, 0, 1, 0, NULL); + if (IS_ERR(clk_mux)) { + ret = PTR_ERR(clk_mux); + goto put_clk_mux_np; + } + + ret = devm_add_action_or_reset(dev, (void(*)(void *))clk_unregister_mux, + clk_mux); + if (ret) { + dev_err(dev, "failed to add clkmux unregister action %d", ret); + goto put_clk_mux_np; + } + + ret = of_clk_add_provider(clk_mux_np, of_clk_src_simple_get, clk_mux); + if (ret) + goto put_clk_mux_np; + + ret = devm_add_action_or_reset(dev, pruss_of_free_clk_provider, + clk_mux_np); + if (ret) { + dev_err(dev, "failed to add clkmux free action %d", ret); + goto put_clk_mux_np; + } + + return 0; + +put_clk_mux_np: + of_node_put(clk_mux_np); + return ret; +} + +static int pruss_clk_init(struct pruss *pruss, struct device_node *cfg_node) +{ + const struct pruss_private_data *data; + struct device_node *clks_np; + struct device *dev = pruss->dev; + int ret = 0; + + data = of_device_get_match_data(dev); + if (IS_ERR(data)) + return -ENODEV; + + clks_np = of_get_child_by_name(cfg_node, "clocks"); + if (!clks_np) { + dev_err(dev, "%pOF is missing its 'clocks' node\n", clks_np); + return -ENODEV; + } + + if (data && data->has_core_mux_clock) { + ret = pruss_clk_mux_setup(pruss, pruss->core_clk_mux, + "coreclk-mux", clks_np); + if (ret) { + dev_err(dev, "failed to setup coreclk-mux\n"); + goto put_clks_node; + } + } + + ret = pruss_clk_mux_setup(pruss, pruss->iep_clk_mux, "iepclk-mux", + clks_np); + if (ret) { + dev_err(dev, "failed to setup iepclk-mux\n"); + goto put_clks_node; + } + +put_clks_node: + of_node_put(clks_np); + + return ret; +} + +static struct regmap_config regmap_conf = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, }; static int pruss_probe(struct platform_device *pdev) @@ -114,21 +252,49 @@ static int pruss_probe(struct platform_device *pdev) goto rpm_put; } - pruss->cfg_regmap = syscon_node_to_regmap(child); - of_node_put(child); + if (of_address_to_resource(child, 0, &res)) { + ret = -ENOMEM; + goto node_put; + } + + pruss->cfg_base = devm_ioremap(dev, res.start, resource_size(&res)); + if (!pruss->cfg_base) { + ret = -ENOMEM; + goto node_put; + } + + regmap_conf.name = kasprintf(GFP_KERNEL, "%pOFn@%llx", child, + (u64)res.start); + regmap_conf.max_register = resource_size(&res) - 4; + + pruss->cfg_regmap = devm_regmap_init_mmio(dev, pruss->cfg_base, + ®map_conf); + kfree(regmap_conf.name); if (IS_ERR(pruss->cfg_regmap)) { - ret = -ENODEV; - goto rpm_put; + dev_err(dev, "regmap_init_mmio failed for cfg, ret = %ld\n", + PTR_ERR(pruss->cfg_regmap)); + ret = PTR_ERR(pruss->cfg_regmap); + goto node_put; + } + + ret = pruss_clk_init(pruss, child); + if (ret) { + dev_err(dev, "failed to setup coreclk-mux\n"); + goto node_put; } ret = devm_of_platform_populate(dev); if (ret) { dev_err(dev, "failed to register child devices\n"); - goto rpm_put; + goto node_put; } + of_node_put(child); + return 0; +node_put: + of_node_put(child); rpm_put: pm_runtime_put_sync(dev); rpm_disable: @@ -157,14 +323,18 @@ static const struct pruss_private_data am437x_pruss0_data = { .has_no_sharedram = true, }; +static const struct pruss_private_data am65x_j721e_pruss_data = { + .has_core_mux_clock = true, +}; + static const struct of_device_id pruss_of_match[] = { { .compatible = "ti,am3356-pruss" }, { .compatible = "ti,am4376-pruss0", .data = &am437x_pruss0_data, }, { .compatible = "ti,am4376-pruss1", .data = &am437x_pruss1_data, }, { .compatible = "ti,am5728-pruss" }, { .compatible = "ti,k2g-pruss" }, - { .compatible = "ti,am654-icssg" }, - { .compatible = "ti,j721e-icssg" }, + { .compatible = "ti,am654-icssg", .data = &am65x_j721e_pruss_data, }, + { .compatible = "ti,j721e-icssg", .data = &am65x_j721e_pruss_data, }, {}, }; MODULE_DEVICE_TABLE(of, pruss_of_match); diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h index 0701fe1..ecfded3 100644 --- a/include/linux/pruss_driver.h +++ b/include/linux/pruss_driver.h @@ -36,13 +36,19 @@ struct pruss_mem_region { /** * struct pruss - PRUSS parent structure * @dev: pruss device pointer + * @cfg_base: base iomap for CFG region * @cfg_regmap: regmap for config region * @mem_regions: data for each of the PRUSS memory regions + * @core_clk_mux: clk handle for PRUSS CORE_CLK_MUX + * @iep_clk_mux: clk handle for PRUSS IEP_CLK_MUX */ struct pruss { struct device *dev; + void __iomem *cfg_base; struct regmap *cfg_regmap; struct pruss_mem_region mem_regions[PRUSS_MEM_MAX]; + struct clk *core_clk_mux; + struct clk *iep_clk_mux; }; #endif /* _PRUSS_DRIVER_H_ */