From patchwork Thu Sep 3 12:05:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249002 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp385420ilg; Thu, 3 Sep 2020 05:12:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy48HZye+ptACXZpzL2jGb/JI8zVsbq/5INy3UhA5mGUAGMQZ9Jkvt+mbLjbGJtJ3mqW4tG X-Received: by 2002:a17:906:a141:: with SMTP id bu1mr1773011ejb.303.1599135151327; Thu, 03 Sep 2020 05:12:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599135151; cv=none; d=google.com; s=arc-20160816; b=avKPMF+bktCpCvCwQahP44iKul1qdhqRiSF/m5RBFPpYBKuQF8v9GhJQMBa1GE0iPi pZZNGffyOLa+UIegPkyNL3PvEY6/XIq5hShm9d+WmDmliwRSy0WYtruK/wKYesjcOxoF Je36/k/VO6W3ETFENun+rgoYbrpSgZqm7URew8lvhQXRBcrWRyGGubsKvRGnlA1Kffgo t2bGlpGPe6BpR27HXatfI3WH6r+B57JsRUtgp3PbFats9YRNlTloh83USIpty4vC5GY8 D8im5X0Ei27gcHhTHlUajkw4yY5IWpodIYqPygb4a0Td9XUbvHxSEMS/u0XFSEtO1IVt km2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=6MW6xuUFdFupg6cBbkQHmmQE+y5gGuZiqi9ePNIY7nw=; b=Ed9U29dyXVpB5OtmqtnLJlEB1EShlEsYkK4xrV3FeqQsrRv01igWGrrvJgS5M9bHGK LyOH/vlffwJyinD57mvG/wPkLBVwV3U3Ht3qbWJwbtNF4jfbxjQMjO8tX65sgmHAtKKg VPBy27Q8xHOm9km51l8jvY9sct4lSsjDcKScSe3Dq/GM6LSenlKNh0p3sUj793VKkEwc tw7AEmPRmIrZWNUr2OQy2RMa+j7SUmYwYS6SpeGy8GI/buStuKiyU0/yWZquMDiQXAMb 09vdRe5f/d9H9+lM5Pg+xKqcn/utrHusrUS6dahrR2WuzVLdiERqJvd1UqerSIofcvT3 zlFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y10si1636903edi.9.2020.09.03.05.12.31; Thu, 03 Sep 2020 05:12:31 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728800AbgICMJm (ORCPT + 6 others); Thu, 3 Sep 2020 08:09:42 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:37492 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728810AbgICMFw (ORCPT ); Thu, 3 Sep 2020 08:05:52 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6FDF925D277F9FD9C604; Thu, 3 Sep 2020 20:05:27 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Thu, 3 Sep 2020 20:05:19 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Kefeng Wang Subject: [PATCH 1/2] dt-bindings: interrupt-controller: add Hisilicon SD5203 vector interrupt controller Date: Thu, 3 Sep 2020 20:05:03 +0800 Message-ID: <20200903120504.2308-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200903120504.2308-1-thunder.leizhen@huawei.com> References: <20200903120504.2308-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings for the Hisilicon SD5203 vector interrupt controller. Signed-off-by: Zhen Lei --- .../hisilicon,sd5203-vic.txt | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt -- 2.26.0.106.g9fadedd diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt new file mode 100644 index 000000000000..a08292e868b0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt @@ -0,0 +1,27 @@ +Hisilicon SD5203 vector interrupt controller (VIC) + +Hisilicon SD5203 VIC based on Synopsys DesignWare APB interrupt controller, but +there's something special: +1. The maximum number of irqs supported is 32. The registers ENABLE, MASK and + FINALSTATUS are 32 bits. +2. There is only one VIC, it's used as primary interrupt controller. + +Required properties: +- compatible: shall be "hisilicon,sd5203-vic" +- reg: physical base address of the controller and length of memory mapped + region starting with ENABLE_LOW register +- interrupt-controller: identifies the node as an interrupt controller +- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 + +The interrupt sources map to the corresponding bits in the interrupt +registers, i.e. +- 0 maps to bit 0 of low interrupts, +- 1 maps to bit 1 of low interrupts, + +Example: + vic: interrupt-controller@10130000 { + compatible = "hisilicon,sd5203-vic"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; From patchwork Thu Sep 3 12:05:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 249001 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp384178ilg; Thu, 3 Sep 2020 05:11:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJysRbvLK7+OWgplmF90P8PGnBbYPYoe2UvTKfR38EtV7ypUDujbmWkxiYI/KnAS798HP7KT X-Received: by 2002:a05:6402:10da:: with SMTP id p26mr2704147edu.77.1599135063632; Thu, 03 Sep 2020 05:11:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599135063; cv=none; d=google.com; s=arc-20160816; b=louUIF4k4Ans3ju2cE1c0lDuR8DIpp/hR180igUxwSBm2Gj7AGAOdodY46b/BkeE22 C87Gdlbki6RrmNRqFlLmmeFmGFtglwpSWSy2V1ypvhldko1/UJ04Y1qvfZL1h4aYkTkl 09YkittOgMDHA3637x3uezt5MIv9LF3EIlDIIRQb/kibW/W3VZqt9rU88YP7HC93+Xvl zbww7Dhq9OR0o69MDO3fbaXUzO65ZdX5IR8qV5li/AqvT1YMjz2xf/ujB4K5IfzCCHCA BWSQEb8UaPTWAl/MNsLLDpbO8I0eyaSZJtA+PIcGoYai43nZU5xcbWHudfVR9iXzC1r7 frMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=5md1h0GG9kvZEeel94kRAIeCVTNUBLTGRQJV8bYfsOQ=; b=ebHW4Yh6BiR+PwLS8c4CFoPWkZhTyB8ukU8wusUrqIkw5SZTNootjx+frFkXU+16hK VM7Bh5dwYAKfwtpdgosVfzmsyEx0PSd12hxa+TWAfG/Hc7ySYpX7ofG9j/vZUlcwOkuG xGx2Hpw7c2Td5lVrvuKs9R79ASaV2n+JD+An2lbMcrASJSlZht4jgMwv3l2Fl69oy/Wx RwQQW8UGg7K5uHqfF4zOti4zh4BLHN80cV2CZWZAkRQTg/S5yAA4J1JKo5EJOCgUYppk mO1hwvxzfcjx+byvebmfFpxRYL6UXgYVSowgzTWpoy89pf+2VOJbNWX81pvLykod1CEI PfeA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y10si1636903edi.9.2020.09.03.05.11.03; Thu, 03 Sep 2020 05:11:03 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728685AbgICMKY (ORCPT + 6 others); Thu, 3 Sep 2020 08:10:24 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:37488 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728812AbgICMFw (ORCPT ); Thu, 3 Sep 2020 08:05:52 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 680E1DE6978487D84FB4; Thu, 3 Sep 2020 20:05:27 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Thu, 3 Sep 2020 20:05:20 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Kefeng Wang Subject: [PATCH 2/2] irqchip: add Hisilicon SD5203 vector interrupt controller Date: Thu, 3 Sep 2020 20:05:04 +0800 Message-ID: <20200903120504.2308-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200903120504.2308-1-thunder.leizhen@huawei.com> References: <20200903120504.2308-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang This adds an irqchip driver and corresponding devicetree binding for the primary interrupt controller based on Hisilicon SD5203 VIC(vector interrupt controller). Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- drivers/irqchip/Kconfig | 5 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sd5203-vic.c | 128 +++++++++++++++++++++++++++++++ 3 files changed, 134 insertions(+) create mode 100644 drivers/irqchip/irq-sd5203-vic.c -- 2.26.0.106.g9fadedd diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bfc9719dbcdc..f64611a47cf2 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -156,6 +156,11 @@ config FARADAY_FTINTC010 select GENERIC_IRQ_MULTI_HANDLER select SPARSE_IRQ +config HISILICON_SD5203_VIC + bool + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN_HIERARCHY + config HISILICON_IRQ_MBIGEN bool select ARM_GIC_V3 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 133f9c45744a..94b98f881940 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o obj-$(CONFIG_ARM_GIC_V3_ITS_PCI) += irq-gic-v3-its-pci-msi.o obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o +obj-$(CONFIG_HISILICON_SD5203_VIC) += irq-sd5203-vic.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o obj-$(CONFIG_ARM_NVIC) += irq-nvic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o diff --git a/drivers/irqchip/irq-sd5203-vic.c b/drivers/irqchip/irq-sd5203-vic.c new file mode 100644 index 000000000000..f6f8fd75f1ab --- /dev/null +++ b/drivers/irqchip/irq-sd5203-vic.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Hisilicon SD5203 irqchip driver. + * Based on Synopsys DW APB ICTL irqchip driver. + * + */ + +#include +#include +#include +#include +#include +#include + +#define HISI_VIC_INT_ENABLE 0x00 +#define HISI_VIC_INT_MASK 0x08 +#define HISI_VIC_INT_FINALSTATUS 0x30 +#define HISI_VIC_MAX_IRQ 32 + +static struct irq_domain *hisi_vic_irq_domain; +static void __iomem *hisi_vic_iobase; + +static void __exception_irq_entry hisi_vic_handle_irq(struct pt_regs *regs) +{ + u32 stat = readl_relaxed(hisi_vic_iobase + HISI_VIC_INT_FINALSTATUS); + u32 hwirq; + + while (stat) { + hwirq = fls(stat) - 1; + handle_domain_irq(hisi_vic_irq_domain, hwirq, regs); + stat &= ~BIT(hwirq); + } +} + +static int hisi_vic_irq_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (WARN_ON(fwspec->param_count < 1)) + return -EINVAL; + + *hwirq = fwspec->param[0]; + *type = IRQ_TYPE_NONE; + + return 0; +} + +static int hisi_vic_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = hisi_vic_irq_domain_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + irq_map_generic_chip(domain, virq + i, hwirq + i); + + return 0; +} + +static const struct irq_domain_ops hisi_vic_irq_domain_ops = { + .translate = hisi_vic_irq_domain_translate, + .alloc = hisi_vic_irq_domain_alloc, + .free = irq_domain_free_irqs_top, +}; + +static int __init hisi_sd5203_vic_init(struct device_node *np, + struct device_node *parent) +{ + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + struct irq_chip_generic *gc; + int ret; + + if (hisi_vic_iobase) { + pr_err("%pOF: the irqchip has been registered.\n", np); + return -EBUSY; + } + + hisi_vic_iobase = of_iomap(np, 0); + if (!hisi_vic_iobase) { + pr_err("%pOF: unable to map resource\n", np); + return -ENOMEM; + } + + hisi_vic_irq_domain = irq_domain_add_linear(np, HISI_VIC_MAX_IRQ, + &hisi_vic_irq_domain_ops, NULL); + if (!hisi_vic_irq_domain) { + pr_err("%pOF: unable to add irq domain\n", np); + ret = -ENOMEM; + goto err_unmap; + } + + ret = irq_alloc_domain_generic_chips(hisi_vic_irq_domain, + HISI_VIC_MAX_IRQ, 1, + np->name, handle_fasteoi_irq, + clr, 0, IRQ_GC_INIT_MASK_CACHE); + if (ret) { + pr_err("%pOF: unable to alloc irq domain gc\n", np); + goto err_unmap; + } + + /* mask and enable all interrupts */ + writel_relaxed(~0, hisi_vic_iobase + HISI_VIC_INT_MASK); + writel_relaxed(~0, hisi_vic_iobase + HISI_VIC_INT_ENABLE); + + gc = irq_get_domain_generic_chip(hisi_vic_irq_domain, 0); + gc->reg_base = hisi_vic_iobase; + gc->chip_types[0].regs.mask = HISI_VIC_INT_MASK; + gc->chip_types[0].regs.enable = HISI_VIC_INT_ENABLE; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_eoi = irq_gc_noop; + + set_handle_irq(hisi_vic_handle_irq); + return 0; + +err_unmap: + iounmap(hisi_vic_iobase); + return ret; +} +IRQCHIP_DECLARE(hisi_sd5203_vic, "hisilicon,sd5203-vic", hisi_sd5203_vic_init);