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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not attempting to use a single cross-compiler for both big-endian and little-endian at this time. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- tests/tcg/configure.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 7d714f902a..598a50cd4f 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -94,7 +94,7 @@ for target in $target_list; do xtensa|xtensaeb) arches=xtensa ;; - alpha|cris|hppa|i386|lm32|m68k|openrisc|riscv64|s390x|sh4|sparc64) + alpha|cris|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64) arches=$target ;; *) From patchwork Mon Aug 31 16:04:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248753 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3441927ilg; Mon, 31 Aug 2020 09:08:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJzptRYr93megXaoMoaEN9BL/BVBh0RQkyzFlEVP3vVbi/ao5LGjy0SJqNitoEFoipKzTC X-Received: by 2002:a25:3b8e:: with SMTP id i136mr3220546yba.64.1598890110232; Mon, 31 Aug 2020 09:08:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890110; cv=none; d=google.com; s=arc-20160816; b=xX2jH9SUMol9yrTX9M9EzrbtPeDhkQwdUdlJX3oC7wqXFCw4U56swvWRPSZdaSdmNO I5NJPrdEyU0MKnwccndTAtZq2RCEQvxQa1W3Aggezqc4PzSoqI6QS1P4PA67h2FcBQzl uw+za0pn+nl5FbBTsQpRcycZgEirO5NNc7K4Aq5nScNbQjZyiuTBRtSv8KWDfMAGh5/U 60RNkNZyMRT+tICoVSFs8ODPPdYyf2H41FN4tbOz88aYuWn/b1Far4VFswa9gPcDb0Mq YTTNpup/jKxuEMeHHTYgVdbmMVrRjQ4eIi+oH+/AC7tKP/GRbK1DDakh6HACAM08p58w rPcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4SYcyC7WRrB7DQoqG8Jlb5pwufeHvMZ+/v7u+myx2PU=; b=v2h6xyRlrI7EbzD4egqLjOokVPknQih8FPjJVMITk9OHBsqArUDh6503XblRR2wawG tfM0v40zoLVExpJYSmMXiISOVWTjIUvWEKBBGESjTL6isPPLGC6n11XvGC8jv2WSD6VY Arfh0JRh25wuf4Rl3Rk7dUabgUvtuIdxPd3rgcOo0TwdSI7apRw01Jlx42JP79+wVwwn ZthutJkIgLngkaNJYrM4qX+lxjTF2ztPM9Ncw/c7xi4sKhBBQ42Crrskt5F2qzieUZEw vHXoroRiQUS8iYXQ/LW2hqIb06ABlalCBTo0qNuzje8XXJSv4HFN25t1SqXFrP3bGugx FqTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=d7LhMucO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is optional in ISO C, and not all cpus provide it. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- tests/tcg/multiarch/float_convs.c | 2 ++ tests/tcg/multiarch/float_madds.c | 2 ++ 2 files changed, 4 insertions(+) -- 2.25.1 diff --git a/tests/tcg/multiarch/float_convs.c b/tests/tcg/multiarch/float_convs.c index 47e24b8b16..e9be75c2d5 100644 --- a/tests/tcg/multiarch/float_convs.c +++ b/tests/tcg/multiarch/float_convs.c @@ -30,7 +30,9 @@ float_mapping round_flags[] = { #ifdef FE_DOWNWARD { FE_DOWNWARD, "downwards" }, #endif +#ifdef FE_TOWARDZERO { FE_TOWARDZERO, "to zero" } +#endif }; static void print_input(float input) diff --git a/tests/tcg/multiarch/float_madds.c b/tests/tcg/multiarch/float_madds.c index eceb4ae38b..e422608ccd 100644 --- a/tests/tcg/multiarch/float_madds.c +++ b/tests/tcg/multiarch/float_madds.c @@ -29,7 +29,9 @@ float_mapping round_flags[] = { #ifdef FE_DOWNWARD { FE_DOWNWARD, "downwards" }, #endif +#ifdef FE_TOWARDZERO { FE_TOWARDZERO, "to zero" } +#endif }; From patchwork Mon Aug 31 16:04:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248754 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3441983ilg; Mon, 31 Aug 2020 09:08:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzUq34j9mCZnc4n9Fx+crXJMPY1eAfyDkXMnKRxWZulc9nSHwUFvwXiwW7m/vIyTxOBgPCI X-Received: by 2002:a25:c2c5:: with SMTP id s188mr3330812ybf.245.1598890114138; Mon, 31 Aug 2020 09:08:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890114; cv=none; d=google.com; s=arc-20160816; b=SkGN+L8iU/83orJQ2vbmIlhV6HYP74hpmoaHscjk+ivJbd2nC8HktsVjzpteM9OlIN SNI7BltHfUjFNYkt83Mh+R86GROkRcyQ4FzevyqrIiZYml8nyGP1VXC6WtRVpvxXBF+5 1FGnT4l6Wncst6Db9WBEu/TiX/cwKk2ygDzDxUdkJZu8q8Immlx2vUeAhmOkVuN8PbAG XinFXnrb7XCPNddfCxHI2aFOrkZiZs7YfG78rHaAhu0Q13iwXwfOfASN4lfL6txh6ZlV anM17hQYFXzI6PNc7vFudXZSK7UE5DtmPy4m2JHPDTeXN7vPsHFYCKyhhpReU3FPSC6n lEZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=unhCEa+c++7uk9+yQ2XBvkX8JjrsH/tZ97/HnRS/zo4=; b=Oe0Z5DTrG6VX68urQIswPPDjx+7cjoY90PnciqRN6C8B2yGZrBpJbZwpF1Qj75lAaH oInOfndpB/lheOxa1facelW/yavWz9giCaLuBlL7V/EBHrKY0hoSqbwsMP4gU1WRlDWx bOEzGsq+Yy6T6LW1/MqmuhbacVN8NMwjxOl7KsrxqVEixn89e+k0Rp32Zzcfff58wrpI qv0nnQ4AmjZMCYKtsIF+AGvJAEQBmDd/DvzJqExXE43PObQESwQAxQWHU0PCg15Lgzgu t0OBoIbtWoWByAVA5ZQzdfIoM+ofATBEL+8Uhu8Vi2a1D4uz9p97WeOx9TPW7iQ2h5jl KsRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C9aKhV9z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Define anything that is missing as 0, so that flags & FE_FOO is false for any missing FOO. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- tests/tcg/multiarch/float_helpers.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.25.1 diff --git a/tests/tcg/multiarch/float_helpers.h b/tests/tcg/multiarch/float_helpers.h index 6337bc66c1..309f3f4bf1 100644 --- a/tests/tcg/multiarch/float_helpers.h +++ b/tests/tcg/multiarch/float_helpers.h @@ -8,6 +8,23 @@ #include +/* Some hosts do not have support for all of these; not required by ISO C. */ +#ifndef FE_OVERFLOW +#define FE_OVERFLOW 0 +#endif +#ifndef FE_UNDERFLOW +#define FE_UNDERFLOW 0 +#endif +#ifndef FE_DIVBYZERO +#define FE_DIVBYZERO 0 +#endif +#ifndef FE_INEXACT +#define FE_INEXACT 0 +#endif +#ifndef FE_INVALID +#define FE_INVALID 0 +#endif + /* Number of constants in each table */ int get_num_f16(void); int get_num_f32(void); From patchwork Mon Aug 31 16:04:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248758 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3443269ilg; Mon, 31 Aug 2020 09:10:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyiND9vv4cvaxTKutJkYiV5JMYB5UvJ600B7rqS6uLsoXgoHGqJYVA+GvK4OKny9kXtLW03 X-Received: by 2002:a25:7b44:: with SMTP id w65mr3166100ybc.243.1598890213037; Mon, 31 Aug 2020 09:10:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890213; cv=none; d=google.com; s=arc-20160816; b=Pyny261DJ7UdTUh/Hs+ZR3KQNcmZjw/0fqMs+Nry6cOxgFfVomeVOMappPCft+aFBf vFR43Xo1MiG6HBPQEdLLrGH/UKc/PaSaGEhZR6ZoPfeLCgDeKqDCqUCzO7p4aFwgh0Yt E2Ss85ZEmObqSAf6XtVKU51BuvJZuAPzLkb8A9TbxMwqcTMJ7eFbGBfX8kuJjzXFFXlH Yrus3V448sbwwmuznr4FIMs2RJxypE5NUd1VlomSrJlvRQYdkh2VJbiaE3jdxKihE1Bo BPlsxLT7jEAPEFbcQWauUzuLhqB2CStUn94bvNVqtfw2AWreyXOjv0imI1AZqFT3iKJJ Hbcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EAqHVd7k8qnFGYSw1XH+Q9LqQUEdcVQsZIdVmMRUJCo=; b=aC/zDNwJMrChABmR5r1Icid5DoRX991Izar0ihSx3Jz+qOFSGpUBDb8K2yyWctOGQf j0ZPpboeOs8e8F0d/bweBE5aHr5hvBWUzU4CLmJT40VtMx8x3vwciugpilFLaElikedd DUSB999QDUggq7AKewcUpoQlDQqE8QiLciHmCtDjR5vuZV0e+s8yWqk18FoBpgLeH/kp +tpLSGgMlZ8I4S30jSSl0YT4+RU95RNKIHPxkC926whj8t8wP5gjFVKyez8Zl/KwjYcg V4AyxvfJQZzSR6kFODsjBTzhTqV2l5XRkj8QgDvQioww6ke1uFmr669BZMbnkw/gNWsK i4UA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yaEv84Dw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f5si4722433ybp.213.2020.08.31.09.10.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:10:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yaEv84Dw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmNo-0001th-HN for patch@linaro.org; Mon, 31 Aug 2020 12:10:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmJy-0003SX-Pp for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:14 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:40379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmJv-0005u4-Qe for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:14 -0400 Received: by mail-pf1-x430.google.com with SMTP id c142so804699pfb.7 for ; Mon, 31 Aug 2020 09:06:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EAqHVd7k8qnFGYSw1XH+Q9LqQUEdcVQsZIdVmMRUJCo=; b=yaEv84DwJSc1LaJNI+Yu4tyRP9PN6oLWy6S+wvSiSuMRkFUi5Qvs8ajcINvPTck8Qs Kcx9UUjk0fC2BOh67v2j4VRB+82fNqU3wgv6nYEA5j/ynLyjbAOKe3rI0h/aLUXntwjW T5liPMFFEUagpYpYBaMjJ111D6GonBo8TUaArh8AEbz9RFVF5h7BjLfZrRSXx0PU/DMi qQZoqRZyS+7tvcWMdsXmaNmz8fxCrFlgqhLJAkucrB0il68gM9WYb7q7dCKv0rI6ZEKN clpEzrQp814qqpE1It1VhQlIv5cZ3LAGQUkn0lhlo7tlyJAm4LgWub/EnypNJ+Qnakgj IyRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EAqHVd7k8qnFGYSw1XH+Q9LqQUEdcVQsZIdVmMRUJCo=; b=A/42wvBBVzyt434rzFYtQRSqcYt/NlG6ZjiREUGADoRh6bUzH4EStFRNdYJFftErXL SZ7mPlCoO3Ytxgs4CkoQzeEtgXFSz3VdSJ9wnGzeTqbgvB/EpzA9yo/04REzl110CHGl NYl35cr940YqbxlJebNWAsKzJ31M6I8QW2mKc2ymjgXLCHFS+nU+MBFjJbccnzdmIkaL 57+x+eT2/HbvuwJusUhehW5khLCGUkrTyW3aun35oVtcYu/K1Ckcb4z2W19GaoNnJvuB BhjDazT3DdCVPJwd5AH2WblxuiqW9qQESVLVqk4keNsikYaWswTfxgE8wElf+sQIHA/J 7boQ== X-Gm-Message-State: AOAM533Wb8ilfXsKN092F3rfac2smz3Ms9xJ6xqG2X8xyno8tO2cw3FC 8rFRDyBCJvuckHiWkjccXMx0M6haRl0r3A== X-Received: by 2002:a62:8c91:: with SMTP id m139mr1822568pfd.267.1598889969889; Mon, 31 Aug 2020 09:06:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/76] target/microblaze: Tidy gdbstub Date: Mon, 31 Aug 2020 09:04:49 -0700 Message-Id: <20200831160601.833692-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use an enumeration for the gdb register mapping. Use one switch statement for the entire dispatch. Drop sreg_map and simply enumerate those cases explicitly. Force r0 to have value 0 and ignore writes. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/gdbstub.c | 193 +++++++++++++++++++----------------- 1 file changed, 101 insertions(+), 92 deletions(-) -- 2.25.1 diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 73e8973597..e65ec051a5 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -21,58 +21,80 @@ #include "cpu.h" #include "exec/gdbstub.h" +/* + * GDB expects SREGs in the following order: + * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. + * + * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't + * map them to anything and return a value of 0 instead. + */ + +enum { + GDB_PC = 32 + 0, + GDB_MSR = 32 + 1, + GDB_EAR = 32 + 2, + GDB_ESR = 32 + 3, + GDB_FSR = 32 + 4, + GDB_BTR = 32 + 5, + GDB_PVR0 = 32 + 6, + GDB_PVR11 = 32 + 17, + GDB_EDR = 32 + 18, + GDB_SLR = 32 + 25, + GDB_SHR = 32 + 26, +}; + int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUClass *cc = CPU_GET_CLASS(cs); CPUMBState *env = &cpu->env; - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything and return a value of 0 instead. - */ - static const uint8_t sreg_map[6] = { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; + uint32_t val; - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { - return gdb_get_reg32(mem_buf, env->regs[n]); - } else { - n -= 32; - switch (n) { - case 0 ... 5: - return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]); - /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -= 6; - return gdb_get_reg32(mem_buf, env->pvr.regs[n]); - case 18: - return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]); - /* Other SRegs aren't modeled, so report a value of 0 */ - case 19 ... 24: - return gdb_get_reg32(mem_buf, 0); - case 25: - return gdb_get_reg32(mem_buf, env->slr); - case 26: - return gdb_get_reg32(mem_buf, env->shr); - default: - return 0; - } + if (n > cc->gdb_num_core_regs) { + return 0; } + + switch (n) { + case 1 ... 31: + val = env->regs[n]; + break; + case GDB_PC: + val = env->sregs[SR_PC]; + break; + case GDB_MSR: + val = env->sregs[SR_MSR]; + break; + case GDB_EAR: + val = env->sregs[SR_EAR]; + break; + case GDB_ESR: + val = env->sregs[SR_ESR]; + break; + case GDB_FSR: + val = env->sregs[SR_FSR]; + break; + case GDB_BTR: + val = env->sregs[SR_BTR]; + break; + case GDB_PVR0 ... GDB_PVR11: + /* PVR12 is intentionally skipped */ + val = env->pvr.regs[n - GDB_PVR0]; + break; + case GDB_EDR: + val = env->sregs[SR_EDR]; + break; + case GDB_SLR: + val = env->slr; + break; + case GDB_SHR: + val = env->shr; + break; + default: + /* Other SRegs aren't modeled, so report a value of 0 */ + val = 0; + break; + } + return gdb_get_reg32(mem_buf, val); } int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) @@ -82,60 +104,47 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) CPUMBState *env = &cpu->env; uint32_t tmp; - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything. - */ - static const uint8_t sreg_map[6] = { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; - if (n > cc->gdb_num_core_regs) { return 0; } tmp = ldl_p(mem_buf); - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { + switch (n) { + case 1 ... 31: env->regs[n] = tmp; - } else { - n -= 32; - switch (n) { - case 0 ... 5: - env->sregs[sreg_map[n]] = tmp; - break; + break; + case GDB_PC: + env->sregs[SR_PC] = tmp; + break; + case GDB_MSR: + env->sregs[SR_MSR] = tmp; + break; + case GDB_EAR: + env->sregs[SR_EAR] = tmp; + break; + case GDB_ESR: + env->sregs[SR_ESR] = tmp; + break; + case GDB_FSR: + env->sregs[SR_FSR] = tmp; + break; + case GDB_BTR: + env->sregs[SR_BTR] = tmp; + break; + case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -= 6; - env->pvr.regs[n] = tmp; - break; - /* Only EDR is modeled in these indeces, so ignore the rest */ - case 18: - env->sregs[SR_EDR] = tmp; - break; - case 25: - env->slr = tmp; - break; - case 26: - env->shr = tmp; - break; - } + env->pvr.regs[n - GDB_PVR0] = tmp; + break; + case GDB_EDR: + env->sregs[SR_EDR] = tmp; + break; + case GDB_SLR: + env->slr = tmp; + break; + case GDB_SHR: + env->shr = tmp; + break; } return 4; } From patchwork Mon Aug 31 16:04:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248751 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3440527ilg; Mon, 31 Aug 2020 09:06:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxQp5fKHhDhlB73vyo9wLSqSIVcwetW2yfH8Qz5uUH7agRV6xXv3BxpAKb4hw3PTcVDlGOA X-Received: by 2002:a25:af05:: with SMTP id a5mr3029339ybh.411.1598890018418; Mon, 31 Aug 2020 09:06:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890018; cv=none; d=google.com; s=arc-20160816; b=yeb2BjERvGtZLqgliyTgVYO6HJqxg+O9ume6ejjVt7JXRG82aDfROrLYE/eccV10Ih 7KsjmTo/d/Cg46ubPvgiN7G9SV3roj39zGxqdy88OMHd9+aicLL4pEZjX9kKlks4S8JY r+fED2M/Gf/sM1ZU2c8R0Mr8MhXDCYDZ6lY/JeCzB6ARfiCfHJ44uy9dbJn4MSvma0DP vFs7jswx/nuHqLhfpgs+sCxsaivl6rUuk9drPCwpwlv9smglzYKblbdr64w3txHHMfhU PpvBmdQDiqB0QvVnmPuN+rm/Fkh7SSKI9ucuRLhrJgzEA5QCMYXLKW7AH90YidU/NvR+ qhNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oASypVqUWEIg4ZAe6my1fFp1ehvS0890ZEtdtTj14Ic=; b=y4m4dHNDqOsPtl4kOzXe67AWGk+pY0mQqv5DZ2IYW5k8JAJNEU4orrLJb4YagW1gRx R0mALlxQP0da4N7Wi8g1UsZloap3vKcVkauJ5htTFafQOOpvSYfnANpwYVAQLBTrATR/ f+CYlV5TqHVP78QEIjQLXv7VxE82HO7Jfycz5uSc74f+Imjb0YBH7YnijxAq7ltpAQOZ ntHscQytesIw6NNh0ekzxeh51HIlnY+OXUIrQX8L0kJ2VMfWrtbiLfEOrQW+HrYNwAHz ANMSScJIeZ41UfcOjTz4DCA0UwnZYAvI5Glshf7yBvky+yo+LDWpWbmAM8tWfizRxhHI 6rsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cf8sysRC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k10si8070032ybd.491.2020.08.31.09.06.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:06:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cf8sysRC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmKf-0003XY-Mv for patch@linaro.org; Mon, 31 Aug 2020 12:06:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmJz-0003Uk-S9 for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:15 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:39936) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmJx-0005uQ-BW for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:15 -0400 Received: by mail-pl1-x632.google.com with SMTP id z15so3239817plo.7 for ; Mon, 31 Aug 2020 09:06:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oASypVqUWEIg4ZAe6my1fFp1ehvS0890ZEtdtTj14Ic=; b=cf8sysRCyeGQFHWm8dEuvB5PVympOMwjLZoZc2LOM6noT4BCIDgYZpXTRmCbG3RFou j5p6vcLFJjA9htpnmwupAbrKlN0pKS+JeBjYIBDEa7IRLdnZ7FQIVecDc+aqh5annIqA 1qpCSyIaGPOb8jQ4lbNVmygi65eaNcK+i/1cqIhI+Mg+e1wfQNJ8ov6tuqxLOsanqTsL FVcWf9etgLP/lLR8wQZOvQAUlpf+omZEoCetSTHEW9lRrzVVodWVGTEIQr3Fa6L/jlD8 GSZhtIEZCua22VWEbP8q8VN5nTl+8jqRk4x2zoUF6uvPjq9HoUYscFt1u2jAcw8R3Mwo GnfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oASypVqUWEIg4ZAe6my1fFp1ehvS0890ZEtdtTj14Ic=; b=tYzs2wddVCAFBhky1aj9ymqJNcamMp2KR0kelBhRxKKXakI1bQPtrmFIzkyQ+UAiCl jJsC+8q+Ym71odYeZ5h28n5y9l/LX2NFYWjq/3cUkNMV5VRunTnqmb6tRKa4TVR+JY63 cKnh/DPnK7M7I7AS9ugt6kqGZ/Uq5iX9aDwzpQnEuU/cNt9d5kf0YhmGpqnmYkfofiFB yacH5k77IIutY9DrDf3nqBCA0Ze7ygAhDNcsmnf9BIdl6Zm06D214UVdDME29QRZNXga oaaCrLSyoFBI1MV8w/xbUm6JYD57EElkCyK9rhK46sb5xcBcFtcLl8D9yV3VlgmXKL0A ql+Q== X-Gm-Message-State: AOAM533ysYkQU1cKGVBSXUBwfQ/AsegAN5DeixHAf2+rHozxRLWR7365 B6RfBbzrfGj8AxjvEcWEj75179OuRvAWkg== X-Received: by 2002:a17:90a:d496:: with SMTP id s22mr58657pju.167.1598889971284; Mon, 31 Aug 2020 09:06:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/76] target/microblaze: Split out PC from env->sregs Date: Mon, 31 Aug 2020 09:04:50 -0700 Message-Id: <20200831160601.833692-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin eliminating the sregs array in favor of individual members. Does not correct the width of pc, yet. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 ++- linux-user/microblaze/cpu_loop.c | 12 +++++------ linux-user/microblaze/signal.c | 8 ++++---- target/microblaze/cpu.c | 4 ++-- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 34 ++++++++++++++++---------------- target/microblaze/mmu.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 10 +++++++--- 9 files changed, 42 insertions(+), 37 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a31134b65c..d1f91bb318 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -236,6 +236,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; + uint64_t pc; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ @@ -351,7 +352,7 @@ typedef MicroBlazeCPU ArchCPU; static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { - *pc = env->sregs[SR_PC]; + *pc = env->pc; *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 3e0a7f730b..3c693086f4 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -51,7 +51,7 @@ void cpu_loop(CPUMBState *env) case EXCP_BREAK: /* Return address is 4 bytes after the call. */ env->regs[14] += 4; - env->sregs[SR_PC] = env->regs[14]; + env->pc = env->regs[14]; ret = do_syscall(env, env->regs[12], env->regs[5], @@ -63,7 +63,7 @@ void cpu_loop(CPUMBState *env) 0, 0); if (ret == -TARGET_ERESTARTSYS) { /* Wind back to before the syscall. */ - env->sregs[SR_PC] -= 4; + env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->regs[3] = ret; } @@ -73,13 +73,13 @@ void cpu_loop(CPUMBState *env) * not a userspace-usable register, as the kernel may clobber it * at any point.) */ - env->regs[14] = env->sregs[SR_PC]; + env->regs[14] = env->pc; break; case EXCP_HW_EXCP: - env->regs[17] = env->sregs[SR_PC] + 4; + env->regs[17] = env->pc + 4; if (env->iflags & D_FLAG) { env->sregs[SR_ESR] |= 1 << 12; - env->sregs[SR_PC] -= 4; + env->pc -= 4; /* FIXME: if branch was immed, replay the imm as well. */ } @@ -165,5 +165,5 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->regs[29] = regs->r29; env->regs[30] = regs->r30; env->regs[31] = regs->r31; - env->sregs[SR_PC] = regs->pc; + env->pc = regs->pc; } diff --git a/linux-user/microblaze/signal.c b/linux-user/microblaze/signal.c index 80950c2181..b4eeef4673 100644 --- a/linux-user/microblaze/signal.c +++ b/linux-user/microblaze/signal.c @@ -87,7 +87,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUMBState *env) __put_user(env->regs[29], &sc->regs.r29); __put_user(env->regs[30], &sc->regs.r30); __put_user(env->regs[31], &sc->regs.r31); - __put_user(env->sregs[SR_PC], &sc->regs.pc); + __put_user(env->pc, &sc->regs.pc); } static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env) @@ -124,7 +124,7 @@ static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env) __get_user(env->regs[29], &sc->regs.r29); __get_user(env->regs[30], &sc->regs.r30); __get_user(env->regs[31], &sc->regs.r31); - __get_user(env->sregs[SR_PC], &sc->regs.pc); + __get_user(env->pc, &sc->regs.pc); } static abi_ulong get_sigframe(struct target_sigaction *ka, @@ -188,7 +188,7 @@ void setup_frame(int sig, struct target_sigaction *ka, env->regs[7] = frame_addr += offsetof(typeof(*frame), uc); /* Offset of 4 to handle microblaze rtid r14, 0 */ - env->sregs[SR_PC] = (unsigned long)ka->_sa_handler; + env->pc = (unsigned long)ka->_sa_handler; unlock_user_struct(frame, frame_addr, 1); return; @@ -228,7 +228,7 @@ long do_sigreturn(CPUMBState *env) restore_sigcontext(&frame->uc.tuc_mcontext, env); /* We got here through a sigreturn syscall, our path back is via an rtb insn so setup r14 for that. */ - env->regs[14] = env->sregs[SR_PC]; + env->regs[14] = env->pc; unlock_user_struct(frame, frame_addr, 0); return -TARGET_QEMU_ESIGRETURN; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 51e5c85b10..bde9992535 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -79,7 +79,7 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - cpu->env.sregs[SR_PC] = value; + cpu->env.pc = value; } static bool mb_cpu_has_work(CPUState *cs) @@ -117,7 +117,7 @@ static void mb_cpu_reset(DeviceState *dev) /* Disable stack protector. */ env->shr = ~0; - env->sregs[SR_PC] = cpu->cfg.base_vectors; + env->pc = cpu->cfg.base_vectors; #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e65ec051a5..9ea31f8d2f 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -59,7 +59,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->regs[n]; break; case GDB_PC: - val = env->sregs[SR_PC]; + val = env->pc; break; case GDB_MSR: val = env->sregs[SR_MSR]; @@ -115,7 +115,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->regs[n] = tmp; break; case GDB_PC: - env->sregs[SR_PC] = tmp; + env->pc = tmp; break; case GDB_MSR: env->sregs[SR_MSR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ab2ceeb055..5c392deea4 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -35,7 +35,7 @@ void mb_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; env->res_addr = RES_ADDR_NONE; - env->regs[14] = env->sregs[SR_PC]; + env->regs[14] = env->pc; } bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -126,7 +126,7 @@ void mb_cpu_do_interrupt(CPUState *cs) return; } - env->regs[17] = env->sregs[SR_PC] + 4; + env->regs[17] = env->pc + 4; env->sregs[SR_ESR] &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ @@ -145,15 +145,15 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_EAR], + env->pc, env->sregs[SR_EAR], env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; + env->pc = cpu->cfg.base_vectors + 0x20; break; case EXCP_MMU: - env->regs[17] = env->sregs[SR_PC]; + env->regs[17] = env->pc; env->sregs[SR_ESR] &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ @@ -169,7 +169,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "bimm exception at pc=%" PRIx64 " " "iflags=%x\n", - env->sregs[SR_PC], env->iflags); + env->pc, env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } @@ -188,10 +188,10 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=%" PRIx64 " ear=%" PRIx64 " " "iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); + env->pc, env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; + env->pc = cpu->cfg.base_vectors + 0x20; break; case EXCP_IRQ: @@ -209,14 +209,14 @@ void mb_cpu_do_interrupt(CPUState *cs) { const char *sym; - sym = lookup_symbol(env->sregs[SR_PC]); + sym = lookup_symbol(env->pc); if (sym && (!strcmp("netif_rx", sym) || !strcmp("process_backlog", sym))) { qemu_log( "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags, + env->pc, env->sregs[SR_MSR], t, env->iflags, sym); log_cpu_state(cs, 0); @@ -226,14 +226,14 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); + env->pc, env->sregs[SR_MSR], t, env->iflags); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ | MSR_UM | MSR_IE); env->sregs[SR_MSR] |= t; - env->regs[14] = env->sregs[SR_PC]; - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10; + env->regs[14] = env->pc; + env->pc = cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; @@ -245,17 +245,17 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); + env->pc, env->sregs[SR_MSR], t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; if (cs->exception_index == EXCP_HW_BREAK) { - env->regs[16] = env->sregs[SR_PC]; + env->regs[16] = env->pc; env->sregs[SR_MSR] |= MSR_BIP; - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18; + env->pc = cpu->cfg.base_vectors + 0x18; } else - env->sregs[SR_PC] = env->btarget; + env->pc = env->btarget; break; default: cpu_abort(cs, "unhandled exception type=%d\n", diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 6763421ba2..3f403b567b 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -251,7 +251,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%" PRIx64 "\n", - i, env->sregs[SR_PC]); + i, env->pc); env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f3b17a95b3..2deef32740 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -75,7 +75,7 @@ void helper_debug(CPUMBState *env) { int i; - qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]); + qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a96cb21d96..9f6815cc1f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1805,7 +1805,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", - env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); + env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", @@ -1868,7 +1868,11 @@ void mb_tcg_init(void) offsetof(CPUMBState, regs[i]), regnames[i]); } - for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) { + + cpu_SR[SR_PC] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + + for (i = 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); @@ -1878,5 +1882,5 @@ void mb_tcg_init(void) void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, target_ulong *data) { - env->sregs[SR_PC] = data[0]; + env->pc = data[0]; } From patchwork Mon Aug 31 16:04:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248755 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3442087ilg; Mon, 31 Aug 2020 09:08:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwhcjHODimK8ZJgjyOghrRTj+w4g0+5qxmIXTcS09lDOPWzkf2lxwRzTjy8vZXRTVJAi52y X-Received: by 2002:a25:f42:: with SMTP id 63mr3313502ybp.348.1598890121245; Mon, 31 Aug 2020 09:08:41 -0700 (PDT) ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of MSR, yet. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 7 ++--- target/microblaze/cpu.c | 4 +-- target/microblaze/gdbstub.c | 4 +-- target/microblaze/helper.c | 49 +++++++++++++++++------------------ target/microblaze/op_helper.c | 22 ++++++++-------- target/microblaze/translate.c | 14 +++++----- 6 files changed, 51 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d1f91bb318..36de61d9f9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -237,6 +237,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint64_t pc; + uint64_t msr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ @@ -355,7 +356,7 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | - (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); + (env->msr & (MSR_UM | MSR_VM | MSR_EE)); } #if !defined(CONFIG_USER_ONLY) @@ -370,11 +371,11 @@ static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) MicroBlazeCPU *cpu = env_archcpu(env); /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { return MMU_NOMMU_IDX; } - if (env->sregs[SR_MSR] & MSR_UM) { + if (env->msr & MSR_UM) { return MMU_USER_IDX; } return MMU_KERNEL_IDX; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bde9992535..0eac068570 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -121,9 +121,9 @@ static void mb_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ - env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; + env->msr = MSR_EE | MSR_IE | MSR_VM | MSR_UM; #else - env->sregs[SR_MSR] = 0; + env->msr = 0; mmu_init(&env->mmu); env->mmu.c_mmu = 3; env->mmu.c_mmu_tlb_access = 3; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 9ea31f8d2f..e4c4936a7a 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -62,7 +62,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pc; break; case GDB_MSR: - val = env->sregs[SR_MSR]; + val = env->msr; break; case GDB_EAR: val = env->sregs[SR_EAR]; @@ -118,7 +118,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pc = tmp; break; case GDB_MSR: - env->sregs[SR_MSR] = tmp; + env->msr = tmp; break; case GDB_EAR: env->sregs[SR_EAR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5c392deea4..a18314540f 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -117,7 +117,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); -/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ +/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; switch (cs->exception_index) { case EXCP_HW_EXCP: @@ -136,11 +136,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |= t; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |= t; /* Exception in progress. */ - env->sregs[SR_MSR] |= MSR_EIP; + env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " @@ -179,11 +179,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |= t; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |= t; /* Exception in progress. */ - env->sregs[SR_MSR] |= MSR_EIP; + env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, "exception at pc=%" PRIx64 " ear=%" PRIx64 " " @@ -195,11 +195,11 @@ void mb_cpu_do_interrupt(CPUState *cs) break; case EXCP_IRQ: - assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))); - assert(env->sregs[SR_MSR] & MSR_IE); + assert(!(env->msr & (MSR_EIP | MSR_BIP))); + assert(env->msr & MSR_IE); assert(!(env->iflags & D_FLAG)); - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; #if 0 #include "disas/disas.h" @@ -216,7 +216,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log( "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->pc, env->sregs[SR_MSR], t, env->iflags, + env->pc, env->msr, t, env->iflags, sym); log_cpu_state(cs, 0); @@ -226,11 +226,10 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->pc, env->sregs[SR_MSR], t, env->iflags); + env->pc, env->msr, t, env->iflags); - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ - | MSR_UM | MSR_IE); - env->sregs[SR_MSR] |= t; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); + env->msr |= t; env->regs[14] = env->pc; env->pc = cpu->cfg.base_vectors + 0x10; @@ -241,18 +240,18 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->pc, env->sregs[SR_MSR], t, env->iflags); + env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |= t; - env->sregs[SR_MSR] |= MSR_BIP; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |= t; + env->msr |= MSR_BIP; if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->pc; - env->sregs[SR_MSR] |= MSR_BIP; + env->msr |= MSR_BIP; env->pc = cpu->cfg.base_vectors + 0x18; } else env->pc = env->btarget; @@ -293,8 +292,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) CPUMBState *env = &cpu->env; if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->sregs[SR_MSR] & MSR_IE) - && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) + && (env->msr & MSR_IE) + && !(env->msr & (MSR_EIP | MSR_BIP)) && !(env->iflags & (D_FLAG | IMM_FLAG))) { cs->exception_index = EXCP_IRQ; mb_cpu_do_interrupt(cs); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 2deef32740..3668382d36 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,14 +78,14 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, - (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (bool)(env->sregs[SR_MSR] & MSR_EIP), - (bool)(env->sregs[SR_MSR] & MSR_IE)); + (env->msr & MSR_UM) ? "user" : "kernel", + (env->msr & MSR_UMS) ? "user" : "kernel", + (bool)(env->msr & MSR_EIP), + (bool)(env->msr & MSR_IE)); for (i = 0; i < 32; i++) { qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); if ((i + 1) % 4 == 0) @@ -135,15 +135,15 @@ static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) MicroBlazeCPU *cpu = env_archcpu(env); if (b == 0) { - env->sregs[SR_MSR] |= MSR_DZ; + env->msr |= MSR_DZ; - if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) { + if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { env->sregs[SR_ESR] = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; } - env->sregs[SR_MSR] &= ~MSR_DZ; + env->msr &= ~MSR_DZ; return 1; } @@ -192,7 +192,7 @@ static void update_fpu_flags(CPUMBState *env, int flags) } if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) - && (env->sregs[SR_MSR] & MSR_EE)) { + && (env->msr & MSR_EE)) { raise_fpu_exception(env); } } @@ -437,7 +437,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr, if (mask == 3) { env->sregs[SR_ESR] |= 1 << 11; } - if (!(env->sregs[SR_MSR] & MSR_EE)) { + if (!(env->msr & MSR_EE)) { return; } helper_raise_exception(env, EXCP_HW_EXCP); @@ -484,7 +484,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, env = &cpu->env; cpu_restore_state(cs, retaddr, true); - if (!(env->sregs[SR_MSR] & MSR_EE)) { + if (!(env->msr & MSR_EE)) { return; } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9f6815cc1f..9f2dcd82cd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,16 +1809,16 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", - env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", env->btaken, env->btarget, - (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (bool)(env->sregs[SR_MSR] & MSR_EIP), - (bool)(env->sregs[SR_MSR] & MSR_IE)); + (env->msr & MSR_UM) ? "user" : "kernel", + (env->msr & MSR_UMS) ? "user" : "kernel", + (bool)(env->msr & MSR_EIP), + (bool)(env->msr & MSR_IE)); for (i = 0; i < 12; i++) { qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); if ((i + 1) % 4 == 0) { @@ -1871,8 +1871,10 @@ void mb_tcg_init(void) cpu_SR[SR_PC] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + cpu_SR[SR_MSR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - for (i = 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Mon Aug 31 16:04:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248757 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3442683ilg; Mon, 31 Aug 2020 09:09:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzF9ksgx2gVno0rimxf3oW4bpyH0mLXZgkhrmQX4qHmVLmntgKHb6o6BE2t3OG9rodvcxSU X-Received: by 2002:a25:4883:: with SMTP id v125mr2999053yba.503.1598890169357; Mon, 31 Aug 2020 09:09:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890169; cv=none; d=google.com; s=arc-20160816; b=gOEOf/oYIm7n/X4LIBxh056uxcL1aRhrMnxJyzl/SvTIGq3R5lYU+uvZSZS+K+CUcj Pn7Mn5fpOl93OHdLvg4NNymgo68JiyrthMKiwxl/OlJASlBt6AU5YifAdzud5DaEZQgE Sm4iCzfv2KzA7jjcALuXmO7achiIMsYSC5slMwvHdUrXqdmcv9t/aNYhhDR/Jmlql5Su 25W4BXPNu/30YmJTmykmaG4XqIa78N9XGbLcpM1YOxX5+scphANoQHDee3bcoz27PRth aSao6lpC7tohSI8C1uYQVQiZ5Q135tA/77t7xq4IF4WycwgbIbiWnSiO5Ztb9mehEfmb Fp4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Y/1nd0STg2fwgw26kyAhRI4aPsi6vfmi/pGgkxdn03M=; b=kSXn70RX5Zqrql+e8vAhOq5xVweFpncV/qsqMVU1OkGMkjiUXL0XFJ0rYdLSJnDpyg mDCWe6JTX+vXnP5ceHBWofjqLy81U6P2mhphE36Edav2inbKbeffOYnly7dZhQkbe7Gn Fqp+6E4vJV9Y+/KpQGoCKzZsab8VECmPxaEFNeOV4zI2tybJAK+SCrzlMBn3/MBgKLGD IqVILFGv2mAqmgGf5DHQP3mTX6d208z0n9G9Cy4/5L7DR4SHk5+gfZLhMHbuOhDkz5Uj VyuG7N3gkfq7pBVYn6KO2SETVCHO5wXKaT5IOK1tFMPnOkOSnyq6txq9S90xx8hFVwVA Ipog== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="n1vuf/U5"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 6 +++--- target/microblaze/op_helper.c | 8 ++++---- target/microblaze/translate.c | 6 ++++-- 5 files changed, 14 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 36de61d9f9..c9035b410e 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -238,6 +238,7 @@ struct CPUMBState { uint32_t regs[32]; uint64_t pc; uint64_t msr; + uint64_t ear; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e4c4936a7a..e33a613efe 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -65,7 +65,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->msr; break; case GDB_EAR: - val = env->sregs[SR_EAR]; + val = env->ear; break; case GDB_ESR: val = env->sregs[SR_ESR]; @@ -121,7 +121,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->msr = tmp; break; case GDB_EAR: - env->sregs[SR_EAR] = tmp; + env->ear = tmp; break; case GDB_ESR: env->sregs[SR_ESR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a18314540f..afe9634781 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -85,7 +85,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", mmu_idx, address); - env->sregs[SR_EAR] = address; + env->ear = address; switch (lu.err) { case ERR_PROT: env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; @@ -145,7 +145,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", - env->pc, env->sregs[SR_EAR], + env->pc, env->ear, env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); @@ -188,7 +188,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=%" PRIx64 " ear=%" PRIx64 " " "iflags=%x\n", - env->pc, env->sregs[SR_EAR], env->iflags); + env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->pc = cpu->cfg.base_vectors + 0x20; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 3668382d36..5bacd29663 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, @@ -431,7 +431,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr, "unaligned access addr=" TARGET_FMT_lx " mask=%x, wr=%d dr=r%d\n", addr, mask, wr, dr); - env->sregs[SR_EAR] = addr; + env->ear = addr; env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ | (dr & 31) << 5; if (mask == 3) { @@ -450,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); - env->sregs[SR_EAR] = addr; + env->ear = addr; env->sregs[SR_ESR] = ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } @@ -488,7 +488,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, return; } - env->sregs[SR_EAR] = addr; + env->ear = addr; if (access_type == MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { env->sregs[SR_ESR] = ESR_EC_INSN_BUS; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9f2dcd82cd..62747b02f3 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->ear, env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " @@ -1873,8 +1873,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_SR[SR_MSR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + cpu_SR[SR_EAR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); - for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Mon Aug 31 16:04:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248759 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3443353ilg; Mon, 31 Aug 2020 09:10:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxzSQehoslcnuWNgp+5JegdzusBB7t9bj3pYh4nAmxM6SmQzqtPAAhs+I7GMKR7V7KywS+e X-Received: by 2002:a25:3c07:: with SMTP id j7mr2998747yba.49.1598890218958; Mon, 31 Aug 2020 09:10:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890218; cv=none; d=google.com; s=arc-20160816; b=OAwKTuz5MF15oncfZP5zGsT/hkuhuiMxm29W60CQYm3AvCzYLVMC0K7XQHdIAkLVeo opFSiIL9pmqDVXYF46fXgqMusINmblbGcOn/0N4nPq7mey/N9SmBTHIOQqpp6VmcWIxu HgBFab/WX9I6MBVPKnauCRs3BrtCrQFHDTOhQALb3mpRwNVS/xivPgrCuzRmT93YxZpk zHaatPPYxtRW8FFBoHDBfYFcKeI00dodvj+xE5wwl4DkrZfBVSO/qux6w0IP27MQSbkV UaZWxGRusX5WGRHxL7fwlMHnqCXhCdy6lXDJmRJMt8O6FvW3nb6S20WaC7mpcauE+iS9 KWOQ== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of ESR, yet. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 6 +++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 18 +++++++++--------- target/microblaze/op_helper.c | 17 ++++++++--------- target/microblaze/translate.c | 6 ++++-- 6 files changed, 27 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c9035b410e..7d94af43ed 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,6 +239,7 @@ struct CPUMBState { uint64_t pc; uint64_t msr; uint64_t ear; + uint64_t esr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 3c693086f4..c10e3e0261 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -78,14 +78,14 @@ void cpu_loop(CPUMBState *env) case EXCP_HW_EXCP: env->regs[17] = env->pc + 4; if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |= 1 << 12; + env->esr |= 1 << 12; env->pc -= 4; /* FIXME: if branch was immed, replay the imm as well. */ } env->iflags &= ~(IMM_FLAG | D_FLAG); - switch (env->sregs[SR_ESR] & 31) { + switch (env->esr & 31) { case ESR_EC_DIVZERO: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; @@ -107,7 +107,7 @@ void cpu_loop(CPUMBState *env) break; default: fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n", - env->sregs[SR_ESR] & ESR_EC_MASK); + env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); break; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e33a613efe..05e22f233d 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -68,7 +68,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->ear; break; case GDB_ESR: - val = env->sregs[SR_ESR]; + val = env->esr; break; case GDB_FSR: val = env->sregs[SR_FSR]; @@ -124,7 +124,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->ear = tmp; break; case GDB_ESR: - env->sregs[SR_ESR] = tmp; + env->esr = tmp; break; case GDB_FSR: env->sregs[SR_FSR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index afe9634781..ea290be780 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -88,12 +88,12 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, env->ear = address; switch (lu.err) { case ERR_PROT: - env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; - env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + env->esr = access_type == MMU_INST_FETCH ? 17 : 16; + env->esr |= (access_type == MMU_DATA_STORE) << 10; break; case ERR_MISS: - env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 19 : 18; - env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + env->esr = access_type == MMU_INST_FETCH ? 19 : 18; + env->esr |= (access_type == MMU_DATA_STORE) << 10; break; default: abort(); @@ -127,11 +127,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } env->regs[17] = env->pc + 4; - env->sregs[SR_ESR] &= ~(1 << 12); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |= 1 << 12 ; + env->esr |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; } @@ -146,7 +146,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", env->pc, env->ear, - env->sregs[SR_ESR], env->iflags); + env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->pc = cpu->cfg.base_vectors + 0x20; @@ -155,11 +155,11 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] = env->pc; - env->sregs[SR_ESR] &= ~(1 << 12); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); - env->sregs[SR_ESR] |= 1 << 12 ; + env->esr |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; /* Reexecute the branch. */ diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 5bacd29663..f01cf9be64 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, @@ -138,7 +138,7 @@ static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) env->msr |= MSR_DZ; if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { - env->sregs[SR_ESR] = ESR_EC_DIVZERO; + env->esr = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; @@ -166,7 +166,7 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) /* raise FPU exception. */ static void raise_fpu_exception(CPUMBState *env) { - env->sregs[SR_ESR] = ESR_EC_FPU; + env->esr = ESR_EC_FPU; helper_raise_exception(env, EXCP_HW_EXCP); } @@ -432,10 +432,9 @@ void helper_memalign(CPUMBState *env, target_ulong addr, " mask=%x, wr=%d dr=r%d\n", addr, mask, wr, dr); env->ear = addr; - env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ - | (dr & 31) << 5; + env->esr = ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) << 5; if (mask == 3) { - env->sregs[SR_ESR] |= 1 << 11; + env->esr |= 1 << 11; } if (!(env->msr & MSR_EE)) { return; @@ -451,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); env->ear = addr; - env->sregs[SR_ESR] = ESR_EC_STACKPROT; + env->esr = ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } } @@ -491,12 +490,12 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, env->ear = addr; if (access_type == MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] = ESR_EC_INSN_BUS; + env->esr = ESR_EC_INSN_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } else { if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] = ESR_EC_DATA_BUS; + env->esr = ESR_EC_DATA_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 62747b02f3..411c7b6e49 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " @@ -1875,8 +1875,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_SR[SR_EAR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); + cpu_SR[SR_ESR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); - for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Mon Aug 31 16:04:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248763 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3444897ilg; Mon, 31 Aug 2020 09:12:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQTBUWhVluU5Tm6jKvJsw67gf8vi2lyoxkhKimhkQkAGxSLMLANAyvmlHJicMxrvZ/t8yf X-Received: by 2002:a25:a85:: with SMTP id 127mr3177788ybk.327.1598890324512; Mon, 31 Aug 2020 09:12:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890324; cv=none; d=google.com; s=arc-20160816; b=urOiu3vyCnlrnaXOj5pIT+Pf8KI86ZTgFjeTZ+ccBXUHHBqadbPg1A0AaIKL8Q1TZM g2zrEZx0sCRExWmoYIZpBSdBFkz2V9VvqQUjbvfUt19QC2v9LIm1r2yupRKSyHQwFoRf p4fXMOqDXbHEdfvGGFm+dZvHRKo6fepuyVdXEuX3XzE9wIlP7dXl5nzPeTWLVG6MQlI2 +Ps3MvBz1qeOquqJaIEmBrcbCn15wtPP7ydUm53oY5LkOuixroStn9Lr0CG0jDVBOZUG NewrLOLauwgf8KWJXsngXTmofNlAwL3BuJFEJV789OB9sBmLqxcOZGL2ojiOE1rr2yKW hdWw== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of FSR, yet. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 4 ++-- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/op_helper.c | 8 ++++---- target/microblaze/translate.c | 6 ++++-- 5 files changed, 13 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7d94af43ed..bcafef99b0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -240,6 +240,7 @@ struct CPUMBState { uint64_t msr; uint64_t ear; uint64_t esr; + uint64_t fsr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index c10e3e0261..da5e98b784 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env) case ESR_EC_FPU: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; - if (env->sregs[SR_FSR] & FSR_IO) { + if (env->fsr & FSR_IO) { info.si_code = TARGET_FPE_FLTINV; } - if (env->sregs[SR_FSR] & FSR_DZ) { + if (env->fsr & FSR_DZ) { info.si_code = TARGET_FPE_FLTDIV; } info._sifields._sigfault._addr = 0; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 05e22f233d..2634ce49fc 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -71,7 +71,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->esr; break; case GDB_FSR: - val = env->sregs[SR_FSR]; + val = env->fsr; break; case GDB_BTR: val = env->sregs[SR_BTR]; @@ -127,7 +127,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->esr = tmp; break; case GDB_FSR: - env->sregs[SR_FSR] = tmp; + env->fsr = tmp; break; case GDB_BTR: env->sregs[SR_BTR] = tmp; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f01cf9be64..ae57d45536 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -175,19 +175,19 @@ static void update_fpu_flags(CPUMBState *env, int flags) int raise = 0; if (flags & float_flag_invalid) { - env->sregs[SR_FSR] |= FSR_IO; + env->fsr |= FSR_IO; raise = 1; } if (flags & float_flag_divbyzero) { - env->sregs[SR_FSR] |= FSR_DZ; + env->fsr |= FSR_DZ; raise = 1; } if (flags & float_flag_overflow) { - env->sregs[SR_FSR] |= FSR_OF; + env->fsr |= FSR_OF; raise = 1; } if (flags & float_flag_underflow) { - env->sregs[SR_FSR] |= FSR_UF; + env->fsr |= FSR_UF; raise = 1; } if (raise diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 411c7b6e49..c58c49ea8f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1810,7 +1810,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags, env->sregs[SR_FSR], + env->debug, env->imm, env->iflags, env->fsr, env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", @@ -1877,8 +1877,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_SR[SR_ESR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); + cpu_SR[SR_FSR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); - for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Mon Aug 31 16:04:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248767 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3445956ilg; Mon, 31 Aug 2020 09:13:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy1TT6zLtxzeaxX7ImFwSB5jFq/+JUwbjasV/LQHpMoQ4O79B1BWmB8MwsQQBKhHbw2UStj X-Received: by 2002:a25:9247:: with SMTP id e7mr3514194ybo.293.1598890401870; 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[209.51.188.17]) by mx.google.com with ESMTPS id d197si8593193ybc.65.2020.08.31.09.13.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:13:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X2lRUWSf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmQr-0000WJ-7W for patch@linaro.org; Mon, 31 Aug 2020 12:13:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33514) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmK5-0003ih-Sm for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:21 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:38483) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmK3-0005wO-V1 for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:21 -0400 Received: by mail-pl1-x643.google.com with SMTP id t11so3245408plr.5 for ; Mon, 31 Aug 2020 09:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2lk+ZBWQv/ZXsPrb8oTjpivGovxY9zx2pXrc7J4dxPM=; b=X2lRUWSfLxP75aJVqWsUnA87fqiUroI4bDp2dCk9ctGSgd7fwNJ0nrQSXDDQhicmLM DN8qq9+nAZmNOlHOBNQROdqwUnyVGfD9P8IHPk2aacLpZ3AmnBVbfKCDV8wmnnmFIXeG mW9GcR35z6BmQnrEX7VAJn1hNn/Y3nR/hS4YjkxmcR35npPmJuCI6wi0AnJW9qzBS0AK /jcHlQTNeffUf7tBFz0++7f5F53D7jb+VTLNk1vwsUUJOelXX6ZUxCgXBXSmw7hc5qii M7Em6nvUAnQkhEYA8EadPs6TntAJ7J8kWTs4ANubbw3Dn9seG9/+efRmw4No8yxSrDIB 4xOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2lk+ZBWQv/ZXsPrb8oTjpivGovxY9zx2pXrc7J4dxPM=; b=hBiRE3w4t4ERTNFqiEMaOyMPnTXvNFPbZhavTmbrJ9ve/bkQIrSo20WIiHSNfmPJGB d6YaE/XsV9tuBDm9lRTbTKKIaP0fNcDDdBtWYxKd3T/vuK1+b6lBNhRbs249J4W3jcwk DpdaxiC8IamUEbneAbT5gVACgetTK8+HRgXmG76yaB7JX8TpAsKdCCYpGIlOh/2kmpEV ZJYLUpNKXDYqcIWxdQhLz5qNbXfNSMpK+bz3MdMIxE8aX1jr7IKDXkA6AfgJENnfr9Bs T2vqDB3dqluzeCngIp3BMhbujHoU1pCrhV9yiFt/L//N6QyZuF1ggDDxI6bMJEUWVeLG plkw== X-Gm-Message-State: AOAM530s2W2Hzrbes+Zx4tVhiY8uj7DMpi0ymHs50N66v6UDo5387cI3 JPX3llMF07P/ec59uKzAtaPjP3VIumvUZQ== X-Received: by 2002:a17:902:708b:: with SMTP id z11mr1577952plk.326.1598889978061; Mon, 31 Aug 2020 09:06:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/76] target/microblaze: Split out BTR from env->sregs Date: Mon, 31 Aug 2020 09:04:55 -0700 Message-Id: <20200831160601.833692-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of BTR, yet. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 4 ++-- target/microblaze/translate.c | 6 ++++-- 4 files changed, 9 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index bcafef99b0..deddb47abb 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,6 +241,7 @@ struct CPUMBState { uint64_t ear; uint64_t esr; uint64_t fsr; + uint64_t btr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 2634ce49fc..cde8c169bf 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -74,7 +74,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->fsr; break; case GDB_BTR: - val = env->sregs[SR_BTR]; + val = env->btr; break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ @@ -130,7 +130,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->fsr = tmp; break; case GDB_BTR: - env->sregs[SR_BTR] = tmp; + env->btr = tmp; break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ea290be780..b240dc76f6 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -132,7 +132,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { env->esr |= 1 << 12 ; - env->sregs[SR_BTR] = env->btarget; + env->btr = env->btarget; } /* Disable the MMU. */ @@ -160,7 +160,7 @@ void mb_cpu_do_interrupt(CPUState *cs) if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); env->esr |= 1 << 12 ; - env->sregs[SR_BTR] = env->btarget; + env->btr = env->btarget; /* Reexecute the branch. */ env->regs[17] -= 4; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c58c49ea8f..469e1f103a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1811,7 +1811,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, - env->sregs[SR_BTR]); + env->btr); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", env->btaken, env->btarget, @@ -1879,8 +1879,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); cpu_SR[SR_FSR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); + cpu_SR[SR_BTR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Mon Aug 31 16:04:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248762 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3444710ilg; Mon, 31 Aug 2020 09:11:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqQl5irwwueA6M6fUi7/vifH2WTznDaT52d+qXzkUJtkknw0o7PPlOZcJm5EXUnLvyXne5 X-Received: by 2002:a25:aab1:: with SMTP id t46mr2932768ybi.249.1598890314062; Mon, 31 Aug 2020 09:11:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890314; cv=none; d=google.com; s=arc-20160816; b=B2ykZuaM/lyG0pC8JVYCot/aULaauzop340rVWc0men//Led2cQFZH1S7KMw+MyNcY JoLYos259rNBXyVKCupedKTcrq32pb+OsH2E10FSb04BAIDM6qHm0RD7Lbfe0PKc2zxH As3U6Nyz7o7SaPxvyhDNs0qmJWsxOYCQnbC0XrcMTaF2gkSZtnS5gvdqID067y8boBih 4PHgObgVYzNdD4GUPBmAl5JLPErIg00cKHslCjZPOVyGtnYybNQHm8E1jfwcBArqo81N X2ppi/eG4/E8j2qrsKxePcHmMYHTL9tMmBQH7PdvjPw1wJoQcD2JPDV0LFubxvz+9yuK uaVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=guRLfyQ5/XhJ1Mgq6/AuaC/qOXaXu2B07mw+FlYgWKE=; b=BQ4Q0//ui8qyZQX0SgNWA2+H7HIbcTys4guowH0idoW3zxZ2P0b95G0e/ckZVitH+X 2wh/2ZFEHM/z6DNmB6kb9rZEaxWlzp4HIczg89mtID8X0HJHUsQittSW6GnG37dP/oL6 0iHFNYID9c0j8zEyP75mmQsVQh16mhblfnV3RQLRIN5IyPZie93nrVmK2Vkkv1YXUF1u 5+l0XnmMBMMjjreupkMQE5ntuAIU2Alza8+MMa81bweyrcqdpjX3zOvuBqRBjJMFSNWU rsbg+Gyyqg+BO+neo4xq88W+j8NKS1fasLeBGaA8wo/JoeBc6WRzGKmydkh1urAKkDWl bV8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YbKVajac; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Finish eliminating the sregs array in favor of individual members. Does not correct the width of EDR, yet. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/elfload.c | 9 ++++++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/translate.c | 16 +++------------- 4 files changed, 12 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index deddb47abb..610ddfb719 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint64_t esr; uint64_t fsr; uint64_t btr; - uint64_t sregs[14]; + uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 69936dcd45..58b3f4ef4d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1038,9 +1038,12 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env (*regs)[pos++] = tswapreg(env->regs[i]); } - for (i = 0; i < 6; i++) { - (*regs)[pos++] = tswapreg(env->sregs[i]); - } + (*regs)[pos++] = tswapreg(env->pc); + (*regs)[pos++] = tswapreg(env->msr); + (*regs)[pos++] = 0; + (*regs)[pos++] = tswapreg(env->ear); + (*regs)[pos++] = 0; + (*regs)[pos++] = tswapreg(env->esr); } #endif /* TARGET_MICROBLAZE */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index cde8c169bf..9cba9d2215 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -81,7 +81,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pvr.regs[n - GDB_PVR0]; break; case GDB_EDR: - val = env->sregs[SR_EDR]; + val = env->edr; break; case GDB_SLR: val = env->slr; @@ -137,7 +137,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pvr.regs[n - GDB_PVR0] = tmp; break; case GDB_EDR: - env->sregs[SR_EDR] = tmp; + env->edr = tmp; break; case GDB_SLR: env->slr = tmp; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 469e1f103a..7d307e6b48 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -103,12 +103,6 @@ static const char *regnames[] = "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", }; -static const char *special_regnames[] = -{ - "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr", - "sr8", "sr9", "sr10", "rbtr", "sr12", "redr" -}; - static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1828,7 +1822,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) /* Registers that aren't modeled are reported as 0 */ qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " - "rtlblo=0 rtlbhi=0\n", env->sregs[SR_EDR]); + "rtlblo=0 rtlbhi=0\n", env->edr); qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); @@ -1881,12 +1875,8 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_SR[SR_BTR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - - for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) { - cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUMBState, sregs[i]), - special_regnames[i]); - } + cpu_SR[SR_EDR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Mon Aug 31 16:04:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248752 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3440711ilg; Mon, 31 Aug 2020 09:07:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzvlpUPk5ArhRDdLWXTw35imHq2Ss2UXRuhPXxhFL86n7cMV+5/pbG2Ch4X3dQrRdTiVo5H X-Received: by 2002:a25:6901:: with SMTP id e1mr3275893ybc.192.1598890030246; Mon, 31 Aug 2020 09:07:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890030; cv=none; d=google.com; s=arc-20160816; b=qs8++fSAVSqjnOpvU7hBp5PIlXRc/kz2d8/jWQSMfpne7WAnwIdlQIhx4zrsBH8Cs1 z6Kl85RcMjHZ/O/eRS5jgXlNALOINZBGj4/D7MXR/+HhKiQ9AyyXhN+4t/nZw9nBcr12 bESg51XpB29966bnYhGVimvI1RVgU6qAzAQN5MTB3EhKXitZDHJ+Kf6VgNVm2IsN+5r8 dICFAjaU+ovVbLq02UcL8VFNxYKr72bXamWaz3e8pKWPf+YUIsJSOeQuVVk6UTQ/aIlp yswOaKUbXc45uQmY1tZ/D7FX4BgNKqA83L2miJvafNx4tCEM1S42whteIkJ+ktkfOwIH pDYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rviE8ITGPbpKSnQ4cqqSurUDqrYfoOOIiBP/tQ1BJEU=; b=X/R7R0xo37lLiPC6esVKL28mI4V5vTRWPZt3zaDSMjLoXJo7voM2rsQ68VTX72K5qJ 8H//UR6I8kYT3fV0VsHuK1nMZlnbmYq9S1bZw7a/YdMQX1m/LJhdzxnKN/kiBWV0uNQG d4h04lP2owLsWaYz0qjxjh4BgOcEoHq3wsZm0lB15InLiAAEhuACx8RkER8ZQWwECpqn +vYdJhSMvqhUNwFXy6RN9wNc1WpAseTY2SSyNRWAwAwLeXJDiaZzOAA8LGHkx1lylSwU JxAn0g4WFJc7GDM9oYerSZixcdzkheyF2OwMq/QM73KgmzBOhppwGCr2QdBtGiHCevNn /rgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CAyq3DFy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Similar to splitting the sregs array, this will allow further fixes and cleanups. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 106 +++++++++++++++++++++------------- 1 file changed, 65 insertions(+), 41 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7d307e6b48..19d7b8abfd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -55,7 +55,13 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; -static TCGv_i64 cpu_SR[14]; +static TCGv_i64 cpu_pc; +static TCGv_i64 cpu_msr; +static TCGv_i64 cpu_ear; +static TCGv_i64 cpu_esr; +static TCGv_i64 cpu_fsr; +static TCGv_i64 cpu_btr; +static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i64 env_btarget; @@ -117,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) TCGv_i32 tmp = tcg_const_i32(index); t_sync_flags(dc); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; @@ -136,17 +142,17 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); } else { - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(d, cpu_msr); tcg_gen_shri_i32(d, d, 31); } @@ -159,8 +165,8 @@ static void write_carry(DisasContext *dc, TCGv_i32 v) TCGv_i64 t0 = tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t0, v); /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); - tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); + tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1); + tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1); tcg_temp_free_i64(t0); } @@ -180,7 +186,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -196,7 +202,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -431,7 +437,7 @@ static void dec_xor(DisasContext *dc) static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(d, cpu_msr); } static inline void msr_write(DisasContext *dc, TCGv_i32 v) @@ -443,8 +449,8 @@ static inline void msr_write(DisasContext *dc, TCGv_i32 v) /* PVR bit is not writable. */ tcg_gen_extu_i32_i64(t, v); tcg_gen_andi_i64(t, t, ~MSR_PVR); - tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); - tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); + tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR); + tcg_gen_or_i64(cpu_msr, cpu_msr, t); tcg_temp_free_i64(t); } @@ -503,7 +509,7 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_pc, dc->pc + 4); dc->is_jmp = DISAS_UPDATE; return; } @@ -535,15 +541,25 @@ static void dec_msr(DisasContext *dc) if (to) { LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); switch (sr) { - case 0: + case SR_PC: break; - case 1: + case SR_MSR: msr_write(dc, cpu_R[dc->ra]); break; case SR_EAR: + tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); + break; case SR_ESR: + tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]); + break; case SR_FSR: - tcg_gen_extu_i32_i64(cpu_SR[sr], cpu_R[dc->ra]); + tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); + break; + case SR_BTR: + tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); + break; + case SR_EDR: + tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], @@ -561,22 +577,30 @@ static void dec_msr(DisasContext *dc) LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); switch (sr) { - case 0: + case SR_PC: tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); break; - case 1: + case SR_MSR: msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); - break; + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); + } else { + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); } + break; case SR_ESR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr); + break; case SR_FSR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); + break; case SR_BTR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); + break; case SR_EDR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -749,7 +773,7 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t0, cpu_msr); tcg_gen_andi_i32(t0, t0, MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { @@ -995,7 +1019,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); tcg_temp_free_i32(t0); @@ -1115,7 +1139,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1169,7 +1193,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false) TCGv_i64 tmp_zero = tcg_const_i64(0); tcg_gen_extu_i32_i64(tmp_btaken, env_btaken); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_SR[SR_PC], + tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tmp_btaken, tmp_zero, pc_true, pc_false); @@ -1253,7 +1277,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_pc, dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1309,7 +1333,7 @@ static inline void do_rti(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_ori_i32(t1, t1, MSR_IE); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1327,7 +1351,7 @@ static inline void do_rtb(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_andi_i32(t1, t1, ~MSR_BIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1346,7 +1370,7 @@ static inline void do_rte(DisasContext *dc) t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_ori_i32(t1, t1, MSR_EE); tcg_gen_andi_i32(t1, t1, ~MSR_EIP); tcg_gen_shri_i32(t0, t1, 1); @@ -1401,7 +1425,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU); + tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; @@ -1652,7 +1676,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_debug(); } #endif @@ -1730,7 +1754,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); sync_jmpstate(dc); } else npc = dc->jmp_pc; @@ -1740,7 +1764,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); } t_sync_flags(dc); @@ -1748,7 +1772,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1863,19 +1887,19 @@ void mb_tcg_init(void) regnames[i]); } - cpu_SR[SR_PC] = + cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); - cpu_SR[SR_MSR] = + cpu_msr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_SR[SR_EAR] = + cpu_ear = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); - cpu_SR[SR_ESR] = + cpu_esr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_SR[SR_FSR] = + cpu_fsr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); - cpu_SR[SR_BTR] = + cpu_btr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - cpu_SR[SR_EDR] = + cpu_edr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } From patchwork Mon Aug 31 16:04:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248766 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3445802ilg; Mon, 31 Aug 2020 09:13:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkeZQfEVmeuHrMg0k72XZCDUR4MZ9/hExxHOt5Q1AQNUJ0UWpG8z6zHhZADrVccGShiETv X-Received: by 2002:a25:cbca:: with SMTP id b193mr3494264ybg.202.1598890391726; Mon, 31 Aug 2020 09:13:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890391; cv=none; d=google.com; s=arc-20160816; b=dWX2mFS3HFv/vkCiK136NpidqG6i+1m9K3lfQMpofzPLTb/InwN57N9L2PuaLVRU5o mbXnSpqB4RGYW4Oq4/3IRrmBbK4DHZC5L1sEoRlTn2YtXx8dsnyVGQIm0fANn+YkaTci yGTOJIghQPKwJVPgYhuX+8eszje8WdUw0R4sRI1hmnQf+d/TC8JwQUAmOGKmG/It4JiA w5K4Fu1yLvDvxg/j2FU4cOrqdNhE+dKzGjuL2FUZ+0OcyWmhAsjnv3gGfyCODcLwxGbH RB/sC8joMZGEbVfzUqYFwRIem99652AefBNe106+VdGE0BNf83Q7MAW9tcx+ay8qBRpS vWWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7wpRkYrXRxnWUCPbRdAvlCNGmdZ4UaHFTCGkl7XSQEo=; b=NcTuVQDrOb8z9n1/5aY9lowjAu9D1u3BwWE/tXnD3tRaDGoz1ajS8g90ezKKE6NH9Z mlOrDL20+H9gMBeGUBYJbMpnQ/7rJutl0EJ+ljyBoZM1QJlyA2TytuikNbkUd8kTuxd4 seSWZ4CXOHqhnL5Mr0/xz5eTMQM+7CXPhf8yz/YbgpC37mNJx3bjEe3PoxwAo49d0Brj NDyCMVLyn+CeAjju58gqF8fPM/nebpWiJVpsafgmkZvETkGBUYuiF44na6kdjsKYxzRB 0BmY03ZoD0PzLjvJBUeKieuDhb00SIwi1U6TWeMO78JvUMlvxVis3rDDIclnHxr5G92a M65Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vzfFOdR7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The program counter is only 32-bits wide. Do not use a 64-bit type to represent it. Since they are so closely related, fix btarget at the same time. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/helper.c | 16 +++---- target/microblaze/mmu.c | 4 +- target/microblaze/op_helper.c | 4 +- target/microblaze/translate.c | 78 ++++++++++++++--------------------- 5 files changed, 43 insertions(+), 63 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 610ddfb719..f4c3c09b09 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -231,12 +231,12 @@ typedef struct CPUMBState CPUMBState; struct CPUMBState { uint32_t debug; uint32_t btaken; - uint64_t btarget; + uint32_t btarget; uint32_t bimm; uint32_t imm; uint32_t regs[32]; - uint64_t pc; + uint32_t pc; uint64_t msr; uint64_t ear; uint64_t esr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b240dc76f6..b95617a81a 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -143,7 +143,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, - "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " + "hw exception at pc=%x ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", env->pc, env->ear, env->esr, env->iflags); @@ -167,8 +167,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* was the branch immprefixed?. */ if (env->bimm) { qemu_log_mask(CPU_LOG_INT, - "bimm exception at pc=%" PRIx64 " " - "iflags=%x\n", + "bimm exception at pc=%x iflags=%x\n", env->pc, env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); @@ -186,8 +185,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, - "exception at pc=%" PRIx64 " ear=%" PRIx64 " " - "iflags=%x\n", + "exception at pc=%x ear=%" PRIx64 " iflags=%x\n", env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); @@ -224,8 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " - "iflags=%x\n", + "interrupt at pc=%x msr=%" PRIx64 " %x iflags=%x\n", env->pc, env->msr, t, env->iflags); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); @@ -242,9 +239,8 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & D_FLAG)); t = (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, - "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " - "iflags=%x\n", - env->pc, env->msr, t, env->iflags); + "break at pc=%x msr=%" PRIx64 " %x iflags=%x\n", + env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->msr |= t; diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 3f403b567b..6e583d78d9 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -250,8 +250,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) if (rn == MMU_R_TLBHI) { if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) qemu_log_mask(LOG_GUEST_ERROR, - "invalidating index %x at pc=%" PRIx64 "\n", - i, env->pc); + "invalidating index %x at pc=%x\n", + i, env->pc); env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index ae57d45536..fdf706a723 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -75,12 +75,12 @@ void helper_debug(CPUMBState *env) { int i; - qemu_log("PC=%" PRIx64 "\n", env->pc); + qemu_log("PC=%08x\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); - qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", + qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 19d7b8abfd..72783c1d8a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -55,7 +55,7 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; -static TCGv_i64 cpu_pc; +static TCGv_i32 cpu_pc; static TCGv_i64 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i64 cpu_esr; @@ -64,7 +64,7 @@ static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; -static TCGv_i64 env_btarget; +static TCGv_i32 cpu_btarget; static TCGv_i32 env_iflags; static TCGv env_res_addr; static TCGv_i32 env_res_val; @@ -123,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) TCGv_i32 tmp = tcg_const_i32(index); t_sync_flags(dc); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; @@ -142,10 +142,10 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_i64(cpu_pc, dest); + tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); } else { - tcg_gen_movi_i64(cpu_pc, dest); + tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } @@ -509,7 +509,7 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i64(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); dc->is_jmp = DISAS_UPDATE; return; } @@ -850,7 +850,7 @@ static inline void sync_jmpstate(DisasContext *dc) tcg_gen_movi_i32(env_btaken, 1); } dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i64(env_btarget, dc->jmp_pc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } } @@ -1019,7 +1019,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); tcg_temp_free_i32(t0); @@ -1139,7 +1139,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1187,18 +1187,15 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, } } -static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false) +static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) { - TCGv_i64 tmp_btaken = tcg_temp_new_i64(); - TCGv_i64 tmp_zero = tcg_const_i64(0); + TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_extu_i32_i64(tmp_btaken, env_btaken); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, - tmp_btaken, tmp_zero, + tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, + env_btaken, zero, pc_true, pc_false); - tcg_temp_free_i64(tmp_btaken); - tcg_temp_free_i64(tmp_zero); + tcg_temp_free_i32(zero); } static void dec_setup_dslot(DisasContext *dc) @@ -1229,14 +1226,12 @@ static void dec_bcc(DisasContext *dc) if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - tcg_gen_movi_i64(env_btarget, dc->pc + offset); + tcg_gen_movi_i32(cpu_btarget, dc->pc + offset); dc->jmp = JMP_DIRECT_CC; dc->jmp_pc = dc->pc + offset; } else { dc->jmp = JMP_INDIRECT; - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); } @@ -1277,7 +1272,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i64(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1303,7 +1298,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_INDIRECT; if (abs) { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) t_gen_raise_exception(dc, EXCP_BREAK); @@ -1321,9 +1316,7 @@ static void dec_br(DisasContext *dc) dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); } else { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } } } @@ -1387,7 +1380,6 @@ static inline void do_rte(DisasContext *dc) static void dec_rts(DisasContext *dc) { unsigned int b_bit, i_bit, e_bit; - TCGv_i64 tmp64; i_bit = dc->ir & (1 << 21); b_bit = dc->ir & (1 << 22); @@ -1413,13 +1405,7 @@ static void dec_rts(DisasContext *dc) dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(env_btaken, 1); - - tmp64 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_extu_i32_i64(tmp64, cpu_R[dc->ra]); - tcg_gen_add_i64(env_btarget, env_btarget, tmp64); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); - tcg_temp_free_i64(tmp64); + tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } static int dec_check_fpuv2(DisasContext *dc) @@ -1676,7 +1662,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_debug(); } #endif @@ -1718,10 +1704,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) dc->tb_flags &= ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp == JMP_INDIRECT) { - TCGv_i64 tmp_pc = tcg_const_i64(dc->pc); - eval_cond_jmp(dc, env_btarget, tmp_pc); - tcg_temp_free_i64(tmp_pc); - + TCGv_i32 tmp_pc = tcg_const_i32(dc->pc); + eval_cond_jmp(dc, cpu_btarget, tmp_pc); + tcg_temp_free_i32(tmp_pc); dc->is_jmp = DISAS_JUMP; } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); @@ -1754,7 +1739,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); sync_jmpstate(dc); } else npc = dc->jmp_pc; @@ -1764,7 +1749,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); } t_sync_flags(dc); @@ -1772,7 +1757,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1822,7 +1807,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) return; } - qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", + qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " @@ -1830,8 +1815,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, env->btr); - qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " - "eip=%d ie=%d\n", + qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", @@ -1869,7 +1853,7 @@ void mb_tcg_init(void) env_imm = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); - env_btarget = tcg_global_mem_new_i64(cpu_env, + cpu_btarget = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btarget), "btarget"); env_btaken = tcg_global_mem_new_i32(cpu_env, @@ -1888,7 +1872,7 @@ void mb_tcg_init(void) } cpu_pc = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_ear = From patchwork Mon Aug 31 16:04:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248761 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3444261ilg; Mon, 31 Aug 2020 09:11:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxEXiFxA18JzcT1wC5Fex+NMsq1LDXNt17Xsx6BqKqnGgHsCgRioY1q4VVhk81MGyoo+6wQ X-Received: by 2002:a5b:d08:: with SMTP id y8mr3626013ybp.476.1598890278793; Mon, 31 Aug 2020 09:11:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890278; cv=none; d=google.com; s=arc-20160816; b=lazjHGqwp+47FUv0IrZMo7K5y/D9bl9CEg1OMNxOlFzUordF4YF+g1PiRj5yhlwzc8 KXW92Qfxka5hrhDbu/FGXols9uTKBF7SWfdjXw8EHY17H5n8nN7aUO4ymFF6iWhnaACi 6LWYae4lSrqHW3O/IixvFTOznWv9ACn43RGL/Lxf7JkavDjZGOAUcHkgMCd3zcqAfO1C IGOhMpi4vgDzNgTEwmniGtuKJyHtNYRL81fzCVh4OpoRX5f3UUIKTmNbZ3vvX+A5/LEB DRyJsSh7hJFITLrUqA3eJ7ksIW3GekGymTApYiuKWCttwyOvEvOM9TiL1j+WSV6e7wiH ih4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M4lPpeA/HUa0K6dYkBR9tjNHwEHg5QIOBuo5I8jj/mI=; b=IGPTODcC6GhNe255EVOW8pPvRGJ2acA+hPNMb7qO/pu2TtIfYVh5J7/QsQ6iqyp2Ax vhnSOI3ikCq1ci1IywksJ0cXJ75IKQ7ykMEPUFJHG86GftTpNUQSmoEbM6pRct+R8C1J yRos3JEQwr/OI74v46LVH+4o9elah8VofHixeHszzCo3pxGZmZ1qtd8V/WA1uHjdfVzH xtWO8SZNCIOHonC59DjY1v+XIkMZxjPOfqc0kCTyy+90X7EncvhpQDIORwolf0BatgFr yVoLm73i7GmjdXzySWXISgr8YUBfV4MGciMPvzc8om1e9QdJfv6XDJq3xvSMhpjvRPdo 3caA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zPVVq9Au; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l17si7509129ybm.328.2020.08.31.09.11.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:11:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zPVVq9Au; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47258 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmOs-0005IM-8s for patch@linaro.org; Mon, 31 Aug 2020 12:11:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33590) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKB-0003vG-46 for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:27 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:33628) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmK9-0005x7-2N for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:26 -0400 Received: by mail-pl1-x643.google.com with SMTP id h2so3256455plr.0 for ; Mon, 31 Aug 2020 09:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M4lPpeA/HUa0K6dYkBR9tjNHwEHg5QIOBuo5I8jj/mI=; b=zPVVq9AuyPucbq3wRxfr3pZbqXctgPSWxcdaAN7zgYbo8DlCaaavKQxjjTBYQ9Cged oEKLr5XYh0tl+4qHkRdHnon79rYPhH5ayIFLYgiidka4OPgRgv883VNNYOHKeOPRE9Ok Yn463gb3i3v0YVhGX/crJjhxAOTw+uYmcq2uIMTLP3ysyeOHDRup6MNnGQe1PQRP9vIJ amHw+AM9yHKPH/jIJsehHRosJUJE0aTsN8q8E6GHuqEaSQds4e3XRh6dnLdEJNYUrsbN hLUejHevWWQij+wiFejfL6KlqM1Pr2SW2zS+OOapupGnrFXqGKhOyTzlozQTRQXTvB+6 kGiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M4lPpeA/HUa0K6dYkBR9tjNHwEHg5QIOBuo5I8jj/mI=; b=hKDn2rJZeHn6GyBr0xhGTTeenz6zdt0sMAtD+BNSZjeD46MVC9EuTOGug8laoGYct1 +CN9hkTMm3BlW3OCqtRTNgImzggxUlPt10taMvZ6BAA4dHw88XFKTK48gQCBIq7HLjw2 FZt3NtJrxC57pkO7ccMCWAw0xwQcjZCTQPB8xt6dd4cyMJdWc5tWvQ7fUksfsRX6DLWb ShOE17L1lJYzjUSTKfbLaNRzbmnlHwrGFbc5EGRBhomH9OIscPdL+NEpQvBC/92+Tajs ojyzqIvAQsaS9CXBxlFWYfO2GSKOykY49QVJLrYcjwhwivuOqQC94kXwb8KbBQAktVN9 b7Fw== X-Gm-Message-State: AOAM533Hfkzgv55mh6+brtI0mCmGDPN7s9kGnxFN1cs+NpIqnvwlK7+F df1+tMzgBDz6Uc2d0XB+SBOA8NK/l5IlPA== X-Received: by 2002:a17:90a:f117:: with SMTP id cc23mr57930pjb.155.1598889983274; Mon, 31 Aug 2020 09:06:23 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 14/76] target/microblaze: Fix width of MSR Date: Mon, 31 Aug 2020 09:04:59 -0700 Message-Id: <20200831160601.833692-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The machine status register is only 32-bits wide. Do not use a 64-bit type to represent it. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 38 ++++++++++++----------------------- 4 files changed, 17 insertions(+), 29 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f4c3c09b09..019e5dfa26 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -237,7 +237,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint32_t pc; - uint64_t msr; + uint32_t msr; uint64_t ear; uint64_t esr; uint64_t fsr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b95617a81a..af79091fd2 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%x msr=%" PRIx64 " %x iflags=%x\n", + "interrupt at pc=%x msr=%x %x iflags=%x\n", env->pc, env->msr, t, env->iflags); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); @@ -239,7 +239,7 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & D_FLAG)); t = (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, - "break at pc=%x msr=%" PRIx64 " %x iflags=%x\n", + "break at pc=%x msr=%x %x iflags=%x\n", env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index fdf706a723..a7f6cb71f1 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 72783c1d8a..0e71e7ed01 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,7 +56,7 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; -static TCGv_i64 cpu_msr; +static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i64 cpu_esr; static TCGv_i64 cpu_fsr; @@ -152,8 +152,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_msr); - tcg_gen_shri_i32(d, d, 31); + tcg_gen_shri_i32(d, cpu_msr, 31); } /* @@ -162,12 +161,9 @@ static void read_carry(DisasContext *dc, TCGv_i32 d) */ static void write_carry(DisasContext *dc, TCGv_i32 v) { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(t0, v); /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1); - tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1); - tcg_temp_free_i64(t0); + tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1); + tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1); } static void write_carryi(DisasContext *dc, bool carry) @@ -437,21 +433,14 @@ static void dec_xor(DisasContext *dc) static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_msr); + tcg_gen_mov_i32(d, cpu_msr); } static inline void msr_write(DisasContext *dc, TCGv_i32 v) { - TCGv_i64 t; - - t = tcg_temp_new_i64(); dc->cpustate_changed = 1; - /* PVR bit is not writable. */ - tcg_gen_extu_i32_i64(t, v); - tcg_gen_andi_i64(t, t, ~MSR_PVR); - tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR); - tcg_gen_or_i64(cpu_msr, cpu_msr, t); - tcg_temp_free_i64(t); + /* PVR bit is not writable, and is never set. */ + tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR); } static void dec_msr(DisasContext *dc) @@ -773,8 +762,7 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_extrl_i64_i32(t0, cpu_msr); - tcg_gen_andi_i32(t0, t0, MSR_CC); + tcg_gen_andi_i32(t0, cpu_msr, MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); @@ -1326,7 +1314,7 @@ static inline void do_rti(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_ori_i32(t1, t1, MSR_IE); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1344,7 +1332,7 @@ static inline void do_rtb(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_andi_i32(t1, t1, ~MSR_BIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1363,7 +1351,7 @@ static inline void do_rte(DisasContext *dc) t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_ori_i32(t1, t1, MSR_EE); tcg_gen_andi_i32(t1, t1, ~MSR_EIP); tcg_gen_shri_i32(t0, t1, 1); @@ -1809,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_fprintf(f, "rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, @@ -1874,7 +1862,7 @@ void mb_tcg_init(void) cpu_pc = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_ear = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = From patchwork Mon Aug 31 16:05:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248770 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3446828ilg; Mon, 31 Aug 2020 09:14:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw4wCtdrj/DukszGaAUhN5fCUSt+fMr6J/zSh7LYTZsB+zYXKrowTqwv49UElbuyYyKKFFF X-Received: by 2002:a5b:b45:: with SMTP id b5mr3236922ybr.294.1598890467831; Mon, 31 Aug 2020 09:14:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890467; cv=none; d=google.com; s=arc-20160816; b=UpC5EcsB5MyccWiFIbKJLpl20JSnYFx9CiU+8I264Ba9Wuzmhl64gZbTzG463Dd3Pa bAam0M2rcZF1thcbegLBxDIjc3DO9zQJACqGeMJ5EaupxpkVbuyNPLqXMOexF6ESFz0G jt1Xmv2NT4Mfucu0uZZO6WZgwmh4GhIKLDvDCd/ap0ssQ44Eva2SIDKkN7q12qhQh2BC ojCdRhSwgmy/ahZBn9cVBaw2zSfqJU92/fQu/2Fas+//rO+EJKav82dtEnqL3TaN6Cf4 LSfq3Kj85Esw33alU+Yi2fRjF31wuXPopD/gGc1MNUBR0jYPW0Ylrl7jzDQLIL7s+Z2Q d98Q== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id s135si8536069ybc.128.2020.08.31.09.14.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:14:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZVWIK+fJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmRv-0003R4-2O for patch@linaro.org; Mon, 31 Aug 2020 12:14:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKC-0003yq-Gf for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:28 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:45575) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKA-0005xO-Df for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:28 -0400 Received: by mail-pl1-x644.google.com with SMTP id bh1so3226485plb.12 for ; Mon, 31 Aug 2020 09:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L9xfsBjzirj6XKVdMLPG8wUDAQP5YXeed0MwjLYymYM=; b=ZVWIK+fJFijSS8zFQtk50sLCYQrStpVuJGsVnmZ7WtHESnSGHX8bOgkk4nQxFf7RCC w9bf0+MG07hn1GpH6yKrAZw8fzdZf36rExmpqvZBHmrRF6Q24OP2ceUwFVUgNg3KOMxF RhEhFBr9w02GVzBkVTmVwZBteZlsHRvtoF3snRDDnf1DdsnyLVwJEAPQEpcorSubQKhl Kw/96u6NBRyUHd5KzTJgss6QUbKPVoWzRoCUKuKYQPhjTFarxrbRdeGMhhIst4jc/dCp 8MDh1aJgOxDf2PIIwwDc9d7yq8uhYDocGjh9G6kTQ7UbqwwuV8dFZ1ZFKTRoR/UVjv7f yHwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L9xfsBjzirj6XKVdMLPG8wUDAQP5YXeed0MwjLYymYM=; b=nxrV4btx2vi/r0W8FyliBnTSlZbL7XNnvNPH8Byw4/FXF8EV6ib0ZxItSJ8Z5hfvav trdp10+x9C/yaHI7uA7YPb633SDSHhr5DD3aH440oGz0BIitGNbo8WNLZuJZqXDeFA5a DNqpn7RxXYnYrrBJXe7WrQX/XIansTgABqJ+VYK7bwKHwkEdHiDUtvpPEzZ+Juv3P2ZR M8GjfIrgB55sgdeNjuLjxeWEoR9WoRle1TEFra+WHpcJG4ezo04Uv4BNP60ZODN2j+sU IhkA7ZCajt4nhK656rNvrEFjZBckaGN6ckttJ9mkfaFKjWzOdg1uaLDnvmSZgXwcTjHy 5vXw== X-Gm-Message-State: AOAM531ods1Pa4nrLfy/cnTAorJs8OHimdfWfQ9HK0KbM0h2ciMZZ3Iu jRrGoSty0Td8yZW/W6k/lNLmHw0fp5Z0qg== X-Received: by 2002:a17:902:720a:: with SMTP id ba10mr1548099plb.41.1598889984647; Mon, 31 Aug 2020 09:06:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 15/76] target/microblaze: Fix width of ESR Date: Mon, 31 Aug 2020 09:05:00 -0700 Message-Id: <20200831160601.833692-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 16 ++++++++-------- 5 files changed, 12 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 019e5dfa26..aaac0c9a6c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,7 +239,7 @@ struct CPUMBState { uint32_t pc; uint32_t msr; uint64_t ear; - uint64_t esr; + uint32_t esr; uint64_t fsr; uint64_t btr; uint64_t edr; diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index da5e98b784..3de99ea311 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -106,7 +106,7 @@ void cpu_loop(CPUMBState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; default: - fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n", + fprintf(stderr, "Unhandled hw-exception: 0x%x\n", env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index af79091fd2..b2373f6a23 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -144,7 +144,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%x ear=%" PRIx64 " " - "esr=%" PRIx64 " iflags=%x\n", + "esr=%x iflags=%x\n", env->pc, env->ear, env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index a7f6cb71f1..dc2bec0c99 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_log("rmsr=%x resr=%x rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0e71e7ed01..f63aae6de9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,7 +58,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; -static TCGv_i64 cpu_esr; +static TCGv_i32 cpu_esr; static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; @@ -182,7 +182,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -198,7 +198,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -539,7 +539,7 @@ static void dec_msr(DisasContext *dc) tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); break; case SR_ESR: - tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]); + tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); @@ -580,7 +580,7 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr); + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); @@ -1399,7 +1399,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU); + tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; @@ -1797,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, @@ -1866,7 +1866,7 @@ void mb_tcg_init(void) cpu_ear = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); cpu_fsr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr = From patchwork Mon Aug 31 16:05:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248773 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3448428ilg; Mon, 31 Aug 2020 09:16:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyQbkpBqOizFe+npqUhBMNKCUe6QosmucXVfSVMqio+8+pX79LiMi4HOfT6n2spG8J0uuPC X-Received: by 2002:a25:2612:: with SMTP id m18mr3336154ybm.184.1598890586391; Mon, 31 Aug 2020 09:16:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890586; cv=none; d=google.com; s=arc-20160816; b=CojfUu1MFo07Wnv7+uobTz3zPdYIHmsI7zww9qAr+QX2114yJBXP2KtRt5loGj2RFn 43LzxlkwIWCX6h8YHI6/gS6FxyfTp2BIMiVn059iAv5S+U5xcJo8apDxgDD3Ktin+AAy wNDRJPYtZd0/esGtktfZ7XV6lHMDh6vmw4DFl7Dc5DCGFs9VivpXNZx0xIzekLNSA63N JfMmMij9kD6DanI5/mrgUz0JBJFn+FoAKr+yl9yQmL/MdDkPLuaDOmhqmQKuf1o7hbIE J+kJiFqEv8aD5s/IkQmH2qRCvirhYi5JXDs6lLggNGaC9RbT+mqHN77ZXUvwyeIDj9+W smHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=haB+kLrfuYUnX1QRhCRrExdmXpWhe0msojEhc/6IfBE=; b=AXVucuNqebujc7ua6TSQgySJFGpIK8YNE1pGLzCpxozQ9rDwC5knI/ecvIjnGEuI6a zXo1Eg30bKDZlgi3YHWcQBJPanKUim5IoblcgtONtQarLU2zewekfXF7QvniFOLeB+sM LcPmO5dwd3N0qKtJMt2Hy2/+Qy6z8bGgVrFkQp9+/41HIRCK5F+YXHTqJuf0N3hzJMUH XstVa9Edf22NqzEVo+APPk9BnN9OHcYTz9+hjFWFMNCECofIBRQuD4UV6/tzA3WCUHuz //V5n0Ta7Dq5hwbh7lEfaVtv3MEAGRpnA3qJOrKZt9u731bs6s8sep88wZGoyJpC/QWv D2Ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q+k2ihij; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_fsr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index aaac0c9a6c..34177f9b28 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -240,7 +240,7 @@ struct CPUMBState { uint32_t msr; uint64_t ear; uint32_t esr; - uint64_t fsr; + uint32_t fsr; uint64_t btr; uint64_t edr; float_status fp_status; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f63aae6de9..3fc2feda3d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; @@ -542,7 +541,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: - tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); @@ -583,7 +583,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); @@ -1798,7 +1799,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " + "debug=%x imm=%x iflags=%x fsr=%x " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, @@ -1867,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_fsr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr = From patchwork Mon Aug 31 16:05:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248772 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3447371ilg; Mon, 31 Aug 2020 09:15:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMxOtq8oWV1b/OsKN3Zd+wXK5881WAy6Hidn99XNCSCM9sMxwaMYoNGpjpzjZBkaGR8AMQ X-Received: by 2002:a1f:1a0e:: with SMTP id a14mr1645422vka.87.1598890508052; Mon, 31 Aug 2020 09:15:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890508; cv=none; d=google.com; s=arc-20160816; b=XGGXFo44LNIjXPfACTEYhyT7/7U0Scs/718fLHQjSi4/srCAs9Kj31RK5A+4/KsGns ztJarPSmcsJYUgxbeuDZSiHQavYniMSlSgFGfJb4W2G7C9fNDytaGQ+77cv6TL1tk7c0 8+d/f5Y+aQ/N9cbjgc34vjLfjeyH5CrsL7OQaZCrH90jDIyafeVC3GL8IL/LGERfbmS0 pA7M1zswPrjO/B/YGnGbRdN3ki1kwEU6W99t0lwg0i7Fp/SPs40ZBrobNnrcWoDQVD1X w8b+8W2u7WBfj8cakaXEi2k1rurAjX2oLobhUeReShW4xHh1lemd5DawUTUAEOLEjU7a +7Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5ShF+BY48IwWmImvy13quKmLT6LR29ss78JGb2qClWk=; b=cSYeP98i91wy/9TJjkjfEh2kObdKu0/4vhVi6urnPhWmSfF8soba0qfCgDaXxh8ila uZYFxmThowsgrevumo2gst7V702GtAHLSPt32rWr5w9k/Wd3xcfHXK1MgN6nI41QQSdR 94KepTY93hhGD7gVlYdhIhVEt6bjgGMqBh1oc7xkUhbP1CivuJAEfTq/E8mtU1mTyQfb uKAwdLSy0nQDJ2I4v/ZTkZhncahydRotmICz3V0l3rO0UHzJJ+4iuNr4WPQhVgnja1ss qULw+WQnVKzqF8ueTEVGCCnkHLgifNd0JHAdZ9A7Jn/oskQqM61da9CIjWLfFmVCnSN9 /BaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e6H9RCuE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v7si1194339vsm.174.2020.08.31.09.15.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:15:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e6H9RCuE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmSZ-00054c-Dh for patch@linaro.org; Mon, 31 Aug 2020 12:15:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKF-00047A-JS for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:31 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:54430) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKD-0005yF-8J for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:31 -0400 Received: by mail-pj1-x1036.google.com with SMTP id mm21so22366pjb.4 for ; Mon, 31 Aug 2020 09:06:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5ShF+BY48IwWmImvy13quKmLT6LR29ss78JGb2qClWk=; b=e6H9RCuEKvAL+dLt6N7M3C0TcE2anGkJN9Z91jPzXhZEYoyYmMu+DD394dp6CGlApu 04cwemSEhZ2q1QcrIrjbuCpF6UIYoMB0TiSyRGLGpA18eKJDefax0/LMj3p2E1STxzJl Ea5aPjD8n+Wgf4rrgXORlgUeHQxlwuAdLlqXDk+MPTwPLUzO3mXJJmt5aTijoZGS6UHw oSjpkmCMsA5kUNJKBty02udS1fhu9CVDsgiJnA62EUF/XB5A3Rucgu8MkG2IQhHIb7F3 Qa2KDzaelkVfWP2a7nE/MfMSN5PxO8cq9IeMLHdiqo0bDK4vU/di/xkk5u6XJVj4j2Zp 8cSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5ShF+BY48IwWmImvy13quKmLT6LR29ss78JGb2qClWk=; b=Fd7tInKS2d4TOR5LZQFEOY+e8WZzXah8nQTz7AWQ0W+bvKmbYgV0DIOSs2pP+dV8fn FdDQTGUPNxNYkseXfp0vT2gJ21EV+sB0O21kI83t9wepb4+vXZzvynLMxa0AFKR7mfIi tLSMvfAkYZEvKjVnmcpeDSaMai3xMDoPmF67A2QSj7eNCF2MU4SXyD9BNTJElTQhzP4y sMjaHEIO4/w1rL5Wn/XZudWi+cNL/kbGwmg7CBTib/5FK6QdzstLJao6zbzgi0YzL2OO gYPAiGgX3IoQBqx5FhF2pppzm00MhwmoGr3JKLPOGoxQSsqE/ZuKgYuMl4CMJbzeLd+S rVHA== X-Gm-Message-State: AOAM531xR2KIO2fDfW25A3XbZ6QXaVSOxPAyT2b+uynIGRmXVwwyknBH OQrlN907chO/nufb2yQh23QNSi1YOpbogg== X-Received: by 2002:a17:902:6ac3:: with SMTP id i3mr1591333plt.21.1598889987492; Mon, 31 Aug 2020 09:06:27 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/76] target/microblaze: Fix width of BTR Date: Mon, 31 Aug 2020 09:05:02 -0700 Message-Id: <20200831160601.833692-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The branch target register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_btr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 12 +++++------- 2 files changed, 6 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 34177f9b28..72f068a5fd 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,7 +241,7 @@ struct CPUMBState { uint64_t ear; uint32_t esr; uint32_t fsr; - uint64_t btr; + uint32_t btr; uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3fc2feda3d..a2bba0fe61 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -545,7 +544,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); @@ -587,7 +587,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); @@ -1799,8 +1800,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%x " - "rbtr=%" PRIx64 "\n", + "debug=%x imm=%x iflags=%x fsr=%x rbtr=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, env->btr); @@ -1868,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_btr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } From patchwork Mon Aug 31 16:05:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248756 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3442245ilg; Mon, 31 Aug 2020 09:08:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhCf0Z13i5jea2fDN+8+MUMBKOyaWTG2oQyaHAeNa4TAZkSvh6aSmH8Ay3Eo/LQ0+Ez2W8 X-Received: by 2002:a25:d4e:: with SMTP id 75mr3029339ybn.480.1598890134583; Mon, 31 Aug 2020 09:08:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890134; cv=none; d=google.com; s=arc-20160816; b=zYgngI3QWzs0ZbZpXDyU9oma23ej4Myq2vLC0pDDuG03VSmvkbpMl+phcPom4wIKhL GvRRiutN0NU8lOU+IhpN6NVASDoeEJb4PLk8g0X7mY6wMLY01YC/qqPiYfD4SIFvYXhM yR5AR1asmaa1XXAn7As4+rk1SS0/mS7E8yk/GZHcl36Elv8AeJchMKa3HhoKvhanbe7H Iw9TKBXPcltcsMs9E88Jph4a+1W3PDuASc95Y1aVr4EEWQC+7DiwH3n2+Co8/V1HVCBk BVUx2+NTaNc04Hy0ayFcUGldmf84IA3rmHLizKeRrQfJgZLmZntZesRkxnVQ1uYisSe1 yJMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=a0lsjfSJGV5n3EJZlHS5Bf00XbvDVFjsqHd/6iA5EWQ=; b=NCoJwHhupXydBhqjvKDe93XsnLtXipn8mdiKDXG+/z/uMFXDbeL+T+pzTX71Vdxvef tb17RonlI+eEORRs59d9oZw8fhtNGc2xpRVxwIKCgVdOevAHc5Y9mCL1ZDipSkMS7bSr ku0e7QNRtnAcNf2TxF7IU79QhPplu2QT+xSxUxG8/9Ujd036W8RtE7nEWDuaZSd5rcGs rlMYXCzaOpJFKCKAitr16hCUv25QIFdv2HNdzQh7yyHi3z+sWEn5/8OQVJWobT4P2GNL QRvVcHBpymXgegzDTUdHLQGEPHu6WkJP4KrvgvEgqhHynf3nF/PxBh5Wb4/4mAb83OSR mmjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cd4Tt9Ej; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s6si7997249ybk.233.2020.08.31.09.08.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:08:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cd4Tt9Ej; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmMY-0007aY-0R for patch@linaro.org; Mon, 31 Aug 2020 12:08:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKH-0004B5-14 for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:33 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:52758) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKE-0005yU-HE for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:32 -0400 Received: by mail-pj1-x1029.google.com with SMTP id o16so28034pjr.2 for ; Mon, 31 Aug 2020 09:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a0lsjfSJGV5n3EJZlHS5Bf00XbvDVFjsqHd/6iA5EWQ=; b=cd4Tt9EjTc04eHfBPpNFdFwM2EJFVGUleFLVKLO/1Xn7FKNJXOJQ45ms7tdsgp8drQ mTKbN1+3yAnbzMYmC4YWufv8uTwjl2AVYRqn6F4D/zFDWn2dhxdrGJo+jmYz25C9KLU8 fsUf1hE40hAAn8C5Rg75cjhO08XGmJTr5E+T83LXDD5ZOrrQKeVRshE1BwsIvw2DNiGO 2SHMeXoaO8E7YBTSGZgeZuaGS//iIs5mO41ATcB+kfvsg2hpK8JsuQPlIhmt8JMNsDw2 2XanwJMvtvBU0ebC+Q74Acj1PjY++ZRbcnN2ZiD/Rvoi5fVKd/6PKJgnteEqQ/k6Rdws dPCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a0lsjfSJGV5n3EJZlHS5Bf00XbvDVFjsqHd/6iA5EWQ=; b=do9AjA8NABMrixZjA414emnwyFbBUuDzmhqlbGiKpZzbsKI6gVCS8f7pAna0WDfDwO X34kLdDvbjuDyjeX5vyOTArERRosoFOhSkYNu+bqxldDHTtamwVmI4nlk3UqW5IpDX6p eY5258Od2Wo2MnDvpdSlCPwSewJWS8T7DEV6f94lPIiRmykfoQMh/Zqm68MPYd/F2mvL 9sOSd/P5ZIOJlyF3IWOPWbzftDEap+jnicfi7WGjgpxN9D+umk4+qpybENu/KI5EObYX j9Vel1zjBuhL6curOPvVSYjUASmam54q+RhsHzqjV0zVmwORDq3KrF985eA7T1SUm8Cz 07JA== X-Gm-Message-State: AOAM532S6BwPxH3x/YGFXQr1ICRuxsCrChbs5q4gJ68XusQO9sgTTaBy SGOMMgzThAe5yAdEP6rxT7YfN5eeW+LJMg== X-Received: by 2002:a17:90a:5a48:: with SMTP id m8mr61640pji.181.1598889988664; Mon, 31 Aug 2020 09:06:28 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 18/76] target/microblaze: Fix width of EDR Date: Mon, 31 Aug 2020 09:05:03 -0700 Message-Id: <20200831160601.833692-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception data register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_edr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 72f068a5fd..b88acba12b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint32_t esr; uint32_t fsr; uint32_t btr; - uint64_t edr; + uint32_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a2bba0fe61..a862ac4055 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 cpu_btarget; @@ -548,7 +547,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: - tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, edr)); break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], @@ -591,7 +591,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, edr)); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -1818,7 +1819,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } /* Registers that aren't modeled are reported as 0 */ - qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " + qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " "rtlblo=0 rtlbhi=0\n", env->edr); qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { @@ -1868,8 +1869,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_edr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Mon Aug 31 16:05:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248760 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3443636ilg; Mon, 31 Aug 2020 09:10:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyX68UVzOhaTQ7a8paup3fJ2aIxOcODS7D4xNqecvK6YegwGV9amUHtx3RjV3o1mF7VeOCz X-Received: by 2002:a25:c606:: with SMTP id k6mr3223707ybf.183.1598890237369; Mon, 31 Aug 2020 09:10:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890237; cv=none; d=google.com; s=arc-20160816; b=hO1Tjpxv8y41b63uEWZrBisHiYJpzkZPImCycVMZp07gLRkZTbcYfsLUE1+z7LzSRG Xoh8UbNdaFM4ME9hlsOIYAPNn1SWVo7EFI+WsLLMMoRxUW3ugfW1kRVpKU5v3IpM1fnw +eIVOiLoFLNim1LvhKBXpS7a+Fw92UjyoLR4BNGl1FAcs/ASTdVcdr9cNI8r+17DlFcZ TopoQD7DR02q/Uo3hJcOXXqBA4f2y+xYzOvd9jtbEK00Awe8ckl+3V4o4BWmNKWg0fJR QEEi1zE1xxTYP6AzD+2jW71HBKvzHwkWAQOibR0gozGoDV+A1lcPuGjs/tkbOjYPCKXm U+ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hvfzFSYLvytasBwqaxM3erubgzY88RSzpHLi7SaenA4=; b=decRIiPZdgyzpKTgcwxgyRCJiltpE6edlWeugf4DIadr0fOqNsdjp95gkljiFpvyo6 uw3UQCCIrWEvWbhx3r7iogeF/OM29h9r7Kk/ksfrwPLiRaTYzVzE65MARrb61qVRusED gqz1Qp+EugJRbh04D1gu+EYMlp8CLaY4vlin9ZUN1xBp7MylzVqm2wEP5zKBB+/ONCAj Kz5lqd2bTLjG/zfS1k1miS3cUGeMg1lBZSm6dUN5bxU8q6HRePnwvZHVAqMvECe1HKqa DtBS5mCcUCTrERkE8JqP+Gg0aIhO95jjaSeLRrOkr4pvCRzBbZ6a2Yhj27tFai3s9iDn Y8Yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="GiahcZs/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since cpu_ear is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a862ac4055..f5ca25cead 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,6 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -533,7 +532,12 @@ static void dec_msr(DisasContext *dc) msr_write(dc, cpu_R[dc->ra]); break; case SR_EAR: - tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); + tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_temp_free_i64(t64); + } break; case SR_ESR: tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); @@ -573,10 +577,15 @@ static void dec_msr(DisasContext *dc) msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: - if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); - } else { - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + if (extended) { + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); + } else { + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); + } + tcg_temp_free_i64(t64); } break; case SR_ESR: @@ -1865,8 +1874,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_ear = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); } From patchwork Mon Aug 31 16:05:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248764 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3445043ilg; Mon, 31 Aug 2020 09:12:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyWIc4yd78KRwbXoy/8PjPvcPn5AoQvlNiIDsXWEAQNthTHJZB4SMLcET61BOosIkr6PLvK X-Received: by 2002:a25:6e54:: with SMTP id j81mr3139597ybc.194.1598890334646; Mon, 31 Aug 2020 09:12:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890334; cv=none; d=google.com; s=arc-20160816; b=Nm7bQgNIqcHmiPyz9XpkHC0+Kr3jimi9bCbxFIbXsGzhoPFOtWeOJlZPD2buszcerc awU9zv1QgB+kiymcvuCkmDUlt1IM8hPnR+aXwX7OT5W/z4M5kPMVw+yMqOZFq1l4IGI4 rw3b5eGaKGEa4yyE7Q/clEbNsKvsy0hxREznq2zV+Rx7xBJO8dIi2K4Ju5iRg4aJzjze 9VDn/SJJSeMnBy1HWuRLq4nkd3qL92musEPS0b8OgpNgxCJ9H4cDYBOnyjBNKPUEydcE jijDc6jDyIPZxH4L/1e1x7PBXbmFu+7spQrIPqQNhuMNwEPp1nQyDEtvOt66N6k2wYg4 a38Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=A5jlK0T95NH3JH2keCbWDldYP2nsIY3hCH9MCVLy8Ng=; b=fhocT4ayXEAfyowyNLJUM5ZcB6cZztG+iUACZXSNGzb46G8XLSyTar7bGpuHEYdqBn PzCaHG12nqoQy6SHcULmImnBV4WJbZSYg3rCK3mQbZGHMZk3deZd7MI09ZFqOQOY/+y5 48EeAVOIS/AEDW6QfQ8MHRvtTFKX6pcLCWZWDJZ8cDIaAa/GkItKQ2GlR2aFTEbjy5jG CKNzqF+ItQrcIyxI12q3CL0NAik78XenbQ6wvQIh4AJql4GbKxvMrcZAh6odhgd5C+J5 YFciYmtmjuBbyOz/GbiansoFvPWglYWs3nCbeJuQ4OSGsHP8xQteuPBqkXEsSXQfbA2f FSWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=npAPzeI3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out gen_raise_exception which does no cpu state sync. Rename t_gen_raise_exception to gen_raise_exception_sync to emphasize that it does a sync. Create gen_raise_hw_excp to simplify code raising EXCP_HW_EXCP. Since there is now only one use of cpu_esr, perform a store instead and remove the TCG variable. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 62 +++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f5ca25cead..9a00a78b8a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,6 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i32 cpu_esr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 cpu_btarget; @@ -114,17 +113,31 @@ static inline void t_sync_flags(DisasContext *dc) } } -static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) +static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); - t_sync_flags(dc); - tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; } +static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) +{ + t_sync_flags(dc); + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_raise_exception(dc, index); +} + +static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) +{ + TCGv_i32 tmp = tcg_const_i32(esr_ec); + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr)); + tcg_temp_free_i32(tmp); + + gen_raise_exception_sync(dc, EXCP_HW_EXCP); +} + static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { #ifndef CONFIG_USER_ONLY @@ -178,8 +191,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); } return cond; } @@ -194,8 +206,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); } return cond_user; } @@ -540,7 +551,8 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, esr)); break; case SR_FSR: tcg_gen_st_i32(cpu_R[dc->ra], @@ -589,7 +601,8 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, esr)); break; case SR_FSR: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -1258,8 +1271,7 @@ static void dec_br(DisasContext *dc) /* mbar IMM & 16 decodes to sleep. */ if (mbar_imm & 16) { - TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT); - TCGv_i32 tmp_1 = tcg_const_i32(1); + TCGv_i32 tmp_1; LOG_DIS("sleep\n"); @@ -1269,13 +1281,16 @@ static void dec_br(DisasContext *dc) } t_sync_flags(dc); + + tmp_1 = tcg_const_i32(1); tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); - gen_helper_raise_exception(cpu_env, tmp_hlt); - tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); + + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); + + gen_raise_exception(dc, EXCP_HLT); return; } /* Break the TB. */ @@ -1300,14 +1315,15 @@ static void dec_br(DisasContext *dc) tcg_gen_movi_i32(env_btaken, 1); tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { - if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) - t_gen_raise_exception(dc, EXCP_BREAK); + if (!(dc->tb_flags & IMM_FLAG) && + (dc->imm == 8 || dc->imm == 0x18)) { + gen_raise_exception_sync(dc, EXCP_BREAK); + } if (dc->imm == 0) { if (trap_userspace(dc, true)) { return; } - - t_gen_raise_exception(dc, EXCP_DEBUG); + gen_raise_exception_sync(dc, EXCP_DEBUG); } } } else { @@ -1411,8 +1427,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_FPU); } return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; } @@ -1668,8 +1683,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) #endif if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { - t_gen_raise_exception(dc, EXCP_DEBUG); - dc->is_jmp = DISAS_UPDATE; + gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that @@ -1874,8 +1888,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_esr = - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Mon Aug 31 16:05:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248765 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3445535ilg; Mon, 31 Aug 2020 09:12:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyc3tyIWuunc4o7iPbLIJPwDYVrCMUEZj5jGFb16iEVTN+9H9i00aEHUzvyeNOFw01COJM6 X-Received: by 2002:a25:a4c2:: with SMTP id g60mr3155731ybi.134.1598890373503; Mon, 31 Aug 2020 09:12:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890373; cv=none; d=google.com; s=arc-20160816; b=GO2i4JhnGLQ2bFIz5E0vxWtwBUkbR+oTNfW6iC2GPL3myhxVtmjRP1JiItBThglrpT dcgzkSgiiFu3oQuk7U564j9cXEuUA1ucBmrMAm5pbsz+EZIBHSssEJNeSWqvQjh6HwyN IKJoKgOSilzqDKIL30RkjR8guqr6mWjnZ1swM4Nv6lNoA3fbfimxlPsx9Y1gJX0Lc3E3 zDANgxI+czuV6pcYKbARVnOXp3iI+U565p/DMkq35blnEdOXvuqdYCiwtFNvJQfeIWh/ rK1eo3qXvFJtKMQS63E/hW0eeXQmChPMsf2V3GIjmI02NXPv5m+yl2UcX29ikwPVih6u xncA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=m3MYH1ZpDTZxIcPbri13lEz6BY7Q37pNtVKufrg+PL0=; b=u07K7zY0eTY++XO8ezUad4Mf3baWyOMkoFkzswap0FucAp81Td9Z0xQ3UgPGoUnZhb ZffI8QDQDPIk+4Lz4JMLMUaFHY/zmGW8G1H+aulBP86tG0jE56PZbU9p7ZYDlAgFVDpp JEYolrYIXY8tQy9ILATAJwJFrCOw99lvUJ8hgSE+dzfOHb4nZbZKbUskWbktIb6akYJK 1GfcmSZK5+dpo2bFU+EFa989siT73MEkbPyVF2Du/rBkgG31YiTaVspdG1PIBSn47IEp AwUgrHclJf0ovQ5+HgBcgTo8wgVynwNj+MESmI/7YuokcLIHUGOT7U+xHodPUwQ8zmqC R+yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iO2f8HVe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will allow tcg to remove any dead code that might follow an exception. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 2f8bdea22b..820711366d 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,4 +1,4 @@ -DEF_HELPER_2(raise_exception, void, env, i32) +DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_1(debug, void, env) DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) From patchwork Mon Aug 31 16:05:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248769 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3446600ilg; Mon, 31 Aug 2020 09:14:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzzIxrmgTnltyJ8XAh0NT+KxDejjyqqu03/00HzjQEBYKADdHJXyBT095AmMwig7L/WjfFQ X-Received: by 2002:a25:5384:: with SMTP id h126mr3353581ybb.445.1598890447236; Mon, 31 Aug 2020 09:14:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890447; cv=none; d=google.com; s=arc-20160816; b=GPPqtw6P9x5RlBWLuKQs7cAPr6ifgG9UMIjwKu+6rSXCr0/NeisAi4eDcslwjngU/+ 3jDb+pi6VOywXjtrwo/lNTrRfCCi2vGAeagUyir03OSSBHuoiz0SKQHI8XPsF6Oq0upz mP4sSzm2VvRXX1fsnnFHm10SbM1mSggiPUwovnAw4JSV5RVmObp7Y3ZIQ1XXt0qZBmuZ dejmJ9Ms22ZPWGgTc0KoENeI5KlVKXlDKQ9+LLgvFGy0OKjiBc3C/6VjUkFWxEPwliXL kJt/H+C1iphkhO0MojERNEhOhR83x0KoXWuhIYqRjsdLQTrGaHmEilorCQuZMlRFeDeu f5Hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=392OYT6LHbH2eWUoF1akQuoZ1nr82ScpvX4flFh2VTg=; b=N3E0/SPGyDTOjXF5TK5o8yy2x22n0RoUS680pAkETPJEbqi2zsAi00cJZatm0SU4PS 11D5UupRXKCi8sl7aezGrZVogDxtaY87IibxxtYKtIp43zltLNEAWoRHIJyFEsJGPKv6 R0fndynthI0pjMhuVHnrev+aXNgDHtcWrx/VIeuNXoHoxgNsJMhJ9YeNHG+A1fTZNv0F y/uFa4ARIWdqsRfLj+b2WvHp5YhX0Wb/cA2yErNjbOsMiIZKPfX9jUXBvAWP7BQakR6/ VuRYCV1jMeQn5fC82Gm+oY71K8r312bVRoyqmevL6H9YOVR0Sg90bAjKUmw9aiUpzU8S 8HhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QvLWtPYi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f198si8380027yba.96.2020.08.31.09.14.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:14:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QvLWtPYi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmRa-0003Vm-NY for patch@linaro.org; Mon, 31 Aug 2020 12:14:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKL-0004NJ-Tu for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:37 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:35652) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKJ-0005zZ-Tt for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:37 -0400 Received: by mail-pf1-x429.google.com with SMTP id o68so816367pfg.2 for ; Mon, 31 Aug 2020 09:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=392OYT6LHbH2eWUoF1akQuoZ1nr82ScpvX4flFh2VTg=; b=QvLWtPYiDmT/JFY+iWf7kBEhWERphk0tnv7rZxz1sh1y8oYKyAMRbmM43MuLX8FZli ejpBvfklhRwz71cdg9LU0UxnxjKF5slDWRhpiS9+no/PdvxMdIsnY99NsQU5z0t2w90g u3wIYMWh7vKSrPL14mKvlj4lA4ngqwM/uCYj73aTls6vCrmmzqEY3/JlsbRv3MDwjXbz RFvQk7tDCvq1+y8GoweUGJqFReF8m4qd3nurI42NcyrCSPDIlh+jjMfGVwPphtsLuAFW ALOpFx4IYQcdpot5v52fS43dNL+9Ur6YaIcN15OIq6v+EfpCiRzQBnvH9QPbNuu/7LHU SUzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=392OYT6LHbH2eWUoF1akQuoZ1nr82ScpvX4flFh2VTg=; b=klzPCJhRfZ56AZWuRSn0tMtgBP3F1Uk7RgOKQmXAH75sRdHq2QBslvm2KCLnerkoFq 6UqVBIcrMG22C1EMLZztjX1VarFozmYm4fUlrUTXSgwzp3aBji+sdn8HsW+DLifV6oMR f31FnCu+mf1pA4W1978inlPolNWXkKtOADmbjfGfMaz9Em7R4O2Q9E8iiPYYLPl4QzJx /YNPwhHpBr87bBBC6v2hsky+sVsWoC6OkRiqO+Wa0PoTKNMAcslGAhEtY8IR5bbRjbld /xEg1/OceYi3SCYCgWLl8nCmTj6t7rcDZ1dQuNX7yrdUNK7aS/tvmQ9BaaeA7w/tPpJQ p4dQ== X-Gm-Message-State: AOAM531solpkcPg3fBz6mBS7txQJN0WuKT5DEhxRuGlnYApvSG0WT0Yb 5ZOWw9SDBntF9YR9EdCgMnMQdxGKD8tM/Q== X-Received: by 2002:a65:670d:: with SMTP id u13mr1761993pgf.280.1598889993678; Mon, 31 Aug 2020 09:06:33 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/76] target/microblaze: Remove helper_debug and env->debug Date: Mon, 31 Aug 2020 09:05:07 -0700 Message-Id: <20200831160601.833692-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not used, and seems redundant with -d cpu. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 - target/microblaze/helper.h | 1 - target/microblaze/op_helper.c | 23 ----------------------- target/microblaze/translate.c | 16 ++-------------- 4 files changed, 2 insertions(+), 39 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b88acba12b..7708c9a3d3 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -229,7 +229,6 @@ typedef struct CPUMBState CPUMBState; #define STREAM_NONBLOCK (1 << 4) struct CPUMBState { - uint32_t debug; uint32_t btaken; uint32_t btarget; uint32_t bimm; diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 820711366d..9309142f8d 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_1(debug, void, env) DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) DEF_HELPER_2(cmpu, i32, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index dc2bec0c99..d79202c3f8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -71,29 +71,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -void helper_debug(CPUMBState *env) -{ - int i; - - qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%x resr=%x rear=%" PRIx64 " " - "debug[%x] imm=%x iflags=%x\n", - env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags); - qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", - env->btaken, env->btarget, - (env->msr & MSR_UM) ? "user" : "kernel", - (env->msr & MSR_UMS) ? "user" : "kernel", - (bool)(env->msr & MSR_EIP), - (bool)(env->msr & MSR_IE)); - for (i = 0; i < 32; i++) { - qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); - if ((i + 1) % 4 == 0) - qemu_log("\n"); - } - qemu_log("\n\n"); -} - static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) { uint32_t cout = 0; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9a00a78b8a..ecfa6b86a4 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -53,7 +53,6 @@ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ -static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; @@ -1675,13 +1674,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) tcg_gen_insn_start(dc->pc); num_insns++; -#if SIM_COMPAT - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_debug(); - } -#endif - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in @@ -1824,10 +1816,9 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%x rbtr=%x\n", + "imm=%x iflags=%x fsr=%x rbtr=%x\n", env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags, env->fsr, - env->btr); + env->imm, env->iflags, env->fsr, env->btr); qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", @@ -1857,9 +1848,6 @@ void mb_tcg_init(void) { int i; - env_debug = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, debug), - "debug0"); env_iflags = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, iflags), "iflags"); From patchwork Mon Aug 31 16:05:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248774 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3448481ilg; Mon, 31 Aug 2020 09:16:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJww/WtFNd+Rnp+NmyS9duENZQXE4LJS+0MFKck8+W/eVYFrX6KJZVx/pN4uC+2SDRobR7/n X-Received: by 2002:a25:af05:: with SMTP id a5mr3087650ybh.411.1598890590907; Mon, 31 Aug 2020 09:16:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890590; cv=none; d=google.com; s=arc-20160816; b=de8vJxRWmv3XWTKZq8Ihst4wTtz/y70v86Ja/7eYwDm28WPBj8S/yO1APqWllVBrgZ SAj9gsgPhg/u79YgrWy/nWskXiWtn4t5JLdxBDc9rak8r2b9y71VriFavgWzewBGesiw wVJ2uYY9aFR0tvquG7Mu00zRW0GwnqFXalnUNnmuM84BjTT3VYlGU9ShrnJmtb95LMIJ YbrAHa8iiDTsYEzcq5o8YVenv2Ek+Una6bfoxM0NZEhVmUbl9f1BA+LFCIy2VLE5CjHg WNB+FNU/eiXugwWICtNYQmghfIbYZKeauvKljAwCuk4yt1fr7C/u/ZoVM/TMcpt72qmp OKUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FX8jCFtFLdRyMWFPeEfLBpL1wb+Y9mzpfQMTMdMGMF0=; b=WpWCttctSr+MafgY4uiRi7pbmk2FNgjAlNurPk9ewfKzNWLPrHpWSGebeNO/+tjsEb jAtEAFG0orqbnlWo/ldRjJ5jdg47skKqbh+Wl32S3bzap50NVJbQJ5fIUfJZ/+omkcwu KzfmUwjYzstHnn2lcRDURDH13jneXa/hVbeC0tNi+Lai9QXZJhfULf6pFnuQvT5z2OyS 9/roN7wmBq8SqcEGdQ9umIadOhqcD6+vlSK8agxEIHl8muxT3HcP0rAoylcd9s9PN9BZ jI3c+xdTjR5W80jsdYaXbowAra7uJJfyIW0t6qOngeixVu/JpkzE4gq/0eqWGGhIjn1z Mggw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KgVxiYAY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is cpu_imm, cpu_btaken, cpu_iflags, cpu_res_addr and cpu_res_val. It is standard for these file-scope globals to begin with cpu_*. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 54 +++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ecfa6b86a4..9aa63ddcc5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,12 +56,12 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i32 env_imm; -static TCGv_i32 env_btaken; +static TCGv_i32 cpu_imm; +static TCGv_i32 cpu_btaken; static TCGv_i32 cpu_btarget; -static TCGv_i32 env_iflags; -static TCGv env_res_addr; -static TCGv_i32 env_res_val; +static TCGv_i32 cpu_iflags; +static TCGv cpu_res_addr; +static TCGv_i32 cpu_res_val; #include "exec/gen-icount.h" @@ -107,7 +107,7 @@ static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ if (dc->tb_flags != dc->synced_flags) { - tcg_gen_movi_i32(env_iflags, dc->tb_flags); + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); dc->synced_flags = dc->tb_flags; } } @@ -222,10 +222,10 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_i32(env_imm, env_imm, dc->imm); + tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm); else - tcg_gen_movi_i32(env_imm, (int32_t)((int16_t)dc->imm)); - return &env_imm; + tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm)); + return &cpu_imm; } else return &cpu_R[dc->rb]; } @@ -859,7 +859,7 @@ static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); } dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); @@ -869,7 +869,7 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { LOG_DIS("imm %x\n", dc->imm << 16); - tcg_gen_movi_i32(env_imm, (dc->imm << 16)); + tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; } @@ -1040,8 +1040,8 @@ static void dec_load(DisasContext *dc) } if (ex) { - tcg_gen_mov_tl(env_res_addr, addr); - tcg_gen_mov_i32(env_res_val, v); + tcg_gen_mov_tl(cpu_res_addr, addr); + tcg_gen_mov_i32(cpu_res_val, v); } if (dc->rd) { tcg_gen_mov_i32(cpu_R[dc->rd], v); @@ -1103,7 +1103,7 @@ static void dec_store(DisasContext *dc) write_carryi(dc, 1); swx_skip = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, addr, swx_skip); + tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); /* * Compare the value loaded at lwx with current contents of @@ -1111,11 +1111,11 @@ static void dec_store(DisasContext *dc) */ tval = tcg_temp_new_i32(); - tcg_gen_atomic_cmpxchg_i32(tval, addr, env_res_val, + tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val, cpu_R[dc->rd], mem_index, mop); - tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip); + tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); write_carryi(dc, 0); tcg_temp_free_i32(tval); } @@ -1204,7 +1204,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) TCGv_i32 zero = tcg_const_i32(0); tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, - env_btaken, zero, + cpu_btaken, zero, pc_true, pc_false); tcg_temp_free_i32(zero); @@ -1245,7 +1245,7 @@ static void dec_bcc(DisasContext *dc) dc->jmp = JMP_INDIRECT; tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } - eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); + eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } static void dec_br(DisasContext *dc) @@ -1311,7 +1311,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_INDIRECT; if (abs) { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && @@ -1330,7 +1330,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_DIRECT; dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); } else { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } } @@ -1419,7 +1419,7 @@ static void dec_rts(DisasContext *dc) LOG_DIS("rts ir=%x\n", dc->ir); dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } @@ -1722,7 +1722,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) TCGLabel *l1 = gen_new_label(); t_sync_flags(dc); /* Conditional jmp. */ - tcg_gen_brcondi_i32(TCG_COND_NE, env_btaken, 0, l1); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); gen_goto_tb(dc, 1, dc->pc); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); @@ -1848,22 +1848,22 @@ void mb_tcg_init(void) { int i; - env_iflags = tcg_global_mem_new_i32(cpu_env, + cpu_iflags = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, iflags), "iflags"); - env_imm = tcg_global_mem_new_i32(cpu_env, + cpu_imm = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); cpu_btarget = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btarget), "btarget"); - env_btaken = tcg_global_mem_new_i32(cpu_env, + cpu_btaken = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btaken), "btaken"); - env_res_addr = tcg_global_mem_new(cpu_env, + cpu_res_addr = tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); - env_res_val = tcg_global_mem_new_i32(cpu_env, + cpu_res_val = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, res_val), "res_val"); for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { From patchwork Mon Aug 31 16:05:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248768 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3446063ilg; Mon, 31 Aug 2020 09:13:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyYYPZz12BbFjPoi01AFV88mInaNGejiVHEGzT8Xgr6s1XDWyvPQg0LvC1xu6XpOJCDdKWJ X-Received: by 2002:a5b:1c4:: with SMTP id f4mr3230937ybp.48.1598890410631; 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[209.51.188.17]) by mx.google.com with ESMTPS id r32si8885237ybd.365.2020.08.31.09.13.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:13:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LzRSJzg+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmR0-0000sx-30 for patch@linaro.org; Mon, 31 Aug 2020 12:13:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKN-0004Rp-Pk for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:39 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:36781) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKL-000600-Tx for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:39 -0400 Received: by mail-pg1-x544.google.com with SMTP id p37so839657pgl.3 for ; Mon, 31 Aug 2020 09:06:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AL0uzCSfOumwHkpirTGBR8ikbqPuw1vczWQqngjG3N0=; b=LzRSJzg+9xLDiAfHG2MiCqfHY3rfpM7pRsngkZIBkIxLXE1Z13CuRkrmV2R7gYZdaT twX5EQP9nCJVl/VnULtIbP1lwrCTDDY/bzt62WZIi0KyHoiEpdYXkM6Cjyo61CMUmnoX FqpeV6jeIdPOiQi7fuC+rk6sh9I5VCRkXQNrPjaz1jWurnj3b2ILvcuYizkp+45N0X5h ptxbtNNwJ80gZCppo1N5SNEMYjATF7ku3k5k3q1VIF+f3dWM8000CWEnDh58f/s9x7Wz o6hh9+CvW1NxoX5RSZpPp0gWnwSR/E2hkWQnt9El/8l7wAfHZ7TzqDspVWIFhoV3gBnQ P1gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AL0uzCSfOumwHkpirTGBR8ikbqPuw1vczWQqngjG3N0=; b=jsGGUlYFIV0kfGMTEyXIH+IgoAulzaBI/yPdqhCdI7FsXev8sIwAiFamge5zHp5TID 95zdcgxVS/Hu4T5i3VyCk2Sd06wdO2YCJD4/yQ0jkODGYYq8UFfbVgt79Cmgi34Og+cP wkHp4l4KGtTGT3GHeWFr1TFy6Tc0t7pYdXPo6j4cBdZLZCzbh1mQjGm+jNIonjglGCdJ XiLZ7QXMP41hoERS/2Lb9JQLNljscHHXSdVCA3mMAe+xNo3S597a9CXiv1ASIuP2R1JO ggcpAe4PP9Otl25nVetMSvx7/aP3jb+149ZmZwkjj0plD7hcsRDk8H6A+9PaS/2HkkPy 9b/w== X-Gm-Message-State: AOAM531s4BaGEPoEus3+R1m8LLXe3Ljp+FRUSTfmsU5XsG8FL/mS5E/y hvi/8OMVZsmE4THOeXD1xVwnxPlGnvAENQ== X-Received: by 2002:a63:1f42:: with SMTP id q2mr1692764pgm.265.1598889996131; Mon, 31 Aug 2020 09:06:36 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 24/76] target/microblaze: Tidy mb_tcg_init Date: Mon, 31 Aug 2020 09:05:09 -0700 Message-Id: <20200831160601.833692-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All of the tcg globals can be recorded in the same table. Drop the "r" prefix from "rpc" and "rmsr". Obviates the need for regnames[], which was incorrectly not const. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 62 +++++++++++++++-------------------- 1 file changed, 27 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9aa63ddcc5..e709884f2d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -95,14 +95,6 @@ typedef struct DisasContext { int singlestep_enabled; } DisasContext; -static const char *regnames[] = -{ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", -}; - static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1846,36 +1838,36 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) void mb_tcg_init(void) { - int i; +#define R(X) { &cpu_R[X], offsetof(CPUMBState, regs[X]), "r" #X } +#define SP(X) { &cpu_##X, offsetof(CPUMBState, X), #X } - cpu_iflags = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, iflags), - "iflags"); - cpu_imm = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, imm), - "imm"); - cpu_btarget = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, btarget), - "btarget"); - cpu_btaken = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, btaken), - "btaken"); - cpu_res_addr = tcg_global_mem_new(cpu_env, - offsetof(CPUMBState, res_addr), - "res_addr"); - cpu_res_val = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, res_val), - "res_val"); - for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { - cpu_R[i] = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, regs[i]), - regnames[i]); + static const struct { + TCGv_i32 *var; int ofs; char name[8]; + } i32s[] = { + R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), + R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), + R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), + R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), + + SP(pc), + SP(msr), + SP(imm), + SP(iflags), + SP(btaken), + SP(btarget), + SP(res_val), + }; + +#undef R +#undef SP + + for (int i = 0; i < ARRAY_SIZE(i32s); ++i) { + *i32s[i].var = + tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name); } - cpu_pc = - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); - cpu_msr = - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + cpu_res_addr = + tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Mon Aug 31 16:05:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248778 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3450002ilg; Mon, 31 Aug 2020 09:18:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyrKyoSwbEOpGrd5gCKUpQYoiSoWlmWTBpI8Rm7AZ53TfI7ldx6PNh1bTpBFga4gYH60CAO X-Received: by 2002:a5b:30b:: with SMTP id j11mr3432405ybp.483.1598890710332; Mon, 31 Aug 2020 09:18:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890710; cv=none; d=google.com; s=arc-20160816; b=mJtX64JInnKSsff1kFAbWbHKAjN8lo0MoRTzJ+3iATSW5BoDXq3IJ42uOf1++Dzs/l cz9+TjU0TGnk0fcHvstDvyQDr7rz5ecBe21CWEc3Cizt/dTGkhhBYQsQV5shOQhyDGLE jqc3O9VkjmNaYJYy1ze79iCxWrxKmKzki0Uzb4MxRF5CghTt6sDrE+9DxumavliaRJAT AP6/6Z0Zc+u58lC4IJWptcF1J++6qmSJyZw2DctytFsoPI+ZiDVIyFM54wPaMvW8GH0W sYpIBuGMfm0VttmDMPsyvVhrK9CGoCDUqnRX/jVE6/adoQcpoQIxxLT45y/yejAklpom klrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DtzY55Tus/r5J7PSj8eWDw4XOCX5k4lFWrzVagsDTBc=; b=ahRSzBPyWYY7Z9ESr63kLlnOi3S00LZNg+Cr8Z7jOmyFxmbrpOITqqkgjpcRZM06b1 XKMFHB8u8ESI6rowfvN7exdpgLptyTDLo2hfLDgJSWV4ej5cm6VwlPe7A9xiz9sSf6x5 uILvgVyRQ2cOch0MGc37ole4ahNpQa9/Os+gDLbVbDMoaMFeXEU4ScHSUvvA5PCNP5bh berdm1tv+XXHD+5lA4BVppACRYn9qQVlX4yD6Mjcj9hHf5L9mmviCOBgRLcC0wti7iBE VyJjJixE9HVXtRseLo+679o308qrA7+j6Jd7hdw9itaryUjueGvmtEhiRDAIzgeEdyAQ ZjeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="E/72jU4F"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Having the MSR[C] bit separate will improve arithmetic that operates on the carry bit. Having mb_cpu_read_msr() populate MSR[CC] will prevent the carry copy not matching the carry bit. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 19 +++++++- linux-user/elfload.c | 2 +- target/microblaze/cpu.c | 4 +- target/microblaze/gdbstub.c | 4 +- target/microblaze/helper.c | 58 +++++++++++----------- target/microblaze/translate.c | 91 +++++++++++------------------------ 6 files changed, 82 insertions(+), 96 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7708c9a3d3..7066878ac7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -236,7 +236,8 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint32_t pc; - uint32_t msr; + uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ + uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ uint64_t ear; uint32_t esr; uint32_t fsr; @@ -327,6 +328,22 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +static inline uint32_t mb_cpu_read_msr(const CPUMBState *env) +{ + /* Replicate MSR[C] to MSR[CC]. */ + return env->msr | (env->msr_c * (MSR_C | MSR_CC)); +} + +static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) +{ + env->msr_c = (val >> 2) & 1; + /* + * Clear both MSR[C] and MSR[CC] from the saved copy. + * MSR_PVR is not writable and is always clear. + */ + env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR); +} + void mb_tcg_init(void); /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 58b3f4ef4d..04c28cbb9e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1039,7 +1039,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env } (*regs)[pos++] = tswapreg(env->pc); - (*regs)[pos++] = tswapreg(env->msr); + (*regs)[pos++] = tswapreg(mb_cpu_read_msr(env)); (*regs)[pos++] = 0; (*regs)[pos++] = tswapreg(env->ear); (*regs)[pos++] = 0; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 0eac068570..1eabf5cc3f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -121,9 +121,9 @@ static void mb_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ - env->msr = MSR_EE | MSR_IE | MSR_VM | MSR_UM; + mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); #else - env->msr = 0; + mb_cpu_write_msr(env, 0); mmu_init(&env->mmu); env->mmu.c_mmu = 3; env->mmu.c_mmu_tlb_access = 3; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 9cba9d2215..08d6a0e807 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -62,7 +62,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pc; break; case GDB_MSR: - val = env->msr; + val = mb_cpu_read_msr(env); break; case GDB_EAR: val = env->ear; @@ -118,7 +118,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pc = tmp; break; case GDB_MSR: - env->msr = tmp; + mb_cpu_write_msr(env, tmp); break; case GDB_EAR: env->ear = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b2373f6a23..9a95456401 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -112,12 +112,11 @@ void mb_cpu_do_interrupt(CPUState *cs) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; - uint32_t t; + uint32_t t, msr = mb_cpu_read_msr(env); /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); -/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; switch (cs->exception_index) { case EXCP_HW_EXCP: @@ -136,11 +135,12 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->msr & (MSR_VM | MSR_UM)) << 1; - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |= t; + t = (msr & (MSR_VM | MSR_UM)) << 1; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; /* Exception in progress. */ - env->msr |= MSR_EIP; + msr |= MSR_EIP; + mb_cpu_write_msr(env, msr); qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%x ear=%" PRIx64 " " @@ -178,11 +178,12 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->msr & (MSR_VM | MSR_UM)) << 1; - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |= t; + t = (msr & (MSR_VM | MSR_UM)) << 1; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; /* Exception in progress. */ - env->msr |= MSR_EIP; + msr |= MSR_EIP; + mb_cpu_write_msr(env, msr); qemu_log_mask(CPU_LOG_INT, "exception at pc=%x ear=%" PRIx64 " iflags=%x\n", @@ -193,11 +194,11 @@ void mb_cpu_do_interrupt(CPUState *cs) break; case EXCP_IRQ: - assert(!(env->msr & (MSR_EIP | MSR_BIP))); - assert(env->msr & MSR_IE); + assert(!(msr & (MSR_EIP | MSR_BIP))); + assert(msr & MSR_IE); assert(!(env->iflags & D_FLAG)); - t = (env->msr & (MSR_VM | MSR_UM)) << 1; + t = (msr & (MSR_VM | MSR_UM)) << 1; #if 0 #include "disas/disas.h" @@ -212,21 +213,20 @@ void mb_cpu_do_interrupt(CPUState *cs) && (!strcmp("netif_rx", sym) || !strcmp("process_backlog", sym))) { - qemu_log( - "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->pc, env->msr, t, env->iflags, - sym); + qemu_log("interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", + env->pc, msr, t, env->iflags, sym); log_cpu_state(cs, 0); } } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%x msr=%x %x iflags=%x\n", - env->pc, env->msr, t, env->iflags); + "interrupt at pc=%x msr=%x %x iflags=%x\n", + env->pc, msr, t, env->iflags); - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); - env->msr |= t; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); + msr |= t; + mb_cpu_write_msr(env, msr); env->regs[14] = env->pc; env->pc = cpu->cfg.base_vectors + 0x10; @@ -237,20 +237,22 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); - t = (env->msr & (MSR_VM | MSR_UM)) << 1; + t = (msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=%x msr=%x %x iflags=%x\n", - env->pc, env->msr, t, env->iflags); + env->pc, msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |= t; - env->msr |= MSR_BIP; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; + msr |= MSR_BIP; if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->pc; - env->msr |= MSR_BIP; + msr |= MSR_BIP; env->pc = cpu->cfg.base_vectors + 0x18; - } else + } else { env->pc = env->btarget; + } + mb_cpu_write_msr(env, msr); break; default: cpu_abort(cs, "unhandled exception type=%d\n", diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e709884f2d..0c9b4ffa5a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,6 +56,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; +static TCGv_i32 cpu_msr_c; static TCGv_i32 cpu_imm; static TCGv_i32 cpu_btaken; static TCGv_i32 cpu_btarget; @@ -150,30 +151,6 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) } } -static void read_carry(DisasContext *dc, TCGv_i32 d) -{ - tcg_gen_shri_i32(d, cpu_msr, 31); -} - -/* - * write_carry sets the carry bits in MSR based on bit 0 of v. - * v[31:1] are ignored. - */ -static void write_carry(DisasContext *dc, TCGv_i32 v) -{ - /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1); - tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1); -} - -static void write_carryi(DisasContext *dc, bool carry) -{ - TCGv_i32 t0 = tcg_temp_new_i32(); - tcg_gen_movi_i32(t0, carry); - write_carry(dc, t0); - tcg_temp_free_i32(t0); -} - /* * Returns true if the insn an illegal operation. * If exceptions are enabled, an exception is raised. @@ -243,11 +220,7 @@ static void dec_add(DisasContext *dc) if (c) { /* c - Add carry into the result. */ - cf = tcg_temp_new_i32(); - - read_carry(dc, cf); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free_i32(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); } } return; @@ -257,21 +230,15 @@ static void dec_add(DisasContext *dc) /* Extract carry. */ cf = tcg_temp_new_i32(); if (c) { - read_carry(dc, cf); + tcg_gen_mov_i32(cf, cpu_msr_c); } else { tcg_gen_movi_i32(cf, 0); } + gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); if (dc->rd) { - TCGv_i32 ncf = tcg_temp_new_i32(); - gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - write_carry(dc, ncf); - tcg_temp_free_i32(ncf); - } else { - gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - write_carry(dc, cf); } tcg_temp_free_i32(cf); } @@ -309,11 +276,7 @@ static void dec_sub(DisasContext *dc) if (c) { /* c - Add carry into the result. */ - cf = tcg_temp_new_i32(); - - read_carry(dc, cf); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free_i32(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); } } return; @@ -324,7 +287,7 @@ static void dec_sub(DisasContext *dc) cf = tcg_temp_new_i32(); na = tcg_temp_new_i32(); if (c) { - read_carry(dc, cf); + tcg_gen_mov_i32(cf, cpu_msr_c); } else { tcg_gen_movi_i32(cf, 1); } @@ -332,16 +295,10 @@ static void dec_sub(DisasContext *dc) /* d = b + ~a + c. carry defaults to 1. */ tcg_gen_not_i32(na, cpu_R[dc->ra]); + gen_helper_carry(cpu_msr_c, na, *(dec_alu_op_b(dc)), cf); if (dc->rd) { - TCGv_i32 ncf = tcg_temp_new_i32(); - gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf); tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - write_carry(dc, ncf); - tcg_temp_free_i32(ncf); - } else { - gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf); - write_carry(dc, cf); } tcg_temp_free_i32(cf); tcg_temp_free_i32(na); @@ -429,16 +386,26 @@ static void dec_xor(DisasContext *dc) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } -static inline void msr_read(DisasContext *dc, TCGv_i32 d) +static void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_mov_i32(d, cpu_msr); + TCGv_i32 t; + + /* Replicate the cpu_msr_c boolean into the proper bit and the copy. */ + t = tcg_temp_new_i32(); + tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC); + tcg_gen_or_i32(d, cpu_msr, t); + tcg_temp_free_i32(t); } -static inline void msr_write(DisasContext *dc, TCGv_i32 v) +static void msr_write(DisasContext *dc, TCGv_i32 v) { dc->cpustate_changed = 1; - /* PVR bit is not writable, and is never set. */ - tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR); + + /* Install MSR_C. */ + tcg_gen_extract_i32(cpu_msr_c, v, 2, 1); + + /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */ + tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } static void dec_msr(DisasContext *dc) @@ -778,8 +745,8 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_i32(t0, cpu_msr, MSR_CC); - write_carry(dc, cpu_R[dc->ra]); + tcg_gen_shli_i32(t0, cpu_msr_c, 31); + tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); @@ -792,8 +759,7 @@ static void dec_bit(DisasContext *dc) /* srl. */ LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); - /* Update carry. Note that write carry only looks at the LSB. */ - write_carry(dc, cpu_R[dc->ra]); + tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { if (op == 0x41) tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); @@ -1042,7 +1008,7 @@ static void dec_load(DisasContext *dc) if (ex) { /* lwx */ /* no support for AXI exclusive so always clear C */ - write_carryi(dc, 0); + tcg_gen_movi_i32(cpu_msr_c, 0); } tcg_temp_free(addr); @@ -1093,7 +1059,7 @@ static void dec_store(DisasContext *dc) /* swx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - write_carryi(dc, 1); + tcg_gen_movi_i32(cpu_msr_c, 1); swx_skip = gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); @@ -1108,7 +1074,7 @@ static void dec_store(DisasContext *dc) mop); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); - write_carryi(dc, 0); + tcg_gen_movi_i32(cpu_msr_c, 0); tcg_temp_free_i32(tval); } @@ -1851,6 +1817,7 @@ void mb_tcg_init(void) SP(pc), SP(msr), + SP(msr_c), SP(imm), SP(iflags), SP(btaken), From patchwork Mon Aug 31 16:05:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248771 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3447132ilg; Mon, 31 Aug 2020 09:14:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsZPO7Pb1EyZPIsUXwDp+F6F61OkFz4wILJmFcxfha4ObKJ1whojBr+4xvn5S3hfs8BOFG X-Received: by 2002:a25:8b89:: with SMTP id j9mr3450603ybl.457.1598890489869; Mon, 31 Aug 2020 09:14:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890489; cv=none; d=google.com; s=arc-20160816; b=oSfAv9OA/vUW79lx6R/S0pjjfJe92j+jWnTZNzOP5r1xKFHihhlGRUn6e1LwaQgE76 0o9XFIoKZi9kEFhidKMBlg6kAYu1YcnPYdQZETA2n/6r5PQEj33vq8HdUWI/efr43IYF XYzOYHcYriRIBc3VC3nJeB8RtratVhOXgumyF7+tKeAhHrof5JqOlUXUZ1TbiJnvwWxl bOyo+Xl1sOhpB9UhXW2D8XUjTJ/vESQW1ZP0UxbQ4dVN2MPnEMf0rYaG/lDl38NAB2Ba Qncl9I1B9NMzqLRoim+6F9t6OCP1kfFkVuVNwjjMGOnNZb04gz0/3JcuBW26gXY/MVwW ofoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uIKhTONsxJcHP4WPV5M1NnbEZDfvPYoEbwvp1GTDwH0=; b=nbpoS9sNDvD7S83T5nEVj1KxcR9PSedDULpdZ2GoO0WALENh8Nn2UScu/DfI8oht3w l9weX0le5KPKhsH4IRnJd9MgM074JoxrQx+FWZgA+ptwG/wSrcParqVqVLz74+H3w94m TA0HTiDBXlsCwjiVQ0ScjJvVKeQujJdxouk2Jk2CIjzdRE/DBGEt78R3cKynW5drQbFN LZMTUqmRilSXwloy6nTHG8yU9D/UM2oxt82Zj/AgAASLlqZZtgTuu+yj5pI3OTNg7IJR 8Tq4+lRaFE1j0zSYwxD9qVWACYvEwTXa9oFUkykf8wLwiv4p6Nz4vxfM8WWi+bJvDlaH vapA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UzXAKX5F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both exceptions and gen_goto_tb do not return. Use the official DISAS_NORETURN enumerator for this case. This eliminates all use of DISAS_TB_JUMP. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0c9b4ffa5a..53ca0bfb38 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -51,7 +51,6 @@ /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ -#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; @@ -111,7 +110,7 @@ static void gen_raise_exception(DisasContext *dc, uint32_t index) gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; } static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) @@ -149,6 +148,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } + dc->is_jmp = DISAS_NORETURN; } /* @@ -1675,7 +1675,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); gen_goto_tb(dc, 0, dc->jmp_pc); - dc->is_jmp = DISAS_TB_JUMP; } else if (dc->jmp == JMP_DIRECT_CC) { TCGLabel *l1 = gen_new_label(); t_sync_flags(dc); @@ -1684,8 +1683,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) gen_goto_tb(dc, 1, dc->pc); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); - - dc->is_jmp = DISAS_TB_JUMP; } break; } @@ -1717,7 +1714,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } t_sync_flags(dc); - if (unlikely(cs->singlestep_enabled)) { + if (dc->is_jmp == DISAS_NORETURN) { + /* nothing more to generate */ + } else if (unlikely(cs->singlestep_enabled)) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { @@ -1730,16 +1729,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) case DISAS_NEXT: gen_goto_tb(dc, 1, npc); break; - default: case DISAS_JUMP: case DISAS_UPDATE: /* indicate that the hash table must be used to find the next TB */ tcg_gen_exit_tb(NULL, 0); break; - case DISAS_TB_JUMP: - /* nothing more to generate */ - break; + default: + g_assert_not_reached(); } } gen_tb_end(tb, num_insns); From patchwork Mon Aug 31 16:05:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248782 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3451264ilg; Mon, 31 Aug 2020 09:20:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzH8NCOoI/IA7by7tBY83/xnsD/vuTiuvjQgKmkss/cvBOgQYtg6Tu6gF4n5SzTHSzmk0ks X-Received: by 2002:a25:ae43:: with SMTP id g3mr3373472ybe.459.1598890807868; Mon, 31 Aug 2020 09:20:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890807; cv=none; d=google.com; s=arc-20160816; b=UhCvasFAzCpM9ad1WE8A2Mx1+2bc7L7lHtCyC//2Xh5QT+w5DmvZoD+rtwIoq3sWAh p+/pKNB+eG7Ffv2c88mAtdtZyjq7nu9LboWAL+5zvYovLgyyd6v8RU8ICxhWrNMJrRDT bZPGJqhYSUeYtEA0lpsWJ4A8l7cs0bDO8OmozsOUr3QAZS3PIqaqFB4/j9o7FRQjoiaa bGWQ40QgMF2ijK4MmlmoYigBxj62XeteLvswzT96shHvA4dLkZsE20V5HrcyUdR1XwxY t8uqO0cpvhnpqA/jr305CP+eLYDH2gnUUEBSzMF9yooMbj1qgQ4wQsynDyMvgkHPu8l9 QKJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eBuYjOca47LEZmSV1uuh9RJRYYiGMfYcTJpeBHPz1GU=; b=X23TFGBv0PdxX7xvlOOcBsGjxy2I3YXvvlTeVOGScWB3tCYPnF9I0e9AFmiU5aGP27 xDduYEvTFNCEIZgFHo2KFpausj5bTBg45Wgy+t6BHtp9sePREwm+qoUnA//xgNRpKQFL AAE0JuWofsGstPG1PNsH4XciQla1WOTidpuS2S4J/ZoGNe5CrxgbhQxN6nZdX5dwE+pb RCGTPheP/jGCYMmxH+MaaO2AYG30UKh4yVXhjCp0zpdDBzbUHz5SWhhdw5woSVBbdW05 CVo8RXQwqPgUxqQ7a8k+MI/kP9V5ylhdYaXRroD072wBEspzAcp1ga/sGvn7fgU1EzgB s0Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zkkg6TU0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not use goto_tb if we're single-stepping. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 53ca0bfb38..2e753fa621 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -140,7 +140,12 @@ static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { - if (use_goto_tb(dc, dest)) { + if (dc->singlestep_enabled) { + TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); + tcg_gen_movi_i32(cpu_pc, dest); + gen_helper_raise_exception(cpu_env, tmp); + tcg_temp_free_i32(tmp); + } else if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); From patchwork Mon Aug 31 16:05:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248776 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3449415ilg; Mon, 31 Aug 2020 09:17:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz/01jHGxTwBtAwgkBaCKbWhpcxY6AbvwjC27Vg6DpYIzWmYIbdNq2ZXE3tWhN5f3u6MQeJ X-Received: by 2002:a25:e80e:: with SMTP id k14mr3669049ybd.16.1598890663323; Mon, 31 Aug 2020 09:17:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890663; cv=none; d=google.com; s=arc-20160816; b=twgK4DsApRBYQ/27qXt4Jt7fLw/LkKE+5yOxd/KUB5kCyVqSpOsTjqbqq0J6SDl+Mc d+KL0mMRIMuO4pC8DKMdZ1bpXTftB/Y+z/T5oOOsCBkfwngbtylRd0Yfye+3onr5MV03 wld/zCwnXHPfHvMcso7YgXiRWalSScd2IbzjG6vd89XjvOsjLAMtkWTmOC+zDvovlPSN ypiTpF++/gnYg/Sx6Sac8ml2XlrAi4sD1nOAAHMJ9N6rm4yE3673auFaeI+oN64lo2Mj PIFqp//3kaMGiWKW9BYEK5uYRhESJ+/BYPtTfkSiHeTQmwE8vZV+HqlMJTlO0P/bC+vN pbfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TUaCG/37x9/qPmniyRnuUw2LNh2fo7hqPxFHr142yyg=; b=iCJC76s/7Ru7zLK5Fd8qxqX0hg3mOPJSxXYCVmlrzh916zy6SDtl9lDExhkxRxi9Pq wtZSndwsdF7M4HIryezuHHo76vf3yeD8/BLyOuV+nYuGoxQpUxD4b1O0iJZ4hzhqVqAH 5zbLyg6nrc2n7IZyUGFenc119BPbtXRK+O79OTyB1SyHd+zIFi2M030Ahth6BUChcLOy ivvBiNya6UQwyz4yu3Ht0ObzwL7T9S8OpfkhGv7e+SckHLY5MdPs2LHw+t4Dc+WYuR69 IlvU+FGnlrfILvDXa/YPS49bZG0EwmZvjrYnvTOBT+LHplMaSRu2A5Kaa8HmEqJ6ajt5 SAXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jf4eNezL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Part one of conversion to the generic translator_loop is to use the DisasContextBase and the members therein. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 102 +++++++++++++++++----------------- 1 file changed, 51 insertions(+), 51 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2e753fa621..45b1555f85 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -67,8 +67,8 @@ static TCGv_i32 cpu_res_val; /* This is the state at translation time. */ typedef struct DisasContext { + DisasContextBase base; MicroBlazeCPU *cpu; - uint32_t pc; /* Decoder. */ int type_b; @@ -81,7 +81,6 @@ typedef struct DisasContext { unsigned int delayed_branch; unsigned int tb_flags, synced_flags; /* tb dependent flags. */ unsigned int clear_imm; - int is_jmp; #define JMP_NOJMP 0 #define JMP_DIRECT 1 @@ -91,8 +90,6 @@ typedef struct DisasContext { uint32_t jmp_pc; int abort_at_next_insn; - struct TranslationBlock *tb; - int singlestep_enabled; } DisasContext; static inline void t_sync_flags(DisasContext *dc) @@ -110,13 +107,13 @@ static void gen_raise_exception(DisasContext *dc, uint32_t index) gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; } static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) { t_sync_flags(dc); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_raise_exception(dc, index); } @@ -132,7 +129,7 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); + return (dc->base.pc_first & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); #else return true; #endif @@ -140,7 +137,7 @@ static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { - if (dc->singlestep_enabled) { + if (dc->base.singlestep_enabled) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); tcg_gen_movi_i32(cpu_pc, dest); gen_helper_raise_exception(cpu_env, tmp); @@ -148,12 +145,12 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) } else if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb(dc->tb, n); + tcg_gen_exit_tb(dc->base.tb, n); } else { tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; } /* @@ -468,8 +465,8 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); - dc->is_jmp = DISAS_UPDATE; + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); + dc->base.is_jmp = DISAS_UPDATE; return; } @@ -546,7 +543,7 @@ static void dec_msr(DisasContext *dc) switch (sr) { case SR_PC: - tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); break; case SR_MSR: msr_read(dc, cpu_R[dc->rd]); @@ -813,7 +810,7 @@ static void dec_bit(DisasContext *dc) break; default: cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", - dc->pc, op, dc->rd, dc->ra, dc->rb); + (uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->rb); break; } } @@ -994,7 +991,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); tcg_temp_free_i32(t0); @@ -1114,7 +1111,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1201,12 +1198,12 @@ static void dec_bcc(DisasContext *dc) if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - tcg_gen_movi_i32(cpu_btarget, dc->pc + offset); + tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset); dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->pc + offset; + dc->jmp_pc = dc->base.pc_next + offset; } else { dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); } eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } @@ -1250,7 +1247,7 @@ static void dec_br(DisasContext *dc) +offsetof(CPUState, halted)); tcg_temp_free_i32(tmp_1); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); gen_raise_exception(dc, EXCP_HLT); return; @@ -1270,7 +1267,7 @@ static void dec_br(DisasContext *dc) dec_setup_dslot(dc); } if (link && dc->rd) - tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); dc->jmp = JMP_INDIRECT; if (abs) { @@ -1291,10 +1288,10 @@ static void dec_br(DisasContext *dc) } else { if (dec_alu_op_b_is_small_imm(dc)) { dc->jmp = JMP_DIRECT; - dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); + dc->jmp_pc = dc->base.pc_next + (int32_t)((int16_t)dc->imm); } else { tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); } } } @@ -1459,7 +1456,8 @@ static void dec_fpu(DisasContext *dc) qemu_log_mask(LOG_UNIMP, "unimplemented fcmp fpu_insn=%x pc=%x" " opc=%x\n", - fpu_insn, dc->pc, dc->opcode); + fpu_insn, (uint32_t)dc->base.pc_next, + dc->opcode); dc->abort_at_next_insn = 1; break; } @@ -1489,7 +1487,7 @@ static void dec_fpu(DisasContext *dc) default: qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" " opc=%x\n", - fpu_insn, dc->pc, dc->opcode); + fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode); dc->abort_at_next_insn = 1; break; } @@ -1500,7 +1498,8 @@ static void dec_null(DisasContext *dc) if (trap_illegal(dc, true)) { return; } - qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode); + qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", + (uint32_t)dc->base.pc_next, dc->opcode); dc->abort_at_next_insn = 1; } @@ -1610,19 +1609,20 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) pc_start = tb->pc; dc->cpu = cpu; - dc->tb = tb; org_flags = dc->synced_flags = dc->tb_flags = tb->flags; - dc->is_jmp = DISAS_NEXT; dc->jmp = 0; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); if (dc->delayed_branch) { dc->jmp = JMP_INDIRECT; } - dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->base.pc_first = pc_start; + dc->base.pc_next = pc_start; + dc->base.singlestep_enabled = cs->singlestep_enabled; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; + dc->base.is_jmp = DISAS_NEXT; + dc->base.tb = tb; if (pc_start & 3) { cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); @@ -1634,31 +1634,31 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) gen_tb_start(tb); do { - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->base.pc_next); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - dc->pc += 4; + dc->base.pc_next += 4; break; } /* Pretty disas. */ - LOG_DIS("%8.8x:\t", dc->pc); + LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next); if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } dc->clear_imm = 1; - decode(dc, cpu_ldl_code(env, dc->pc)); + decode(dc, cpu_ldl_code(env, dc->base.pc_next)); if (dc->clear_imm) dc->tb_flags &= ~IMM_FLAG; - dc->pc += 4; + dc->base.pc_next += 4; if (dc->delayed_branch) { dc->delayed_branch--; @@ -1673,10 +1673,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) dc->tb_flags &= ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp == JMP_INDIRECT) { - TCGv_i32 tmp_pc = tcg_const_i32(dc->pc); + TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); eval_cond_jmp(dc, cpu_btarget, tmp_pc); tcg_temp_free_i32(tmp_pc); - dc->is_jmp = DISAS_JUMP; + dc->base.is_jmp = DISAS_JUMP; } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); gen_goto_tb(dc, 0, dc->jmp_pc); @@ -1685,26 +1685,26 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) t_sync_flags(dc); /* Conditional jmp. */ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); - gen_goto_tb(dc, 1, dc->pc); + gen_goto_tb(dc, 1, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); } break; } } - if (cs->singlestep_enabled) { + if (dc->base.singlestep_enabled) { break; } - } while (!dc->is_jmp && !dc->cpustate_changed + } while (!dc->base.is_jmp && !dc->cpustate_changed && !tcg_op_buf_full() && !singlestep - && (dc->pc - page_start < TARGET_PAGE_SIZE) + && (dc->base.pc_next - page_start < TARGET_PAGE_SIZE) && num_insns < max_insns); - npc = dc->pc; + npc = dc->base.pc_next; if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { - dc->is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_UPDATE; tcg_gen_movi_i32(cpu_pc, npc); sync_jmpstate(dc); } else @@ -1712,25 +1712,25 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } /* Force an update if the per-tb cpu state has changed. */ - if (dc->is_jmp == DISAS_NEXT + if (dc->base.is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { - dc->is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_UPDATE; tcg_gen_movi_i32(cpu_pc, npc); } t_sync_flags(dc); - if (dc->is_jmp == DISAS_NORETURN) { + if (dc->base.is_jmp == DISAS_NORETURN) { /* nothing more to generate */ } else if (unlikely(cs->singlestep_enabled)) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); - if (dc->is_jmp != DISAS_JUMP) { + if (dc->base.is_jmp != DISAS_JUMP) { tcg_gen_movi_i32(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); } else { - switch(dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, npc); break; @@ -1746,7 +1746,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } gen_tb_end(tb, num_insns); - tb->size = dc->pc - pc_start; + tb->size = dc->base.pc_next - pc_start; tb->icount = num_insns; #ifdef DEBUG_DISAS @@ -1755,7 +1755,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) && qemu_log_in_addr_range(pc_start)) { FILE *logfile = qemu_log_lock(); qemu_log("--------------\n"); - log_target_disas(cs, pc_start, dc->pc - pc_start); + log_target_disas(cs, pc_start, dc->base.pc_next - pc_start); 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[209.51.188.17]) by mx.google.com with ESMTPS id f188si7338186ybb.286.2020.08.31.09.19.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:19:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jMOVuMS4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmWu-00057i-EQ for patch@linaro.org; Mon, 31 Aug 2020 12:19:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKW-0004fT-TU for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:48 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:54423) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKS-00060r-Sh for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:48 -0400 Received: by mail-pj1-x102e.google.com with SMTP id mm21so22826pjb.4 for ; Mon, 31 Aug 2020 09:06:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h8ixAKf5iBBm6uV3Q0Hu5wc/Ce959qgsl6yMfOofqSw=; b=jMOVuMS4/GlAgCquzd5DzaEEW+fElE5ujf7k58+e/DWxuzTN3RMcFg62fkZi5n57lR 9L5eA5axFf1Lgu5i9qOiXRe9z1BY9QETHl/xn3FRcFrRJW5Y7BgCRmF/Fy1lhruh0sKk bUyV9faKxqva58Kk8Q3Y20tcqoPQoGA1+iViwf4kmol0zcVDvofBnzIBN3nmMM2CTqQH 5GOrEi+bTpDGRG8JIZaJvX17Etbu7s1gP+vFHeBdaPpxzZtOs9JjxdFcVZdt5zJ94YGi +QpatJuF1B1y+fBhguwRSHY5czAtSPWTX6jJ4QpGadvP06ceG2JbK5U+SHWAQfvnfLwr n/Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h8ixAKf5iBBm6uV3Q0Hu5wc/Ce959qgsl6yMfOofqSw=; b=VX3Yu1uq6e33SEtvy9XsVkjx6WlyXZaFKB3a3Siv+GdjKNs0fsthAGo68i5mwvuV8N cAPN/YIadQ9nqHBizhLn/L2oiXjc5+25TntCo4NWMu42fg+W/LYFyv8rpdLuRlr2z5WO yQN9JWjhOTC+3SNWGeZjBzaga7QPqH9q/Wf9UpCjb+qz34cAS58IqfvnKYjV815vGNXe rYPgFXzKbyFApNFxeM4voDWzpMWvBeYrVYhgPNKGMKtTFIiWShfDRSh97T4yICpVa3t/ B30beCrMeplxzTDKTKNyiJmgiT+YHJvNWmicbbehX7LLF17lW3V91tKMkwtUTxrDcLFF swPg== X-Gm-Message-State: AOAM531qWLxj24iHx6zxloBvoYLjJuuJSIXnQ1dQ8Lw6tDx0C7zIuOoG ON3vJVDCIoZsne0LT9CQDZT0AuKL2Gdvjg== X-Received: by 2002:a17:902:d201:: with SMTP id t1mr1591129ply.174.1598890002986; Mon, 31 Aug 2020 09:06:42 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 29/76] target/microblaze: Convert to translator_loop Date: Mon, 31 Aug 2020 09:05:14 -0700 Message-Id: <20200831160601.833692-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Finish the conversion to the generic translator_loop. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 289 ++++++++++++++++++---------------- 1 file changed, 149 insertions(+), 140 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 45b1555f85..6a9710d76d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1595,172 +1595,181 @@ static inline void decode(DisasContext *dc, uint32_t ir) } } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) +static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { - CPUMBState *env = cs->env_ptr; - MicroBlazeCPU *cpu = env_archcpu(env); - uint32_t pc_start; - struct DisasContext ctx; - struct DisasContext *dc = &ctx; - uint32_t page_start, org_flags; - uint32_t npc; - int num_insns; + DisasContext *dc = container_of(dcb, DisasContext, base); + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + int bound; - pc_start = tb->pc; dc->cpu = cpu; - org_flags = dc->synced_flags = dc->tb_flags = tb->flags; - - dc->jmp = 0; + dc->synced_flags = dc->tb_flags = dc->base.tb->flags; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); - if (dc->delayed_branch) { - dc->jmp = JMP_INDIRECT; - } - dc->base.pc_first = pc_start; - dc->base.pc_next = pc_start; - dc->base.singlestep_enabled = cs->singlestep_enabled; + dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; - dc->base.is_jmp = DISAS_NEXT; - dc->base.tb = tb; - if (pc_start & 3) { - cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); + bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + dc->base.max_insns = MIN(dc->base.max_insns, bound); +} + +static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs) +{ +} + +static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) +{ + tcg_gen_insn_start(dcb->pc_next); +} + +static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcb, DisasContext, base); + + gen_raise_exception_sync(dc, EXCP_DEBUG); + + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + dc->base.pc_next += 4; + return true; +} + +static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc = container_of(dcb, DisasContext, base); + CPUMBState *env = cs->env_ptr; + + /* TODO: This should raise an exception, not terminate qemu. */ + if (dc->base.pc_next & 3) { + cpu_abort(cs, "Microblaze: unaligned PC=%x\n", + (uint32_t)dc->base.pc_next); } - page_start = pc_start & TARGET_PAGE_MASK; - num_insns = 0; + dc->clear_imm = 1; + decode(dc, cpu_ldl_code(env, dc->base.pc_next)); + if (dc->clear_imm) { + dc->tb_flags &= ~IMM_FLAG; + } + dc->base.pc_next += 4; - gen_tb_start(tb); - do - { - tcg_gen_insn_start(dc->base.pc_next); - num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { - gen_raise_exception_sync(dc, EXCP_DEBUG); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next += 4; - break; + if (dc->delayed_branch && --dc->delayed_branch == 0) { + if (dc->tb_flags & DRTI_FLAG) { + do_rti(dc); } - - /* Pretty disas. */ - LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next); - - if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); + if (dc->tb_flags & DRTB_FLAG) { + do_rtb(dc); } - - dc->clear_imm = 1; - decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) - dc->tb_flags &= ~IMM_FLAG; - dc->base.pc_next += 4; - - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - if (dc->tb_flags & DRTI_FLAG) - do_rti(dc); - if (dc->tb_flags & DRTB_FLAG) - do_rtb(dc); - if (dc->tb_flags & DRTE_FLAG) - do_rte(dc); - /* Clear the delay slot flag. */ - dc->tb_flags &= ~D_FLAG; - /* If it is a direct jump, try direct chaining. */ - if (dc->jmp == JMP_INDIRECT) { - TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); - dc->base.is_jmp = DISAS_JUMP; - } else if (dc->jmp == JMP_DIRECT) { - t_sync_flags(dc); - gen_goto_tb(dc, 0, dc->jmp_pc); - } else if (dc->jmp == JMP_DIRECT_CC) { - TCGLabel *l1 = gen_new_label(); - t_sync_flags(dc); - /* Conditional jmp. */ - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); - gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); - gen_goto_tb(dc, 0, dc->jmp_pc); - } - break; - } + if (dc->tb_flags & DRTE_FLAG) { + do_rte(dc); } - if (dc->base.singlestep_enabled) { - break; - } - } while (!dc->base.is_jmp && !dc->cpustate_changed - && !tcg_op_buf_full() - && !singlestep - && (dc->base.pc_next - page_start < TARGET_PAGE_SIZE) - && num_insns < max_insns); - - npc = dc->base.pc_next; - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->tb_flags & D_FLAG) { - dc->base.is_jmp = DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); - sync_jmpstate(dc); - } else - npc = dc->jmp_pc; + /* Clear the delay slot flag. */ + dc->tb_flags &= ~D_FLAG; + dc->base.is_jmp = DISAS_JUMP; } - /* Force an update if the per-tb cpu state has changed. */ - if (dc->base.is_jmp == DISAS_NEXT - && (dc->cpustate_changed || org_flags != dc->tb_flags)) { + /* Force an exit if the per-tb cpu state has changed. */ + if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) { dc->base.is_jmp = DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); } - t_sync_flags(dc); +} + +static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc = container_of(dcb, DisasContext, base); + + assert(!dc->abort_at_next_insn); if (dc->base.is_jmp == DISAS_NORETURN) { - /* nothing more to generate */ - } else if (unlikely(cs->singlestep_enabled)) { - TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); - - if (dc->base.is_jmp != DISAS_JUMP) { - tcg_gen_movi_i32(cpu_pc, npc); - } - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - gen_goto_tb(dc, 1, npc); - break; - case DISAS_JUMP: - case DISAS_UPDATE: - /* indicate that the hash table must be used - to find the next TB */ - tcg_gen_exit_tb(NULL, 0); - break; - default: - g_assert_not_reached(); - } + /* We have already exited the TB. */ + return; } - gen_tb_end(tb, num_insns); - tb->size = dc->base.pc_next - pc_start; - tb->icount = num_insns; + t_sync_flags(dc); + if (dc->tb_flags & D_FLAG) { + sync_jmpstate(dc); + dc->jmp = JMP_NOJMP; + } + switch (dc->base.is_jmp) { + case DISAS_TOO_MANY: + assert(dc->jmp == JMP_NOJMP); + gen_goto_tb(dc, 0, dc->base.pc_next); + return; + + case DISAS_UPDATE: + assert(dc->jmp == JMP_NOJMP); + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; + + case DISAS_JUMP: + switch (dc->jmp) { + case JMP_INDIRECT: + { + TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); + eval_cond_jmp(dc, cpu_btarget, tmp_pc); + tcg_temp_free_i32(tmp_pc); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + } + return; + + case JMP_DIRECT_CC: + { + TCGLabel *l1 = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + gen_goto_tb(dc, 1, dc->base.pc_next); + gen_set_label(l1); + } + /* fall through */ + + case JMP_DIRECT: + gen_goto_tb(dc, 0, dc->jmp_pc); + return; + } + /* fall through */ + + default: + g_assert_not_reached(); + } +} + +static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) +{ #ifdef DEBUG_DISAS #if !SIM_COMPAT - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - FILE *logfile = qemu_log_lock(); - qemu_log("--------------\n"); - log_target_disas(cs, pc_start, dc->base.pc_next - pc_start); - qemu_log_unlock(logfile); - } + qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); + log_target_disas(cs, dcb->pc_first, dcb->tb->size); #endif #endif - assert(!dc->abort_at_next_insn); +} + +static const TranslatorOps mb_tr_ops = { + .init_disas_context = mb_tr_init_disas_context, + .tb_start = mb_tr_tb_start, + .insn_start = mb_tr_insn_start, + .breakpoint_check = mb_tr_breakpoint_check, + .translate_insn = mb_tr_translate_insn, + .tb_stop = mb_tr_tb_stop, + .disas_log = mb_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns) +{ + DisasContext dc; + translator_loop(&mb_tr_ops, &dc.base, cpu, tb, max_insns); } void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) From patchwork Mon Aug 31 16:05:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248777 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3450009ilg; Mon, 31 Aug 2020 09:18:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxQr0W2tAwEvX1ry/0wiqz5/Avs2l1o56hoZBhC2scX/DsobKBrMaB3Dqm5y5zqnNah9+y9 X-Received: by 2002:a25:7804:: with SMTP id t4mr3105487ybc.450.1598890710923; Mon, 31 Aug 2020 09:18:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890710; cv=none; d=google.com; s=arc-20160816; b=peqZ3xDOrLMAcTk81ngZtzwZK7/gyRX0o3CEt2fjeUFaTD//PpgSgSaSSSGdTlTUBF Xh1Inrib/lNadTeb7JdHRObbIUdCGg9Won9UuhGRyE7fHk1QXAhsFDeX0vtIFkaTFGOz hI/3RhsF/EEiWzxO9XwkpDf6vJ6bMFwVGpxEduLIOWpIehy9rZRQieuj4iHvPhlVFdYi jIIG1uQ7UC2DV9diP1S6gBXE4xsyMa3OOjCIvnvWC2Leb8tZqiecBAe4AqgmEe8vEwpv 3/RyQbp0fBUA+gzlbFXYEtyKkr1MV6Dtuma6TWeJ0v6z3B971HwMKmSUQ7fZNev+tMfA hZTw== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6a9710d76d..a90e56a17f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -34,10 +34,9 @@ #include "exec/log.h" -#define SIM_COMPAT 0 #define DISAS_GNU 1 #define DISAS_MB 1 -#if DISAS_MB && !SIM_COMPAT +#if DISAS_MB # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) #else # define LOG_DIS(...) do { } while (0) @@ -1749,11 +1748,9 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) { #ifdef DEBUG_DISAS -#if !SIM_COMPAT qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); log_target_disas(cs, dcb->pc_first, dcb->tb->size); #endif -#endif } static const TranslatorOps mb_tr_ops = { From patchwork Mon Aug 31 16:05:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248785 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3452495ilg; Mon, 31 Aug 2020 09:21:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxOBqNY06xP9G4XUcnaB9YclbgkmsnG9qQZrgGXRiag9MUFHrzZAMqJ/mLuSGTVfvNSIcFi X-Received: by 2002:a25:c606:: with SMTP id k6mr3291635ybf.183.1598890900287; Mon, 31 Aug 2020 09:21:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890900; cv=none; d=google.com; s=arc-20160816; b=R8RfjUINqbPoYTy33dcuxGReIdjisFe4S7XnF+HbXxkICxPHnry/A+4EKIW4aoEJV2 wO0i2+R3d/tgsRVTjjqlXaGdOH6qo3uDAagAu92d5D/5NQFxpiEDZxF2XWwZFuheGiZ4 zKvCaqyUsjvmWcB0hZEt7e1HWM696PSonIneE6MWzCcnWwhaFQHWbOjS/9p64IFCBBdX Y7u6e45i3BMHHx18eLGWGnrkGoIeh/YoShGXp+kUmklE7ygi261LFohDvwFhEbHMph0H dEV5ymVLk/kQS6soKEVtxqf4gCPK7opcZw92b+Kvg7Eoh5yG0mTZH05/MMCMuQYPw2Ym y6xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LC4GQajG5DLWT6OieJHaqxMjuNV3BYGqh/KPNTdIZYE=; b=nNi1X8rjmPFaw4lx15sChUhtxXGxFlR2VmT63tnCZGmMN/Mttqk+F2/LMdSNz+A97j S4k//rfj8CPiItLUEBofx5dNla6PbA5aesikGhu9CkGSLvbQjhcKlDIKN3OLOsTKee7B XfzkEr4Dl5z6ptV+ecYTU8SmM98SGzfy3tb+s2qJwj1c6rbRxhh+eYzaC+0AzX40H8eq MdTgOUcLX5A31gSZb3rn5s7kyUi2OtbSVcn78/6CzD8XdlmcDWgc35wfS3P8bCbQC5aW 1bQlY5fAokMTdsEg5y700/YtpcUD34EhZq5HTueL16x5Qwusb8uUHbZsfPLHib+DVs5h 0zdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a20srPZ4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is never used. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 1 - 1 file changed, 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a90e56a17f..6757720776 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -34,7 +34,6 @@ #include "exec/log.h" -#define DISAS_GNU 1 #define DISAS_MB 1 #if DISAS_MB # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) From patchwork Mon Aug 31 16:05:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248786 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3452505ilg; Mon, 31 Aug 2020 09:21:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzToonU5iTclJdOXCE0F/roJHeQc3ystr6oGzW7PeHZ2nDv6lzRT2HTKCAv88Fs/+1fklF/ X-Received: by 2002:a25:8448:: with SMTP id r8mr3230136ybm.119.1598890900798; Mon, 31 Aug 2020 09:21:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890900; cv=none; d=google.com; s=arc-20160816; b=IR05Brpg5fWoiPVFOgf+gCf9c0FLsQA9BCEOwBoY9qj9w90sq+arF78WL5vJmzjE0M AhwaeyaxNsh/yUSmj8sDn2XW7krN5ZVt1cUcVKgylvlpwOWKWC/kndwjoGITTkNkIQrC T647Crw3qFTr05SL3tiYtMq6E2jHnC8beqitGbQoyjfhqX+6LgMLipbPc931algLGbte Zf/D4Z/I8jZJeEEgZF2TRgPDpvjY21e/TfrlRZN86L+FdPTG9Pl8/i9MJCvqbD7pj+pH FalRq7KfC/8CbwrCBzDIOod71+NCxQFb22alP9oG/3u+81NvorTtyIB+lxquczjMVKVZ FhVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8/3WDLS8b0IqACNGFAn6ZPwsL1jv2U3misGXJGmlm9U=; b=P2aV9+AKE/tIel1GKgCDkG2J1uBRtglTxtve7d3JMwJI/f6sTP2ODvkBvQBndrZOCE Y09K/2iEHsrk6C4ik3S3mY+Aj50fvgPodJhqY4UURBeyvOloRhG1m2U9rolF9NRf5Vd3 U+fh6S3rQj+BhDagI/OhuEEH+P2N/mlYQlSPU3jlKGUIbe7ZEom8oBzuinW6x1b9ivT3 Ix+dkescfYL/OgpxWegAoJ0qKm4iSgA5y0jKJrJdQy0dLq8WhPm5G4UxvB/0pF6ba8B4 OdNX28Qc7Ye7IH6HeJ+Z/GoxRGGyFS8ChxWC628glg7BLTKfS8rVnXEyFogVkdyt9Q3J J64g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hMjqixW8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p18si11046676ybc.313.2020.08.31.09.21.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:21:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hMjqixW8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmYu-00005Y-6h for patch@linaro.org; Mon, 31 Aug 2020 12:21:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKY-0004kJ-Tn for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:51 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40493) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKX-00061d-0J for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:50 -0400 Received: by mail-pg1-x541.google.com with SMTP id h12so831243pgm.7 for ; Mon, 31 Aug 2020 09:06:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8/3WDLS8b0IqACNGFAn6ZPwsL1jv2U3misGXJGmlm9U=; b=hMjqixW8wDfqzZh/oashrCrrsp68fpjiMQZgyeyawZUWBq0GA1a+r33mBfmk4z8pqQ u9oR7vLexxWV56ZhLsSsXwDBpv4+wuW2GhP1isW1SheE1rQVsG07vxE6aoyK3yJg7g8P lrRDbNMbk28bUyC4UDpPAdtcxPBejNHw+Fvtrc0x6jeuM2oyNL+eauE+a0mAEG2DpfUv ViwWyy7sVzGKNno46llcwb0O6qyiyptJ3cXftXxZKhIKaVRFUT+tbiqxQey7D41MjvsA vGKevJTS/YHZaCmQ9ubzPB1S7cCif62XHLTuf3sRZrJMQd4OqPpqPRBCBxUgmYHq35Qw J4Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8/3WDLS8b0IqACNGFAn6ZPwsL1jv2U3misGXJGmlm9U=; b=VzLmafOw4VPqyGH2NK+0HlyZsOPOYG30WVvoiwEpOnrnlIa3eGPFZWq1jmOI/CEGu/ DYx9dfRG09Lmcw3UEn/IfKEAIrKRYNrCC8ubqgsN4OELfW2+oc4VBtB64ULcwflHKuum EOvuv6cKOLminQrMG6WnKaKdAT45HemWsN691rp4nssYFZ3+ebskAxrLvDHU99ao6ZrV w38xDzTSexQlnLZkaJtnkpAfOILf5T8rqze04sy9TINMiUhvj48S96nhg2i4PjSjmG62 SNfrCk6Yr8dAWQnIAWEOxneEoGqBXwGWTJ/gwt7JUxC0tvqxohprNz3ANi48D2e4E7Lu 0VAQ== X-Gm-Message-State: AOAM5333dlKneUhGDiAsp2CzrDhbe0/xZduiMQVmTqToJyENoxHWYLx+ eZZ135if/3Gh4+CxUhvh/DDxL0CtZtqh9A== X-Received: by 2002:a62:928d:: with SMTP id o135mr1888007pfd.22.1598890006946; Mon, 31 Aug 2020 09:06:46 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 32/76] target/microblaze: Remove empty D macros Date: Mon, 31 Aug 2020 09:05:17 -0700 Message-Id: <20200831160601.833692-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is never used in op_helper.c and translate.c. There are two trivial uses in helper.c which can be improved by always logging MMU_EXCP to CPU_LOG_INT. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.c | 11 ++++------- target/microblaze/op_helper.c | 2 -- target/microblaze/translate.c | 2 -- 3 files changed, 4 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 9a95456401..f8e2ca12a9 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,8 +24,6 @@ #include "qemu/host-utils.h" #include "exec/log.h" -#define D(x) - #if defined(CONFIG_USER_ONLY) void mb_cpu_do_interrupt(CPUState *cs) @@ -155,10 +153,13 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] = env->pc; + qemu_log_mask(CPU_LOG_INT, + "MMU exception at pc=%x iflags=%x ear=%" PRIx64 "\n", + env->pc, env->iflags, env->ear); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); env->esr |= 1 << 12 ; env->btr = env->btarget; @@ -166,14 +167,10 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[17] -= 4; /* was the branch immprefixed?. */ if (env->bimm) { - qemu_log_mask(CPU_LOG_INT, - "bimm exception at pc=%x iflags=%x\n", - env->pc, env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } } else if (env->iflags & IMM_FLAG) { - D(qemu_log("IMM_FLAG set at exception\n")); env->regs[17] -= 4; } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index d79202c3f8..decdca0fd8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -26,8 +26,6 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" -#define D(x) - void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { int test = ctrl & STREAM_TEST; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6757720776..860859324a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -41,8 +41,6 @@ # define LOG_DIS(...) do { } while (0) #endif -#define D(x) - #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) From patchwork Mon Aug 31 16:05:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248775 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3449336ilg; Mon, 31 Aug 2020 09:17:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzwOrHSVRSw9Q6VlSEkTpJn4GybUzJBw09uDMe5QaqsTWjyhx6owNxCsFN1nbCKp0cF4WkQ X-Received: by 2002:a25:e692:: with SMTP id d140mr3368847ybh.159.1598890657936; Mon, 31 Aug 2020 09:17:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890657; cv=none; d=google.com; s=arc-20160816; b=K924awH3IZ/4qW9wY0oI7Tnrm/o6Cq4IaDSHInEt7+j6JPfWk24KcBiN5bOxufLQY5 uG5aNP89rizME5oMPnQB3bjcd3jG0ubo6iJ3i3B5PMeWlBgAGIhfRv5GYG1LSqCOhn0k 03tz6Y8oegR7tUjx27j4PZ40sYKO2BXbm6ZVtZKlamK2DiQ1XFS0D2VDHjCJiVTWOUg5 BFYJNKZVpMNoj5zbw5uUEXBLWpLaNCoS3a0dWPHMgh5Dij8zTmsV9am0DkZRmVb55bM2 8IfekPq2JF1wisGV4YUuIqJzFzx91aSH9ePvYohiTQby04LzI6a5e+QPtw4WmmRls8W5 e5pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=y+eHAmaw1Ds6wITBRFmUibj1vZ5XgTDmW3pkg4vTY5U=; b=MOaIL00Ajk8aaHUgAwepXLcbe+ihNzEm4NrQyXcQhiwsEAxuG/iN76ZfoMvb8rmETK u7gc7AlO1nJz1fiXmq6IYYOtgBradAaa/9KBdJQxwwEsVrCCRKMEtKsM/ClCT7Lamn1Q kPm6+XpqZJJ3a46XrwcHJqmvDJSv01x4OHC/iw1ypyD79bt6oRfjT7/lsIktypsb+kxT 97Cs8/snMyL5u04TBK30fOVhbmsl9Q0CLeIJcXO59tW3UsJ00XkH9N2GdOeHeuYXawBb GWLZ4Jh8MwCEZUMjtUqsdxNSK8BajpL21KS7Zxpqakn8cKjQ4ena5ZlFHUn4aq8/78ts AW8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BVSrvxe9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also remove the related defines, DISAS_MB and DEBUG_DISAS. Rely on print_insn_microblaze. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 78 +---------------------------------- 1 file changed, 1 insertion(+), 77 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 860859324a..133ec24870 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -33,14 +33,6 @@ #include "trace-tcg.h" #include "exec/log.h" - -#define DISAS_MB 1 -#if DISAS_MB -# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) -#else -# define LOG_DIS(...) do { } while (0) -#endif - #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) @@ -205,10 +197,6 @@ static void dec_add(DisasContext *dc) k = dc->opcode & 4; c = dc->opcode & 2; - LOG_DIS("add%s%s%s r%d r%d r%d\n", - dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "", - dc->rd, dc->ra, dc->rb); - /* Take care of the easy cases first. */ if (k) { /* k - keep carry, no need to update MSR. */ @@ -252,7 +240,6 @@ static void dec_sub(DisasContext *dc) cmp = (dc->imm & 1) && (!dc->type_b) && k; if (cmp) { - LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir); if (dc->rd) { if (u) gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); @@ -262,9 +249,6 @@ static void dec_sub(DisasContext *dc) return; } - LOG_DIS("sub%s%s r%d, r%d r%d\n", - k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb); - /* Take care of the easy cases first. */ if (k) { /* k - keep carry, no need to update MSR. */ @@ -314,19 +298,16 @@ static void dec_pattern(DisasContext *dc) switch (mode) { case 0: /* pcmpbf. */ - LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 2: - LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); } break; case 3: - LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); @@ -349,7 +330,6 @@ static void dec_and(DisasContext *dc) } not = dc->opcode & (1 << 1); - LOG_DIS("and%s\n", not ? "n" : ""); if (!dc->rd) return; @@ -367,7 +347,6 @@ static void dec_or(DisasContext *dc) return; } - LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm); if (dc->rd) tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } @@ -379,7 +358,6 @@ static void dec_xor(DisasContext *dc) return; } - LOG_DIS("xor r%d\n", dc->rd); if (dc->rd) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } @@ -433,9 +411,6 @@ static void dec_msr(DisasContext *dc) if (clrset) { bool clr = extract32(dc->ir, 16, 1); - LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", - dc->rd, dc->imm); - if (!dc->cpu->cfg.use_msr_instr) { /* nop??? */ return; @@ -478,7 +453,6 @@ static void dec_msr(DisasContext *dc) sr &= 7; tmp_sr = tcg_const_i32(sr); - LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); if (to) { gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); } else { @@ -491,7 +465,6 @@ static void dec_msr(DisasContext *dc) #endif if (to) { - LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); switch (sr) { case SR_PC: break; @@ -535,8 +508,6 @@ static void dec_msr(DisasContext *dc) break; } } else { - LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); - switch (sr) { case SR_PC: tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); @@ -609,7 +580,6 @@ static void dec_mul(DisasContext *dc) subcode = dc->imm & 3; if (dc->type_b) { - LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); return; } @@ -622,21 +592,17 @@ static void dec_mul(DisasContext *dc) tmp = tcg_temp_new_i32(); switch (subcode) { case 0: - LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 1: - LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 2: - LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 3: - LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; default: @@ -652,7 +618,6 @@ static void dec_div(DisasContext *dc) unsigned int u; u = dc->imm & 2; - LOG_DIS("div\n"); if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { return; @@ -688,10 +653,6 @@ static void dec_barrel(DisasContext *dc) imm_w = extract32(dc->imm, 6, 5); imm_s = extract32(dc->imm, 0, 5); - LOG_DIS("bs%s%s%s r%d r%d r%d\n", - e ? "e" : "", - s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); - if (e) { if (imm_w + imm_s > 32 || imm_w == 0) { /* These inputs have an undefined behavior. */ @@ -742,7 +703,6 @@ static void dec_bit(DisasContext *dc) /* src. */ t0 = tcg_temp_new_i32(); - LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); tcg_gen_shli_i32(t0, cpu_msr_c, 31); tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { @@ -755,8 +715,6 @@ static void dec_bit(DisasContext *dc) case 0x1: case 0x41: /* srl. */ - LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { if (op == 0x41) @@ -766,11 +724,9 @@ static void dec_bit(DisasContext *dc) } break; case 0x60: - LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra); tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x61: - LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra); tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x64: @@ -778,12 +734,10 @@ static void dec_bit(DisasContext *dc) case 0x74: case 0x76: /* wdc. */ - LOG_DIS("wdc r%d\n", dc->ra); trap_userspace(dc, true); break; case 0x68: /* wic. */ - LOG_DIS("wic r%d\n", dc->ra); trap_userspace(dc, true); break; case 0xe0: @@ -796,12 +750,10 @@ static void dec_bit(DisasContext *dc) break; case 0x1e0: /* swapb */ - LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra); tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x1e2: /*swaph */ - LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra); tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); break; default: @@ -824,7 +776,6 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { - LOG_DIS("imm %x\n", dc->imm << 16); tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; @@ -928,10 +879,6 @@ static void dec_load(DisasContext *dc) return; } - LOG_DIS("l%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", - ex ? "x" : "", - ea ? "ea" : ""); - t_sync_flags(dc); addr = tcg_temp_new(); compute_ldst_addr(dc, ea, addr); @@ -1039,9 +986,6 @@ static void dec_store(DisasContext *dc) trap_userspace(dc, ea); - LOG_DIS("s%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", - ex ? "x" : "", - ea ? "ea" : ""); t_sync_flags(dc); /* If we get a fault on a dslot, the jmpstate better be in sync. */ sync_jmpstate(dc); @@ -1184,7 +1128,6 @@ static void dec_bcc(DisasContext *dc) cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); - LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm); dc->delayed_branch = 1; if (dslot) { @@ -1217,8 +1160,6 @@ static void dec_br(DisasContext *dc) if (mbar == 2 && dc->imm == 4) { uint16_t mbar_imm = dc->rd; - LOG_DIS("mbar %d\n", mbar_imm); - /* Data access memory barrier. */ if ((mbar_imm & 2) == 0) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); @@ -1228,8 +1169,6 @@ static void dec_br(DisasContext *dc) if (mbar_imm & 16) { TCGv_i32 tmp_1; - LOG_DIS("sleep\n"); - if (trap_userspace(dc, true)) { /* Sleep is a privileged instruction. */ return; @@ -1253,11 +1192,6 @@ static void dec_br(DisasContext *dc) return; } - LOG_DIS("br%s%s%s%s imm=%x\n", - abs ? "a" : "", link ? "l" : "", - dc->type_b ? "i" : "", dslot ? "d" : "", - dc->imm); - dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); @@ -1363,16 +1297,12 @@ static void dec_rts(DisasContext *dc) dec_setup_dslot(dc); if (i_bit) { - LOG_DIS("rtid ir=%x\n", dc->ir); dc->tb_flags |= DRTI_FLAG; } else if (b_bit) { - LOG_DIS("rtbd ir=%x\n", dc->ir); dc->tb_flags |= DRTB_FLAG; } else if (e_bit) { - LOG_DIS("rted ir=%x\n", dc->ir); dc->tb_flags |= DRTE_FLAG; - } else - LOG_DIS("rts ir=%x\n", dc->ir); + } dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(cpu_btaken, 1); @@ -1505,9 +1435,6 @@ static void dec_stream(DisasContext *dc) TCGv_i32 t_id, t_ctrl; int ctrl; - LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put", - dc->type_b ? "" : "d", dc->imm); - if (trap_userspace(dc, true)) { return; } @@ -1565,7 +1492,6 @@ static inline void decode(DisasContext *dc, uint32_t ir) int i; dc->ir = ir; - LOG_DIS("%8.8x\t", dc->ir); if (ir == 0) { trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); @@ -1744,10 +1670,8 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) { -#ifdef DEBUG_DISAS qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); log_target_disas(cs, dcb->pc_first, dcb->tb->size); -#endif } static const TranslatorOps mb_tr_ops = { From patchwork Mon Aug 31 16:05:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248789 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3453512ilg; Mon, 31 Aug 2020 09:22:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzCIq7NeZJeZRb3Mf2ZRY4Iw+Xmb2ifXAWVdsgjD35ZNW+prxFet3RIctBh5NMWX26pLUTQ X-Received: by 2002:a25:aa84:: with SMTP id t4mr2974199ybi.493.1598890979111; Mon, 31 Aug 2020 09:22:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890979; cv=none; d=google.com; s=arc-20160816; b=SlhpCqwqQgDtNsNeEhEDZS0RN/KIlgjc3YjPIVvx91+zgYNrA6AHpuFi54oh5dPL1N XcED1CsADfnZe/QV/el64mfnl/kC1yWT2djCxsDsvH0UZluo/pYNdFm/16QLxRvu10+u 2RcYZO8oS30wg4e6EctincCEE/zQJgGpa9QUfdr8Kd//WgpKxVfy/YKy9PmzkBwWZqmt JcV1nsVjnYLYc0x8O9vtOYy4QPvm4pMvPMtLW/fkl550xN+68PdqcY/x1PZzFaREKZwl VN6lxCEpJd4NZhsAgppAh5KK/Iui4TiW1HPwIjdPwrDyvViHa6GlFBpIgfxfPf43EDbm yFvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DDk0bD1wuoNSUreN9eTM7AkDLzVuLK9UdGTmJ9+LUls=; b=XMDkUEMvVdBVD5QWYq5u50tPJMPLD8qKgotIzVp8xgOicEMVoYh3GJRsD5n+sqWhOv QVSP7mQ89amJ5HHiE0eBgJhOZJRcA5n3L8PaPx5ocZbX8uyzlpNIshQgOXJ06lIf3VAw riZZwbM+F+xCDKeI0IGLVdkXWU1NDILHexXXCrRRvqxZnfACMUvUm0lwWXfYk2KEsIp4 ZIbnmfCRpFA9HpqNUNzRgRkCAN6KN0CxMztEhYgyJtWZbM7V64HV764XcJFnbVbPVZWk AZRrVE3SkBV1a9mv6csCkbK+X8iqQlPok9M0H4AfkpEanZf8IWIzhkCcFN0d/n2RAiP1 6EXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Y1GBuBP/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e8si7920270ybq.133.2020.08.31.09.22.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:22:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Y1GBuBP/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49320 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmaA-0003Rn-IO for patch@linaro.org; Mon, 31 Aug 2020 12:22:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKb-0004qY-LY for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:53 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:39594) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKZ-00062C-Ip for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:53 -0400 Received: by mail-pg1-x52e.google.com with SMTP id v15so833512pgh.6 for ; Mon, 31 Aug 2020 09:06:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DDk0bD1wuoNSUreN9eTM7AkDLzVuLK9UdGTmJ9+LUls=; b=Y1GBuBP/xuhOAwUAv329oFgeSiH7DvMzkYzx6T0sn0nLSryjfboz52fuE29n1SD96x ZQRkh/urqejnsT3Im3thSxEezS/IQO3fsGR2tEqU+p15cK5qFACMiTrRRBkdEQj/c4Gy a7H2M80EDwZJQCaCGSoeSLzYNea8AEc/xlp4HIAS+CmqVqnb/RH+LJsHoGsMCVwf5vnA 8b0hhf512QvxmLIcxpp2f6bUphtwVfdQPA5OeztRkv9ZRwYjgyrMd+knXTaG7DFe+PYG v5VzF4jAA7CRjihq8CuKj+C3Q968oWOSCAK8tk0t8zDo+c5JzUfKbCu+vybOToAm78Kv 45NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DDk0bD1wuoNSUreN9eTM7AkDLzVuLK9UdGTmJ9+LUls=; b=nL3aBDisirbmT19eqHsV62zVGrhmhf0kZFNKfyrAoDF5gzzQotkaRjX1aa6ScHUh0/ 15lI2JytHeDUSVOM7CaVouXB+eXiGYRrssA0kSKA7dAkpxfSPXqV0BSUy9SkhmM+wvvW x4IbRNzBmjvmn5+AKVr+Zyf84BMhCRDaTCpYM49prx07SbtHj16eGdujhJAhBrlKqwvJ swHf4TipjqCtjOekojo/X/FIIIll4qxiNKxfLSwH/MCUTLfLHBZiZLEhTCPRkdmIFtzQ mlIzSJvEacEXbeGn0P2qwc9ergpAw3Ulgc+ATxmT9zOj+TBOi8n5OJm8zROGvO9YZrsf oOKQ== X-Gm-Message-State: AOAM5322I5l3YInCVUV413GIFRYXBLN99UqtoP+uWDWgjfqu5JS0Rrbw xRZI7E/vR1uYR7UXxYNHriaQQrMrw5LEfQ== X-Received: by 2002:a63:b10a:: with SMTP id r10mr1785727pgf.431.1598890009765; Mon, 31 Aug 2020 09:06:49 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 34/76] target/microblaze: Ensure imm constant is always available Date: Mon, 31 Aug 2020 09:05:19 -0700 Message-Id: <20200831160601.833692-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 111 ++++++++++++++++++++-------------- 2 files changed, 67 insertions(+), 46 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7066878ac7..013858b8e0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -374,9 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { *pc = env->pc; - *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & (MSR_UM | MSR_VM | MSR_EE)); + *cs_base = (*flags & IMM_FLAG ? env->imm : 0); } #if !defined(CONFIG_USER_ONLY) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 133ec24870..65ce8f3cd6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -61,6 +61,7 @@ typedef struct DisasContext { /* Decoder. */ int type_b; uint32_t ir; + uint32_t ext_imm; uint8_t opcode; uint8_t rd, ra, rb; uint16_t imm; @@ -169,24 +170,23 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } -/* True if ALU operand b is a small immediate that may deserve - faster treatment. */ -static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) +static int32_t dec_alu_typeb_imm(DisasContext *dc) { - /* Immediate insn without the imm prefix ? */ - return dc->type_b && !(dc->tb_flags & IMM_FLAG); + tcg_debug_assert(dc->type_b); + if (dc->tb_flags & IMM_FLAG) { + return dc->ext_imm | dc->imm; + } else { + return (int16_t)dc->imm; + } } static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { - if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm); - else - tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm)); + tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); return &cpu_imm; - } else - return &cpu_R[dc->rb]; + } + return &cpu_R[dc->rb]; } static void dec_add(DisasContext *dc) @@ -776,14 +776,14 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { - tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); + dc->ext_imm = dc->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; } static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) { - bool extimm = dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ bool stackprot = false; TCGv_i32 t32; @@ -836,11 +836,7 @@ static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) } /* Immediate. */ t32 = tcg_temp_new_i32(); - if (!extimm) { - tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm); - } else { - tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); - } + tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); tcg_gen_extu_i32_tl(t, t32); tcg_temp_free_i32(t32); @@ -1134,15 +1130,13 @@ static void dec_bcc(DisasContext *dc) dec_setup_dslot(dc); } - if (dec_alu_op_b_is_small_imm(dc)) { - int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - - tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset); + if (dc->type_b) { dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->base.pc_next + offset; + dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } @@ -1192,38 +1186,63 @@ static void dec_br(DisasContext *dc) return; } + if (abs && link && !dslot) { + if (dc->type_b) { + /* BRKI */ + uint32_t imm = dec_alu_typeb_imm(dc); + if (trap_userspace(dc, imm != 8 && imm != 0x18)) { + return; + } + } else { + /* BRK */ + if (trap_userspace(dc, true)) { + return; + } + } + } + dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); } - if (link && dc->rd) + if (link && dc->rd) { tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); + } - dc->jmp = JMP_INDIRECT; if (abs) { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); - if (link && !dslot) { - if (!(dc->tb_flags & IMM_FLAG) && - (dc->imm == 8 || dc->imm == 0x18)) { + if (dc->type_b) { + uint32_t dest = dec_alu_typeb_imm(dc); + + dc->jmp = JMP_DIRECT; + dc->jmp_pc = dest; + tcg_gen_movi_i32(cpu_btarget, dest); + if (link && !dslot) { + switch (dest) { + case 8: + case 0x18: + gen_raise_exception_sync(dc, EXCP_BREAK); + break; + case 0: + gen_raise_exception_sync(dc, EXCP_DEBUG); + break; + } + } + } else { + dc->jmp = JMP_INDIRECT; + tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); + if (link && !dslot) { gen_raise_exception_sync(dc, EXCP_BREAK); } - if (dc->imm == 0) { - if (trap_userspace(dc, true)) { - return; - } - gen_raise_exception_sync(dc, EXCP_DEBUG); - } } + } else if (dc->type_b) { + dc->jmp = JMP_DIRECT; + dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { - if (dec_alu_op_b_is_small_imm(dc)) { - dc->jmp = JMP_DIRECT; - dc->jmp_pc = dc->base.pc_next + (int32_t)((int16_t)dc->imm); - } else { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); - } + dc->jmp = JMP_INDIRECT; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } + tcg_gen_movi_i32(cpu_btaken, 1); } static inline void do_rti(DisasContext *dc) @@ -1529,6 +1548,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; + dc->ext_imm = dc->base.tb->cs_base; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1573,8 +1593,9 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->clear_imm = 1; decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) { + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; + tcg_gen_discard_i32(cpu_imm); } dc->base.pc_next += 4; From patchwork Mon Aug 31 16:05:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248790 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3453518ilg; Mon, 31 Aug 2020 09:22:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQt9U4S88oLZg8PWDETrcKVHVnRBPo4ya/X9GTiyfFRgFLvlwz8HYIftv1IQWol0jQbIHy X-Received: by 2002:a25:b44d:: with SMTP id c13mr3149667ybg.375.1598890979458; Mon, 31 Aug 2020 09:22:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890979; cv=none; d=google.com; s=arc-20160816; b=uh+r8mQ1f/CG5GM0GIycHYgDFO/A+xdv+UO3w01hh/V08/wGVGFHfR8KM4AIAACRLO 33Zrg+jo0yf/ti/sgyjcm8XdV9R7DSfrtSF1uJbT/HdxEiHlK4gGp9euytNVtq/3QiqC gY6HRid7hCbl0xpGd5UWnASQ0h7C0l9/LTXkk7CL7eLVXGIzVCZMqbPqb9dw7+1iQzkO MrqOMReoXBoSDG6wPX8cf0+awpU5mcXmdrBJGL5ubq6WIWch2jTwac5OvTnCrW/Y1NXK VkedO6Gx4CthESY/9HAC/70hQ2/C6gPGWKAO6S1xGriJeqO9N68a5OsMSTy1Lpy1zaAC lQrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4WVvMqAD78oNbWSebHTpYzLYCLnpF5xHe/3shPVHdfE=; b=cZWoVNhzkFzf+0L2wSePZZOIvJznVeUgA84SdCBJ5uRyg6uE0Y+JP6bb40nu/KFff1 OG61gbVkHThmnK5jUUaXAFkoQUCsS/RQhRA8bC+LEAv4ERJS4J/8L/zLE9VDeOc5eqwD mLDqkl1I8pWGB/WA1SUQ/+11CqZZ3xLWADGFtj/8ZD6Sm0eC6AVYV49Ec9elGABRRVIQ 9xfsxn9CU5Z+7wTSxdV+QTdIewyfztnYCov3KXTWatoA1jSouc1AZRTnVD3oXY4BegaX el4lQBb8fOB5ssgqF2VZOBCWS0aW3fkV1q3T9B4L/YvIDCyMRwcNvYnea7Mq8Oi2+NxN JSgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QTHtXdGy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d1si5848401ybe.473.2020.08.31.09.22.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:22:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QTHtXdGy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmaA-0003Rm-R7 for patch@linaro.org; Mon, 31 Aug 2020 12:22:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKc-0004td-TL for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:54 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:33304) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKa-00062K-Pz for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:54 -0400 Received: by mail-pl1-x634.google.com with SMTP id h2so3257164plr.0 for ; Mon, 31 Aug 2020 09:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4WVvMqAD78oNbWSebHTpYzLYCLnpF5xHe/3shPVHdfE=; b=QTHtXdGy2iVUcaumxu4SBJlBPqlteNQpRMWOqRE4TXv1J1YI1IgiFgSYm/HHH1GpG0 3DcoutpxqcEd53DWPc7MnkGHFWNFyDHNCfgtbuFHDUFqA57I++V+NElScpn6JY865yqe yN4fX3y2CUWo9DnaHOrBPD4/d/eUnPD9hDAGrezR0DTCcT7VDG4HxGT1I7UOqzYpCpJd TWxG3CXPX8t5BQLOwv7kbKFzvL17INAmpiUhk4fVewCsZBjKOD3OykimeM0Ea+fduwTV J6yDBBLayK5mbyvddu9V55bV+iprwOcgDL84Q9WFvAxMNrqZwO/H5mpThO1LS2iBX8t9 omyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4WVvMqAD78oNbWSebHTpYzLYCLnpF5xHe/3shPVHdfE=; b=Nx89meKhIlD7AOBtRM6nNEvuHmJBKnrG76GyMwSrMFdoFe/zjC81gBk7x2MG0fjZAG mSkHfPsiKi9m6LFQMCGSyz8Vf22963xhT6o5yCwwPFzeTzo1qfp0LA8JhuUCcV0Zbxk6 eYADAinK412Tp4CSXpu4buFZ/CBu376E79WVoBrBxaritOX/GKuIF9OzkULTHY2lP4BP pp65OyMKbwj8uBM3q1PggPLFmh1GuFSwK7CbA+GeFCfg9Xa1usTCd/4apk5XdgINfEah /5bn72rdrG/pjhGNTtOPpxMSKM53wMo5ErES8SAwHQNgWEnO3Mjvzcm6pswTX8DzZOqZ MMxg== X-Gm-Message-State: AOAM533dLHQ+S927Tmfwsa0AfWWhFVoSQQ8hD++zGalOsbD1m0MCIE5m IqyOcAQA+UmN6TPNC/BgcHIxy9l9avskbg== X-Received: by 2002:a17:90b:4b89:: with SMTP id lr9mr92919pjb.190.1598890010991; Mon, 31 Aug 2020 09:06:50 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 35/76] target/microblaze: Add decodetree infrastructure Date: Mon, 31 Aug 2020 09:05:20 -0700 Message-Id: <20200831160601.833692-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The new interface is a stub that recognizes no instructions. It falls back to the old decoder for all instructions. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 18 ++++++++++++++++++ target/microblaze/translate.c | 11 +++++++++-- target/microblaze/meson.build | 3 +++ 3 files changed, 30 insertions(+), 2 deletions(-) create mode 100644 target/microblaze/insns.decode -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode new file mode 100644 index 0000000000..1ed9ca0731 --- /dev/null +++ b/target/microblaze/insns.decode @@ -0,0 +1,18 @@ +# +# MicroBlaze instruction decode definitions. +# +# Copyright (c) 2020 Richard Henderson +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 65ce8f3cd6..e624093745 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -81,6 +81,9 @@ typedef struct DisasContext { int abort_at_next_insn; } DisasContext; +/* Include the auto-generated decoder. */ +#include "decode-insns.c.inc" + static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1506,7 +1509,7 @@ static struct decoder_info { {{0, 0}, dec_null} }; -static inline void decode(DisasContext *dc, uint32_t ir) +static void old_decode(DisasContext *dc, uint32_t ir) { int i; @@ -1584,6 +1587,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); CPUMBState *env = cs->env_ptr; + uint32_t ir; /* TODO: This should raise an exception, not terminate qemu. */ if (dc->base.pc_next & 3) { @@ -1592,7 +1596,10 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) } dc->clear_imm = 1; - decode(dc, cpu_ldl_code(env, dc->base.pc_next)); + ir = cpu_ldl_code(env, dc->base.pc_next); + if (!decode(dc, ir)) { + old_decode(dc, ir); + } if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; tcg_gen_discard_i32(cpu_imm); diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index b8fe4afe61..639c3f73a8 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -1,4 +1,7 @@ +gen = decodetree.process('insns.decode') + microblaze_ss = ss.source_set() +microblaze_ss.add(gen) microblaze_ss.add(files( 'cpu.c', 'gdbstub.c', From patchwork Mon Aug 31 16:05:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248779 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3450528ilg; Mon, 31 Aug 2020 09:19:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzdrCRS9gJaDSbXWEiram/NNWd4ZUhI8caJOoQ5G2LJnqxDaeDDJChVt6NdztqwVF0TE+AP X-Received: by 2002:a25:5056:: with SMTP id e83mr3565502ybb.352.1598890752298; Mon, 31 Aug 2020 09:19:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890752; cv=none; d=google.com; s=arc-20160816; b=XED3/cHgXAZC6GzHSUCJYXHqI7v3YtT3bQegm6qmHbAeiLfGhdjryXCVeZBIRcRVBn C3lmPavLExoTQpov2Ql5dSXoKmeWsXBe2ro9v6cjXAK4wRkHfWtE2/HX+zUzLjue8Jrm 2nLfd+zVdHdnMLv/l6++8RLlICOPRKZYo5gJw3XgHpuISE14gprZQJYgDKnK+2cx2Xqq Cp228WcNVZD6czpyDvNrE8NmAenWZdERHdSMBWMM9w4W6G1A8LQahWBfXa5zN16nhZBX t0VsXfmF00KG/6G+aM8xgmVW6kF/zBq8e1kLAaWfF6udg9VOQa+zcf+BceJBxVdU6wJ/ nXdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VmZy4CC4Agx9NCtoKuwwK/fciLRRLjW+EqgcQ2NqDr4=; b=uvo367jOJDmoB5fKfPmkm7uU590nCKhXlbhjZqGx3qUNXnV1aA5I/mmPbT2Ct/prBF cQ+IWtCJgUDiEoAmobqIB1SyojpbwO9r3k5ev6B663ylY6mgC7zqKdMut4uDDO1Ibzmo sxzJO3BdVB5dX0xs5WslxsJ/BeABAFWVXyf2vVNNfp5ajndmJWAftelYdAKo6o0JGVIq McTWj/Hk4nSqReMi+3/xCAq/QVfIWXWGG4c3fGaLjzNO5/igDXBdC7xU+B6F+cCGRHBs CX7UpIMxZT4+Qn1Sz5YZNqP0uHIOKr3htQoDUguWwE/ZYwoi6FkWWClo4I4VaDbgHaP4 r0rQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=E449g7d+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Adds infrastrucure for translation of instructions, which could not be added before their first use. Cache a temporary which represents r0 as the immediate 0 value, or a sink. Move the special case of opcode_0_illegal from old_decode() into decodetree as well, lest this get interpreted as add. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 24 ++++ target/microblaze/translate.c | 197 ++++++++++++++++++++++++++------- 2 files changed, 178 insertions(+), 43 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 1ed9ca0731..5f289a446c 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -16,3 +16,27 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +&typea rd ra rb +&typeb rd ra imm + +# Include any IMM prefix in the value reported. +%extimm 0:s16 !function=typeb_imm + +@typea ...... rd:5 ra:5 rb:5 ... .... .... &typea +@typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm + +### + +{ + zero 000000 00000 00000 00000 000 0000 0000 + add 000000 ..... ..... ..... 000 0000 0000 @typea +} +addc 000010 ..... ..... ..... 000 0000 0000 @typea +addk 000100 ..... ..... ..... 000 0000 0000 @typea +addkc 000110 ..... ..... ..... 000 0000 0000 @typea + +addi 001000 ..... ..... ................ @typeb +addic 001010 ..... ..... ................ @typeb +addik 001100 ..... ..... ................ @typeb +addikc 001110 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e624093745..de822bd7b7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; + TCGv_i32 r0; + bool r0_set; + /* Decoder. */ int type_b; uint32_t ir; @@ -81,6 +84,14 @@ typedef struct DisasContext { int abort_at_next_insn; } DisasContext; +static int typeb_imm(DisasContext *dc, int x) +{ + if (dc->tb_flags & IMM_FLAG) { + return deposit32(dc->ext_imm, 0, 16, x); + } + return x; +} + /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -176,11 +187,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) static int32_t dec_alu_typeb_imm(DisasContext *dc) { tcg_debug_assert(dc->type_b); - if (dc->tb_flags & IMM_FLAG) { - return dc->ext_imm | dc->imm; - } else { - return (int16_t)dc->imm; - } + return typeb_imm(dc, (int16_t)dc->imm); } static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) @@ -192,44 +199,146 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) return &cpu_R[dc->rb]; } -static void dec_add(DisasContext *dc) +static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { - unsigned int k, c; - TCGv_i32 cf; - - k = dc->opcode & 4; - c = dc->opcode & 2; - - /* Take care of the easy cases first. */ - if (k) { - /* k - keep carry, no need to update MSR. */ - /* If rd == r0, it's a nop. */ - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - - if (c) { - /* c - Add carry into the result. */ - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); - } + if (likely(reg != 0)) { + return cpu_R[reg]; + } + if (!dc->r0_set) { + if (dc->r0 == NULL) { + dc->r0 = tcg_temp_new_i32(); } - return; + tcg_gen_movi_i32(dc->r0, 0); + dc->r0_set = true; + } + return dc->r0; +} + +static TCGv_i32 reg_for_write(DisasContext *dc, int reg) +{ + if (likely(reg != 0)) { + return cpu_R[reg]; + } + if (dc->r0 == NULL) { + dc->r0 = tcg_temp_new_i32(); + } + return dc->r0; +} + +static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, rb; + + if (arg->rd == 0 && !side_effects) { + return true; } - /* From now on, we can assume k is zero. So we need to update MSR. */ - /* Extract carry. */ - cf = tcg_temp_new_i32(); - if (c) { - tcg_gen_mov_i32(cf, cpu_msr_c); - } else { - tcg_gen_movi_i32(cf, 0); + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + rb = reg_for_read(dc, arg->rb); + fn(rd, ra, rb); + return true; +} + +static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects, + void (*fni)(TCGv_i32, TCGv_i32, int32_t)) +{ + TCGv_i32 rd, ra; + + if (arg->rd == 0 && !side_effects) { + return true; } - gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + fni(rd, ra, arg->imm); + return true; +} + +static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, imm; + + if (arg->rd == 0 && !side_effects) { + return true; } - tcg_temp_free_i32(cf); + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + imm = tcg_const_i32(arg->imm); + + fn(rd, ra, imm); + + tcg_temp_free_i32(imm); + return true; +} + +#define DO_TYPEA(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ + { return do_typea(dc, a, SE, FN); } + +#define DO_TYPEBI(NAME, SE, FNI) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_imm(dc, a, SE, FNI); } + +#define DO_TYPEBV(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_val(dc, a, SE, FN); } + +/* No input carry, but output carry. */ +static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + + tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero); + + tcg_temp_free_i32(zero); +} + +/* Input and output carry. */ +static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero); + tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(zero); +} + +/* Input carry, but no output carry. */ +static void gen_addkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_add_i32(out, ina, inb); + tcg_gen_add_i32(out, out, cpu_msr_c); +} + +DO_TYPEA(add, true, gen_add) +DO_TYPEA(addc, true, gen_addc) +DO_TYPEA(addk, false, tcg_gen_add_i32) +DO_TYPEA(addkc, true, gen_addkc) + +DO_TYPEBV(addi, true, gen_add) +DO_TYPEBV(addic, true, gen_addc) +DO_TYPEBI(addik, false, tcg_gen_addi_i32) +DO_TYPEBV(addikc, true, gen_addkc) + +static bool trans_zero(DisasContext *dc, arg_zero *arg) +{ + /* If opcode_0_illegal, trap. */ + if (dc->cpu->cfg.opcode_0_illegal) { + trap_illegal(dc, true); + return true; + } + /* + * Otherwise, this is "add r0, r0, r0". + * Continue to trans_add so that MSR[C] gets cleared. + */ + return false; } static void dec_sub(DisasContext *dc) @@ -1488,7 +1597,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_ADD, dec_add}, {DEC_SUB, dec_sub}, {DEC_AND, dec_and}, {DEC_XOR, dec_xor}, @@ -1515,12 +1623,6 @@ static void old_decode(DisasContext *dc, uint32_t ir) dc->ir = ir; - if (ir == 0) { - trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); - /* Don't decode nop/zero instructions any further. */ - return; - } - /* bit 2 seems to indicate insn type. */ dc->type_b = ir & (1 << 29); @@ -1552,6 +1654,8 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; + dc->r0 = NULL; + dc->r0_set = false; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1600,6 +1704,13 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) if (!decode(dc, ir)) { old_decode(dc, ir); } + + if (dc->r0) { + tcg_temp_free_i32(dc->r0); + dc->r0 = NULL; + dc->r0_set = false; + } + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use tcg_gen_add2_i32 for computing carry. This removes the last use of helper_carry, so remove that. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 1 - target/microblaze/insns.decode | 13 ++++ target/microblaze/op_helper.c | 16 ----- target/microblaze/translate.c | 110 ++++++++++++++++----------------- 4 files changed, 65 insertions(+), 75 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 9309142f8d..988abf7661 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) DEF_HELPER_2(cmpu, i32, i32, i32) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 5f289a446c..a611cc83a7 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -40,3 +40,16 @@ addi 001000 ..... ..... ................ @typeb addic 001010 ..... ..... ................ @typeb addik 001100 ..... ..... ................ @typeb addikc 001110 ..... ..... ................ @typeb + +cmp 000101 ..... ..... ..... 000 0000 0001 @typea +cmpu 000101 ..... ..... ..... 000 0000 0011 @typea + +rsub 000001 ..... ..... ..... 000 0000 0000 @typea +rsubc 000011 ..... ..... ..... 000 0000 0000 @typea +rsubk 000101 ..... ..... ..... 000 0000 0000 @typea +rsubkc 000111 ..... ..... ..... 000 0000 0000 @typea + +rsubi 001001 ..... ..... ................ @typeb +rsubic 001011 ..... ..... ................ @typeb +rsubik 001101 ..... ..... ................ @typeb +rsubikc 001111 ..... ..... ................ @typeb diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index decdca0fd8..9bb6a2ad76 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,17 +69,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) -{ - uint32_t cout = 0; - - if ((b == ~0) && cin) - cout = 1; - else if ((~0 - a) < (b + cin)) - cout = 1; - return cout; -} - uint32_t helper_cmp(uint32_t a, uint32_t b) { uint32_t t; @@ -100,11 +89,6 @@ uint32_t helper_cmpu(uint32_t a, uint32_t b) return t; } -uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) -{ - return compute_carry(a, b, cf); -} - static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { MicroBlazeCPU *cpu = env_archcpu(env); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index de822bd7b7..0e7d24ddca 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -327,6 +327,58 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) +DO_TYPEA(cmp, false, gen_helper_cmp) +DO_TYPEA(cmpu, false, gen_helper_cmpu) + +/* No input carry, but output carry. */ +static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_msr_c, inb, ina); + tcg_gen_sub_i32(out, inb, ina); +} + +/* Input and output carry. */ +static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_not_i32(tmp, ina); + tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero); + tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); + + tcg_temp_free_i32(zero); + tcg_temp_free_i32(tmp); +} + +/* No input or output carry. */ +static void gen_rsubk(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_sub_i32(out, inb, ina); +} + +/* Input carry, no output carry. */ +static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 nota = tcg_temp_new_i32(); + + tcg_gen_not_i32(nota, ina); + tcg_gen_add_i32(out, inb, nota); + tcg_gen_add_i32(out, out, cpu_msr_c); + + tcg_temp_free_i32(nota); +} + +DO_TYPEA(rsub, true, gen_rsub) +DO_TYPEA(rsubc, true, gen_rsubc) +DO_TYPEA(rsubk, false, gen_rsubk) +DO_TYPEA(rsubkc, true, gen_rsubkc) + +DO_TYPEBV(rsubi, true, gen_rsub) +DO_TYPEBV(rsubic, true, gen_rsubc) +DO_TYPEBV(rsubik, false, gen_rsubk) +DO_TYPEBV(rsubikc, true, gen_rsubkc) + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -341,63 +393,6 @@ static bool trans_zero(DisasContext *dc, arg_zero *arg) return false; } -static void dec_sub(DisasContext *dc) -{ - unsigned int u, cmp, k, c; - TCGv_i32 cf, na; - - u = dc->imm & 2; - k = dc->opcode & 4; - c = dc->opcode & 2; - cmp = (dc->imm & 1) && (!dc->type_b) && k; - - if (cmp) { - if (dc->rd) { - if (u) - gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - else - gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - } - return; - } - - /* Take care of the easy cases first. */ - if (k) { - /* k - keep carry, no need to update MSR. */ - /* If rd == r0, it's a nop. */ - if (dc->rd) { - tcg_gen_sub_i32(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); - - if (c) { - /* c - Add carry into the result. */ - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); - } - } - return; - } - - /* From now on, we can assume k is zero. So we need to update MSR. */ - /* Extract carry. And complement a into na. */ - cf = tcg_temp_new_i32(); - na = tcg_temp_new_i32(); - if (c) { - tcg_gen_mov_i32(cf, cpu_msr_c); - } else { - tcg_gen_movi_i32(cf, 1); - } - - /* d = b + ~a + c. carry defaults to 1. */ - tcg_gen_not_i32(na, cpu_R[dc->ra]); - - gen_helper_carry(cpu_msr_c, na, *(dec_alu_op_b(dc)), cf); - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - } - tcg_temp_free_i32(cf); - tcg_temp_free_i32(na); -} - static void dec_pattern(DisasContext *dc) { unsigned int mode; @@ -1597,7 +1592,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_SUB, dec_sub}, {DEC_AND, dec_and}, {DEC_XOR, dec_xor}, {DEC_OR, dec_or}, From patchwork Mon Aug 31 16:05:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248793 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3454131ilg; Mon, 31 Aug 2020 09:23:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxzaApnILCvp3xceZkNFYlMHkYJpmX5Or9NWsrseWlZI4RkQ2nWjJ5B1CL2iIVSgaGga3AY X-Received: by 2002:a25:a383:: with SMTP id e3mr3229995ybi.158.1598891034782; Mon, 31 Aug 2020 09:23:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891034; cv=none; d=google.com; s=arc-20160816; b=k+3tFC/7AJELXyUtTp7sHoHsczSpppgNsWzj9md42xbzjOkdfVHubxsfnwRPkgn0sb WXFb3dRnbNzF2STwr9zhokwna6P0erZT2gttLp99GUYe2mhqH4YwdhJxUE86BnlaFbAR y4dFKWeOTxF+6kqVhe3aqtdLXx52vuDoAwGTjPFKixeLfwc9WBaCQ+OTlwhYFcdDvYvn 3xZFF2xlsxyHbZ+VGotSjZwbIM6yTIVpACO3x3B0gczTe/x/zzIgRtKfFLcX8iF2HsFA mDuyh/w9Q/uNaCkkzEZjRvbPjWBPifzGwS6GiaYATJOOwciegHiEKR3uoNnA/4V3vrWQ wEhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=S6laip3Wpd4WZffve1nLJPULOpaH60wT+1ALfz+5yig=; b=BZXRxGua8k/XAhvlLsfsTDygADjPxgQEaA5J5eVDJvAl4ff8TlaSmXbMJLwHi1n6FV YdNxZ2L0nR+7l3OzOisQlsX3yPFbN7ozJWNXJ8lfFHCxqVTbAKWVSJKXuemX8p8Z1fzw IsdWPwCWLFe8hVAUGEvQTNuXbMhJaBCUh+XHR8Lpqx3QKzutCkZaXIDz0exo8fb6okbs EIQZAjXCPYxIclSTJpJox7uTytc0kGJ+lXoDbX+TDEAAefvxt7ybvXxI+x5TQN10/q8y ToABh8XeFiIPTZQvHetU63fyPUuSUJ4Yu1VQpWEg0qxGzAUGoRjFYLda6rZbpSzQ7O+j TTiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RocHciQO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are simple enough operations; we do not need to call an out-of-line helper. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 -- target/microblaze/op_helper.c | 20 -------------------- target/microblaze/translate.c | 24 ++++++++++++++++++++++-- 3 files changed, 22 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 988abf7661..6f7f96421f 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,6 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_2(cmp, i32, i32, i32) -DEF_HELPER_2(cmpu, i32, i32, i32) DEF_HELPER_3(divs, i32, env, i32, i32) DEF_HELPER_3(divu, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 9bb6a2ad76..f976d112eb 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,26 +69,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -uint32_t helper_cmp(uint32_t a, uint32_t b) -{ - uint32_t t; - - t = b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t = (t & 0x7fffffff) | (b & 0x80000000); - return t; -} - -uint32_t helper_cmpu(uint32_t a, uint32_t b) -{ - uint32_t t; - - t = b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t = (t & 0x7fffffff) | (a & 0x80000000); - return t; -} - static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { MicroBlazeCPU *cpu = env_archcpu(env); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0e7d24ddca..8da477457d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -327,8 +327,28 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) -DO_TYPEA(cmp, false, gen_helper_cmp) -DO_TYPEA(cmpu, false, gen_helper_cmpu) +static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt = tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt = tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +DO_TYPEA(cmp, false, gen_cmp) +DO_TYPEA(cmpu, false, gen_cmpu) /* No input carry, but output carry. */ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) From patchwork Mon Aug 31 16:05:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248784 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3452452ilg; Mon, 31 Aug 2020 09:21:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxwgjgHaU9YoS/E2R14KQVFEAZZUqcQ5o12b6RJrX4Lb7dU3Dp3D8dHCGfJcS2gNORsw5hr X-Received: by 2002:a25:c7cd:: with SMTP id w196mr3024816ybe.351.1598890896435; Mon, 31 Aug 2020 09:21:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890896; cv=none; d=google.com; s=arc-20160816; b=SLxTFp3/HN0XFFjO+kqxugHzHjlvEB9azid2pTIH8xwQ3PU5X6c1yowEsK6r/tcE9Q uk7VtkLTy4+9ualVzJJ/cgL5k4QjO3yuoesWinaTybw/NXCq2QPYs2+vUesEL2j8dAct Hx55mBaVS5Ba4M/nohO+LqkYkJ3vmzhEk33Xa5KVjbTgVyNND/DUko+bScpo8/kC9T+D t5ppO+ySusP+VsMhd9mgWkHj0JVnle7eVZ0cRd6rK/Q3sZDNJokfak/BR5M0aGAjlAcN trdQTWnZMK6/TV5zELbtLdUX0l7z6ReeOvtfC71rrY+BMngokuF+aIgWnOj/aQtL4VjG LblQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=McrdZ6KxrFqHOEaBx6VbvyuikujwerCjRA8qh9K2y7E=; b=W/7FKSlhYFW4FC3CukaBQaq3rCUJJIssweoXOUMp563K36rjXAjxKvzqhkpml6GZ3B tP1dF3bjl51dXKyTUuQchY/iQ4rFEFAV4fuOodO9glv14RTzeESD41qI1vV5+FObMH4T T6eUCoQFnCACXhkaRbqo4VwWlZaiUQtoxZssivjXc273RKDFrZ80x6YYIPt8pth6Exuf Xn1FF0KkiLh35G2yU3vluVE9semx+vIF5I+2Bttyi5ho81QxWRVP3rpFaQ4+1aTJDXve wM36xsIvTVDCkA3XoVK1dMDOgmX0lqY0P46LIM5uh/vutAfsWDzf4YcC4YRqLlaXxhyt 9XHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=F5SxQKa3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 4 ++ target/microblaze/translate.c | 67 +++++++++------------------------- 2 files changed, 22 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index a611cc83a7..16519f05dc 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -44,6 +44,10 @@ addikc 001110 ..... ..... ................ @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea +pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea +pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea + rsub 000001 ..... ..... ..... 000 0000 0000 @typea rsubc 000011 ..... ..... ..... 000 0000 0000 @typea rsubk 000101 ..... ..... ..... 000 0000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8da477457d..7ebf0e1e7d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -279,6 +279,10 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ { return do_typea(dc, a, SE, FN); } +#define DO_TYPEA_CFG(NAME, CFG, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ + { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } + #define DO_TYPEBI(NAME, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } @@ -350,6 +354,20 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); +} + +static void gen_pcmpne(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_NE, out, ina, inb); +} + +DO_TYPEA_CFG(pcmpbf, use_pcmp_instr, false, gen_helper_pcmpbf) +DO_TYPEA_CFG(pcmpeq, use_pcmp_instr, false, gen_pcmpeq) +DO_TYPEA_CFG(pcmpne, use_pcmp_instr, false, gen_pcmpne) + /* No input carry, but output carry. */ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { @@ -413,49 +431,10 @@ static bool trans_zero(DisasContext *dc, arg_zero *arg) return false; } -static void dec_pattern(DisasContext *dc) -{ - unsigned int mode; - - if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { - return; - } - - mode = dc->opcode & 3; - switch (mode) { - case 0: - /* pcmpbf. */ - if (dc->rd) - gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - if (dc->rd) { - tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - } - break; - case 3: - if (dc->rd) { - tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - } - break; - default: - cpu_abort(CPU(dc->cpu), - "unsupported pattern insn opcode=%x\n", dc->opcode); - break; - } -} - static void dec_and(DisasContext *dc) { unsigned int not; - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - not = dc->opcode & (1 << 1); if (!dc->rd) @@ -469,22 +448,12 @@ static void dec_and(DisasContext *dc) static void dec_or(DisasContext *dc) { - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - if (dc->rd) tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } static void dec_xor(DisasContext *dc) { - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - if (dc->rd) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } From patchwork Mon Aug 31 16:05:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248794 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3454382ilg; Mon, 31 Aug 2020 09:24:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyYqPn9S4hpHQUCm/ZL3C7K4op4SMSnjkKmBqXGYn73EnYueGBdHQcWBmQbhKI2+yRwR4aZ X-Received: by 2002:a25:810a:: with SMTP id o10mr3431371ybk.239.1598891058562; Mon, 31 Aug 2020 09:24:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891058; cv=none; d=google.com; s=arc-20160816; b=NqrTAGRSkemJpxE2AY6LNabQCd9IVE/I5AEKNmzyRlVHwnvdRhE3wrfXDdn8FYJnmD 0diTM+1qu3VFnnXc8QYKwzHoVr9/iBQxInCXTwei/8wVnh3n29eA1xEukScPYQYMkrWQ WPgyTQd4r4Q03N4Ijc09gje80vx1Rww3RDmv78lmKeqkL4I1sjVfoshY+GYWZmw0MB+g 6cT9N4onhqoe1uV+nAsuMGF7OT7L4iAnTRclXhQryirnt3WORk3xy/pun5ncaDuEMEcs pIN23ilysR+KSLF/lXL/3nV5I4QxeAMm6iBHDAHxgJVxvuw58VssjU6lKdg+TEYnPBVk 88Gw== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 12 +++++++++ target/microblaze/translate.c | 46 ++++++++++++---------------------- 2 files changed, 28 insertions(+), 30 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 16519f05dc..93bd51c78b 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -41,9 +41,18 @@ addic 001010 ..... ..... ................ @typeb addik 001100 ..... ..... ................ @typeb addikc 001110 ..... ..... ................ @typeb +and 100001 ..... ..... ..... 000 0000 0000 @typea +andi 101001 ..... ..... ................ @typeb + +andn 100011 ..... ..... ..... 000 0000 0000 @typea +andni 101011 ..... ..... ................ @typeb + cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +or 100000 ..... ..... ..... 000 0000 0000 @typea +ori 101000 ..... ..... ................ @typeb + pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea @@ -57,3 +66,6 @@ rsubi 001001 ..... ..... ................ @typeb rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb + +xor 100010 ..... ..... ..... 000 0000 0000 @typea +xori 101010 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7ebf0e1e7d..a143f17e9d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -331,6 +331,16 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) +static void gen_andni(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + tcg_gen_andi_i32(out, ina, ~imm); +} + +DO_TYPEA(and, false, tcg_gen_and_i32) +DO_TYPEBI(andi, false, tcg_gen_andi_i32) +DO_TYPEA(andn, false, tcg_gen_andc_i32) +DO_TYPEBI(andni, false, gen_andni) + static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 lt = tcg_temp_new_i32(); @@ -354,6 +364,9 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +DO_TYPEA(or, false, tcg_gen_or_i32) +DO_TYPEBI(ori, false, tcg_gen_ori_i32) + static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); @@ -417,6 +430,9 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) +DO_TYPEA(xor, false, tcg_gen_xor_i32) +DO_TYPEBI(xori, false, tcg_gen_xori_i32) + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -431,33 +447,6 @@ static bool trans_zero(DisasContext *dc, arg_zero *arg) return false; } -static void dec_and(DisasContext *dc) -{ - unsigned int not; - - not = dc->opcode & (1 << 1); - - if (!dc->rd) - return; - - if (not) { - tcg_gen_andc_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - } else - tcg_gen_and_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - -static void dec_or(DisasContext *dc) -{ - if (dc->rd) - tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - -static void dec_xor(DisasContext *dc) -{ - if (dc->rd) - tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - static void msr_read(DisasContext *dc, TCGv_i32 d) { TCGv_i32 t; @@ -1581,9 +1570,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_AND, dec_and}, - {DEC_XOR, dec_xor}, - {DEC_OR, dec_or}, {DEC_BIT, dec_bit}, {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, From patchwork Mon Aug 31 16:05:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248788 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3453461ilg; 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Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 77 ++++++++++++++-------------------- 2 files changed, 37 insertions(+), 46 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 93bd51c78b..1a2e22e44a 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -50,6 +50,12 @@ andni 101011 ..... ..... ................ @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +mul 010000 ..... ..... ..... 000 0000 0000 @typea +mulh 010000 ..... ..... ..... 000 0000 0001 @typea +mulhu 010000 ..... ..... ..... 000 0000 0011 @typea +mulhsu 010000 ..... ..... ..... 000 0000 0010 @typea +muli 011000 ..... ..... ................ @typeb + or 100000 ..... ..... ..... 000 0000 0000 @typea ori 101000 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a143f17e9d..617e208583 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -287,6 +287,10 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } +#define DO_TYPEBI_CFG(NAME, CFG, SE, FNI) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return dc->cpu->cfg.CFG && do_typeb_imm(dc, a, SE, FNI); } + #define DO_TYPEBV(NAME, SE, FN) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_val(dc, a, SE, FN); } @@ -364,6 +368,33 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_muls2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +static void gen_mulhu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mulu2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +static void gen_mulhsu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mulsu2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +DO_TYPEA_CFG(mul, use_hw_mul, false, tcg_gen_mul_i32) +DO_TYPEA_CFG(mulh, use_hw_mul >= 2, false, gen_mulh) +DO_TYPEA_CFG(mulhu, use_hw_mul >= 2, false, gen_mulhu) +DO_TYPEA_CFG(mulhsu, use_hw_mul >= 2, false, gen_mulhsu) +DO_TYPEBI_CFG(muli, use_hw_mul, false, tcg_gen_muli_i32) + DO_TYPEA(or, false, tcg_gen_or_i32) DO_TYPEBI(ori, false, tcg_gen_ori_i32) @@ -652,51 +683,6 @@ static void dec_msr(DisasContext *dc) } } -/* Multiplier unit. */ -static void dec_mul(DisasContext *dc) -{ - TCGv_i32 tmp; - unsigned int subcode; - - if (trap_illegal(dc, !dc->cpu->cfg.use_hw_mul)) { - return; - } - - subcode = dc->imm & 3; - - if (dc->type_b) { - tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - return; - } - - /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ - if (subcode >= 1 && subcode <= 3 && dc->cpu->cfg.use_hw_mul < 2) { - /* nop??? */ - } - - tmp = tcg_temp_new_i32(); - switch (subcode) { - case 0: - tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 1: - tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 3: - tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - default: - cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); - break; - } - tcg_temp_free_i32(tmp); -} - /* Div unit. */ static void dec_div(DisasContext *dc) { @@ -1579,7 +1565,6 @@ static struct decoder_info { {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_FPU, dec_fpu}, - {DEC_MUL, dec_mul}, {DEC_DIV, dec_div}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, From patchwork Mon Aug 31 16:05:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248792 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3454101ilg; Mon, 31 Aug 2020 09:23:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzzjsgS8KKS0/KQucFnJTYnlgqjWlbWzrLkuK8b2txx1TvBpGafa5ufKOWpBd7rQ9grJkjQ X-Received: by 2002:a25:97c9:: with SMTP id j9mr3542048ybo.420.1598891031489; Mon, 31 Aug 2020 09:23:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891031; cv=none; d=google.com; s=arc-20160816; b=tEZd35ut4GrKwAI6dzJDvCIwtjMSTdVQ9YngwPP2B1XTTzi4rTbg++W8Uw9ryzZc7s KjkoHtX41W846X8NVbIntTxgBSHUQuIyrs6BNbq6MbOdpjSMGg8+7apmd2l9xQG8zZMT W5Sey6nb8Ix4klqsKj9Sm7EfIAIi4daaAm5eCitoKmmwDP/Du3auj4TeIpTNA5nvvd9x C5x0f6PLdfgCmtebxp1oDb9Qb8b14J4GPDGe4S2qy8d38LO9cXqxit7eauay2pDe6YrG yilIAQOWA2RNWjhWhFLLOz87nXHaVbGUDw+1ofetLU8mf3B6awqDvloUYB8rOZcEEW/w +Ugg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rWOc9BwUZsVi//eDSn3YgBVyZRgNAuFh68+VKq4fp/Q=; b=InX30Y5EK146qSju9z9+XwzyJaKEpV4uwpSr1yVzW3rJrYC6pxh4xckCPRYb8q61Xi kTYIP3hqTr034D4QdkKT87Y0XvvmG0/xgx+/YL0SN0bqVWh7gQ2OJzWJuQQUlqk703U4 aT1gBxsVH5CDgL9n1vv8cMfpuIar5uJ/Gu7wFGOfMUm9k9IG4CpnAGg3RyecA6DIVEH1 4kfRKAybUEufHazl91VmI/oEN0bkc4oTMnBP9BQpRj99z3hHwAF8AsZF/9T+4jh98TdJ WfUayGWCyjCku+D2KCdYUMyH1x4SmuHiFNfgjQ/uBZnjJyjS7Cunet9/R9oSmPsYvqjh 7+Kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="LD+/DsM6"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 +++ target/microblaze/translate.c | 35 +++++++++++++--------------------- 2 files changed, 16 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 1a2e22e44a..b2dcbdf784 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -50,6 +50,9 @@ andni 101011 ..... ..... ................ @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +idiv 010010 ..... ..... ..... 000 0000 0000 @typea +idivu 010010 ..... ..... ..... 000 0000 0010 @typea + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 617e208583..9763b9d77c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -368,6 +368,19 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + gen_helper_divs(out, cpu_env, inb, ina); +} + +static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + gen_helper_divu(out, cpu_env, inb, ina); +} + +DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) +DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) + static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp = tcg_temp_new_i32(); @@ -683,27 +696,6 @@ static void dec_msr(DisasContext *dc) } } -/* Div unit. */ -static void dec_div(DisasContext *dc) -{ - unsigned int u; - - u = dc->imm & 2; - - if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { - return; - } - - if (u) - gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), - cpu_R[dc->ra]); - else - gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), - cpu_R[dc->ra]); - if (!dc->rd) - tcg_gen_movi_i32(cpu_R[dc->rd], 0); -} - static void dec_barrel(DisasContext *dc) { TCGv_i32 t0; @@ -1565,7 +1557,6 @@ static struct decoder_info { {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_FPU, dec_fpu}, - {DEC_DIV, dec_div}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} From patchwork Mon Aug 31 16:05:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248783 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3451807ilg; Mon, 31 Aug 2020 09:20:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzccXV6YW2hpGkEFQyUz/2VLCYu7/j2uE92a5VfClcbJn8RR6d0uFLEiaPhFTs4dJScB+6K X-Received: by 2002:a25:b08b:: with SMTP id f11mr3085919ybj.463.1598890847994; Mon, 31 Aug 2020 09:20:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890847; cv=none; d=google.com; s=arc-20160816; b=KYbMskqSYhfX6ymZLcDJvHNmpQAEb1Ilyz+w43aHvg7rNnjGtI4PT8Yl8cy1JVAIuT WQMPjeeRPuUYn29pEm6aAnT0ZPKCpSa89y9PDUv5cdUpv7QBxdns8xHjsGbzSrsKOrma pOyhJ662kL+gb3RT+JBj2lmFTvOCiQa8r1R8K1OKhxxCDURpBIcG3NrwlO/hY0jZq+7m 0VH9tKQ8lcFaMOL+qfQjrPwGf+w8ttsUVkhlhqhHPBU77kyUINc4OEZVG0owZ9PQdipA IcQ02YMUxDpnWGets1Wmvp4y1NRcR06kIeIkPyBlcpbI+PPtDhJvcrcTg/G2ASBI3z7z PR0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MvUJVsNPWoeKhWUV8ldYPjhJGjA7j8IztAPyoO2B77I=; b=ao5vI1B93T2S7Fi2mcf/6ElDV3vwM899nw4AOHLCIiu56DxQsOB68PUnfXyvtEK8Jm lBhPfiB8cLtPJBzgV9GuSFpxeJSSXzRJRQx/ow4QpuvVgDh2X5VNPUOeuLGj0GtYojlU S1KmHuZLA4DonYahKJDuo9ihp3ghZrwypqVCm6QtIrmPpoMsqQQb9HwRFNku2w9Mx5u1 CWfzU8CcBkHamfpQnUpJpQdwBBMZk6VO40/COq/yNWbJ4pKSsTRbqn1PmxK2DDK9LDCw fylec+6gLymG3Ur8upKZmeyBt1P9CUUqLVA2xyEtG6krPvUY8ox9pxltufLC7nCKhuyW KQ6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QWjYyzpk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Restore the correct pc when raising divide-by-zero. Also, the MSR[DZO] bit is sticky -- it is not cleared with a successful divide. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 4 ++-- target/microblaze/op_helper.c | 23 ++++++++++++----------- 2 files changed, 14 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 6f7f96421f..79e1e8ecc7 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,7 +1,7 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_3(divs, i32, env, i32, i32) -DEF_HELPER_3(divu, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_3(fadd, i32, env, i32, i32) DEF_HELPER_3(frsub, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f976d112eb..d99d98051a 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,26 +69,27 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) +static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t ra) { - MicroBlazeCPU *cpu = env_archcpu(env); - - if (b == 0) { + if (unlikely(b == 0)) { env->msr |= MSR_DZ; - if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { + if ((env->msr & MSR_EE) && + env_archcpu(env)->cfg.div_zero_exception) { + CPUState *cs = env_cpu(env); + env->esr = ESR_EC_DIVZERO; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); } - return 0; + return false; } - env->msr &= ~MSR_DZ; - return 1; + return true; } uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(env, a, b)) { + if (!check_divz(env, a, b, GETPC())) { return 0; } return (int32_t)a / (int32_t)b; @@ -96,7 +97,7 @@ uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(env, a, b)) { + if (!check_divz(env, a, b, GETPC())) { return 0; } return a / b; From patchwork Mon Aug 31 16:05:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248797 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3455671ilg; Mon, 31 Aug 2020 09:26:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEcP9i8IrAIY2elXjMThcWx1AofQSo7/LKWWGshlUcOzhVRq5/C50+NsuE22InlXX2fytC X-Received: by 2002:a25:c2c7:: with SMTP id s190mr3302929ybf.161.1598891162829; Mon, 31 Aug 2020 09:26:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891162; cv=none; d=google.com; s=arc-20160816; b=CYyXfG0/onY/Inlt2oJiGVPMrYAP5pQj5kpcgFeVqxUjgojdK/VzR2/ZIvECvoiHKF qwxE1vX+1k2HZe3OPWcRIJ2jOrHnhc4IWsFqN53PKqbZh8Xyx+H1cJu1jvQgXz1C9HCC pZA4SERNSbdspMh0fKHIB1fNSrQpjo6jTjAypxfPTQaEMFytb0oUWF1vVqVGYYFC+PQZ pspXC8r2OCb/ewDMUklgPV6oIVTggN9wE2GjIkDw8VGpDqXHymmTR3oJvyJ7lmfsz7KM VFtY0/6x6zrrmrOqyTj1IMvp4miPRj3q/DrEMp/na3vCCLtcVMPibiiUYm03ITTLsVwU 3+xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=POrx1e7tQeBQnqQjkRXe3vAU3cEgwFbJYpvJaAU7rEQ=; b=fGH5cx4Dlc5jZMZ9cVNTrMKaXhKSo6qaOZSXOaQrR2ZTqN/ATtVWKbh75NI4lejG8v J7Gt+MSBoD56yT6uQ4iXJ7JpM8ZyKiCXUmj5hVDHKjoZ/vdhohxekKDlpRIwVjctu7J/ VE0pv+Od6bx7FdQPWuC2LCBa9r6WLbs9BR1bwsm6T8xbor2u5dI6D+tPlaKdMYNcLRna inbArOB2jzenjmW8HV0mFIRAYV0QGbi5HsmMBT/oiveXFbr8gg4OzLErB8OxAzT4yO8K 52aUi0OF0ZfM9tfaXpjR5y+Anz4PXsB9UoKpmmxZs1d1t+16k3S02Qs3umFmf2JzDQCR HpjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=p5VrgDqr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 +++++ target/microblaze/translate.c | 148 +++++++++++++++++---------------- 2 files changed, 95 insertions(+), 73 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index b2dcbdf784..d265e36044 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -17,6 +17,7 @@ # License along with this library; if not, see . # +&typea0 rd ra &typea rd ra rb &typeb rd ra imm @@ -26,6 +27,9 @@ @typea ...... rd:5 ra:5 rb:5 ... .... .... &typea @typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm +# Officially typea, but with rb==0, which is not used. +@typea0 ...... rd:5 ra:5 ................ &typea0 + ### { @@ -47,6 +51,8 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +clz 100100 ..... ..... 00000 000 1110 0000 @typea0 + cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea @@ -76,5 +82,19 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +sext8 100100 ..... ..... 00000 000 0110 0000 @typea0 +sext16 100100 ..... ..... 00000 000 0110 0001 @typea0 + +sra 100100 ..... ..... 00000 000 0000 0001 @typea0 +src 100100 ..... ..... 00000 000 0010 0001 @typea0 +srl 100100 ..... ..... 00000 000 0100 0001 @typea0 + +swapb 100100 ..... ..... 00000 001 1110 0000 @typea0 +swaph 100100 ..... ..... 00000 001 1110 0010 @typea0 + +# Cache operations have no effect in qemu: discard the arguments. +wdic 100100 00000 ----- ----- -00 -11- 01-0 # wdc +wdic 100100 00000 ----- ----- 000 0110 1000 # wic + xor 100010 ..... ..... ..... 000 0000 0000 @typea xori 101010 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9763b9d77c..2d57f76548 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -241,6 +241,21 @@ static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, return true; } +static bool do_typea0(DisasContext *dc, arg_typea0 *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra; + + if (arg->rd == 0 && !side_effects) { + return true; + } + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + fn(rd, ra); + return true; +} + static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects, void (*fni)(TCGv_i32, TCGv_i32, int32_t)) { @@ -283,6 +298,14 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } +#define DO_TYPEA0(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ + { return do_typea0(dc, a, SE, FN); } + +#define DO_TYPEA0_CFG(NAME, CFG, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ + { return dc->cpu->cfg.CFG && do_typea0(dc, a, SE, FN); } + #define DO_TYPEBI(NAME, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } @@ -345,6 +368,13 @@ DO_TYPEBI(andi, false, tcg_gen_andi_i32) DO_TYPEA(andn, false, tcg_gen_andc_i32) DO_TYPEBI(andni, false, gen_andni) +static void gen_clz(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_clzi_i32(out, ina, 32); +} + +DO_TYPEA0_CFG(clz, use_pcmp_instr, false, gen_clz) + static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 lt = tcg_temp_new_i32(); @@ -474,6 +504,51 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) +DO_TYPEA0(sext8, false, tcg_gen_ext8s_i32) +DO_TYPEA0(sext16, false, tcg_gen_ext16s_i32) + +static void gen_sra(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_sari_i32(out, ina, 1); +} + +static void gen_src(TCGv_i32 out, TCGv_i32 ina) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_mov_i32(tmp, cpu_msr_c); + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_extract2_i32(out, ina, tmp, 1); + + tcg_temp_free_i32(tmp); +} + +static void gen_srl(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_shri_i32(out, ina, 1); +} + +DO_TYPEA0(sra, false, gen_sra) +DO_TYPEA0(src, false, gen_src) +DO_TYPEA0(srl, false, gen_srl) + +static void gen_swaph(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_rotri_i32(out, ina, 16); +} + +DO_TYPEA0(swapb, false, tcg_gen_bswap32_i32) +DO_TYPEA0(swaph, false, gen_swaph) + +static bool trans_wdic(DisasContext *dc, arg_wdic *a) +{ + /* Cache operations are nops: only check for supervisor mode. */ + trap_userspace(dc, true); + return true; +} + DO_TYPEA(xor, false, tcg_gen_xor_i32) DO_TYPEBI(xori, false, tcg_gen_xori_i32) @@ -754,78 +829,6 @@ static void dec_barrel(DisasContext *dc) } } -static void dec_bit(DisasContext *dc) -{ - CPUState *cs = CPU(dc->cpu); - TCGv_i32 t0; - unsigned int op; - - op = dc->ir & ((1 << 9) - 1); - switch (op) { - case 0x21: - /* src. */ - t0 = tcg_temp_new_i32(); - - tcg_gen_shli_i32(t0, cpu_msr_c, 31); - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); - if (dc->rd) { - tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); - } - tcg_temp_free_i32(t0); - break; - - case 0x1: - case 0x41: - /* srl. */ - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); - if (dc->rd) { - if (op == 0x41) - tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - else - tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - } - break; - case 0x60: - tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x61: - tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x64: - case 0x66: - case 0x74: - case 0x76: - /* wdc. */ - trap_userspace(dc, true); - break; - case 0x68: - /* wic. */ - trap_userspace(dc, true); - break; - case 0xe0: - if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { - return; - } - if (dc->cpu->cfg.use_pcmp_instr) { - tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); - } - break; - case 0x1e0: - /* swapb */ - tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x1e2: - /*swaph */ - tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); - break; - default: - cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", - (uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->rb); - break; - } -} - static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { @@ -1548,7 +1551,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BIT, dec_bit}, {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, {DEC_ST, dec_store}, From patchwork Mon Aug 31 16:05:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248798 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3455682ilg; Mon, 31 Aug 2020 09:26:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzZyASSqX8qAxeLLeNvSaHKCCSl4R8NDZkBIHHmshWp3pzNn/ubTf1UF6tnYHyYrEewimvc X-Received: by 2002:a25:3754:: with SMTP id e81mr3378753yba.133.1598891163682; Mon, 31 Aug 2020 09:26:03 -0700 (PDT) ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 ++++++ target/microblaze/translate.c | 125 +++++++++++++++++---------------- 2 files changed, 86 insertions(+), 59 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index d265e36044..4644defbfe 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -30,6 +30,15 @@ # Officially typea, but with rb==0, which is not used. @typea0 ...... rd:5 ra:5 ................ &typea0 +# Officially typeb, but any immediate extension is unused. +@typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb + +# For convenience, extract the two imm_w/imm_s fields, then pack +# them back together as "imm". Doing this makes it easiest to +# match the required zero at bit 5. +%ieimm 6:5 0:5 +@typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=%ieimm + ### { @@ -51,6 +60,17 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +bsrl 010001 ..... ..... ..... 000 0000 0000 @typea +bsra 010001 ..... ..... ..... 010 0000 0000 @typea +bsll 010001 ..... ..... ..... 100 0000 0000 @typea + +bsrli 011001 ..... ..... 00000 000000 ..... @typeb_bs +bsrai 011001 ..... ..... 00000 010000 ..... @typeb_bs +bslli 011001 ..... ..... 00000 100000 ..... @typeb_bs + +bsefi 011001 ..... ..... 01000 .....0 ..... @typeb_ie +bsifi 011001 ..... ..... 10000 .....0 ..... @typeb_ie + clz 100100 ..... ..... 00000 000 1110 0000 @typea0 cmp 000101 ..... ..... ..... 000 0000 0001 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2d57f76548..964525f75e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -368,6 +368,72 @@ DO_TYPEBI(andi, false, tcg_gen_andi_i32) DO_TYPEA(andn, false, tcg_gen_andc_i32) DO_TYPEBI(andni, false, gen_andni) +static void gen_bsra(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_sar_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_shr_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_shl_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsefi(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + /* Note that decodetree has extracted and reassembled imm_w/imm_s. */ + int imm_w = extract32(imm, 5, 5); + int imm_s = extract32(imm, 0, 5); + + if (imm_w + imm_s > 32 || imm_w == 0) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", + imm_w, imm_s); + } else { + tcg_gen_extract_i32(out, ina, imm_s, imm_w); + } +} + +static void gen_bsifi(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + /* Note that decodetree has extracted and reassembled imm_w/imm_s. */ + int imm_w = extract32(imm, 5, 5); + int imm_s = extract32(imm, 0, 5); + int width = imm_w - imm_s + 1; + + if (imm_w < imm_s) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", + imm_w, imm_s); + } else { + tcg_gen_deposit_i32(out, out, ina, imm_s, width); + } +} + +DO_TYPEA_CFG(bsra, use_barrel, false, gen_bsra) +DO_TYPEA_CFG(bsrl, use_barrel, false, gen_bsrl) +DO_TYPEA_CFG(bsll, use_barrel, false, gen_bsll) + +DO_TYPEBI_CFG(bsrai, use_barrel, false, tcg_gen_sari_i32) +DO_TYPEBI_CFG(bsrli, use_barrel, false, tcg_gen_shri_i32) +DO_TYPEBI_CFG(bslli, use_barrel, false, tcg_gen_shli_i32) + +DO_TYPEBI_CFG(bsefi, use_barrel, false, gen_bsefi) +DO_TYPEBI_CFG(bsifi, use_barrel, false, gen_bsifi) + static void gen_clz(TCGv_i32 out, TCGv_i32 ina) { tcg_gen_clzi_i32(out, ina, 32); @@ -771,64 +837,6 @@ static void dec_msr(DisasContext *dc) } } -static void dec_barrel(DisasContext *dc) -{ - TCGv_i32 t0; - unsigned int imm_w, imm_s; - bool s, t, e = false, i = false; - - if (trap_illegal(dc, !dc->cpu->cfg.use_barrel)) { - return; - } - - if (dc->type_b) { - /* Insert and extract are only available in immediate mode. */ - i = extract32(dc->imm, 15, 1); - e = extract32(dc->imm, 14, 1); - } - s = extract32(dc->imm, 10, 1); - t = extract32(dc->imm, 9, 1); - imm_w = extract32(dc->imm, 6, 5); - imm_s = extract32(dc->imm, 0, 5); - - if (e) { - if (imm_w + imm_s > 32 || imm_w == 0) { - /* These inputs have an undefined behavior. */ - qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", - imm_w, imm_s); - } else { - tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w); - } - } else if (i) { - int width = imm_w - imm_s + 1; - - if (imm_w < imm_s) { - /* These inputs have an undefined behavior. */ - qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", - imm_w, imm_s); - } else { - tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra], - imm_s, width); - } - } else { - t0 = tcg_temp_new_i32(); - - tcg_gen_mov_i32(t0, *(dec_alu_op_b(dc))); - tcg_gen_andi_i32(t0, t0, 31); - - if (s) { - tcg_gen_shl_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } else { - if (t) { - tcg_gen_sar_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } else { - tcg_gen_shr_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } - } - tcg_temp_free_i32(t0); - } -} - static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { @@ -1551,7 +1559,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, {DEC_ST, dec_store}, {DEC_IMM, dec_imm}, From patchwork Mon Aug 31 16:05:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248796 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3455605ilg; Mon, 31 Aug 2020 09:25:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyREdtPrKnT7Ul6Vp1EMWEbW2cRXmfAyJTqgj+Mn4br2yk4UNno6zlpPwVNGKH7/NlKFAZ1 X-Received: by 2002:a25:5755:: with SMTP id l82mr3457399ybb.175.1598891158946; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 2 ++ target/microblaze/translate.c | 18 +++++++++--------- 2 files changed, 11 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 4644defbfe..ad15c16f9b 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -79,6 +79,8 @@ cmpu 000101 ..... ..... ..... 000 0000 0011 @typea idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea +imm 101100 00000 00000 imm:16 + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 964525f75e..54de136a16 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -477,6 +477,15 @@ static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) +static bool trans_imm(DisasContext *dc, arg_imm *arg) +{ + dc->ext_imm = arg->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); + dc->tb_flags |= IMM_FLAG; + dc->clear_imm = 0; + return true; +} + static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp = tcg_temp_new_i32(); @@ -848,14 +857,6 @@ static inline void sync_jmpstate(DisasContext *dc) } } -static void dec_imm(DisasContext *dc) -{ - dc->ext_imm = dc->imm << 16; - tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags |= IMM_FLAG; - dc->clear_imm = 0; -} - static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) { /* Should be set to true if r1 is used by loadstores. */ @@ -1561,7 +1562,6 @@ static struct decoder_info { } decinfo[] = { {DEC_LD, dec_load}, {DEC_ST, dec_store}, - {DEC_IMM, dec_imm}, {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, From patchwork Mon Aug 31 16:05:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248800 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3456798ilg; Mon, 31 Aug 2020 09:27:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwY9rTwuVFhm9/p73yHYmZQWVV//12BVgPtsFOz9pi2x1a3tATngHRmYq1rIU+nD28En+7H X-Received: by 2002:a25:2d13:: with SMTP id t19mr3374386ybt.113.1598891245276; Mon, 31 Aug 2020 09:27:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891245; cv=none; d=google.com; s=arc-20160816; b=vLRqwe4P7jhSFqh59z3i2dgpNRmLILVec+ttfaH+m2hunZMZWClCb9QNrFL+qF7zbt VIIhCzy7O7Bj1H3BoBgfqhDwGF+JLCvG4RhU3wZq5bYAvNQqRBwBJqLEeXkEIRao3IKh C1Aa68LK9RCT45LzCPs716SzZMEaZRfRyDmL6p9wOe2gXkIyZcj5uytJL2uI2W0okp14 7Mrq5pmZ04a7S8CztoJrHsaJkJhDu+cqz+YNkb/Ld2hQMNgTSuE0VKKvMCDWIQXW76h6 m5PgbZvDNfkJZR9EACc7FHiuSTq9qdGbMkaHAV3F6ID/CYQnEOdnAEzv0J+eukUk7FYB iBjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CtMYJ7CIPlKie9ABXlTJ3VIrDUZQvNuQ4dYjI8dHmfc=; b=Bfop2uRKlEWHUGr8OzHqLurZ7SXr3MW4hlc0Tr88Mw8FVOfj+ubvIf/z/vslV4V2gg PldqZVqMflUcPwPkER/aHLx5NIl/i2ZL8Mvm4CJHcjh3MMEXBUCxXWgnADruyjn5rkYn xWq3sxszf3eiVjUC+sg1pjpzv8hGAU4a3JMSFdGB6zcC2DUOdog5befmzSomemYuvrsW Ze5ztc7m+rtsF+/FyDls1mWDubpHDAnPEVwiQCDaBrRAOzXiNmiX9r1pbrUKO7hdhJSi oJtjIeGGcTt5HbejjCSJQT0mmMNq54JWxopfJDGtAuW/bj/MZoNKAtX/znDiD3u+wsC+ CMBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dh6R+Lfj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The current dec_check_fpuv2 test, raising an FPU exception for an unimplemented instruction, appears to be contradictory to the manual. Drop that and merely check use_fpu == 2. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 19 +++++ target/microblaze/translate.c | 152 +++++++++------------------------ 2 files changed, 60 insertions(+), 111 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index ad15c16f9b..87e8f5679b 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -76,6 +76,25 @@ clz 100100 ..... ..... 00000 000 1110 0000 @typea0 cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +fadd 010110 ..... ..... ..... 0000 000 0000 @typea +frsub 010110 ..... ..... ..... 0001 000 0000 @typea +fmul 010110 ..... ..... ..... 0010 000 0000 @typea +fdiv 010110 ..... ..... ..... 0011 000 0000 @typea +fcmp_un 010110 ..... ..... ..... 0100 000 0000 @typea +fcmp_lt 010110 ..... ..... ..... 0100 001 0000 @typea +fcmp_eq 010110 ..... ..... ..... 0100 010 0000 @typea +fcmp_le 010110 ..... ..... ..... 0100 011 0000 @typea +fcmp_gt 010110 ..... ..... ..... 0100 100 0000 @typea +fcmp_ne 010110 ..... ..... ..... 0100 101 0000 @typea +fcmp_ge 010110 ..... ..... ..... 0100 110 0000 @typea + +# Note that flt and fint, unlike fsqrt, are documented as having the RB +# operand which is unused. So allow the field to be non-zero but discard +# the value and treat as 2-operand insns. +flt 010110 ..... ..... ----- 0101 000 0000 @typea0 +fint 010110 ..... ..... ----- 0110 000 0000 @typea0 +fsqrt 010110 ..... ..... 00000 0111 000 0000 @typea0 + idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 54de136a16..72541905ec 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -318,6 +318,14 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_val(dc, a, SE, FN); } +#define ENV_WRAPPER2(NAME, HELPER) \ + static void NAME(TCGv_i32 out, TCGv_i32 ina) \ + { HELPER(out, cpu_env, ina); } + +#define ENV_WRAPPER3(NAME, HELPER) \ + static void NAME(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) \ + { HELPER(out, cpu_env, ina, inb); } + /* No input carry, but output carry. */ static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { @@ -464,6 +472,39 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +ENV_WRAPPER3(gen_fadd, gen_helper_fadd) +ENV_WRAPPER3(gen_frsub, gen_helper_frsub) +ENV_WRAPPER3(gen_fmul, gen_helper_fmul) +ENV_WRAPPER3(gen_fdiv, gen_helper_fdiv) +ENV_WRAPPER3(gen_fcmp_un, gen_helper_fcmp_un) +ENV_WRAPPER3(gen_fcmp_lt, gen_helper_fcmp_lt) +ENV_WRAPPER3(gen_fcmp_eq, gen_helper_fcmp_eq) +ENV_WRAPPER3(gen_fcmp_le, gen_helper_fcmp_le) +ENV_WRAPPER3(gen_fcmp_gt, gen_helper_fcmp_gt) +ENV_WRAPPER3(gen_fcmp_ne, gen_helper_fcmp_ne) +ENV_WRAPPER3(gen_fcmp_ge, gen_helper_fcmp_ge) + +DO_TYPEA_CFG(fadd, use_fpu, true, gen_fadd) +DO_TYPEA_CFG(frsub, use_fpu, true, gen_frsub) +DO_TYPEA_CFG(fmul, use_fpu, true, gen_fmul) +DO_TYPEA_CFG(fdiv, use_fpu, true, gen_fdiv) +DO_TYPEA_CFG(fcmp_un, use_fpu, true, gen_fcmp_un) +DO_TYPEA_CFG(fcmp_lt, use_fpu, true, gen_fcmp_lt) +DO_TYPEA_CFG(fcmp_eq, use_fpu, true, gen_fcmp_eq) +DO_TYPEA_CFG(fcmp_le, use_fpu, true, gen_fcmp_le) +DO_TYPEA_CFG(fcmp_gt, use_fpu, true, gen_fcmp_gt) +DO_TYPEA_CFG(fcmp_ne, use_fpu, true, gen_fcmp_ne) +DO_TYPEA_CFG(fcmp_ge, use_fpu, true, gen_fcmp_ge) + +ENV_WRAPPER2(gen_flt, gen_helper_flt) +ENV_WRAPPER2(gen_fint, gen_helper_fint) +ENV_WRAPPER2(gen_fsqrt, gen_helper_fsqrt) + +DO_TYPEA0_CFG(flt, use_fpu >= 2, true, gen_flt) +DO_TYPEA0_CFG(fint, use_fpu >= 2, true, gen_fint) +DO_TYPEA0_CFG(fsqrt, use_fpu >= 2, true, gen_fsqrt) + +/* Does not use ENV_WRAPPER3, because arguments are swapped as well. */ static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { gen_helper_divs(out, cpu_env, inb, ina); @@ -1403,116 +1444,6 @@ static void dec_rts(DisasContext *dc) tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } -static int dec_check_fpuv2(DisasContext *dc) -{ - if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - gen_raise_hw_excp(dc, ESR_EC_FPU); - } - return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; -} - -static void dec_fpu(DisasContext *dc) -{ - unsigned int fpu_insn; - - if (trap_illegal(dc, !dc->cpu->cfg.use_fpu)) { - return; - } - - fpu_insn = (dc->ir >> 7) & 7; - - switch (fpu_insn) { - case 0: - gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 1: - gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 2: - gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 3: - gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 4: - switch ((dc->ir >> 4) & 7) { - case 0: - gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 1: - gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 3: - gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 4: - gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 5: - gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 6: - gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - default: - qemu_log_mask(LOG_UNIMP, - "unimplemented fcmp fpu_insn=%x pc=%x" - " opc=%x\n", - fpu_insn, (uint32_t)dc->base.pc_next, - dc->opcode); - dc->abort_at_next_insn = 1; - break; - } - break; - - case 5: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - case 6: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - case 7: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - default: - qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" - " opc=%x\n", - fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode); - dc->abort_at_next_insn = 1; - break; - } -} - static void dec_null(DisasContext *dc) { if (trap_illegal(dc, true)) { @@ -1565,7 +1496,6 @@ static struct decoder_info { {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, - {DEC_FPU, dec_fpu}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} From patchwork Mon Aug 31 16:05:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248803 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3457675ilg; Mon, 31 Aug 2020 09:28:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwdbBHH6EgKECBihktjYj9/OnJ6FrVyNB+vad1YwafcuyYl4rKpxfUQbR6g2Zh95uQNS/PR X-Received: by 2002:a25:bec3:: with SMTP id k3mr3480659ybm.399.1598891313694; Mon, 31 Aug 2020 09:28:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891313; cv=none; d=google.com; s=arc-20160816; b=Abl6ORHsNtbYzg3/6Rh4brRfHt0c9pzJBW4cf3B2VPy2JTCZpRpmXJ2KSdlHt7steZ aKRB5jCb2TOPLDxljuv3z9lZYXboTEMqeOqNUt4NsTIT3uRHJMwrAShkMhxtfl095ohO YlnPUEXquzMmqI/l+Vwg/OQb/QkLdniFQbS3NYaqK9Yzcm5VHyR3mBHYPD8qK33jaLQm 6Xf2jHTXxoNv4fJlZPYSpEsZz2xyv2Vwnf5VHwjllF621PaH9cUpYiPiS3TOMOkhBhFC s3SpjG/5XtjlCDaUFunGXXnkWoKhSubpvF0acY38MAJH9ybsGHU3VvOmtaqXt0TuBWiY 3kCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5MvRykgMTcIF07iOKyUuKHIQ1MzsLcRrDLZyuwy1N1o=; b=sjWq8z6eX6VRUwQCQ9wfKO0Gh8wMTAo9zm4ICR6XtDlrcY9ajBTSomW6AJniPTycpg oYgiaTykexJladzNHiOye9PPuzlhGLWpDbMlqlQU8iiQr9dyfJ7UEnxDuEzb2kaaKHdQ yNCtWzcALqSIomQGlmpqFArCmBt/bDUO9EX3Ing9+a8kUfUpQWJcP2sXQy0Asissfr0e uJlFcjCCzZ7UpREddnSPonevlB0sN6E14GyqpDYNYCFNpcuglUGYyvyLpIqwwiuDzmjG eiDe29JC74URpGplW7LxuK7cV39GLPyC1Tv/Je5lj4Pfuf7L4yFVIaKZNyivePungb6N /XFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RxGguRan; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Restore the correct PC when an exception must be raised. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 37 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index d99d98051a..2c59d4492d 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -104,13 +104,16 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) } /* raise FPU exception. */ -static void raise_fpu_exception(CPUMBState *env) +static void raise_fpu_exception(CPUMBState *env, uintptr_t ra) { + CPUState *cs = env_cpu(env); + env->esr = ESR_EC_FPU; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); } -static void update_fpu_flags(CPUMBState *env, int flags) +static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) { int raise = 0; @@ -133,7 +136,7 @@ static void update_fpu_flags(CPUMBState *env, int flags) if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) && (env->msr & MSR_EE)) { - raise_fpu_exception(env); + raise_fpu_exception(env, ra); } } @@ -148,7 +151,7 @@ uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) fd.f = float32_add(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -162,7 +165,7 @@ uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; fd.f = float32_sub(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -176,7 +179,7 @@ uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; fd.f = float32_mul(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -191,7 +194,7 @@ uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; fd.f = float32_div(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -206,7 +209,7 @@ uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) if (float32_is_signaling_nan(fa.f, &env->fp_status) || float32_is_signaling_nan(fb.f, &env->fp_status)) { - update_fpu_flags(env, float_flag_invalid); + update_fpu_flags(env, float_flag_invalid, GETPC()); r = 1; } @@ -229,7 +232,7 @@ uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; r = float32_lt(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -245,7 +248,7 @@ uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; r = float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -261,7 +264,7 @@ uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = float32_le(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; @@ -277,7 +280,7 @@ uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = float32_lt(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -291,7 +294,7 @@ uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -306,7 +309,7 @@ uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = !float32_lt(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -330,7 +333,7 @@ uint32_t helper_fint(CPUMBState *env, uint32_t a) fa.l = a; r = float32_to_int32(fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return r; } @@ -344,7 +347,7 @@ uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) fa.l = a; fd.l = float32_sqrt(fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; 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[209.51.188.17]) by mx.google.com with ESMTPS id 184si7626060ybl.349.2020.08.31.09.27.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:27:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qhiGN9rI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46332 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmeV-0005Az-F1 for patch@linaro.org; Mon, 31 Aug 2020 12:27:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34394) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKx-0005kQ-3o for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:15 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:37620) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKt-00065N-KL for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:14 -0400 Received: by mail-pj1-x1029.google.com with SMTP id mw10so28221pjb.2 for ; Mon, 31 Aug 2020 09:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ySARoLfSzmE74D4LscfR58zxrdoE7jaYed6YBL0jQs8=; b=qhiGN9rIhhZTCZ+y5TeaYdycrJFmD5xCNU/1efZN8ESQDvCW8XtnJAm3In3XIyb42L O1Ub/fjZW+HexF3AJxOHJLFcu2IiN81+JNPYvOaI6Cx+sq+t7VQ9Dx/lcw/IxieLHhvX o0z6kOf9UgUD3lhGlbazNyAx52AbDNXu6180Y76UCDUiOuO4OjP65nrq2nGuaQuIAABQ sg6aMgKt0jiUCma3FKQD9aAWLGY3FiQpC9qnt++RYXXvPPY9Ob+v/2q+jKI4GHIa/NAv EVxpVy6JxigEgQVGnCKqclDPgPe6JCsMLVcL7eBB3EDG/N8CvSwYvIBopryX1zTSbR1G WPmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ySARoLfSzmE74D4LscfR58zxrdoE7jaYed6YBL0jQs8=; b=oVwMfl9SsEiAz4lwhTsTD+9ZC4FHCHiUQUgADGBTht4KLfBwMdLnDRv7TlVZ0E/mwI BNlkVuhato9Lz+FS/9yQEqwVrAOhnwrnoBvXWV+bmXDphpbD4QfXEkMJd03ISnpkYcjf ULcYaeLImEGKeXOyEo4jFQbLwuIrx2pEKGsDRXZrandBkAHflqdAL8MfJCgkz4ahS3Q0 v0xCVJSCsRTsDtEDjA3OZB9yCxjL8mRCfjoQqSiHAvRT9yODPm1SPvEaSQz8Ni4VOOF3 HmZhOwgu+f+6EameTVs+1t87r0y3O+ZTLvye15AlIYpPnwnhoRI7IeH/a1XXbufg584O pygg== X-Gm-Message-State: AOAM531JtVPLFnlEfyIyjA3/Hal3SeKJ6Gu1nvf/Z1Qa7J3LqN0MCd+O 0jGX5VexsjOoVQ9mymWQjemtgiy4ufONQA== X-Received: by 2002:a17:902:42:: with SMTP id 60mr1027379pla.277.1598890029912; Mon, 31 Aug 2020 09:07:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 49/76] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG Date: Mon, 31 Aug 2020 09:05:34 -0700 Message-Id: <20200831160601.833692-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that FSR is no longer a tcg global temp, we can say that the fpu helpers do not write to tcg temps. All temps are read implicitly by the fpu exception path. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 79e1e8ecc7..64816c89e1 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -3,21 +3,21 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) -DEF_HELPER_3(fadd, i32, env, i32, i32) -DEF_HELPER_3(frsub, i32, env, i32, i32) -DEF_HELPER_3(fmul, i32, env, i32, i32) -DEF_HELPER_3(fdiv, i32, env, i32, i32) -DEF_HELPER_2(flt, i32, env, i32) -DEF_HELPER_2(fint, i32, env, i32) -DEF_HELPER_2(fsqrt, i32, env, i32) +DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(frsub, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_2(flt, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_2(fint, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_2(fsqrt, TCG_CALL_NO_WG, i32, env, i32) -DEF_HELPER_3(fcmp_un, i32, env, i32, i32) -DEF_HELPER_3(fcmp_lt, i32, env, i32, i32) -DEF_HELPER_3(fcmp_eq, i32, env, i32, i32) -DEF_HELPER_3(fcmp_le, i32, env, i32, i32) -DEF_HELPER_3(fcmp_gt, i32, env, i32, i32) -DEF_HELPER_3(fcmp_ne, i32, env, i32, i32) -DEF_HELPER_3(fcmp_ge, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_un, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_lt, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_eq, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_le, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_gt, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) #if !defined(CONFIG_USER_ONLY) From patchwork Mon Aug 31 16:05:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248787 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3452956ilg; Mon, 31 Aug 2020 09:22:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxsTqaVazbJoYgc2XXKDt/HVAbTUS5qZHoaqss79myvPTxJtbaghSEa+sIvLpqmhO4kGbSp X-Received: by 2002:a1f:2dd7:: with SMTP id t206mr1699383vkt.13.1598890937535; Mon, 31 Aug 2020 09:22:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890937; cv=none; d=google.com; s=arc-20160816; b=mCLxXZO8saKY08kzAi0hUUl2N+tMdJD6+3nd4oIBsBKRXCZPw6UsyJlXmJ6uYuny8F 0r7moY6YwOgdjty0dxa4367xEv3itx1t3tkBreycRnkfsuUcs/86V4HswuNMxYYhNYsM JMNzrz/nLlsEXjPZGzoZGsVeeS53dLcitqciopQU+ZMYvxuEHW196VvhEHlHyF400saN K6gy8hGwYzYzQOA8kNJ4/cH+ck7wLP5Ir4NdQdiQ8oUCIPMPZsqkUsjPL78ZRyrg/YF3 fA/It2Qjm2mxHwrQSVM2vk+p/1NyQeXU/V0bpmKmnbIdqlvsz20/mpCQwLyWeygHVHo8 C6WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6UAW/LQVnNBBxfSRwX11wMrvT5qNSW3Igjwiwe99RIE=; b=xnvI+S1V+HRLEwCg4xmNulPzm9R8aI+vOWz15MA4k93qL1c0HgcVcdp2akG21YetEu kkX5JnBPLS056dZCJzvdWsqphzg9Wsq5SsbGlAodLY0FMW0l8i2Zgh4MCBPQly4zvqM7 xy7d3wDz/zQOoGUwQfKsej1uh5HmTsshbo2WqItpGWjWIM2++JlqmeMCckDl7QAIRfTM hCh2DEmkvt59GvPND3OsyMZOokJxTRft2goR9CYT3QVmyBsdrVGzLFBf9CcLIm2jvcTq DQ7dD6xLS0rVCpP2R4HZvXt8m7zJ1Sjv8vVZLDlacSFrnWS1TYS4w7M7UoqbxBmkMRGo nYig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EiJULW20; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d22si1250886vsp.315.2020.08.31.09.22.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:22:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EiJULW20; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmZU-0001lb-Sy for patch@linaro.org; Mon, 31 Aug 2020 12:22:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKx-0005m9-Ly for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:15 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:46348) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKv-00065f-BR for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:15 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 31so821045pgy.13 for ; Mon, 31 Aug 2020 09:07:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6UAW/LQVnNBBxfSRwX11wMrvT5qNSW3Igjwiwe99RIE=; b=EiJULW20SvMhyeruN+0+K4w63UPacbSAHPYsi4E+WLnH8BmlPXu19iH6R1ft1F9Lq2 DdoW+xk7fBQEERNOkqnn4fekIOeJMS1lDZciOQzfVGOBNXNYgW/tSWmMrDwscUOYmr42 syR0i8KCuaOH5pdUbBHx8l9/nxXVLZtAEzYJ6BH66Sq9Ow3DnOEfpgi429bzV2xUUI5H K1/O1Td8vbF0ccqsl7k+vGFh29WV1Ayv62rjyRecoBB1HaoxD+IKSGq2KDYXr0W1e3Ls bx4IbfMN2dseSIKGbjPmpEwbfKyGnoEgn0+AJPJnGTD6Fdr2JqBX5IoaurrwJ5fwPIT+ /eaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6UAW/LQVnNBBxfSRwX11wMrvT5qNSW3Igjwiwe99RIE=; b=Oqe3BaNIv2NPBjreHwr2eEUdvApaLBVS0/fNq9+br64t16KsoDQhTP/6hQ55kUwO/d y6Qul3VDm5YTb8T9KpVc0SCmOiAHCVqrXDBEhyCwevt15OD38OmkhQikZWXmtGHYB8nM h/7SBUWNDP+5H+z85SPaV1TAj3/OIuO29oQGVCau70VvIpwglzLTLVwVWRPJh8dOWswu KuPHv6Xn9LsI9Q2V6U4A5vZEAnUEYVuCU84IukGpCFLeeiqOV+rzHsussBb84SwdWjlC 6OvWg1GdWpW5zyAa2cgUJ4a0nKFSYlDBQ7hMe8UcRjCyqdwvb3tMBAFjTh6sT06OX8l0 ekzw== X-Gm-Message-State: AOAM533ScXbPG3a0vPGzmcknSXwZV8s4JTHMk0jgqBCsk2hqEbCV/XY+ J3TZc7J+d+lPaBy8RxV8aOfAFaDy/accow== X-Received: by 2002:a63:511a:: with SMTP id f26mr1783362pgb.15.1598890031449; Mon, 31 Aug 2020 09:07:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 50/76] target/microblaze: Replace MSR_EE_FLAG with MSR_EE Date: Mon, 31 Aug 2020 09:05:35 -0700 Message-Id: <20200831160601.833692-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There's no reason to define MSR_EE_FLAG; we can just use the original MSR_EE define. Document the other flags copied into tb_flags with iflag to reserve those bits. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +++- target/microblaze/translate.c | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 013858b8e0..594501e4e7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -254,7 +254,9 @@ struct CPUMBState { /* Internal flags. */ #define IMM_FLAG 4 -#define MSR_EE_FLAG (1 << 8) +/* MSR_EE (1 << 8) */ +/* MSR_UM (1 << 11) */ +/* MSR_VM (1 << 13) */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 72541905ec..1f6731e0af 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -162,7 +162,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) */ static bool trap_illegal(DisasContext *dc, bool cond) { - if (cond && (dc->tb_flags & MSR_EE_FLAG) + if (cond && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.illegal_opcode_exception) { gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); } @@ -178,7 +178,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) int mem_index = cpu_mmu_index(&dc->cpu->env, false); bool cond_user = cond && mem_index == MMU_USER_IDX; - if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { + if (cond_user && (dc->tb_flags & MSR_EE)) { gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); } return cond_user; From patchwork Mon Aug 31 16:05:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248806 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3458585ilg; Mon, 31 Aug 2020 09:29:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy/4kBwhFcvFr7i6A2yFpfD0RZs4YaFqhkP+ULSqfuQR5UxqkbcSVcFmLbiSGEoqG5RIvRE X-Received: by 2002:a1f:bd15:: with SMTP id n21mr1773853vkf.16.1598891398977; Mon, 31 Aug 2020 09:29:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891398; cv=none; d=google.com; s=arc-20160816; b=VIqscZlpspv8QMzv2fCSqH7Cq+g2nGm1yGILV8vrtpy2e/uqkIAffH9rAvlNbV8umv 4JPFR0Q6H0oVvVAshvHcSBmUgFuwruk2cJBoapRzuasgC0ktDBHcJ7YXlGVsUcIqxE5M wNnLqoXYWMdGLR9psGtNKDkC3P5HY1K3xaZ36eeetxjSqZXoamFMaJ+gTDmdDI7ugBCW 32p5cW8+iuKFyuXQEseceH7BurKoO5WRg6YF9ii1vmpUG5lFidqfMTLYhnX15k4i5loj sjFu+/Zj8Bso/oyhdBoTvbEmSFO3ugDwoKjHOiSWeLoTfhhICK7luc/gE2yM+RmJHQNe l4mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pM4ivWigF6aGuCdn4jvlwQnVJrMGcBGI733lqrG0wt8=; b=yO7hFhd4udDqT3u3VWI14zx/774IGSg7L6RP8ir3r9gDMuv0ZR1sIkduu0imHntp1y MnmGoB5cEDdSzI0625GIMSrhvp4iH/9hkZ4wB2qjEcv4VeVrPTlukk+cSIPoENIwSBK5 JD/gnLE+Pav8ofOpsUrtEgm1hvBK4m4MON3WfuRvaysSAB/8wo3piEuz9NjWFOJKYM/n HS/gGg9XuMY6kmdoJfk29XNlNRz92KnB22wGyiMLpbDipgQap8/V1s1LVR7a3LKz8n0G ZFo+KGzwnFAL5s/QxGVyo0EfZyt/M3BmH6jRFFdnfZWHo4saBgAiLauqbRiwQJxUpVTf 8ccg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="eo0V4/Vt"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c12si831635vso.153.2020.08.31.09.29.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:29:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="eo0V4/Vt"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmgw-0003Lx-9E for patch@linaro.org; Mon, 31 Aug 2020 12:29:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKy-0005nh-GY for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:16 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:46350) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKw-00065v-Mn for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:16 -0400 Received: by mail-pg1-x531.google.com with SMTP id 31so821100pgy.13 for ; Mon, 31 Aug 2020 09:07:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pM4ivWigF6aGuCdn4jvlwQnVJrMGcBGI733lqrG0wt8=; b=eo0V4/VtOHM1WLUX8u1mPPtH4HcbQbO93GYkPjuc14JcxAKyPyGhWEnWE6Jg8m2lCe hzucK6vnsoY4UvHNCz0OBNTzuhqu3aUdAizlGcMdLUXHjsAcTv9ooOw6oZu6/WsR4DW5 VLQ02C6BdUvf2Mr0vF+6xkhouKPOpTAA3iIZ23gjJs2+vFg1kYGbyqNWwAGgisH8YT7H 94leYBUkLp96J/PfpmL9iy5YQTAtTwELumMYYrsXiDHItoiUp+49+kedSr6Pworb+A4T NvnhH2x6I+H3HGabPGsAWDm3fmJQ1Y4IqLQf0h78ztsrZQcUxlZWVtVPErBNjf6c5NtV oZ2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pM4ivWigF6aGuCdn4jvlwQnVJrMGcBGI733lqrG0wt8=; b=PNOgTakZbNg4Ay2cGrpSdZ/+e9CTrvraCjJ3yAk2ts9Hdhy+mna92Aw9TsQ0tEE+d6 X38OK6sCD7mMxudwmY4c5fq46yKz180p/qPAnZwvp7ZVNuhReDfUfSWxfhr5KNSis4cs zWxRu5BYCh9YTlygmtF6jIjPmTm1QnismhFK626Hc1PKTnKyb0zcOaFjOMRFMIBNSuvs i/GDlVoqkuHZwXH/xakRvAkPDXTGoUjM17nA0svzYuCrgWj27nwvrdAFeqWcbKtvLs5A Y/kRRHJ8rQpTWpflrca+z/TtBPM+EbhzbQ7WzpvUMq/z/RY1mI4ynhKBovqW01/ziOsj YEuA== X-Gm-Message-State: AOAM533EUwCC320kXcSeOhZsuHGrdnKwxdjsPZ9KcZRZeIEIQZdszT4D HPv7kdcLmoashw8mCDAs0jaTynZxvmoXbg== X-Received: by 2002:a62:406:: with SMTP id 6mr1762033pfe.193.1598890032881; Mon, 31 Aug 2020 09:07:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 51/76] target/microblaze: Cache mem_index in DisasContext Date: Mon, 31 Aug 2020 09:05:36 -0700 Message-Id: <20200831160601.833692-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Ideally, nothing outside the top-level of translation even has access to env. Cache the value in init_disas_context. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 1f6731e0af..a55e110171 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -73,6 +73,7 @@ typedef struct DisasContext { unsigned int delayed_branch; unsigned int tb_flags, synced_flags; /* tb dependent flags. */ unsigned int clear_imm; + int mem_index; #define JMP_NOJMP 0 #define JMP_DIRECT 1 @@ -175,8 +176,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) */ static bool trap_userspace(DisasContext *dc, bool cond) { - int mem_index = cpu_mmu_index(&dc->cpu->env, false); - bool cond_user = cond && mem_index == MMU_USER_IDX; + bool cond_user = cond && dc->mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE)) { gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); @@ -968,7 +968,7 @@ static void dec_load(DisasContext *dc) TCGv addr; unsigned int size; bool rev = false, ex = false, ea = false; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); + int mem_index = dc->mem_index; MemOp mop; mop = dc->opcode & 3; @@ -1077,7 +1077,7 @@ static void dec_store(DisasContext *dc) TCGLabel *swx_skip = NULL; unsigned int size; bool rev = false, ex = false, ea = false; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); + int mem_index = dc->mem_index; MemOp mop; mop = dc->opcode & 3; @@ -1540,6 +1540,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; + dc->mem_index = cpu_mmu_index(&cpu->env, false); bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); From patchwork Mon Aug 31 16:05:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248802 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3456869ilg; Mon, 31 Aug 2020 09:27:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzyt2FL+TAmH3d4lv89TnsmQvnenGCEdbkA9+2IRpGpBsQHQCX13fhyf4TwNoLPxt17aqiF X-Received: by 2002:a67:fc49:: with SMTP id p9mr1823452vsq.142.1598891249103; Mon, 31 Aug 2020 09:27:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891249; cv=none; d=google.com; s=arc-20160816; b=H92PS1wsuQDCs8SFRqou2zpKHnXa/Wm8YJdgFprpZ6g8EzzEO/SSyiqf9nOj54+7aP wk/zDBZmqgXIMH7GFGgovj268jyAZU0xl7gmBV/5WFVNrcAKojR9hlt25DdtSwrzzB58 7UyFsPTy4WaRRdPNporOJNuZnSlfyyIF0TAOk2SwmsI90kU2f/Ok1A3uIZgF31O2NdSq sDgPz2ZU8UPPNNkRn4p27Hfk1vM6CcU+FbgB12BURLUl5aVwr58N2nnExyKuMWSUXT32 LuNve2ObG7woXAEjlE9ELew4n/ldIe+ms5FNaARzsTVxNI47O+l7TiKlvEC7ba2lqbZn l0PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2cPf8f8AdkhKlG+8ucMI1Z77vF2YecMji34EykTW4mg=; b=mNT7NkY8c/mLw/1U21ke8iB5KcKNIfjTS4e68+LqahuE/mVgxdt3Ri9kUaYKdaOJ8K ZirnRjhfE3DwTi+MG3yzdNX8b9/RUEqv74k/QcK6zS8x+PqgcwP7lxqB4+Bc36mIReOx cPGueMzj/W2Xv01y86xRG60yBPcfEQMb7WISAeICa5bYlceQAgUEnXA1mQpVFrpnAXYN 9pnl3Jm8KHFRtAs4553ixHy4J4zPSgqCmawJ3xOrpg4dNrUsy6jPKu21AHRcO7pw2KHV 195oM+Gq8vc9cgM9Ut1zTOxpXCe+mM9/7crE6dMgFpcozlMDQyUV97nxtQkWwX3ZNL88 4jRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="BckR/dk3"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Restore the correct PC when an exception must be raised. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 +- target/microblaze/op_helper.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 64816c89e1..a473c1867b 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -26,7 +26,7 @@ DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) #endif DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) -DEF_HELPER_2(stackprot, void, env, tl) +DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_2(get, i32, i32, i32) DEF_HELPER_3(put, void, i32, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 2c59d4492d..a99c467364 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -389,12 +389,16 @@ void helper_memalign(CPUMBState *env, target_ulong addr, void helper_stackprot(CPUMBState *env, target_ulong addr) { if (addr < env->slr || addr > env->shr) { + CPUState *cs = env_cpu(env); + qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); + env->ear = addr; env->esr = ESR_EC_STACKPROT; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, GETPC()); } } From patchwork Mon Aug 31 16:05:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248809 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3460376ilg; Mon, 31 Aug 2020 09:32:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxgMU9iMGiFJ16tHH8MxC1yJlNl3fWrlrOg5PqWvvaWJ+OHK8puNg3i/jrNyK4BSTdXMWIq X-Received: by 2002:a25:d4e:: with SMTP id 75mr3171162ybn.480.1598891543397; Mon, 31 Aug 2020 09:32:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891543; cv=none; d=google.com; s=arc-20160816; b=RWbP+4G3zSXr+hd5QGnSruy5lvXJXBsTJUy10LIfYyNitFGwq5hgbnbzw602+S5oEI qSQ4eanrZggooFc+R4u0nKW2VZ5vASW+BsymKY2Od3wZOKFnRtgxBjaCMI0EZlULvcod tj/bvKmlwNR7RZPsw+rC4QVOhcn+aRilgAuOPXrwYCmLaubQeANyZ3b3WlStIK8YM0ey tKGN8d0CIav3W6qMIn0yRaZvv+EUDdg7dUqIhBKhw2lGePP1mh7fE+xlLgnsjMYS4ToP PF6nl1QdDMYAFG+eU7IW6/Rej3CfLgQlXUxpZrumDo1FB9UVlZSicqzK/VfkARaIjyWD fGZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OF+n4lfXCPrHMxyBmLfVzNw7xG6DYBX8dPoMcyp+q6s=; b=uYlhDoqQeDlrLVOx5KWyZQwnptE1B6TNOJtwoqWGIEe/DACKuFMdnKVxVAQwP1qdvb Y2e98bd2LufCsnsunvl3NOHeBM1XNAgZCf/qhonb1b0cl/0YCF99GAd4LM1GlyylmvCk +M+NiGRu5v94yUh4sLgOXK7587wfTRl9tiooBrzCnET2TjWXPzAKbHVJrssDNIXWVJXp BIwVsaJl7OotOCUH/EoY7+b/MPrCvVoGz5cT46VjKhsxGBfWdAp7DfeIiHiIopWObi7x uKFVIXHvGayph8yb0KENTrm2UpgaI/kdKSY8C4F6SS6M/vj7UZCGgoA2OyianEX8mdA4 TB9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KRKhL0n5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 32 ++ target/microblaze/translate.c | 723 +++++++++++++++++++-------------- 2 files changed, 456 insertions(+), 299 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 87e8f5679b..47b92b9cbc 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -100,6 +100,22 @@ idivu 010010 ..... ..... ..... 000 0000 0010 @typea imm 101100 00000 00000 imm:16 +lbu 110000 ..... ..... ..... 0000 000 0000 @typea +lbur 110000 ..... ..... ..... 0100 000 0000 @typea +lbuea 110000 ..... ..... ..... 0001 000 0000 @typea +lbui 111000 ..... ..... ................ @typeb + +lhu 110001 ..... ..... ..... 0000 000 0000 @typea +lhur 110001 ..... ..... ..... 0100 000 0000 @typea +lhuea 110001 ..... ..... ..... 0001 000 0000 @typea +lhui 111001 ..... ..... ................ @typeb + +lw 110010 ..... ..... ..... 0000 000 0000 @typea +lwr 110010 ..... ..... ..... 0100 000 0000 @typea +lwea 110010 ..... ..... ..... 0001 000 0000 @typea +lwx 110010 ..... ..... ..... 1000 000 0000 @typea +lwi 111010 ..... ..... ................ @typeb + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea @@ -123,6 +139,22 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +sb 110100 ..... ..... ..... 0000 000 0000 @typea +sbr 110100 ..... ..... ..... 0100 000 0000 @typea +sbea 110100 ..... ..... ..... 0001 000 0000 @typea +sbi 111100 ..... ..... ................ @typeb + +sh 110101 ..... ..... ..... 0000 000 0000 @typea +shr 110101 ..... ..... ..... 0100 000 0000 @typea +shea 110101 ..... ..... ..... 0001 000 0000 @typea +shi 111101 ..... ..... ................ @typeb + +sw 110110 ..... ..... ..... 0000 000 0000 @typea +swr 110110 ..... ..... ..... 0100 000 0000 @typea +swea 110110 ..... ..... ..... 0001 000 0000 @typea +swx 110110 ..... ..... ..... 1000 000 0000 @typea +swi 111110 ..... ..... ................ @typeb + sext8 100100 ..... ..... 00000 000 0110 0000 @typea0 sext16 100100 ..... ..... 00000 000 0110 0001 @typea0 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a55e110171..d2baa7db0e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -105,6 +105,17 @@ static inline void t_sync_flags(DisasContext *dc) } } +static inline void sync_jmpstate(DisasContext *dc) +{ + if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { + if (dc->jmp == JMP_DIRECT) { + tcg_gen_movi_i32(cpu_btaken, 1); + } + dc->jmp = JMP_INDIRECT; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + } +} + static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); @@ -668,6 +679,419 @@ static bool trans_wdic(DisasContext *dc, arg_wdic *a) DO_TYPEA(xor, false, tcg_gen_xor_i32) DO_TYPEBI(xori, false, tcg_gen_xori_i32) +static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) +{ + TCGv ret = tcg_temp_new(); + + /* If any of the regs is r0, set t to the value of the other reg. */ + if (ra && rb) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]); + tcg_gen_extu_i32_tl(ret, tmp); + tcg_temp_free_i32(tmp); + } else if (ra) { + tcg_gen_extu_i32_tl(ret, cpu_R[ra]); + } else if (rb) { + tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + } else { + tcg_gen_movi_tl(ret, 0); + } + + if ((ra == 1 || rb == 1) && dc->cpu->cfg.stackprot) { + gen_helper_stackprot(cpu_env, ret); + } + return ret; +} + +static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) +{ + TCGv ret = tcg_temp_new(); + + /* If any of the regs is r0, set t to the value of the other reg. */ + if (ra) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[ra], imm); + tcg_gen_extu_i32_tl(ret, tmp); + tcg_temp_free_i32(tmp); + } else { + tcg_gen_movi_tl(ret, (uint32_t)imm); + } + + if (ra == 1 && dc->cpu->cfg.stackprot) { + gen_helper_stackprot(cpu_env, ret); + } + return ret; +} + +static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) +{ + int addr_size = dc->cpu->cfg.addr_size; + TCGv ret = tcg_temp_new(); + + if (addr_size == 32 || ra == 0) { + if (rb) { + tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + } else { + tcg_gen_movi_tl(ret, 0); + } + } else { + if (rb) { + tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]); + } else { + tcg_gen_extu_i32_tl(ret, cpu_R[ra]); + tcg_gen_shli_tl(ret, ret, 32); + } + if (addr_size < 64) { + /* Mask off out of range bits. */ + tcg_gen_andi_i64(ret, ret, MAKE_64BIT_MASK(0, addr_size)); + } + } + return ret; +} + +static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, + int mem_index, bool rev) +{ + TCGv_i32 v; + MemOp size = mop & MO_SIZE; + + /* + * When doing reverse accesses we need to do two things. + * + * 1. Reverse the address wrt endianness. + * 2. Byteswap the data lanes on the way back into the CPU core. + */ + if (rev) { + if (size > MO_8) { + mop ^= MO_BSWAP; + } + if (size < MO_32) { + tcg_gen_xori_tl(addr, addr, 3 - size); + } + } + + t_sync_flags(dc); + sync_jmpstate(dc); + + /* + * Microblaze gives MMU faults priority over faults due to + * unaligned addresses. That's why we speculatively do the load + * into v. If the load succeeds, we verify alignment of the + * address and if that succeeds we write into the destination reg. + */ + v = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); + + /* TODO: Convert to CPUClass::do_unaligned_access. */ + if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { + TCGv_i32 t0 = tcg_const_i32(0); + TCGv_i32 treg = tcg_const_i32(rd); + TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + gen_helper_memalign(cpu_env, addr, treg, t0, tsize); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); + } + + if (rd) { + tcg_gen_mov_i32(cpu_R[rd], v); + } + + tcg_temp_free_i32(v); + tcg_temp_free(addr); + return true; +} + +static bool trans_lbu(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_lbur(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, true); +} + +static bool trans_lbuea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +} + +static bool trans_lbui(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_lhu(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_lhur(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); +} + +static bool trans_lhuea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +} + +static bool trans_lhui(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_lw(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_lwr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); +} + +static bool trans_lwea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +} + +static bool trans_lwi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_lwx(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + + /* lwx does not throw unaligned access errors, so force alignment */ + tcg_gen_andi_tl(addr, addr, ~3); + + t_sync_flags(dc); + sync_jmpstate(dc); + + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_mov_tl(cpu_res_addr, addr); + tcg_temp_free(addr); + + if (arg->rd) { + tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val); + } + + /* No support for AXI exclusive so always clear C */ + tcg_gen_movi_i32(cpu_msr_c, 0); + return true; +} + +static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, + int mem_index, bool rev) +{ + MemOp size = mop & MO_SIZE; + + /* + * When doing reverse accesses we need to do two things. + * + * 1. Reverse the address wrt endianness. + * 2. Byteswap the data lanes on the way back into the CPU core. + */ + if (rev) { + if (size > MO_8) { + mop ^= MO_BSWAP; + } + if (size < MO_32) { + tcg_gen_xori_tl(addr, addr, 3 - size); + } + } + + t_sync_flags(dc); + sync_jmpstate(dc); + + tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); + + /* TODO: Convert to CPUClass::do_unaligned_access. */ + if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { + TCGv_i32 t1 = tcg_const_i32(1); + TCGv_i32 treg = tcg_const_i32(rd); + TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + /* FIXME: if the alignment is wrong, we should restore the value + * in memory. One possible way to achieve this is to probe + * the MMU prior to the memaccess, thay way we could put + * the alignment checks in between the probe and the mem + * access. + */ + gen_helper_memalign(cpu_env, addr, treg, t1, tsize); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); + } + + tcg_temp_free(addr); + return true; +} + +static bool trans_sb(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_sbr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, true); +} + +static bool trans_sbea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +} + +static bool trans_sbi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_sh(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_shr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); +} + +static bool trans_shea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +} + +static bool trans_shi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_sw(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_swr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); +} + +static bool trans_swea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +} + +static bool trans_swi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_swx(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCGLabel *swx_done = gen_new_label(); + TCGLabel *swx_fail = gen_new_label(); + TCGv_i32 tval; + + t_sync_flags(dc); + sync_jmpstate(dc); + + /* swx does not throw unaligned access errors, so force alignment */ + tcg_gen_andi_tl(addr, addr, ~3); + + /* + * Compare the address vs the one we used during lwx. + * On mismatch, the operation fails. On match, addr dies at the + * branch, but we know we can use the equal version in the global. + * In either case, addr is no longer needed. + */ + tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail); + tcg_temp_free(addr); + + /* + * Compare the value loaded during lwx with current contents of + * the reserved location. + */ + tval = tcg_temp_new_i32(); + + tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, + reg_for_write(dc, arg->rd), + dc->mem_index, MO_TEUL); + + tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); + tcg_temp_free_i32(tval); + + /* Success */ + tcg_gen_movi_i32(cpu_msr_c, 0); + tcg_gen_br(swx_done); + + /* Failure */ + gen_set_label(swx_fail); + tcg_gen_movi_i32(cpu_msr_c, 1); + + gen_set_label(swx_done); + + /* + * Prevent the saved address from working again without another ldx. + * Akin to the pseudocode setting reservation = 0. + */ + tcg_gen_movi_tl(cpu_res_addr, -1); + return true; +} + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -887,303 +1311,6 @@ static void dec_msr(DisasContext *dc) } } -static inline void sync_jmpstate(DisasContext *dc) -{ - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(cpu_btaken, 1); - } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); - } -} - -static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) -{ - /* Should be set to true if r1 is used by loadstores. */ - bool stackprot = false; - TCGv_i32 t32; - - /* All load/stores use ra. */ - if (dc->ra == 1 && dc->cpu->cfg.stackprot) { - stackprot = true; - } - - /* Treat the common cases first. */ - if (!dc->type_b) { - if (ea) { - int addr_size = dc->cpu->cfg.addr_size; - - if (addr_size == 32) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); - return; - } - - tcg_gen_concat_i32_i64(t, cpu_R[dc->rb], cpu_R[dc->ra]); - if (addr_size < 64) { - /* Mask off out of range bits. */ - tcg_gen_andi_i64(t, t, MAKE_64BIT_MASK(0, addr_size)); - } - return; - } - - /* If any of the regs is r0, set t to the value of the other reg. */ - if (dc->ra == 0) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); - return; - } else if (dc->rb == 0) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->ra]); - return; - } - - if (dc->rb == 1 && dc->cpu->cfg.stackprot) { - stackprot = true; - } - - t32 = tcg_temp_new_i32(); - tcg_gen_add_i32(t32, cpu_R[dc->ra], cpu_R[dc->rb]); - tcg_gen_extu_i32_tl(t, t32); - tcg_temp_free_i32(t32); - - if (stackprot) { - gen_helper_stackprot(cpu_env, t); - } - return; - } - /* Immediate. */ - t32 = tcg_temp_new_i32(); - tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); - tcg_gen_extu_i32_tl(t, t32); - tcg_temp_free_i32(t32); - - if (stackprot) { - gen_helper_stackprot(cpu_env, t); - } - return; -} - -static void dec_load(DisasContext *dc) -{ - TCGv_i32 v; - TCGv addr; - unsigned int size; - bool rev = false, ex = false, ea = false; - int mem_index = dc->mem_index; - MemOp mop; - - mop = dc->opcode & 3; - size = 1 << mop; - if (!dc->type_b) { - ea = extract32(dc->ir, 7, 1); - rev = extract32(dc->ir, 9, 1); - ex = extract32(dc->ir, 10, 1); - } - mop |= MO_TE; - if (rev) { - mop ^= MO_BSWAP; - } - - if (trap_illegal(dc, size > 4)) { - return; - } - - if (trap_userspace(dc, ea)) { - return; - } - - t_sync_flags(dc); - addr = tcg_temp_new(); - compute_ldst_addr(dc, ea, addr); - /* Extended addressing bypasses the MMU. */ - mem_index = ea ? MMU_NOMMU_IDX : mem_index; - - /* - * When doing reverse accesses we need to do two things. - * - * 1. Reverse the address wrt endianness. - * 2. Byteswap the data lanes on the way back into the CPU core. - */ - if (rev && size != 4) { - /* Endian reverse the address. t is addr. */ - switch (size) { - case 1: - { - tcg_gen_xori_tl(addr, addr, 3); - break; - } - - case 2: - /* 00 -> 10 - 10 -> 00. */ - tcg_gen_xori_tl(addr, addr, 2); - break; - default: - cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); - break; - } - } - - /* lwx does not throw unaligned access errors, so force alignment */ - if (ex) { - tcg_gen_andi_tl(addr, addr, ~3); - } - - /* If we get a fault on a dslot, the jmpstate better be in sync. */ - sync_jmpstate(dc); - - /* Verify alignment if needed. */ - /* - * Microblaze gives MMU faults priority over faults due to - * unaligned addresses. That's why we speculatively do the load - * into v. If the load succeeds, we verify alignment of the - * address and if that succeeds we write into the destination reg. - */ - v = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); - - if (dc->cpu->cfg.unaligned_exceptions && size > 1) { - TCGv_i32 t0 = tcg_const_i32(0); - TCGv_i32 treg = tcg_const_i32(dc->rd); - TCGv_i32 tsize = tcg_const_i32(size - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_helper_memalign(cpu_env, addr, treg, t0, tsize); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); - } - - if (ex) { - tcg_gen_mov_tl(cpu_res_addr, addr); - tcg_gen_mov_i32(cpu_res_val, v); - } - if (dc->rd) { - tcg_gen_mov_i32(cpu_R[dc->rd], v); - } - tcg_temp_free_i32(v); - - if (ex) { /* lwx */ - /* no support for AXI exclusive so always clear C */ - tcg_gen_movi_i32(cpu_msr_c, 0); - } - - tcg_temp_free(addr); -} - -static void dec_store(DisasContext *dc) -{ - TCGv addr; - TCGLabel *swx_skip = NULL; - unsigned int size; - bool rev = false, ex = false, ea = false; - int mem_index = dc->mem_index; - MemOp mop; - - mop = dc->opcode & 3; - size = 1 << mop; - if (!dc->type_b) { - ea = extract32(dc->ir, 7, 1); - rev = extract32(dc->ir, 9, 1); - ex = extract32(dc->ir, 10, 1); - } - mop |= MO_TE; - if (rev) { - mop ^= MO_BSWAP; - } - - if (trap_illegal(dc, size > 4)) { - return; - } - - trap_userspace(dc, ea); - - t_sync_flags(dc); - /* If we get a fault on a dslot, the jmpstate better be in sync. */ - sync_jmpstate(dc); - /* SWX needs a temp_local. */ - addr = ex ? tcg_temp_local_new() : tcg_temp_new(); - compute_ldst_addr(dc, ea, addr); - /* Extended addressing bypasses the MMU. */ - mem_index = ea ? MMU_NOMMU_IDX : mem_index; - - if (ex) { /* swx */ - TCGv_i32 tval; - - /* swx does not throw unaligned access errors, so force alignment */ - tcg_gen_andi_tl(addr, addr, ~3); - - tcg_gen_movi_i32(cpu_msr_c, 1); - swx_skip = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); - - /* - * Compare the value loaded at lwx with current contents of - * the reserved location. - */ - tval = tcg_temp_new_i32(); - - tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val, - cpu_R[dc->rd], mem_index, - mop); - - tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); - tcg_gen_movi_i32(cpu_msr_c, 0); - tcg_temp_free_i32(tval); - } - - if (rev && size != 4) { - /* Endian reverse the address. t is addr. */ - switch (size) { - case 1: - { - tcg_gen_xori_tl(addr, addr, 3); - break; - } - - case 2: - /* 00 -> 10 - 10 -> 00. */ - /* Force addr into the temp. */ - tcg_gen_xori_tl(addr, addr, 2); - break; - default: - cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); - break; - } - } - - if (!ex) { - tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop); - } - - /* Verify alignment if needed. */ - if (dc->cpu->cfg.unaligned_exceptions && size > 1) { - TCGv_i32 t1 = tcg_const_i32(1); - TCGv_i32 treg = tcg_const_i32(dc->rd); - TCGv_i32 tsize = tcg_const_i32(size - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - /* FIXME: if the alignment is wrong, we should restore the value - * in memory. One possible way to achieve this is to probe - * the MMU prior to the memaccess, thay way we could put - * the alignment checks in between the probe and the mem - * access. - */ - gen_helper_memalign(cpu_env, addr, treg, t1, tsize); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); - } - - if (ex) { - gen_set_label(swx_skip); - } - - tcg_temp_free(addr); -} - static inline void eval_cc(DisasContext *dc, unsigned int cc, TCGv_i32 d, TCGv_i32 a) { @@ -1491,8 +1618,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_LD, dec_load}, - {DEC_ST, dec_store}, {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, From patchwork Mon Aug 31 16:05:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248804 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3457965ilg; Mon, 31 Aug 2020 09:29:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwHZIZr2QjStBTVKT7x3OCgI++tnSW1mMN3AoUAhVm1LmoF5C661EJBP0McuQd5+3PMA8RL X-Received: by 2002:a25:c748:: with SMTP id w69mr3173921ybe.355.1598891342612; Mon, 31 Aug 2020 09:29:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891342; cv=none; d=google.com; s=arc-20160816; b=kOhlkZf51rY6xT3cJbxLk0dacoGeADPOrfnoriX9KjBQ2IJHIWnNpUQpLtiukKW55B eOLJ6kdIQ76jiIffDuglHPUvddwnBUHMcahelyTc7xMgrCj9EUCtF5bD9t701dzCYkJw jnLBHRJgI8ngpHAtTnNHk4zoHOA66xKMauqH1z+mnAGUZV+St4IPUo8DRLljuCfDhDUR JUrs8QUYI5dMvZWEX0hf6FrU07/nCzVEp5sslEu7rjRsyr2Vw9PqaQaf4Fu/jli4kogt iTkYN79NLoq6m7EOFt84TUl3JDC3BkmEWwc/XBCcm8KruY+CNtEGYU/xqKnLtbj/0cJQ VBzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+YTQPSRa7wIGfMOHKJcDIJtbiajs8gBf9sLY+UjyvJI=; b=hiACyc85UgvrqchUmLYHqSwEI0wgGpAuNR3pcHyezceCopfGHtrM7jhk24G4Aj2egz +vYgvp7PlSs7CVHtNNVDoeBWPKyV8wK+AgIEe1efJ2NjOdS4vw5BgrxOlmDXc9painI0 Y6TXnD2ay0FR6LiLXifg9IBL1lUfnrDiw6SlrvCOD2vpkzpyBVBAN9Wlz4MRymuc+6QN XNXF20Etc56BVkWACiJE3xhuEBu2JDHYSeOtQNeu8pFHZyxmhDRyd78+0ZB6+OrERNIx AVVBoPmz4+SebVqxV0JsSwftWsakOFY9AQuKIiH+TNtjioQhtZLgpjecC39Fy9X1bpSQ NJ7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FpY8A4WE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j11si2181495ybj.287.2020.08.31.09.29.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:29:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FpY8A4WE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmg2-000087-3y for patch@linaro.org; Mon, 31 Aug 2020 12:29:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmL1-0005wH-St for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:19 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:46515) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmL0-00067e-7X for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:19 -0400 Received: by mail-pg1-x543.google.com with SMTP id 31so821210pgy.13 for ; Mon, 31 Aug 2020 09:07:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+YTQPSRa7wIGfMOHKJcDIJtbiajs8gBf9sLY+UjyvJI=; b=FpY8A4WEPbglTlZeEI7EV5gOhMujrXdRoz8G+oo80aWvAyeqpg5MCiWqgF+J9vpiN+ LY9c9J+B0bZnCGkX+SE+U/vttDGxajOd2+Emlh8umLnKsHxlOPYnRAWZpTIda0CyynB6 9+7/SNJm+rrqnt/2ZURP6bha4YiEvRPmpbMFKwl4Gi8t9JY4SOVKAoQmOtvOMTEhGLrd /EkBrVgVKR0i2Mt4QwRs9AHGziA6XDRMnpvy1xpxAqY2n8MflZ6LSE+e8TZCsIVZhMKN zahGDdVyMn0zuOV+q0kB4GQYQBY6Xm2d9qmDVYmjSig9SIRZ7gz0isStbt+0H8QGcVQ/ 5OiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+YTQPSRa7wIGfMOHKJcDIJtbiajs8gBf9sLY+UjyvJI=; b=p64gD2pZ1983popEEitFK3vu/oNsDdqYHrP/jAXR7EohAtxY4Ya3BMYrtPliJHzirM tkzW9eQR668WRZdqcQU0wCA3TQmc6hFid0ms7/torpMaN/8fTS2fl7ZvotH906y3hk3w D0F/7eNlGoCbWj/waRzN2YlQisAeqWcrGG12xxVS0ErLKXl3P3Z0bmQfT+THW0qI3Tmc ha8rwBfEVRJkCjEaMBk76wvtMfd6X4dfpP4t/saJtN/M+HeZWMxDvV4EYRgXZ8AgLoVp 85jfnxvE+NRmaKH7KBAsb5CoM+JN/pGoLs1Gcsb/wTV4iEJRHqQCu0LM4af0JfWXvzdr 1zbA== X-Gm-Message-State: AOAM5330cY5GIG85wHLgHGEzn5GNWzSO0TZeUmo+bb27mE+XrQzgwHFE oDBspeNZUg8oF8HD6jqeHOWvEkYuhVom6g== X-Received: by 2002:a65:568b:: with SMTP id v11mr1749842pgs.396.1598890036570; Mon, 31 Aug 2020 09:07:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 54/76] target/microblaze: Assert no overlap in flags making up tb_flags Date: Mon, 31 Aug 2020 09:05:39 -0700 Message-Id: <20200831160601.833692-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create MSR_TB_MASK. Use it in cpu_get_tb_cpu_state, and check that IFLAGS_TB_MASK does not overlap. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 594501e4e7..2fc7cf26f1 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -261,8 +261,11 @@ struct CPUMBState { #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) #define D_FLAG (1 << 19) /* Bit in ESR. */ + /* TB dependent CPUMBState. */ #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) +#define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE) + uint32_t iflags; #if !defined(CONFIG_USER_ONLY) @@ -372,12 +375,14 @@ typedef MicroBlazeCPU ArchCPU; #include "exec/cpu-all.h" +/* Ensure there is no overlap between the two masks. */ +QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); + static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { *pc = env->pc; - *flags = (env->iflags & IFLAGS_TB_MASK) | - (env->msr & (MSR_UM | MSR_VM | MSR_EE)); + *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); *cs_base = (*flags & IMM_FLAG ? env->imm : 0); } From patchwork Mon Aug 31 16:05:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248807 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3458944ilg; Mon, 31 Aug 2020 09:30:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzNsjB+7arczvy3+9aOoPqad55jgqtSfLpUpOeiRsbKNy9aCIjpJmVcUIRyBZHqOknrPejj X-Received: by 2002:a05:6102:5a:: with SMTP id k26mr1998979vsp.52.1598891430442; Mon, 31 Aug 2020 09:30:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891430; cv=none; d=google.com; s=arc-20160816; b=z0OSdFSNxHeZtb8bTOkWNCTWa0aO2rTJ0ZWwxMgLKYKS5Eo/dHjC6MIyX4YUUqFBOB oTa1D83mxMYvgM6yVp6U90cDOgZ556V2l6IZjYKsp7pSya2X2jwsbJp5ohKo2XeIBnXl JgeOLpEyEW+bLwb9+xJNaCs+So+vlohdQiklni4XkuVZPOa/jESqItYjNnmVUpQTOt+m IsWifFXRS2xMSpcRMSJUiFbHme90/G/gBx4M7qgU8AS0RqGYm5LHQCUOPsXlO2pwqNif UBskCWOPo8F1UePHpVOmBWAXbr9mc0ccxJq/MVO0050PYUucL7rYifP+v55f7x8CF+yT uqCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9yukNREp9KLx7ngPQjIPDt7zSrwG6GvjIbptJAOWSaU=; b=LFGLvad6T/wRSNfz2yfbneYc/oOJAWdC3HArdRk9js06A/brxU+GSHyNycF7EoxNkM +6b/tVEVbD4oWWrtBhomHJElKTXDyVwnDUUjtXtw2fBgHumkghOA9eE7ew2BSUMlL1RS Ug9IDvKftdjZjr5jqxJJ2gPXM55DVU0Zbn0hOyX+4+x4iKkm4/X8hfbXAdQSE0/5Zm2o 60sRjUP+St+Kcm6yczG5v5SPBf/zPx2VNn0mcUG7fIuGhUVshCZ+7Mc1Lc1PusoOOSf0 aSevfH4STxj/5Q1nz0Jvano2IJrsZ90W4FsgG6AHqVn9xfqoywVf8vW+zoOrwBGe7EKJ IQfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=S1UuJNZg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It makes sense to keep BIMM with D_FLAG, as they can be written back to iflags at the same time. BIMM_FLAG does not need to be added to IFLAGS_TB_MASK because it does not affect the next TB, only the exception path out of the current TB. Renumber IMM_FLAG, as the value 4 holds no particular significance; pack these two flags at the bottom of the bitfield. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 ++-- target/microblaze/helper.c | 2 +- target/microblaze/translate.c | 12 +++++------- 3 files changed, 8 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 2fc7cf26f1..a5df1fa28f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -231,7 +231,6 @@ typedef struct CPUMBState CPUMBState; struct CPUMBState { uint32_t btaken; uint32_t btarget; - uint32_t bimm; uint32_t imm; uint32_t regs[32]; @@ -253,7 +252,8 @@ struct CPUMBState { uint32_t res_val; /* Internal flags. */ -#define IMM_FLAG 4 +#define IMM_FLAG (1 << 0) +#define BIMM_FLAG (1 << 1) /* MSR_EE (1 << 8) */ /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index f8e2ca12a9..06f4322e09 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -166,7 +166,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* Reexecute the branch. */ env->regs[17] -= 4; /* was the branch immprefixed?. */ - if (env->bimm) { + if (env->iflags & BIMM_FLAG) { env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d2baa7db0e..97a436c8d5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1351,13 +1351,11 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) static void dec_setup_dslot(DisasContext *dc) { - TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)); - - dc->delayed_branch = 2; - dc->tb_flags |= D_FLAG; - - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm)); - tcg_temp_free_i32(tmp); + dc->delayed_branch = 2; + dc->tb_flags |= D_FLAG; + if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + dc->tb_flags |= BIMM_FLAG; + } } static void dec_bcc(DisasContext *dc) From patchwork Mon Aug 31 16:05:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248791 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3453973ilg; Mon, 31 Aug 2020 09:23:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzueirjrVuBrvVPXTCCVv/n7bRhbYo8SVKdcdu1VCRD+/ifhklHqOU2/3tVKtik7gzdZPnj X-Received: by 2002:a25:317:: with SMTP id 23mr3275200ybd.297.1598891020285; Mon, 31 Aug 2020 09:23:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891020; cv=none; d=google.com; s=arc-20160816; b=AvA6qqwvwDIbZUHzz1VJZfYzunr76kQS7S93b1mL1ypR139Cs5xpdFVdQOa4aIplEY Yd8b4njF0e0OmrqwXKa2bd+lp4OhLGby3N2HgUem1uzPIxS3svXF10DeLcuJYkOrbmrz OdnS2H1pEAHtisNbYsMvauu2p3Ku4zOZOo0ZFdyf19OvkRQo1ObmSrADWWgnLfjXmxZj HH+sNuj9mX+NH4d3D3rGHhTKNnObZ8izHCLZpuUHdaNh6/KHuy4Kb8mFd/ArCnWpKWcT Uaq+VytcTGQzFRm84AKz7pu7EnKpfGPW9WwI6RfN4pq2SeeUltAqXbbByaSvItePFEYw oBdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vu1hIGTjP3FaAqDu3kt28iRiwFfoFLPJO2tReGgCbQ0=; b=ICGLysI/NCJ7si+YDeB5sAUVSYPE2x5SFBkSLcoSVu9Gw76v9kFWekju4nR0iZ4NSy DsNmBX6dds0XqrFD/eTqJ3je7URE7Vrc5m0uSWN1P0FUWSS6AU8YGqoWUx0s0Fj6ZINE MIchidhtrgg1O7Z/4MzYgObPuIXzYuTFRjhk0dBymSF+FJ3j+1E4M0dcHnXtBejzL68h b9zVJfjbHI8a8FkHtFmVleTV/s/jGb64ad0iTilC1vfRPm9WpnkFRYhEeNIGrgqSd+PK nIox/HB8Um8LIC9g6BfejkTTAGx2Xf608tyRXo+SjmixjsvZ0PEFiyEK4CPSgEZpcsKc fRGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vf4684yX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org, "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not call cpu_restore_state when no exception will be delivered. This can lead to inconsistent cpu state. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Reported-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index a99c467364..e6dcc79243 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -419,32 +419,33 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - MicroBlazeCPU *cpu; - CPUMBState *env; + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx " physaddr 0x" TARGET_FMT_plx " size %d access type %s\n", addr, physaddr, size, access_type == MMU_INST_FETCH ? "INST_FETCH" : (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE")); - cpu = MICROBLAZE_CPU(cs); - env = &cpu->env; - cpu_restore_state(cs, retaddr, true); if (!(env->msr & MSR_EE)) { return; } - env->ear = addr; if (access_type == MMU_INST_FETCH) { - if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { - env->esr = ESR_EC_INSN_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); + if (!cpu->cfg.iopb_bus_exception) { + return; } + env->esr = ESR_EC_INSN_BUS; } else { - if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { - env->esr = ESR_EC_DATA_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); + if (!cpu->cfg.dopb_bus_exception) { + return; } + env->esr = ESR_EC_DATA_BUS; } + + env->ear = addr; + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, retaddr); } #endif From patchwork Mon Aug 31 16:05:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248810 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3460436ilg; Mon, 31 Aug 2020 09:32:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzEVHp7UnpjdzktBfiE1Q8Qj0ixuON1Eccf0hysZHf/B0RlstCSYz839XzuVvO/o7WfKQaF X-Received: by 2002:a25:7e41:: with SMTP id z62mr3311282ybc.444.1598891547615; Mon, 31 Aug 2020 09:32:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891547; cv=none; d=google.com; s=arc-20160816; b=kKmJTSW0P25OaS/mD1QY4VdQT8f1VEuSg4aFG+3EwMwXxNYJGcsgKf7SW7k3TqI2rr oSt1VTDXzoZ2GAbhvy86jLZZzs02Vxgx4abkQ+wf4RdEicQZoh1jkl5vb637x/9ycn2k tm4P6QPuIfWmhIzMlgh3gH+TnhujeGJP8nPcO4XQvR0etf94L7iWpk0vughuF5yROnzb mdGMff+DJKFg3Z7SFVYAd6g1adQJBNChaclSf84VciRj+FiXyHTLsk33Kd1oizsor7YE bDN+EHBBH98Qhp5fqWiXw6QdOdnh88lhaxlicD92+CmucNGezWk7adjDE5Y+oYbnrVzP R++A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JvfZllGqlVqD0CA01I4iiAGGIf7AsK3G+Mi2JTCVFGs=; b=F2ncorguuXjGiWTeumh5ITtjC1GMY5cBlG4idjos46FLaonRhz+ZP2csNvoS7DmrFO NMNzamPd27yGYORRCrPKGIveDSoFxLFXtRpkLGbqdE74J3i1wepH6eNhPrFIV7eiiIVk C8YY6zzb0OXwevSLYhmIaDgW+UVOnJ+e9pb88ZAaCsx8qYZ0qlxROBvs4BwPuUzqmn98 VmjVaK/ww1GJhq0Rk3pxjAtF/CDIExKhy9AII8E3u1w3cEZhrMJim1ZodTGZgIKXiEEm 7qiM5tM2Y8Ulq+wnUwemTAeEU2PE9o51tpX2d4sOs7WWFflYbLcIDSGWes6ESrEVzBLp VPSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ev6EIxf0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This data is available during exception unwinding, thus we can restore it from there directly, rather than saving it during the TB. Thus we may remove the t_sync_flags() calls in the load/store operations. Note that these calls were missing from the other places where runtime exceptions may be raised, such as idiv and the floating point operations. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 ++ target/microblaze/translate.c | 24 +++++++++++++----------- 2 files changed, 15 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a5df1fa28f..83fadd36a5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -228,6 +228,8 @@ typedef struct CPUMBState CPUMBState; #define STREAM_CONTROL (1 << 3) #define STREAM_NONBLOCK (1 << 4) +#define TARGET_INSN_START_EXTRA_WORDS 1 + struct CPUMBState { uint32_t btaken; uint32_t btarget; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 97a436c8d5..d2ee163294 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; + /* TCG op of the current insn_start. */ + TCGOp *insn_start; + TCGv_i32 r0; bool r0_set; @@ -71,7 +74,7 @@ typedef struct DisasContext { unsigned int cpustate_changed; unsigned int delayed_branch; - unsigned int tb_flags, synced_flags; /* tb dependent flags. */ + unsigned int tb_flags; unsigned int clear_imm; int mem_index; @@ -96,12 +99,11 @@ static int typeb_imm(DisasContext *dc, int x) /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" -static inline void t_sync_flags(DisasContext *dc) +static void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ - if (dc->tb_flags != dc->synced_flags) { - tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); - dc->synced_flags = dc->tb_flags; + if ((dc->tb_flags ^ dc->base.tb->flags) & ~MSR_TB_MASK) { + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & ~MSR_TB_MASK); } } @@ -770,7 +772,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - t_sync_flags(dc); sync_jmpstate(dc); /* @@ -893,7 +894,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - t_sync_flags(dc); sync_jmpstate(dc); tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); @@ -929,7 +929,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - t_sync_flags(dc); sync_jmpstate(dc); tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); @@ -1046,7 +1045,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) TCGLabel *swx_fail = gen_new_label(); TCGv_i32 tval; - t_sync_flags(dc); sync_jmpstate(dc); /* swx does not throw unaligned access errors, so force alignment */ @@ -1655,7 +1653,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) int bound; dc->cpu = cpu; - dc->synced_flags = dc->tb_flags = dc->base.tb->flags; + dc->tb_flags = dc->base.tb->flags; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; @@ -1675,7 +1673,10 @@ static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs) static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) { - tcg_gen_insn_start(dcb->pc_next); + DisasContext *dc = container_of(dcb, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); + dc->insn_start = tcg_last_op(); } static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, @@ -1917,4 +1918,5 @@ void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, target_ulong *data) { env->pc = data[0]; + env->iflags = data[1]; } From patchwork Mon Aug 31 16:05:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248812 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3461382ilg; Mon, 31 Aug 2020 09:33:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyPJVJ4a17HSdFs3TzEFeIKWAaJMPEsy52Ib5eQ7/WLYSlA055Po4ZZWK3MM8fTxFOtZwgF X-Received: by 2002:a67:edca:: with SMTP id e10mr1821151vsp.102.1598891626556; Mon, 31 Aug 2020 09:33:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891626; cv=none; d=google.com; s=arc-20160816; b=THIp8SSoybfqNtBoDZ0A0eMIbMwpIMRmRPd7mjBoAQoJuS+gWd0LlRegBFqbqbMN4K KieVKfP8jC+9dkr2uAfK2xcMaZ2INL5CqafuaYZPbNRHFSWNIeCnox6zJRCtWFKumVty RACPykSQNszpkSziSX8Sw8nTob5wMMdFUvRNW5qprh257tepQc6Ml9IunwZRT0t+H5Jd mRjqrhN1PrRAiAkcMIHNOg5yyhTL/ln3y2Us4z85hH6uix0XQNSrDOfKQiaYJr27BUIq 0/Xdm++sovrMnRx3VcDPOeLT4Cy3PbEQA3gNH4HgiUWeFbtci34DlmTQ1lVs0/65Cu/A lw1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qeeRN7V1Ip0PITMIEYpKMKFZ3d7CJpkC0dYLX2jwgUk=; b=mceRBaNtpQ7eRaVJWcbG7YCmOXoC3WlghhHY3lReZ3xZQazg14KuJEyUaPWwrPresz sjZRnFWnKdzvHzGTrXQx5W197YrOuRuZYFSXvlmeG4O+2uZUPLwGngvPsGdAhyUM/BPt OF6LZyLk7qo4bNZcBoHCUcLJbSv0o1gtfvLIXjRwHdVqpSwSSgP/owMc12BElCTmeb6g BSgYwoIr9LtH92UraTwCTCf5nvmzkbIPyvHMpP6XsCsO4YhFAso/COhYEuVFQ6MLc9/p oufOlQ1BURTbQks+nt9bxj7zZFQggF++q38l8siBGwiy98vmPKL/+0hZjEKP30hLwT5H NSRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fWDvkaHN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" MicroBlaze will shortly need to update a parameter in place. Add an interface to read to match that for write. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d40c925d04..15da46131b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -777,11 +777,26 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) } #endif +static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) +{ + return op->args[arg]; +} + static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) { op->args[arg] = v; } +static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) +{ +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + return tcg_get_insn_param(op, arg); +#else + return tcg_get_insn_param(op, arg * 2) | + (tcg_get_insn_param(op, arg * 2 + 1) << 32); +#endif +} + static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) { #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS From patchwork Mon Aug 31 16:05:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248815 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3462215ilg; Mon, 31 Aug 2020 09:34:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRKX21BG1N5ETs2xbuVLdWjW/BqP6uHrYy+1q9/gPf49RMsnWWOLROJGBBKpAiYF38PVyt X-Received: by 2002:a25:4055:: with SMTP id n82mr3070360yba.168.1598891696364; Mon, 31 Aug 2020 09:34:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891696; cv=none; d=google.com; s=arc-20160816; b=K+L90eva8IMxfXUfV46z57aP+8KDKew5rwtoZ50Bm1npXyS8hpqzu0bA/qTQONjT7J m1LPo/81A1hI8iS7kn0bd4tOhFApC5lXhLoOXuM4tD05rLmxGNObuX8KKWcOFSlawWNG mk6DJGQBZtEAdclpdaGkXahI4FMCqNmoAzUMNgH0t2nylBpS5Mw+SXqyuwXaFxsLbJYA yeCAJe+Kxt4vrKDCrYcBDT1NbtOEneZmVOgOsOSu+XNDwrx7frXHhezqqAyN4UCh7DuY O3+lh9LxjKXCJlEGH3wtsP031tWzY8yc+FMEq8fzAM6CuNtkKIs3sZZT2g3qlGO2DIcF TEaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hPPwhaOv1/f5e78+KPOAqe2Pb1bWVEOSoZwO+mnHc14=; b=lF+uFgRtWy94dWiaH4REbL1pgqtXNabjRj4f/q6X/kz9u/O8coR4hJ1UkGtg2yJG41 IT4d0BTreEnODhgKM6vlUcu3qv0m1+aDo5Bj6v2+Lf5unweEN0Eweah+4+JIgtFLACxD wzdN1go0Ci+Iuj0FTjxvHPjMSzD4N0nQKRt6AmvHtc3xiVRfjPlYmEm83JXS6ZAIO5I+ Yi409kvhJ0ZW/sCHpY8hb2NMucyfJNOrvZFlSlcBYpMNOvoe9XjG7+JDMFQpEnObuON/ MK0vL2+xQZHCZreagCtXkO7do7oh8wHTdDUR+MZ8bCLXSf+d/qh+CjBYh/s7r+VOO4fT s+7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AJuVvrom; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fixes the problem in which unaligned stores succeeded, but then we raised the exception after modifying memory. Store the ESS for the unaligned data access in the iflags for the insn, so that it can be found during unwind. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 10 ++++- target/microblaze/helper.h | 1 - target/microblaze/cpu.c | 1 + target/microblaze/helper.c | 28 ++++++++++++++ target/microblaze/op_helper.c | 21 ---------- target/microblaze/translate.c | 72 +++++++++++++---------------------- 6 files changed, 64 insertions(+), 69 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 83fadd36a5..63b8d93d41 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -79,10 +79,13 @@ typedef struct CPUMBState CPUMBState; /* Exception State Register (ESR) Fields */ #define ESR_DIZ (1<<11) /* Zone Protection */ +#define ESR_W (1<<11) /* Unaligned word access */ #define ESR_S (1<<10) /* Store instruction */ #define ESR_ESS_FSL_OFFSET 5 +#define ESR_ESS_MASK (0x7f << 5) + #define ESR_EC_FSL 0 #define ESR_EC_UNALIGNED_DATA 1 #define ESR_EC_ILLEGAL_OP 2 @@ -256,9 +259,11 @@ struct CPUMBState { /* Internal flags. */ #define IMM_FLAG (1 << 0) #define BIMM_FLAG (1 << 1) -/* MSR_EE (1 << 8) */ +#define ESR_ESS_FLAG (1 << 2) /* indicates ESR_ESS_MASK is present */ +/* MSR_EE (1 << 8) -- these 3 are not in iflags but tb_flags */ /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ +/* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) @@ -330,6 +335,9 @@ struct MicroBlazeCPU { void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index a473c1867b..3980fba797 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -25,7 +25,6 @@ DEF_HELPER_3(mmu_read, i32, env, i32, i32) DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) #endif -DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_2(get, i32, i32, i32) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 1eabf5cc3f..67017ecc33 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -317,6 +317,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = mb_cpu_class_by_name; cc->has_work = mb_cpu_has_work; cc->do_interrupt = mb_cpu_do_interrupt; + cc->do_unaligned_access = mb_cpu_do_unaligned_access; cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 06f4322e09..0e3be251a7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -296,3 +296,31 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return false; } + +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + uint32_t esr, iflags; + + /* Recover the pc and iflags from the corresponding insn_start. */ + cpu_restore_state(cs, retaddr, true); + iflags = cpu->env.iflags; + + qemu_log_mask(CPU_LOG_INT, + "Unaligned access addr=" TARGET_FMT_lx + " pc=%x iflags=%x\n", addr, cpu->env.pc, iflags); + + esr = ESR_EC_UNALIGNED_DATA; + if (likely(iflags & ESR_ESS_FLAG)) { + esr |= iflags & ESR_ESS_MASK; + } else { + qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n"); + } + + cpu->env.ear = addr; + cpu->env.esr = esr; + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit(cs); +} diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index e6dcc79243..4614e99db3 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -365,27 +365,6 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b) return 0; } -void helper_memalign(CPUMBState *env, target_ulong addr, - uint32_t dr, uint32_t wr, - uint32_t mask) -{ - if (addr & mask) { - qemu_log_mask(CPU_LOG_INT, - "unaligned access addr=" TARGET_FMT_lx - " mask=%x, wr=%d dr=r%d\n", - addr, mask, wr, dr); - env->ear = addr; - env->esr = ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) << 5; - if (mask == 3) { - env->esr |= 1 << 11; - } - if (!(env->msr & MSR_EE)) { - return; - } - helper_raise_exception(env, EXCP_HW_EXCP); - } -} - void helper_stackprot(CPUMBState *env, target_ulong addr) { if (addr < env->slr || addr > env->shr) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d2ee163294..597b96ffb3 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -751,10 +751,22 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) return ret; } +static void record_unaligned_ess(DisasContext *dc, int rd, + MemOp size, bool store) +{ + uint32_t iflags = tcg_get_insn_start_param(dc->insn_start, 1); + + iflags |= ESR_ESS_FLAG; + iflags |= rd << 5; + iflags |= store * ESR_S; + iflags |= (size == MO_32) * ESR_W; + + tcg_set_insn_start_param(dc->insn_start, 1, iflags); +} + static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) { - TCGv_i32 v; MemOp size = mop & MO_SIZE; /* @@ -774,34 +786,15 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, sync_jmpstate(dc); - /* - * Microblaze gives MMU faults priority over faults due to - * unaligned addresses. That's why we speculatively do the load - * into v. If the load succeeds, we verify alignment of the - * address and if that succeeds we write into the destination reg. - */ - v = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); - - /* TODO: Convert to CPUClass::do_unaligned_access. */ - if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { - TCGv_i32 t0 = tcg_const_i32(0); - TCGv_i32 treg = tcg_const_i32(rd); - TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_helper_memalign(cpu_env, addr, treg, t0, tsize); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); + if (size > MO_8 && + (dc->tb_flags & MSR_EE) && + dc->cpu->cfg.unaligned_exceptions) { + record_unaligned_ess(dc, rd, size, false); + mop |= MO_ALIGN; } - if (rd) { - tcg_gen_mov_i32(cpu_R[rd], v); - } + tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); - tcg_temp_free_i32(v); tcg_temp_free(addr); return true; } @@ -931,28 +924,15 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, sync_jmpstate(dc); - tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); - - /* TODO: Convert to CPUClass::do_unaligned_access. */ - if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { - TCGv_i32 t1 = tcg_const_i32(1); - TCGv_i32 treg = tcg_const_i32(rd); - TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - /* FIXME: if the alignment is wrong, we should restore the value - * in memory. One possible way to achieve this is to probe - * the MMU prior to the memaccess, thay way we could put - * the alignment checks in between the probe and the mem - * access. - */ - gen_helper_memalign(cpu_env, addr, treg, t1, tsize); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); + if (size > MO_8 && + (dc->tb_flags & MSR_EE) && + dc->cpu->cfg.unaligned_exceptions) { + record_unaligned_ess(dc, rd, size, true); + mop |= MO_ALIGN; } + tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); + tcg_temp_free(addr); return true; } From patchwork Mon Aug 31 16:05:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248818 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3463154ilg; Mon, 31 Aug 2020 09:36:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzimtVm1oziD1iOQew/lpUYSFlxUjJPcwhXJ04okN3EfjGkzSIaKCfq7OLUpNX01lPwKMe1 X-Received: by 2002:a25:1f44:: with SMTP id f65mr3596443ybf.438.1598891772510; Mon, 31 Aug 2020 09:36:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891772; cv=none; d=google.com; s=arc-20160816; b=xi07M13GQbhAPOHfnCqUYIFDt4337uM8Y6AUr5wweh2Bjo4yGl0GV/l+euYy9zYHc9 Dpn86VplBDoOUao62Ky3DCcAS8Qgz+Tp5ovUWTH5vuBH0aKpZT9LJtnXkaSbcEuY4X4h cW3/RP//reH9PzEUrVFaOXBnjquDFTwUb8MpV2wq0q2+54ft05FcqhBg/8gUX0tiQgD6 fQbtFfY7sod3zBpsz5ijJ4DKUUoGYmqUGb7t+PDrIdU9Q4N27omzNlYZjvYrMdWkkG5T 1UzTmZXgfk55SbYXQFBpUWRU/sAT1ZkUT3OSEwxQLSi6CFlzpzof/w8PTIMWX0vHE0X4 CSSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HE8Wik9vttKTZZENz5zVdtMEhiCJ7C/1UlGJaVpED9U=; b=HyJkumsLk3NohSXZyiVdcWXrnVYk65dUcg9BE2kWl6IcjPEZfQ2I3pAcNT3SOW6bwY PWhTtm1HChBGFtrjvvwFYfnfWPlOj8t40uw9WXI01OU6kTjzMCvFlCjVXWdyN92xzS1k PwP589vbPV4OAkcZNiF5gNPsrUO5WJmeFrR5RFzn0YKbM85oc6ZXoYkfsTI1QpRi3Vgw H8kXYDj4/LtnMxSQev2wt8R1ukRkShPo8qyzjUKYEPqvjNDy3PmQQ8Ba5qQWMSQLTWbV +OpXlz5AJZ/AsVz5UIUa3gXtrS8bIS4RV/3FmFhxWUG/VeCkufUY6sc4mHXzQLQrPu72 ZYnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GejGOa5t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j3si8317322ybp.222.2020.08.31.09.36.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:36:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GejGOa5t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34324 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmmx-0006Nw-TT for patch@linaro.org; Mon, 31 Aug 2020 12:36:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmLC-0006Ej-8k for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:30 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:35756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmL8-00068V-LT for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:29 -0400 Received: by mail-pg1-x544.google.com with SMTP id g29so843674pgl.2 for ; Mon, 31 Aug 2020 09:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HE8Wik9vttKTZZENz5zVdtMEhiCJ7C/1UlGJaVpED9U=; b=GejGOa5tD4nNLq3MjRuxcqGWZynkrKKlL80BiRBXfkwhCByzj9HYKafVw5HDHneVKo m1Ndq/hTKE0ouNYm1JaPFF9WwZYSfKdXDktSMHREzWgIiQ/VllYm/mLS8kiCuXHZeRtj Ne8W+RgwkYmVO/Dqqx9otxn+gfhVT6ZuReBqYQ+QBVSjbFWIy/ZF8lK3zs/CE0a++nx8 qZsfLTflRIvAlWrK37g2RJO3hLe0YxDqGDPTy6tPH1eeee9iHpTJ6HjkBYO1PCkY18cH WWzi2kVU5/xSeeI0+VZ1lV4R5PllF+QGkFhbwC0XYP1H3GDK9S9ZmiX71d6c6Mi+vWqG zLaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HE8Wik9vttKTZZENz5zVdtMEhiCJ7C/1UlGJaVpED9U=; b=q4oas1AkJT2/DXTZsCOfHbrQ1bR2k9j6dlBj5FiHxfX6/NPvhyIbSnmSYW8C2n4h2i 19YgPD3GHzP1JxEva07Gl94euN+ewFuKe7LJyMQ4LLkfRqNuoPNTdqkbSeHFs2TSrSCi BgB06MOiUxJqYQr/6pryituqDKoDrkAEd7x6tcsvEDabkAJgH201XBWjm3h9qbNePOP1 5mVLhoXwgJSEniv52M9dQZSG3ijktlTmF20CU0GCkCwmIdj9Q/bDwzKQliVLmbNdAoDC oqDC1dnD4RjPV+Wrs4zlZWzf1XUsREg3qzrkmEMn4rRYg7t7in10+E7L7E2ngEjZ9mOH +SCw== X-Gm-Message-State: AOAM533c6rRrplICqO5gfI7th2icvizO2/LfAn5fbPeh34dL9eWz+FVv PiA/73DTZfsT5p7Ldeb3ollnPKcOHvPVkQ== X-Received: by 2002:a63:b24b:: with SMTP id t11mr1747404pgo.233.1598890044938; Mon, 31 Aug 2020 09:07:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 60/76] target/microblaze: Replace clear_imm with tb_flags_to_set Date: Mon, 31 Aug 2020 09:05:45 -0700 Message-Id: <20200831160601.833692-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This more general update variable will be able to handle delay slots as well. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 597b96ffb3..c0b586f467 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -75,7 +75,7 @@ typedef struct DisasContext { unsigned int cpustate_changed; unsigned int delayed_branch; unsigned int tb_flags; - unsigned int clear_imm; + unsigned int tb_flags_to_set; int mem_index; #define JMP_NOJMP 0 @@ -535,8 +535,7 @@ static bool trans_imm(DisasContext *dc, arg_imm *arg) { dc->ext_imm = arg->imm << 16; tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags |= IMM_FLAG; - dc->clear_imm = 0; + dc->tb_flags_to_set = IMM_FLAG; return true; } @@ -1688,7 +1687,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) (uint32_t)dc->base.pc_next); } - dc->clear_imm = 1; + dc->tb_flags_to_set = 0; + ir = cpu_ldl_code(env, dc->base.pc_next); if (!decode(dc, ir)) { old_decode(dc, ir); @@ -1700,10 +1700,13 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->r0_set = false; } - if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags &= ~IMM_FLAG; + /* Discard the imm global when its contents cannot be used. */ + if ((dc->tb_flags & ~dc->tb_flags_to_set) & IMM_FLAG) { tcg_gen_discard_i32(cpu_imm); } + + dc->tb_flags &= ~IMM_FLAG; + dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; if (dc->delayed_branch && --dc->delayed_branch == 0) { From patchwork Mon Aug 31 16:05:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248821 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3464114ilg; Mon, 31 Aug 2020 09:37:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzNBqB82G5TjuS9x8yyvY1l3Dse4hYoMc3t/VzKEtuMuluK4/cUcb3+lw84ZRVTEYmZ6Iu9 X-Received: by 2002:a25:2d1e:: with SMTP id t30mr3324340ybt.303.1598891860468; Mon, 31 Aug 2020 09:37:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891860; cv=none; d=google.com; s=arc-20160816; b=WxGKiS9jEDFWA0h98moOil3SIS3aDG84y358q9gq3HYNPoQJyF4k3sqkcEicUZEyaG xZ9UGpwq8m35xNrZpXe9BZU6N7oBKqzpGj+1LLxdjRiz6k+IBD2Q0iGsrWlotph4NPRB aAYh2NdbanBumiWnhw7uKPfJbN8e9HIHGgBeYbJTj6gr8zDRNCQqqiHn2kUY27BH4BfW v/FSQZdOdEABmxCMlCFWWBz0T8jdsC+kn7ulFRkQh8qpuslLKcqcadscIhkpbOrJmrLB Qibbq638GdzquvLtsO5P7abb4eBdA7fzHQpZnFhjZX2Ah0x5yLjDooFt3UR8VTAEfRQw E5mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jA1f7A7ZHCufkuLSHghiR/JDH1zZqdVgsEJ9cK+3ePA=; b=VMymZA0eI9p+3RktU26Mxlhr9e1C6EQW7dWeQYpg4+xel4WqE2xkYH6CSJ9Hh/5B12 NT0QHr4fCW/nb9n0QHU0WE8LD+JYHdaX4FQbWk0E8sKI+AQB6A9B+mr+5VfHiaqrGmCt XhSKg80b/192meXWOElClHU/zO18lPxbSljPN+ySm3c/BiU1sIKPBYZsbmdLNSKUC/9c AIHCVQx4sk8YC5E/Z3ECjIElthHnDuiDXZkzHyxNbPMrKNGyA9DaM0+5d5gSnEFIGh90 Sn9vD++irQc9nFozHHZYwuNikUKQJs6yPILMXkOCsn2gVWVNFqXOtO+zB3TIJRdfGmEd lwMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=F3CV60jv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The multi-stage counter can be replaced by clearing D_FLAG, the or'ing in tb_flags_to_set. The jump then happens when D_FLAG is finally cleared. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c0b586f467..811c92d23b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -73,7 +73,6 @@ typedef struct DisasContext { uint16_t imm; unsigned int cpustate_changed; - unsigned int delayed_branch; unsigned int tb_flags; unsigned int tb_flags_to_set; int mem_index; @@ -1328,10 +1327,9 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) static void dec_setup_dslot(DisasContext *dc) { - dc->delayed_branch = 2; - dc->tb_flags |= D_FLAG; + dc->tb_flags_to_set |= D_FLAG; if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags |= BIMM_FLAG; + dc->tb_flags_to_set |= BIMM_FLAG; } } @@ -1343,7 +1341,6 @@ static void dec_bcc(DisasContext *dc) cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); - dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); } @@ -1419,7 +1416,6 @@ static void dec_br(DisasContext *dc) } } - dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); } @@ -1633,8 +1629,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; - dc->delayed_branch = !!(dc->tb_flags & D_FLAG); - dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; + dc->jmp = dc->tb_flags & D_FLAG ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; @@ -1705,11 +1700,11 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) tcg_gen_discard_i32(cpu_imm); } - dc->tb_flags &= ~IMM_FLAG; + dc->tb_flags &= ~(IMM_FLAG | BIMM_FLAG | D_FLAG); dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; - if (dc->delayed_branch && --dc->delayed_branch == 0) { + if (dc->jmp != JMP_NOJMP && !(dc->tb_flags & D_FLAG)) { if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); } @@ -1719,8 +1714,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } - /* Clear the delay slot flag. */ - dc->tb_flags &= ~D_FLAG; dc->base.is_jmp = DISAS_JUMP; } From patchwork Mon Aug 31 16:05:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248822 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3464678ilg; Mon, 31 Aug 2020 09:38:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZL1VwzfJvsG+gFwcXtYDmluKcxRbQ7tdZtdpf+Au2jgmXYCznu3RISqF72qDx59oKQDLQ X-Received: by 2002:a25:1fd5:: with SMTP id f204mr3322109ybf.142.1598891913091; Mon, 31 Aug 2020 09:38:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891913; cv=none; d=google.com; s=arc-20160816; b=1Iuakn7u+nW33CdMlbWOo2BKgFio+rVWZAWqsVQ7VbinrxC3A8qs6TPqQHfF8+F3sK WJWFT/f3FCXdpQr/4gEo/T/pwxXt/lLlFz+ZQTCtEw0I3lNt8jfgJX2MK8a/3fgiqhEw dCrERdb9mu44BMF9/hy6j4sx8tCGUzI7E9EptAd506nMCcNswj7IdsPNjEctB+yR9SaJ EeeRnwVsZUhPnJFXsK1EBia4xCcnMrpcHTv1kCQa6kbahspZWt0IEPZSrhHWmSSguJ7l u5OeENqpfBhNYjt015q+hwvQlXfXfO8ly9SZlL0FScoW73XtwOJza8+n3CMBFbJcwOA7 C28A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0VSksOfKW1ugYJ+R8MPzR710nsFiQJIhTNG7hwTinY4=; b=h+j6y1VkW1M9+XQJu/Ps95kqHM/ff3sohuxWH/l6Ij+PbKRZV2FDfM+K3a1j7ZMcNj /v9nXkjCakKpasV+Ga284ZfGKi7FZsgSBCyg12DYJfcb6ElW/5yVdewpu331hwENZ8xk XPEz5S0EXA/cSxiRsUmPRyL0+OTT2eAfxaFqHfXu9Frpi3o0LSfZ0IuAgdV3eJtxWMuG TWHhIMHw2LPIOInKc6/Ts8PTN2bbruOrDTGkCjGPPg7kBfkUfrybsY/0IstgeYKiGm6q tVVSRxswHiZ0ASk4Y7BN9MY01rAfpbzXsiL4sACK55hfSnLx1wWNUkrzw1V8+HhPJSMX c7Dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="qZw/8raV"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Using lookup_symbol is quite slow; remove that. Decode the various bits of iflags; only show imm, btaken, btarget when they are relevant to iflags. Improve formatting. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 67 +++++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 811c92d23b..3b63fd79e5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1818,41 +1818,56 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; + uint32_t iflags; int i; - if (!env) { - return; - } - - qemu_fprintf(f, "IN: PC=%x %s\n", - env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "imm=%x iflags=%x fsr=%x rbtr=%x\n", - env->msr, env->esr, env->ear, - env->imm, env->iflags, env->fsr, env->btr); - qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", - env->btaken, env->btarget, + qemu_fprintf(f, "pc=0x%08x msr=0x%05x mode=%s(saved=%s) eip=%d ie=%d\n", + env->pc, env->msr, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", (bool)(env->msr & MSR_EIP), (bool)(env->msr & MSR_IE)); - for (i = 0; i < 12; i++) { - qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); - if ((i + 1) % 4 == 0) { - qemu_fprintf(f, "\n"); - } + + iflags = env->iflags; + qemu_fprintf(f, "iflags: 0x%08x", iflags); + if (iflags & IMM_FLAG) { + qemu_fprintf(f, " IMM(0x%08x)", env->imm); + } + if (iflags & BIMM_FLAG) { + qemu_fprintf(f, " BIMM"); + } + if (iflags & D_FLAG) { + qemu_fprintf(f, " D(btaken=%d btarget=0x%08x)", + env->btaken, env->btarget); + } + if (iflags & DRTI_FLAG) { + qemu_fprintf(f, " DRTI"); + } + if (iflags & DRTE_FLAG) { + qemu_fprintf(f, " DRTE"); + } + if (iflags & DRTB_FLAG) { + qemu_fprintf(f, " DRTB"); + } + if (iflags & ESR_ESS_FLAG) { + qemu_fprintf(f, " ESR_ESS(0x%04x)", iflags & ESR_ESS_MASK); + } + + qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n" + "ear=0x%016" PRIx64 " slr=0x%x shr=0x%x\n", + env->esr, env->fsr, env->btr, env->edr, + env->ear, env->slr, env->shr); + + for (i = 0; i < 12; i++) { + qemu_fprintf(f, "rpvr%-2d=%08x%c", + i, env->pvr.regs[i], i % 4 == 3 ? '\n' : ' '); } - /* Registers that aren't modeled are reported as 0 */ - qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " - "rtlblo=0 rtlbhi=0\n", env->edr); - qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { - qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); - if ((i + 1) % 4 == 0) - qemu_fprintf(f, "\n"); - } - qemu_fprintf(f, "\n\n"); + qemu_fprintf(f, "r%2.2d=%08x%c", + i, env->regs[i], i % 4 == 3 ? '\n' : ' '); + } + qemu_fprintf(f, "\n"); } void mb_tcg_init(void) From patchwork Mon Aug 31 16:05:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248805 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3458309ilg; Mon, 31 Aug 2020 09:29:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwDKsZxgxo4r79hy/NIQ27iywKlm1sXsSWz8xrLqvR2a+y1B8Se5gV76e6QQnW1vtUjoKf9 X-Received: by 2002:a67:ee0d:: with SMTP id f13mr1830734vsp.62.1598891372155; Mon, 31 Aug 2020 09:29:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891372; cv=none; d=google.com; s=arc-20160816; b=oJNYmh5hQyQgG6u8Ay5dE1PMfssqR9OZ39c/Acb9w3nEel7HgqFPAds6SsMpHOrv/N W2HxEF0mjjXniCFb4AJ7JJDljJQIF6ozb39hnIo4oQL2mhyMqKYFyag9hf28najz8KSz Ccid0af1dMcAzw2+uTX3A5IZqaTPbg+4y4AnUm9kXOrrAyd7B/OJ+fTggn5V7LniJLD9 GDeaviHKotdfHL+oUwE00wsAItUx5B9dAqF3xY/NBgtmW/MlNtDTLCAcZfCP+kTDzLsq evvZIvhK98/9mgQhltzOv6tAnZ+xTtjLtqqGm8hyTBQPeO0XzlTEGdlNtLj1BBb4P4Sg bG5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GSPxh4SxANPQrDwWc1e6Tl2jupR+kuvykZRFnQlRio0=; b=0uL5m7uZxBwCBngppeymrAkT5jq48UTyTK4ryqEU6f5kxlfC0pS2b195jA7ead3k3A JDJhnkQ5q7ulNTb5pR8V8eRnjz9x/aNhnELLfN4e7ZWYP7QuYmfPwWQ4swnVb0HBCroB xzzIMS8mGYRQ52KXKGj+IojWyQitdgJIJmZQ8td16QMRtI+x3eXQqaBi3bG0Rf6AZso8 0hdH+Tzvbbgd3JskrDR4MFuigCVxnO2QcfR/XuJbIUMlKCJkVkK8X7J/E+clUOF+80dF uEfa7wxhxFyD1qM2PXocLfyE3vo8LLcMmMQDzaZnezHIAVWjK3aPBvTj5htX2D+Jx8/X Z2EA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ApfKIbC4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n12si625241vsr.370.2020.08.31.09.29.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:29:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ApfKIbC4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmgV-0001Kg-EV for patch@linaro.org; Mon, 31 Aug 2020 12:29:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmLF-0006IQ-Al for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:33 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:37630) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmLD-00068x-Ap for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:32 -0400 Received: by mail-pj1-x1033.google.com with SMTP id mw10so28796pjb.2 for ; Mon, 31 Aug 2020 09:07:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GSPxh4SxANPQrDwWc1e6Tl2jupR+kuvykZRFnQlRio0=; b=ApfKIbC46H8iYRd5MhO8HDuWyGgczRwsBMRYc/SWai7Hh4kfVJk5bGA0e98sOKy/ac hDQGRX3I0Sr8mW/qLOEY/c9xyyqw+4bD8JwGkiPOYPOgJpHpMCgcYmT/myvjv253DDlJ JZCfG+UHBDDXvBE4bZJBTGm+xpsVjIBxDrq7w84DXad3rTAiW5muENOq88M/9f8b23qN wZn+OWR3Ig9p1ailZMVsIOwE9saEm5HJiiOkpFMYn44ZdOGjKhYFVtcJ4HWQ864atwq5 bxHVW05KuvPiXESWnKY83UHdBpQA86n/WKZJhDiSvKN4q6W/lQHTjbklX8KNKTPMW0oD 1evA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GSPxh4SxANPQrDwWc1e6Tl2jupR+kuvykZRFnQlRio0=; b=hZ7AzaPya6pMBY+uR7RumT47bFi2Ykix5eWm7QmGhFSTCDLra17W2uQrXRFDMR++Tp 3HlgSy/ndGt1QGjRtg8AIp7f9WURNmPNW481TDmwNpqyCA2wbddZaVlHW73uASXYkH43 H1rG/9VNDiq/jZZoDO4Vyl2iI5iqY4kCbm+OVN6leVZPAYXQquogHAfWNOWkWpTrgIPQ dWB7ZXxqrkLxV/fnRyWzq13r5Zxkvo5MECk0mWQdETG8zdry8j2qDe+j8JkrLXNHBDUm UvBEyrU1zC3uamUIueAw63PQKW5mRETcCt3kaqfk7hf/QHPrCCfAyllBgpOZOX/A+H34 e6lA== X-Gm-Message-State: AOAM531jCTr46S3OcBdDazyc+85wAqHDx1mJRatg1iNW2ZuW+jJivhaV +AhY+sIA5NIuGnv/qBQijlZL+T3ZTypcRQ== X-Received: by 2002:a17:902:6901:: with SMTP id j1mr1591538plk.324.1598890049125; Mon, 31 Aug 2020 09:07:29 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 63/76] target/microblaze: Convert brk and brki to decodetree Date: Mon, 31 Aug 2020 09:05:48 -0700 Message-Id: <20200831160601.833692-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split these out of the normal branch instructions, as they require special handling. Perform the entire operation inline, instead of raising EXCP_BREAK to do the work in mb_cpu_do_interrupt. This fixes a bug in that brki rd, imm, for imm != 0x18 is not supposed to set MSR_BIP. This fixes a bug in that imm == 0 is the reset vector and 0x18 is the debug vector, and neither should raise a tcg exception in system mode. Introduce EXCP_SYSCALL for microblaze-linux-user. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/insns.decode | 11 ++++ linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 10 +-- target/microblaze/translate.c | 107 ++++++++++++++++++------------- 5 files changed, 79 insertions(+), 53 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 63b8d93d41..1528749a0b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -31,7 +31,7 @@ typedef struct CPUMBState CPUMBState; #define EXCP_MMU 1 #define EXCP_IRQ 2 -#define EXCP_BREAK 3 +#define EXCP_SYSCALL 3 /* user-only */ #define EXCP_HW_BREAK 4 #define EXCP_HW_EXCP 5 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 47b92b9cbc..9273a51d20 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -19,7 +19,9 @@ &typea0 rd ra &typea rd ra rb +&typea_br rd rb &typeb rd ra imm +&typeb_br rd imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -30,9 +32,15 @@ # Officially typea, but with rb==0, which is not used. @typea0 ...... rd:5 ra:5 ................ &typea0 +# Officially typea, but with ra as opcode. +@typea_br ...... rd:5 ..... rb:5 ........... &typea_br + # Officially typeb, but any immediate extension is unused. @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb +# Officially typeb, but with ra as opcode. +@typeb_br ...... rd:5 ..... ................ &typeb_br imm=%extimm + # For convenience, extract the two imm_w/imm_s fields, then pack # them back together as "imm". Doing this makes it easiest to # match the required zero at bit 5. @@ -60,6 +68,9 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +brk 100110 ..... 01100 ..... 000 0000 0000 @typea_br +brki 101110 ..... 01100 ................ @typeb_br + bsrl 010001 ..... ..... ..... 000 0000 0000 @typea bsra 010001 ..... ..... ..... 010 0000 0000 @typea bsll 010001 ..... ..... ..... 100 0000 0000 @typea diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 3de99ea311..c3396a6e09 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -48,7 +48,7 @@ void cpu_loop(CPUMBState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_BREAK: + case EXCP_SYSCALL: /* Return address is 4 bytes after the call. */ env->regs[14] += 4; env->pc = env->regs[14]; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 0e3be251a7..1667822fb7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -230,7 +230,6 @@ void mb_cpu_do_interrupt(CPUState *cs) //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; - case EXCP_BREAK: case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); @@ -242,13 +241,8 @@ void mb_cpu_do_interrupt(CPUState *cs) msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); msr |= t; msr |= MSR_BIP; - if (cs->exception_index == EXCP_HW_BREAK) { - env->regs[16] = env->pc; - msr |= MSR_BIP; - env->pc = cpu->cfg.base_vectors + 0x18; - } else { - env->pc = env->btarget; - } + env->regs[16] = env->pc; + env->pc = cpu->cfg.base_vectors + 0x18; mb_cpu_write_msr(env, msr); break; default: diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3b63fd79e5..1c772b95d9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1068,6 +1068,65 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) return true; } +static bool trans_brk(DisasContext *dc, arg_typea_br *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb)); + if (arg->rd) { + tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); + } + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP); + tcg_gen_movi_tl(cpu_res_addr, -1); + + dc->base.is_jmp = DISAS_UPDATE; + return true; +} + +static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) +{ + uint32_t imm = arg->imm; + + if (trap_userspace(dc, imm != 0x8 && imm != 0x18)) { + return true; + } + tcg_gen_movi_i32(cpu_pc, imm); + if (arg->rd) { + tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); + } + tcg_gen_movi_tl(cpu_res_addr, -1); + +#ifdef CONFIG_USER_ONLY + switch (imm) { + case 0x8: /* syscall trap */ + gen_raise_exception_sync(dc, EXCP_SYSCALL); + break; + case 0x18: /* debug trap */ + gen_raise_exception_sync(dc, EXCP_DEBUG); + break; + default: /* eliminated with trap_userspace check */ + g_assert_not_reached(); + } +#else + uint32_t msr_to_set = 0; + + if (imm != 0x18) { + msr_to_set |= MSR_BIP; + } + if (imm == 0x8 || imm == 0x18) { + /* MSR_UM and MSR_VM are in tb_flags, so we know their value. */ + msr_to_set |= (dc->tb_flags & (MSR_UM | MSR_VM)) << 1; + tcg_gen_andi_i32(cpu_msr, cpu_msr, + ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM)); + } + tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set); + dc->base.is_jmp = DISAS_UPDATE; +#endif + + return true; +} + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -1359,6 +1418,7 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { unsigned int dslot, link, abs, mbar; + uint32_t add_pc; dslot = dc->ir & (1 << 20); abs = dc->ir & (1 << 19); @@ -1401,21 +1461,6 @@ static void dec_br(DisasContext *dc) return; } - if (abs && link && !dslot) { - if (dc->type_b) { - /* BRKI */ - uint32_t imm = dec_alu_typeb_imm(dc); - if (trap_userspace(dc, imm != 8 && imm != 0x18)) { - return; - } - } else { - /* BRK */ - if (trap_userspace(dc, true)) { - return; - } - } - } - if (dslot) { dec_setup_dslot(dc); } @@ -1423,38 +1468,14 @@ static void dec_br(DisasContext *dc) tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); } - if (abs) { - if (dc->type_b) { - uint32_t dest = dec_alu_typeb_imm(dc); - - dc->jmp = JMP_DIRECT; - dc->jmp_pc = dest; - tcg_gen_movi_i32(cpu_btarget, dest); - if (link && !dslot) { - switch (dest) { - case 8: - case 0x18: - gen_raise_exception_sync(dc, EXCP_BREAK); - break; - case 0: - gen_raise_exception_sync(dc, EXCP_DEBUG); - break; - } - } - } else { - dc->jmp = JMP_INDIRECT; - tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); - if (link && !dslot) { - gen_raise_exception_sync(dc, EXCP_BREAK); - } - } - } else if (dc->type_b) { + add_pc = abs ? 0 : dc->base.pc_next; + if (dc->type_b) { dc->jmp = JMP_DIRECT; - dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); + dc->jmp_pc = add_pc + dec_alu_typeb_imm(dc); tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); } tcg_gen_movi_i32(cpu_btaken, 1); } From patchwork Mon Aug 31 16:05:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248808 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3459061ilg; Mon, 31 Aug 2020 09:30:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfxVgSzAXyWs4kckA9dAXgY3ncrO0FfTaef2eUpKTfjKd2TS42MXWkcwt0UBpoIC2xnvyW X-Received: by 2002:a05:6102:2403:: with SMTP id j3mr1993032vsi.193.1598891438401; Mon, 31 Aug 2020 09:30:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891438; cv=none; d=google.com; s=arc-20160816; b=AVvo6+Z2sbYwoRFm7rAvc0s6Wm2qPsmV+3M0JsiTC36U2aWaXPItAcHx76YWaAhh6+ sJNS601kZcg2m19zU5WPx4gNRuxcLnNg4YqKixg3jRbNZIKb56+QMMgFivIL7h5mQ5vl 4H++e2b3nC8NBM9XouwB0KZmTFAWuR4+5oVzZB3WQYmTL8kLvIycfGOJ12Y9D/DUdgas SCY8m0v6JUUQMJsRNynfjtUnB5Jl2QbPtRfEe/wP45cz02emjUmsnNMr7opdDrz3CAyB DUN8ryiJB5n884cyv++nXhZgdpzIMxjLrBvlu5dXVKnlYkVsk/ECT+X2NECWR9HQvPK8 U/Pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NQ0LfAVoBPployk6kB6YiHjM59FX58JiRnl2u3IyKWs=; b=mu1uOVv28Mi+UoJ1JlYQT6EBJkiq8tPqAF7+w5GR1m+IrkiO27FeVMEA6ss8CMpmiE qXf8QfVlzigOtVE7U1CeeqF88r9SdRW7waaXzH57JeD63sQNpvbuPqH059TlaBwpIXoI pe+IprIFYYfWmEbFuVHcn6TJpftMGVUqid0lBFUbL2AlS/0zk9hNhiPVuiMw41joBvnA XEplBU3OregEOTvXhAI8bUYUdu1ANEwRTYr7VkpgTtLbJ7ilr3Zxlas4wue7ee0p+bbG TXjhzIgnO8BYsxtQ0LepRrGisGX6G8xTcOfc5fXuf4bJkLABKv9p26AIY+W1xvivX040 yoBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oDqGgh9v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split this out of the normal branch instructions, as it requires special handling. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 2 + target/microblaze/translate.c | 85 +++++++++++++++++++--------------- 2 files changed, 49 insertions(+), 38 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 9273a51d20..8eba47d90c 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -127,6 +127,8 @@ lwea 110010 ..... ..... ..... 0001 000 0000 @typea lwx 110010 ..... ..... ..... 1000 000 0000 @typea lwi 111010 ..... ..... ................ @typeb +mbar 101110 imm:5 00010 0000 0000 0000 0100 + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 1c772b95d9..832cf85c64 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1127,6 +1127,52 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) return true; } +static bool trans_mbar(DisasContext *dc, arg_mbar *arg) +{ + int mbar_imm = arg->imm; + + /* Data access memory barrier. */ + if ((mbar_imm & 2) == 0) { + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + } + + /* Sleep. */ + if (mbar_imm & 16) { + TCGv_i32 tmp_1; + + if (trap_userspace(dc, true)) { + /* Sleep is a privileged instruction. */ + return true; + } + + t_sync_flags(dc); + + tmp_1 = tcg_const_i32(1); + tcg_gen_st_i32(tmp_1, cpu_env, + -offsetof(MicroBlazeCPU, env) + +offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp_1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); + + gen_raise_exception(dc, EXCP_HLT); + } + + /* + * If !(mbar_imm & 1), this is an instruction access memory barrier + * and we need to end the TB so that we recognize self-modified + * code immediately. + * + * However, there are some data mbars that need the TB break + * (and return to main loop) to recognize interrupts right away. + * E.g. recognizing a change to an interrupt controller register. + * + * Therefore, choose to end the TB always. + */ + dc->cpustate_changed = 1; + return true; +} + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -1417,50 +1463,13 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { - unsigned int dslot, link, abs, mbar; + unsigned int dslot, link, abs; uint32_t add_pc; dslot = dc->ir & (1 << 20); abs = dc->ir & (1 << 19); link = dc->ir & (1 << 18); - /* Memory barrier. */ - mbar = (dc->ir >> 16) & 31; - if (mbar == 2 && dc->imm == 4) { - uint16_t mbar_imm = dc->rd; - - /* Data access memory barrier. */ - if ((mbar_imm & 2) == 0) { - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); - } - - /* mbar IMM & 16 decodes to sleep. */ - if (mbar_imm & 16) { - TCGv_i32 tmp_1; - - if (trap_userspace(dc, true)) { - /* Sleep is a privileged instruction. */ - return; - } - - t_sync_flags(dc); - - tmp_1 = tcg_const_i32(1); - tcg_gen_st_i32(tmp_1, cpu_env, - -offsetof(MicroBlazeCPU, env) - +offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp_1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - - gen_raise_exception(dc, EXCP_HLT); - return; - } - /* Break the TB. */ - dc->cpustate_changed = 1; - return; - } - if (dslot) { dec_setup_dslot(dc); } From patchwork Mon Aug 31 16:05:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248795 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3455071ilg; Mon, 31 Aug 2020 09:25:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzcgSVwnzatUTXQ0aXsltlVzbW0ZuPLjNVDLktP6y3hwKDOyNNUi9F66B4xxiD6u7Pi4lq5 X-Received: by 2002:a25:e791:: with SMTP id e139mr3457628ybh.67.1598891117805; Mon, 31 Aug 2020 09:25:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891117; cv=none; d=google.com; s=arc-20160816; b=cS4Dq9/nZzPAwKEOfaIgejo9pGlahvc61q4xMEri8TwOVFs3IyD48/7GIL7Bk/EImg vLlG/cpD/q3XDGnhMQJ0dyZR6rCV31Jv/xY+sZ7kSA2UccGtPwmA5RBH2cra26sfNEzG ofUqfcjMutRqSV1UQuVViB1lgtAcKRduKUPNAe7EKNiGVz6H2nN+izlKeFfqUNiedUAh o6G0VXEpERo0uthahrIGW09Fs2WArVlBdZLBXFQN9WsfT7DWUR33/LlzyJX+0i46TMnB xRqGz98nCPl23QZGhyE3uDz+ImBrkHAWhZPwIhd4zAYotM7N7IrY3+SPlZwxuNTPdEOu +kOA== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the btaken variable, and simplify things by always computing the full branch destination into btarget. This avoids all need for sync_jmpstate(). Retain the direct branch behaviour by remembering the jump destination in jmp_dest, discarding btarget. In the normal case, where the branch delay slot cannot trap (e.g. arithmetic), tcg will remove the computation into btarget, leaving us with just the tcg direct branching at the end. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/translate.c | 192 ++++++++++++++-------------------- 2 files changed, 79 insertions(+), 117 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 1528749a0b..4298f242a6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -234,8 +234,8 @@ typedef struct CPUMBState CPUMBState; #define TARGET_INSN_START_EXTRA_WORDS 1 struct CPUMBState { - uint32_t btaken; - uint32_t btarget; + uint32_t bvalue; /* TCG temporary, only valid during a TB */ + uint32_t btarget; /* Full resolved branch destination */ uint32_t imm; uint32_t regs[32]; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 832cf85c64..1545974669 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -45,7 +45,7 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i32 cpu_msr_c; static TCGv_i32 cpu_imm; -static TCGv_i32 cpu_btaken; +static TCGv_i32 cpu_bvalue; static TCGv_i32 cpu_btarget; static TCGv_i32 cpu_iflags; static TCGv cpu_res_addr; @@ -77,12 +77,11 @@ typedef struct DisasContext { unsigned int tb_flags_to_set; int mem_index; -#define JMP_NOJMP 0 -#define JMP_DIRECT 1 -#define JMP_DIRECT_CC 2 -#define JMP_INDIRECT 3 - unsigned int jmp; - uint32_t jmp_pc; + /* Condition under which to jump, including NEVER and ALWAYS. */ + TCGCond jmp_cond; + + /* Immediate branch-taken destination, or -1 for indirect. */ + uint32_t jmp_dest; int abort_at_next_insn; } DisasContext; @@ -106,17 +105,6 @@ static void t_sync_flags(DisasContext *dc) } } -static inline void sync_jmpstate(DisasContext *dc) -{ - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(cpu_btaken, 1); - } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); - } -} - static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); @@ -782,8 +770,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -885,8 +871,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - sync_jmpstate(dc); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); tcg_gen_mov_tl(cpu_res_addr, addr); tcg_temp_free(addr); @@ -920,8 +904,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -1023,8 +1005,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) TCGLabel *swx_fail = gen_new_label(); TCGv_i32 tval; - sync_jmpstate(dc); - /* swx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); @@ -1392,44 +1372,6 @@ static void dec_msr(DisasContext *dc) } } -static inline void eval_cc(DisasContext *dc, unsigned int cc, - TCGv_i32 d, TCGv_i32 a) -{ - static const int mb_to_tcg_cc[] = { - [CC_EQ] = TCG_COND_EQ, - [CC_NE] = TCG_COND_NE, - [CC_LT] = TCG_COND_LT, - [CC_LE] = TCG_COND_LE, - [CC_GE] = TCG_COND_GE, - [CC_GT] = TCG_COND_GT, - }; - - switch (cc) { - case CC_EQ: - case CC_NE: - case CC_LT: - case CC_LE: - case CC_GE: - case CC_GT: - tcg_gen_setcondi_i32(mb_to_tcg_cc[cc], d, a, 0); - break; - default: - cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); - break; - } -} - -static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) -{ - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, - cpu_btaken, zero, - pc_true, pc_false); - - tcg_temp_free_i32(zero); -} - static void dec_setup_dslot(DisasContext *dc) { dc->tb_flags_to_set |= D_FLAG; @@ -1440,8 +1382,17 @@ static void dec_setup_dslot(DisasContext *dc) static void dec_bcc(DisasContext *dc) { + static const TCGCond mb_to_tcg_cc[] = { + [CC_EQ] = TCG_COND_EQ, + [CC_NE] = TCG_COND_NE, + [CC_LT] = TCG_COND_LT, + [CC_LE] = TCG_COND_LE, + [CC_GE] = TCG_COND_GE, + [CC_GT] = TCG_COND_GT, + }; unsigned int cc; unsigned int dslot; + TCGv_i32 zero, next; cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); @@ -1450,15 +1401,29 @@ static void dec_bcc(DisasContext *dc) dec_setup_dslot(dc); } + dc->jmp_cond = mb_to_tcg_cc[cc]; + + /* Cache the condition register in cpu_bvalue across any delay slot. */ + tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]); + + /* Store the branch taken destination into btarget. */ if (dc->type_b) { - dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb), + dc->base.pc_next); } - eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); + + /* Compute the final destination into btarget. */ + zero = tcg_const_i32(0); + next = tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4); + tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, + reg_for_read(dc, dc->ra), zero, + cpu_btarget, next); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(next); } static void dec_br(DisasContext *dc) @@ -1479,14 +1444,13 @@ static void dec_br(DisasContext *dc) add_pc = abs ? 0 : dc->base.pc_next; if (dc->type_b) { - dc->jmp = JMP_DIRECT; - dc->jmp_pc = add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest = add_pc + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp = JMP_INDIRECT; + dc->jmp_dest = -1; tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); } - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond = TCG_COND_ALWAYS; } static inline void do_rti(DisasContext *dc) @@ -1567,8 +1531,8 @@ static void dec_rts(DisasContext *dc) dc->tb_flags |= DRTE_FLAG; } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond = TCG_COND_ALWAYS; + dc->jmp_dest = -1; tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } @@ -1659,13 +1623,14 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; - dc->jmp = dc->tb_flags & D_FLAG ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; dc->mem_index = cpu_mmu_index(&cpu->env, false); + dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER; + dc->jmp_dest = -1; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1734,14 +1699,12 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; - if (dc->jmp != JMP_NOJMP && !(dc->tb_flags & D_FLAG)) { + if (dc->jmp_cond != TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); - } - if (dc->tb_flags & DRTB_FLAG) { + } else if (dc->tb_flags & DRTB_FLAG) { do_rtb(dc); - } - if (dc->tb_flags & DRTE_FLAG) { + } else if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } dc->base.is_jmp = DISAS_JUMP; @@ -1766,19 +1729,13 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) } t_sync_flags(dc); - if (dc->tb_flags & D_FLAG) { - sync_jmpstate(dc); - dc->jmp = JMP_NOJMP; - } switch (dc->base.is_jmp) { case DISAS_TOO_MANY: - assert(dc->jmp == JMP_NOJMP); gen_goto_tb(dc, 0, dc->base.pc_next); return; case DISAS_UPDATE: - assert(dc->jmp == JMP_NOJMP); if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { @@ -1787,35 +1744,41 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) return; case DISAS_JUMP: - switch (dc->jmp) { - case JMP_INDIRECT: - { - TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); + if (dc->jmp_dest != -1 && !cs->singlestep_enabled) { + /* Direct jump. */ + tcg_gen_discard_i32(cpu_btarget); - if (unlikely(cs->singlestep_enabled)) { - gen_raise_exception(dc, EXCP_DEBUG); - } else { - tcg_gen_exit_tb(NULL, 0); - } - } - return; + if (dc->jmp_cond != TCG_COND_ALWAYS) { + /* Conditional direct jump. */ + TCGLabel *taken = gen_new_label(); + TCGv_i32 tmp = tcg_temp_new_i32(); - case JMP_DIRECT_CC: - { - TCGLabel *l1 = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + /* + * Copy bvalue to a temp now, so we can discard bvalue. + * This can avoid writing bvalue to memory when the + * delay slot cannot raise an exception. + */ + tcg_gen_mov_i32(tmp, cpu_bvalue); + tcg_gen_discard_i32(cpu_bvalue); + + tcg_gen_brcondi_i32(dc->jmp_cond, tmp, 0, taken); gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); + gen_set_label(taken); } - /* fall through */ - - case JMP_DIRECT: - gen_goto_tb(dc, 0, dc->jmp_pc); + gen_goto_tb(dc, 0, dc->jmp_dest); return; } - /* fall through */ + + /* Indirect jump (or direct jump w/ singlestep) */ + tcg_gen_mov_i32(cpu_pc, cpu_btarget); + tcg_gen_discard_i32(cpu_btarget); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; default: g_assert_not_reached(); @@ -1867,8 +1830,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " BIMM"); } if (iflags & D_FLAG) { - qemu_fprintf(f, " D(btaken=%d btarget=0x%08x)", - env->btaken, env->btarget); + qemu_fprintf(f, " D(btarget=0x%08x)", env->btarget); } if (iflags & DRTI_FLAG) { qemu_fprintf(f, " DRTI"); @@ -1918,7 +1880,7 @@ void mb_tcg_init(void) SP(msr_c), SP(imm), SP(iflags), - SP(btaken), + SP(bvalue), SP(btarget), SP(res_val), }; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 14 ++++++ target/microblaze/translate.c | 87 +++++++++++++++++++--------------- 2 files changed, 63 insertions(+), 38 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 8eba47d90c..340dd999b6 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -68,6 +68,20 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +br 100110 ..... 00000 ..... 000 0000 0000 @typea_br +bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br +brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br +brad 100110 ..... 11000 ..... 000 0000 0000 @typea_br +brld 100110 ..... 10100 ..... 000 0000 0000 @typea_br +brald 100110 ..... 11100 ..... 000 0000 0000 @typea_br + +bri 101110 ..... 00000 ................ @typeb_br +brai 101110 ..... 01000 ................ @typeb_br +brid 101110 ..... 10000 ................ @typeb_br +braid 101110 ..... 11000 ................ @typeb_br +brlid 101110 ..... 10100 ................ @typeb_br +bralid 101110 ..... 11100 ................ @typeb_br + brk 100110 ..... 01100 ..... 000 0000 0000 @typea_br brki 101110 ..... 01100 ................ @typeb_br diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 1545974669..5c6e6e599e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1048,6 +1048,53 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) return true; } +static void setup_dslot(DisasContext *dc, bool type_b) +{ + dc->tb_flags_to_set |= D_FLAG; + if (type_b && (dc->tb_flags & IMM_FLAG)) { + dc->tb_flags_to_set |= BIMM_FLAG; + } +} + +static bool do_branch(DisasContext *dc, int dest_rb, int dest_imm, + bool delay, bool abs, int link) +{ + uint32_t add_pc; + + if (delay) { + setup_dslot(dc, dest_rb < 0); + } + + if (link) { + tcg_gen_movi_i32(cpu_R[link], dc->base.pc_next); + } + + /* Store the branch taken destination into btarget. */ + add_pc = abs ? 0 : dc->base.pc_next; + if (dest_rb > 0) { + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], add_pc); + } else { + dc->jmp_dest = add_pc + dest_imm; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); + } + dc->jmp_cond = TCG_COND_ALWAYS; + return true; +} + +#define DO_BR(NAME, NAMEI, DELAY, ABS, LINK) \ + static bool trans_##NAME(DisasContext *dc, arg_typea_br *arg) \ + { return do_branch(dc, arg->rb, 0, DELAY, ABS, LINK ? arg->rd : 0); } \ + static bool trans_##NAMEI(DisasContext *dc, arg_typeb_br *arg) \ + { return do_branch(dc, -1, arg->imm, DELAY, ABS, LINK ? arg->rd : 0); } + +DO_BR(br, bri, false, false, false) +DO_BR(bra, brai, false, true, false) +DO_BR(brd, brid, true, false, false) +DO_BR(brad, braid, true, true, false) +DO_BR(brld, brlid, true, false, true) +DO_BR(brald, bralid, true, true, true) + static bool trans_brk(DisasContext *dc, arg_typea_br *arg) { if (trap_userspace(dc, true)) { @@ -1372,14 +1419,6 @@ static void dec_msr(DisasContext *dc) } } -static void dec_setup_dslot(DisasContext *dc) -{ - dc->tb_flags_to_set |= D_FLAG; - if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags_to_set |= BIMM_FLAG; - } -} - static void dec_bcc(DisasContext *dc) { static const TCGCond mb_to_tcg_cc[] = { @@ -1398,7 +1437,7 @@ static void dec_bcc(DisasContext *dc) dslot = dc->ir & (1 << 25); if (dslot) { - dec_setup_dslot(dc); + setup_dslot(dc, dc->type_b); } dc->jmp_cond = mb_to_tcg_cc[cc]; @@ -1426,33 +1465,6 @@ static void dec_bcc(DisasContext *dc) tcg_temp_free_i32(next); } -static void dec_br(DisasContext *dc) -{ - unsigned int dslot, link, abs; - uint32_t add_pc; - - dslot = dc->ir & (1 << 20); - abs = dc->ir & (1 << 19); - link = dc->ir & (1 << 18); - - if (dslot) { - dec_setup_dslot(dc); - } - if (link && dc->rd) { - tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); - } - - add_pc = abs ? 0 : dc->base.pc_next; - if (dc->type_b) { - dc->jmp_dest = add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); - } else { - dc->jmp_dest = -1; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); - } - dc->jmp_cond = TCG_COND_ALWAYS; -} - static inline void do_rti(DisasContext *dc) { TCGv_i32 t0, t1; @@ -1521,7 +1533,7 @@ static void dec_rts(DisasContext *dc) return; } - dec_setup_dslot(dc); + setup_dslot(dc, true); if (i_bit) { dc->tb_flags |= DRTI_FLAG; @@ -1583,7 +1595,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, From patchwork Mon Aug 31 16:05:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248811 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3460876ilg; Mon, 31 Aug 2020 09:33:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxArBzrxTcUT9zEwWCcAf0LLeKn80oPptuN6POqDyksultJKorN0xk1PBtsmDGZDp9aZ3yn X-Received: by 2002:a25:bc3:: with SMTP id 186mr2892090ybl.2.1598891582469; Mon, 31 Aug 2020 09:33:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891582; cv=none; d=google.com; s=arc-20160816; b=yrIJl1+OtuyCeZblI03cgEKBPhrm8+vZx1j5G15KNYEhs4KTyDBpGqUSn1i3ZC3rBd 1AB4LhHwDTWbAU/bGUXeXMPzCLokWYciGLRXlTJVs4E8mebHVT28AG8r5WB7eA7QTmTO uU8NWVafilkUQp2q/0KGuspya6SKYNIzSrKDjAVSxNG6LEngJB5DcnEX/O8j6RJQ2Sgi gcCk29zWIgIeD/mvG30VZN5qzBUp+bj5QdJUWC/onaoRyEQvKRTC6Q9hBztNErsYea4e ZhMCWKcUfQE0ZNataTg7z8+LC9H4gAkDu1pJGilIeVRIAAXoY+B3T3M4m10ILaS71QM9 e9Eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=epqagA1a4qbo45d4ja0WxukrU+YThDkatfUkMkTy2Oo=; b=MGA6L9mPwytrxypTluOS6JvAR/TcjSPFAh/tr8F398VyiZBSxb42frkERrPNbbckjb GKtxua+0Mycob4dyU9Cl/4sV1p4AKAGERbb7EI3mM8zmWWKnNz14PijxWa8Tg/jYS0c/ UH6F+Bhd5LsfGNcKN/LGUr/rSzavXHhOLMJ9I9awfRJp3ylC3PhZnKwtUi35tcsmimDR eo2pR9bOe6CQsnmh66cghF4J8d7LRYvER+BfxHQrAUUsg1t7wGCkw5ZhxN8SSJeus2i3 yjTrSDT5ULlQrZ6Q5M1BlMz8OKdQeK3T4E6egncxHjG215JXS+TShR9SoxVnrI5pslcA Krfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=izTxemHH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 36 +++++++++++++ target/microblaze/translate.c | 99 ++++++++++++++++++---------------- 2 files changed, 88 insertions(+), 47 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 340dd999b6..e6a61f147a 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -20,8 +20,10 @@ &typea0 rd ra &typea rd ra rb &typea_br rd rb +&typea_bc ra rb &typeb rd ra imm &typeb_br rd imm +&typeb_bc ra imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -35,12 +37,18 @@ # Officially typea, but with ra as opcode. @typea_br ...... rd:5 ..... rb:5 ........... &typea_br +# Officially typea, but with rd as opcode. +@typea_bc ...... ..... ra:5 rb:5 ........... &typea_bc + # Officially typeb, but any immediate extension is unused. @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb # Officially typeb, but with ra as opcode. @typeb_br ...... rd:5 ..... ................ &typeb_br imm=%extimm +# Officially typeb, but with rd as opcode. +@typeb_bc ...... ..... ra:5 ................ &typeb_bc imm=%extimm + # For convenience, extract the two imm_w/imm_s fields, then pack # them back together as "imm". Doing this makes it easiest to # match the required zero at bit 5. @@ -68,6 +76,34 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +beq 100111 00000 ..... ..... 000 0000 0000 @typea_bc +bge 100111 00101 ..... ..... 000 0000 0000 @typea_bc +bgt 100111 00100 ..... ..... 000 0000 0000 @typea_bc +ble 100111 00011 ..... ..... 000 0000 0000 @typea_bc +blt 100111 00010 ..... ..... 000 0000 0000 @typea_bc +bne 100111 00001 ..... ..... 000 0000 0000 @typea_bc + +beqd 100111 10000 ..... ..... 000 0000 0000 @typea_bc +bged 100111 10101 ..... ..... 000 0000 0000 @typea_bc +bgtd 100111 10100 ..... ..... 000 0000 0000 @typea_bc +bled 100111 10011 ..... ..... 000 0000 0000 @typea_bc +bltd 100111 10010 ..... ..... 000 0000 0000 @typea_bc +bned 100111 10001 ..... ..... 000 0000 0000 @typea_bc + +beqi 101111 00000 ..... ................ @typeb_bc +bgei 101111 00101 ..... ................ @typeb_bc +bgti 101111 00100 ..... ................ @typeb_bc +blei 101111 00011 ..... ................ @typeb_bc +blti 101111 00010 ..... ................ @typeb_bc +bnei 101111 00001 ..... ................ @typeb_bc + +beqid 101111 10000 ..... ................ @typeb_bc +bgeid 101111 10101 ..... ................ @typeb_bc +bgtid 101111 10100 ..... ................ @typeb_bc +bleid 101111 10011 ..... ................ @typeb_bc +bltid 101111 10010 ..... ................ @typeb_bc +bneid 101111 10001 ..... ................ @typeb_bc + br 100110 ..... 00000 ..... 000 0000 0000 @typea_br bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 5c6e6e599e..b8dcef8f1c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1095,6 +1095,58 @@ DO_BR(brad, braid, true, true, false) DO_BR(brld, brlid, true, false, true) DO_BR(brald, bralid, true, true, true) +static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm, + TCGCond cond, int ra, bool delay) +{ + TCGv_i32 zero, next; + + if (delay) { + setup_dslot(dc, dest_rb < 0); + } + + dc->jmp_cond = cond; + + /* Cache the condition register in cpu_bvalue across any delay slot. */ + tcg_gen_mov_i32(cpu_bvalue, reg_for_read(dc, ra)); + + /* Store the branch taken destination into btarget. */ + if (dest_rb > 0) { + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], dc->base.pc_next); + } else { + dc->jmp_dest = dc->base.pc_next + dest_imm; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); + } + + /* Compute the final destination into btarget. */ + zero = tcg_const_i32(0); + next = tcg_const_i32(dc->base.pc_next + (delay + 1) * 4); + tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, + reg_for_read(dc, ra), zero, + cpu_btarget, next); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(next); + + return true; +} + +#define DO_BCC(NAME, COND) \ + static bool trans_##NAME(DisasContext *dc, arg_typea_bc *arg) \ + { return do_bcc(dc, arg->rb, 0, COND, arg->ra, false); } \ + static bool trans_##NAME##d(DisasContext *dc, arg_typea_bc *arg) \ + { return do_bcc(dc, arg->rb, 0, COND, arg->ra, true); } \ + static bool trans_##NAME##i(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_bcc(dc, -1, arg->imm, COND, arg->ra, false); } \ + static bool trans_##NAME##id(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_bcc(dc, -1, arg->imm, COND, arg->ra, true); } + +DO_BCC(beq, TCG_COND_EQ) +DO_BCC(bge, TCG_COND_GE) +DO_BCC(bgt, TCG_COND_GT) +DO_BCC(ble, TCG_COND_LE) +DO_BCC(blt, TCG_COND_LT) +DO_BCC(bne, TCG_COND_NE) + static bool trans_brk(DisasContext *dc, arg_typea_br *arg) { if (trap_userspace(dc, true)) { @@ -1419,52 +1471,6 @@ static void dec_msr(DisasContext *dc) } } -static void dec_bcc(DisasContext *dc) -{ - static const TCGCond mb_to_tcg_cc[] = { - [CC_EQ] = TCG_COND_EQ, - [CC_NE] = TCG_COND_NE, - [CC_LT] = TCG_COND_LT, - [CC_LE] = TCG_COND_LE, - [CC_GE] = TCG_COND_GE, - [CC_GT] = TCG_COND_GT, - }; - unsigned int cc; - unsigned int dslot; - TCGv_i32 zero, next; - - cc = EXTRACT_FIELD(dc->ir, 21, 23); - dslot = dc->ir & (1 << 25); - - if (dslot) { - setup_dslot(dc, dc->type_b); - } - - dc->jmp_cond = mb_to_tcg_cc[cc]; - - /* Cache the condition register in cpu_bvalue across any delay slot. */ - tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]); - - /* Store the branch taken destination into btarget. */ - if (dc->type_b) { - dc->jmp_dest = dc->base.pc_next + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); - } else { - dc->jmp_dest = -1; - tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb), - dc->base.pc_next); - } - - /* Compute the final destination into btarget. */ - zero = tcg_const_i32(0); - next = tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4); - tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, - reg_for_read(dc, dc->ra), zero, - cpu_btarget, next); - tcg_temp_free_i32(zero); - tcg_temp_free_i32(next); -} - static inline void do_rti(DisasContext *dc) { TCGv_i32 t0, t1; @@ -1595,7 +1601,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, From patchwork Mon Aug 31 16:05:53 2020 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id b16si1458455uav.169.2020.08.31.09.33.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:33:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uTe0i+4Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmkd-0001QZ-1Q for patch@linaro.org; Mon, 31 Aug 2020 12:33:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmLL-0006YW-6e for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:39 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:37066) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmLJ-0006A7-Ag for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:38 -0400 Received: by mail-pl1-x633.google.com with SMTP id c15so3249219plq.4 for ; Mon, 31 Aug 2020 09:07:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EW6QXoswK1mjFJ4YzGZRvNX8K3Up1egTxlK+WSpOGc8=; b=uTe0i+4QE+wNYDNwd8a4OJHnZhE9zGm7kovUhOCEwL59ffjPLcuqLYMJZhH32ZOF3x 5r70z+njDgkknESnkj5NXk9FFkHHgr01ObxBLsAyTjqVDBv0FcQtUTU7fFmjSKHnqSRv bEVwvF38icp2J9J1WwMELsnvJqImaW1ZoHOWlNpmhXseC420GIKaXuTMh3WLzuFgpwNS fiQA+aM1xbDqA1AIevilz6GRQ3Vseq60erB6z5/+yxDgZVDEGk1ETgRKjWbrKFAs+Ud+ Us/WmS9Vwsdfuk8H0/D6wg+dCNLSftJsDLxTjwy6tsGXsZRn9PfghC6XBjTGI8IJCfvK A85w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EW6QXoswK1mjFJ4YzGZRvNX8K3Up1egTxlK+WSpOGc8=; b=tLg2MWUCuwlHeAuUmA56MPlSrwfNOLjgQgLQeOY+0BLa8GehBl+cvO6LiRE/AAUilc nj/1CFGjF/TJOmLsnPbI6MBXhCvNrsdl4YkccgOCX3HcZ/neNkLlRA+1BnKQ5OETtA01 wJAdiSb1r0utmthbsIJ2ZLg23fNh1GGBic07HB3Fj06OB7Mv79uFs/XIUWCOndE4dYwY C2jHLhZTVfujpfHO5JUfoU4F8Se/Ap8tt3s9EckHscgcbtYIYHD8q2qTgzQXsd2ao82T nmadYuoPgj9kGvP8i4+WKobKn5bRoLwkSd20RtXUPky+NyxFuUGvvOOA+OMQqgbkCMR5 pt6A== X-Gm-Message-State: AOAM5314hbi5Us+HNTEnDSj3wrZOUqQSfuIlOdghK2lTlum+RPU5Bcnr e7JbOdubhcHkRNnFLdm8D/xeJOVYSNlp/g== X-Received: by 2002:a17:902:720a:: with SMTP id ba10mr1552113plb.41.1598890055582; Mon, 31 Aug 2020 09:07:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 68/76] target/microblaze: Convert dec_rts to decodetree Date: Mon, 31 Aug 2020 09:05:53 -0700 Message-Id: <20200831160601.833692-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 5 ++++ target/microblaze/translate.c | 51 +++++++++++++++------------------- 2 files changed, 28 insertions(+), 28 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index e6a61f147a..8906058a29 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -202,6 +202,11 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +rtbd 101101 10010 ..... ................ @typeb_bc +rtid 101101 10001 ..... ................ @typeb_bc +rted 101101 10100 ..... ................ @typeb_bc +rtsd 101101 10000 ..... ................ @typeb_bc + sb 110100 ..... ..... ..... 0000 000 0000 @typea sbr 110100 ..... ..... ..... 0100 000 0000 @typea sbea 110100 ..... ..... ..... 0001 000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b8dcef8f1c..6c1855b29a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1252,6 +1252,29 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg) return true; } +static bool do_rts(DisasContext *dc, arg_typeb_bc *arg, int to_set) +{ + if (trap_userspace(dc, to_set)) { + return true; + } + dc->tb_flags_to_set |= to_set; + setup_dslot(dc, true); + + dc->jmp_cond = TCG_COND_ALWAYS; + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, arg->ra), arg->imm); + return true; +} + +#define DO_RTS(NAME, IFLAG) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_rts(dc, arg, IFLAG); } + +DO_RTS(rtbd, DRTB_FLAG) +DO_RTS(rtid, DRTI_FLAG) +DO_RTS(rted, DRTE_FLAG) +DO_RTS(rtsd, 0) + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -1527,33 +1550,6 @@ static inline void do_rte(DisasContext *dc) dc->tb_flags &= ~DRTE_FLAG; } -static void dec_rts(DisasContext *dc) -{ - unsigned int b_bit, i_bit, e_bit; - - i_bit = dc->ir & (1 << 21); - b_bit = dc->ir & (1 << 22); - e_bit = dc->ir & (1 << 23); - - if (trap_userspace(dc, i_bit || b_bit || e_bit)) { - return; - } - - setup_dslot(dc, true); - - if (i_bit) { - dc->tb_flags |= DRTI_FLAG; - } else if (b_bit) { - dc->tb_flags |= DRTB_FLAG; - } else if (e_bit) { - dc->tb_flags |= DRTE_FLAG; - } - - dc->jmp_cond = TCG_COND_ALWAYS; - dc->jmp_dest = -1; - tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); -} - static void dec_null(DisasContext *dc) { if (trap_illegal(dc, true)) { @@ -1601,7 +1597,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} From patchwork Mon Aug 31 16:05:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248799 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3456384ilg; Mon, 31 Aug 2020 09:26:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4k7ZrIijVziCC5shH8eJCMh1TNlct6Zoeb0MTxcE6SqSdGk/Nwamy97a8YwWt/kIwaoEv X-Received: by 2002:a25:4642:: with SMTP id t63mr3348462yba.329.1598891212176; Mon, 31 Aug 2020 09:26:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891212; cv=none; d=google.com; s=arc-20160816; b=nynsF4GdeQXY/SXNWEEG+YbtXxMERw3BdaOiQoDTB+DrDaofm+cX87TJCSL/k5dP04 hr479YkcYbFb+rDyOiQgjFb+YiR+zG7xTy0oo24FAFjzAryJDEFqqz87CfhVpd1Fg9Uw I5ayoN1GfWT/1iePsgc4f0CfgbSjfUwH8IL+WRWxoGVb+8r/BOIYPqYrAI+wY7rGJSFS LoucmoPJU5t5CeB/2Xs1S/qMlwDr5eof0F/Vw1NHaPfE7VufexZ1EFKwjNNZUZXmBQg1 HbKeEtZIBAO+igHhn9LgYdpGlr4Nj4sK4w7Ekzmacv2U1EYWSNsK5xlew6550t+Ei4pd cEqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QDTm4Rd7QGp1CLW4zO3AZdAzuiw+MvOs5jtCeQIlMUE=; b=C4yAoh7K1fcl44eNlzaSDIiz7uu+fBcP/iI2Y2F/l/CREHpPpzxyIWrLK5rNUzLK8B zhzEH83UKY3wNceejrtFzKv3EyLzTx9Ibq/GUI0fvFUIMIdEikZGl84vvh4DlHQPVJAi Js2StGO+GBj0n3WtFY7sP69hjYxJMxTONNWqdD7t11Hnhs5kKF66AEBlAGkARv0uiUvl SZPJfzieFVsZs0kc6R4oQk792Pi9R16KPiqK44ML/+aaxDr45Zjaglo2ORVlwhc8zo/W RXL/SqF92FomWomQMDPwt4Ls1muwvc+6V9pTH+R6jmDPIllop8m5SAVZ5fJfkVUOke9t i65w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="b/N8Y1oa"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 133si7495676ybe.226.2020.08.31.09.26.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:26:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="b/N8Y1oa"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmdv-0003f0-Mh for patch@linaro.org; Mon, 31 Aug 2020 12:26:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmLM-0006ca-MT for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:40 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:41753) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmLK-0006AO-SE for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:40 -0400 Received: by mail-pl1-x631.google.com with SMTP id l9so1612307plt.8 for ; Mon, 31 Aug 2020 09:07:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QDTm4Rd7QGp1CLW4zO3AZdAzuiw+MvOs5jtCeQIlMUE=; b=b/N8Y1oaLN/rI99/xNazNhszo83o8gaSFxcoLxtu9Obdb97RfUbv7/W/ewpeRdp2ka 3b0cLjvh9+OXpN4nXNWndE2lJsYX+aYEK7cUo0s2e+3QPT6Q0Hmq1aW0IemCU5ONxSiD GmdZ9dN9KheLxXbSF9f9TP+shu0FlLtCo6SllBYFr8NH+iQwLg+vr8ZznYS3sprQ4+fW JztSeOFUrdMq9kRPSnjg8Nh68y/vPLoBOfSZ8OG6aQFPTR5JsSO+JZ06/J8Jyf4pbUl3 2r1Z3s5s1jdfzLxsQFf5Gwh215kXc3ANep8nlxnCBbeKRLeMhCT8W6Z+l8SVUFSmjLpr VQOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QDTm4Rd7QGp1CLW4zO3AZdAzuiw+MvOs5jtCeQIlMUE=; b=Eb/4Wkz2IeJMH28mRCf389rhMlLU1y1TNiGfuXdxqcDTJjutn0Hw7+LAWd8C+YFycM n0kRWZItEWPul1zcY437tVwrYnUm0C8Y0ZzFd5A0sXdnhlqLinvzplKfnZx6NhRn/f0K 9MKrh0j6plyzgjkPyG662f7UmwTQjJW8UTN35h/QhaQMXUiE8Z578dYF6uwHcvsR4W+u W4YxymcWFStZzoI6urIG6pWkOKGnGmVU+SANSp+xCDQaL5uGYI537qqXivcynx4K+/W4 SCMjVCKAc82Arud6Bvn9lLHxxybeft2CuCyAsKPZgENzWm/wVdw4WO+erMrn35CX5bJV 2pnw== X-Gm-Message-State: AOAM533AO6owdo/e0bDlc+K5vc4lRFMBlZeNukMrO28rVKRLmL5ZqMrG inEOrTj2s0AvAL4tFdPa+Pz5uR1UV1h3dQ== X-Received: by 2002:a17:902:6ac3:: with SMTP id i3mr1595395plt.21.1598890057109; Mon, 31 Aug 2020 09:07:37 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 69/76] target/microblaze: Tidy do_rti, do_rtb, do_rte Date: Mon, 31 Aug 2020 09:05:54 -0700 Message-Id: <20200831160601.833692-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since cpu_msr is no longer a 64-bit quantity, we can simplify the arithmetic in these functions. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 65 ++++++++++++++--------------------- 1 file changed, 25 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6c1855b29a..0872795038 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1494,59 +1494,44 @@ static void dec_msr(DisasContext *dc) } } -static inline void do_rti(DisasContext *dc) +static void do_rti(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_ori_i32(t1, t1, MSR_IE); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_IE); + tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); + + tcg_temp_free_i32(tmp); dc->tb_flags &= ~DRTI_FLAG; } -static inline void do_rtb(DisasContext *dc) +static void do_rtb(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_andi_i32(t1, t1, ~MSR_BIP); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP)); + tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); + + tcg_temp_free_i32(tmp); dc->tb_flags &= ~DRTB_FLAG; } -static inline void do_rte(DisasContext *dc) +static void do_rte(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_ori_i32(t1, t1, MSR_EE); - tcg_gen_andi_i32(t1, t1, ~MSR_EIP); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_EE); + tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_temp_free_i32(tmp); dc->tb_flags &= ~DRTE_FLAG; } From patchwork Mon Aug 31 16:05:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248814 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3461699ilg; Mon, 31 Aug 2020 09:34:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyIzIcq6ZZhTPLraRyybz6o6RpXODTIxYoqxqavVxuMbJ7SPYy2f9wEnWJ7pvFULdJKsFIu X-Received: by 2002:a5b:410:: with SMTP id m16mr3299694ybp.309.1598891654586; Mon, 31 Aug 2020 09:34:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891654; cv=none; d=google.com; s=arc-20160816; b=VXPb6Bd2a+6DfHw5sMzNKJYOC7yMVWpynApxjGArhHpGqXIPCQWrhw8kctGHYMII+0 /tgQEcXRcEBiLV+XKq3OCnshY6IIqYkUma/1aT3ihk91VTAifcyMFYiXaZ0CdkeatHYB nhH4TBotRjYUrDQp1ydhbxn5Ayna81HiLAU31v5VSVtKZ31mbbED7FgcFhkg1jyGnlEK gl/FjkqkxMqfJmIPDdxjw98ZJZ+X/HJ6E8rPq2Y27j+6w8AzWddh5VtSlDEJFku0eBm8 lJMS4j4WPsA5+HIBZ8DBWLwUDfMtldPsHxZXCiJzdrgSq2PobtzfTyuUHGht7MUxCQ8G RLtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qD9TO6jGFspxgEuw853gVRm0hcTBzuluIXG7+nD8HAE=; b=hENt8MCjG0bNi0w+BD1ik3SP8tKuZIP/bDt8fbcP1QDbYBnBF8at6UOwGP4KEQc4hF 74aHS+AWFeavSoyrnCZUhFwxsbb9xQ/alxXXeWCZd9bP+QBIlrel6DBHxh/vYSFeESom iYiki5j46iUgsfdwIluKnhLZ2EgOXPTPRs+LAzkSBTY6qrEE85br9L7mGHX20GcM6gaO HLYnuKotAG37jptEiwZURK2rrl7yDILkZvFnw5hSVoufpg4MVojiS0mFSxDSQZJA6koV hdEMzLInon/zTHF2zxFXUK9IKxRCRPds318aYyC6eNrE9WE+79k70G2Bpvewgyzffqxo L/Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=it6gFr26; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j127si1996445ybg.458.2020.08.31.09.34.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:34:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=it6gFr26; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCml4-0002Mi-0d for patch@linaro.org; Mon, 31 Aug 2020 12:34:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmLO-0006gw-Bb for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:42 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:55319) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmLM-0006Ai-1q for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:41 -0400 Received: by mail-pj1-x1042.google.com with SMTP id 2so21717pjx.5 for ; Mon, 31 Aug 2020 09:07:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qD9TO6jGFspxgEuw853gVRm0hcTBzuluIXG7+nD8HAE=; b=it6gFr26EkQ4zo09ApJAmMqAT8cdh8Z8KCxVnMKlTHx0FF9qPpTxFlqaTEM4gC4jB/ Wmy9yt47pENq5WxxWMhT4kJZFJ+iX6cMsELMCBVV3MD3lNYHdhbtdHAbJXkRSHRlzfff QeFaKcUPpKKCv4IUJnZ+0cwmVwLvcnQ+fimHzzn0MKA6gRyqi+WMh1ed14ZTat2145YV NkjHv4FfGA9LsnA03e+66IKfMR5ZbPk+R8IHjOBuhnAUpKaGe5GYEkJO3QdNEYicFS+A dIU7KFrJ2gyondW02IOLFNloMQMCiuziILKBZaG5SnsIW5Tx+iyIkSPrvvEqt9OV/J4t HEMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qD9TO6jGFspxgEuw853gVRm0hcTBzuluIXG7+nD8HAE=; b=P3nOBBntVHDTYXdPObk0dhQmiSS113jE+WaoiwUA8UbaroNJQddQYvD7zFAzYzDdvh oDkdTmJ1Fzn6+TTNwBo3hn14b/8xKSitNgFxYuwT3UW++tZixyYPKyB1Ks1XTcD+PX5A U6W+EmRRjmAQeUlSlMHS8bD7iKBP/dFKCj7aC6EoyEEPUim0LYHLH6zs3UhyqBbUzxg5 5n82CXrGWKFk9dWcTKP8Zeq/5mzjnlpGMjBxzPUimMv1E9YfkvcA+nfkI/8H6+8MzjJd WxcOkDzb6MYyEXkK0BWEIDzb+vK4H/Khqp+Ao1eM62QCUa3rTUfBTYw4sToNPOEHPcAl Lcww== X-Gm-Message-State: AOAM531LbSKPa6bswsnNOsSkwfo1dIvKTCTuhtig1uFQvuRluFyIo4Yh /JJlViykVc91QofI+chZAcHg617MO9GZ6g== X-Received: by 2002:a17:90a:bc8c:: with SMTP id x12mr97622pjr.106.1598890058276; Mon, 31 Aug 2020 09:07:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 70/76] target/microblaze: Convert msrclr, msrset to decodetree Date: Mon, 31 Aug 2020 09:05:55 -0700 Message-Id: <20200831160601.833692-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split this out of dec_msr. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 85 +++++++++++++++++++--------------- 2 files changed, 54 insertions(+), 37 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 8906058a29..ed3312982f 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -24,6 +24,7 @@ &typeb rd ra imm &typeb_br rd imm &typeb_bc ra imm +&type_msr rd imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -55,6 +56,8 @@ %ieimm 6:5 0:5 @typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=%ieimm +@type_msr ...... rd:5 ...... imm:15 &type_msr + ### { @@ -179,6 +182,9 @@ lwi 111010 ..... ..... ................ @typeb mbar 101110 imm:5 00010 0000 0000 0000 0100 +msrclr 100101 ..... 100010 ............... @type_msr +msrset 100101 ..... 100000 ............... @type_msr + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0872795038..9479dbc103 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1311,16 +1311,61 @@ static void msr_write(DisasContext *dc, TCGv_i32 v) tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } +static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) +{ + uint32_t imm = arg->imm; + + if (trap_userspace(dc, imm != MSR_C)) { + return true; + } + + if (arg->rd) { + msr_read(dc, cpu_R[arg->rd]); + } + + /* + * Handle the carry bit separately. + * This is the only bit that userspace can modify. + */ + if (imm & MSR_C) { + tcg_gen_movi_i32(cpu_msr_c, set); + } + + /* + * MSR_C and MSR_CC set above. + * MSR_PVR is not writable, and is always clear. + */ + imm &= ~(MSR_C | MSR_CC | MSR_PVR); + + if (imm != 0) { + if (set) { + tcg_gen_ori_i32(cpu_msr, cpu_msr, imm); + } else { + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); + } + dc->cpustate_changed = 1; + } + return true; +} + +static bool trans_msrclr(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, false); +} + +static bool trans_msrset(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, true); +} + static void dec_msr(DisasContext *dc) { CPUState *cs = CPU(dc->cpu); - TCGv_i32 t0, t1; unsigned int sr, rn; - bool to, clrset, extended = false; + bool to, extended = false; sr = extract32(dc->imm, 0, 14); to = extract32(dc->imm, 14, 1); - clrset = extract32(dc->imm, 15, 1) == 0; dc->type_b = 1; if (to) { dc->cpustate_changed = 1; @@ -1334,40 +1379,6 @@ static void dec_msr(DisasContext *dc) extended = extract32(dc->imm, e_bit[to], 1); } - /* msrclr and msrset. */ - if (clrset) { - bool clr = extract32(dc->ir, 16, 1); - - if (!dc->cpu->cfg.use_msr_instr) { - /* nop??? */ - return; - } - - if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) { - return; - } - - if (dc->rd) - msr_read(dc, cpu_R[dc->rd]); - - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - msr_read(dc, t0); - tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc))); - - if (clr) { - tcg_gen_not_i32(t1, t1); - tcg_gen_and_i32(t0, t0, t1); - } else - tcg_gen_or_i32(t0, t0, t1); - msr_write(dc, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - dc->base.is_jmp = DISAS_UPDATE; - return; - } - if (trap_userspace(dc, to)) { return; } From patchwork Mon Aug 31 16:05:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248824 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3466985ilg; Mon, 31 Aug 2020 09:41:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeCikrSE48MTfy2mCO2rHWloOm5f4BVjlESY6m5Jl/qBcnVf/Jq+FinOw2wEF56ODUcKLC X-Received: by 2002:a1f:141:: with SMTP id 62mr1885308vkb.2.1598892115049; Mon, 31 Aug 2020 09:41:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598892115; cv=none; d=google.com; s=arc-20160816; b=kwMUgi1yX0FF2pKoXEUUe9mH7a8fURpMMGywDCfTel1R4Gf0TUeTt4kt3jIkIWHpop tTekok9biBYjt4xPiXnWMKpU46EoxWKj2b39Ur4HpRFJWdFl+Jq/F5hvp5wlpyxs0fa9 Y5eTY0Pi+qMyfHwHLw6Ed/yGqysJaInWXOCAalbZLuqmYUCz3QQCIZSTnzb5MvZ1QuPB VtzB173NvGwRHk8H14VMiqAsHvv/mNMA1flcRIKrVreqqTqFuG87oUIfIw/tG4iUbG1M 9DH5awW2GXzlRVSnzZIZ3jFgAAC94IYBAfwcnETN8IYm2uo/OQu06UbJKyb9otveKOOh tVbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Hba68ezEWb+nS0e4nSSkWGW78a7UsmlXp2xiIpotygQ=; b=Yfqk+3vVx9OL9ur3mRWacu3J5BC8UjMFfyvmfrtE+dXkBOjb/R+NKYf0Jdlt/7fBaL 9ehqECDfrnQP8+QfzvLoMG/crMUiGikpSy/OC7mxj+1nbL5WMWT0mN8ZE6oc15N9UXIs VhRhpWytVBdoMxuwTmkynfxz31cecP/e+XFfs5AJpTqlC3Qie2kNfc0mjB9X34UR1BfP DwnhMg1okJt+YimgqYJ2ghzLjpw9sv2q/dcYYNtgK+WXQ7Q7MTIjHI9/CLxUOeN8ZflL Mif3lRWwzIpoOIBq+8Wya8WemF5k4N8qujs52hq8Pytv96m+/Lj6I9VNcJn1q5LdfLBO NXOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WzoIcbAP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i5si1232930uan.234.2020.08.31.09.41.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:41:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WzoIcbAP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57546 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmsU-0007r1-CT for patch@linaro.org; Mon, 31 Aug 2020 12:41:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmLP-0006l2-SR for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:43 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:44882) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmLN-0006B0-DK for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:43 -0400 Received: by mail-pl1-x642.google.com with SMTP id q3so3234680pls.11 for ; Mon, 31 Aug 2020 09:07:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hba68ezEWb+nS0e4nSSkWGW78a7UsmlXp2xiIpotygQ=; b=WzoIcbAPp9R7brAgHL5BISzHwIOYaCl+YKm4rFuUOLMHGfLCu35dev5PFuYeg2sVLl PddIUAYIGFI9uMy46kO8/3yZLo0OncFg0gW9C4HWsBZxBlstMrzoSiQ4MO2OLd5X5UR3 3sbrDCyRk0nEz+654EzqJe0MeifuCzWHz3LrhY35J34p+4exOdGmkFyW45gQ4c78zdzx 6AvQcC2NGMWHeIJIH0weCGW6NUW9Rq1hCLmOIDl/ynVpbkjrLwbbJTJElV131cfYPC26 E/cTePPKlpzBvZlPSU1X6fLqNVyswHq4OlYuLACnbKnHxs/axETB5nLOKPrb8GBgueV6 mCbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hba68ezEWb+nS0e4nSSkWGW78a7UsmlXp2xiIpotygQ=; b=CBXFspi333dB1Z3cf1DjiFerIFuy6HPrKXLbTjZ73Cldn3Q1w6kS3gTg448Tq7Ahav 2fbMYarEZdtMilrxR5qJhPOpArCU9cv9jQvwy78JpKZq4IZejdEvI19yDMPY+z+1saC7 UI0BcpuXb+ygLo/uSIRLZyWW3nw9mIJ+L4Qmz5fLaogiuwdNa+H4aGvYgteucS76vld+ 5m3kNwUPsj5PAM5gUBoENS2Z9Se0BQnc91vH0F6TgoIFQwB9vESauE05Ri498iTKefFf GsWEXUZRUU327FgCjF8AIbhu3knGGkP16J2Hk58g+UNuQTI7YlZ0/D9zu+x3oObXSj0f +1xQ== X-Gm-Message-State: AOAM531FHsy1x85YMm861jqBAYICr3NZvN6el6i+xG8+nkyCyuJiuwaS DwzTgNzvysgTihYxm4imrRGpjJYTMQJoJw== X-Received: by 2002:a17:90b:1988:: with SMTP id mv8mr85832pjb.23.1598890059551; Mon, 31 Aug 2020 09:07:39 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 71/76] target/microblaze: Convert dec_msr to decodetree Date: Mon, 31 Aug 2020 09:05:56 -0700 Message-Id: <20200831160601.833692-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 + target/microblaze/translate.c | 270 +++++++++++++++++---------------- 2 files changed, 139 insertions(+), 134 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index ed3312982f..43c9e16819 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -182,6 +182,9 @@ lwi 111010 ..... ..... ................ @typeb mbar 101110 imm:5 00010 0000 0000 0000 0100 +mfs 100101 rd:5 0 e:1 000 10 rs:14 +mts 100101 0 e:1 000 ra:5 11 rs:14 + msrclr 100101 ..... 100010 ............... @type_msr msrset 100101 ..... 100000 ............... @type_msr diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9479dbc103..582f5a1577 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1300,6 +1300,7 @@ static void msr_read(DisasContext *dc, TCGv_i32 d) tcg_temp_free_i32(t); } +#ifndef CONFIG_USER_ONLY static void msr_write(DisasContext *dc, TCGv_i32 v) { dc->cpustate_changed = 1; @@ -1310,6 +1311,7 @@ static void msr_write(DisasContext *dc, TCGv_i32 v) /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */ tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } +#endif static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) { @@ -1358,151 +1360,152 @@ static bool trans_msrset(DisasContext *dc, arg_type_msr *arg) return do_msrclrset(dc, arg, true); } -static void dec_msr(DisasContext *dc) +static bool trans_mts(DisasContext *dc, arg_mts *arg) { - CPUState *cs = CPU(dc->cpu); - unsigned int sr, rn; - bool to, extended = false; - - sr = extract32(dc->imm, 0, 14); - to = extract32(dc->imm, 14, 1); - dc->type_b = 1; - if (to) { - dc->cpustate_changed = 1; + if (trap_userspace(dc, true)) { + return true; } - /* Extended MSRs are only available if addr_size > 32. */ - if (dc->cpu->cfg.addr_size > 32) { - /* The E-bit is encoded differently for To/From MSR. */ - static const unsigned int e_bit[] = { 19, 24 }; - - extended = extract32(dc->imm, e_bit[to], 1); +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + if (arg->e && arg->rs != 0x1003) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid extended mts reg 0x%x\n", arg->rs); + return true; } - if (trap_userspace(dc, to)) { - return; - } + TCGv_i32 src = reg_for_read(dc, arg->ra); + switch (arg->rs) { + case SR_MSR: + msr_write(dc, src); + break; + case SR_FSR: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); + break; + case 0x800: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, slr)); + break; + case 0x802: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, shr)); + break; -#if !defined(CONFIG_USER_ONLY) - /* Catch read/writes to the mmu block. */ - if ((sr & ~0xff) == 0x1000) { - TCGv_i32 tmp_ext = tcg_const_i32(extended); - TCGv_i32 tmp_sr; + case 0x1000: /* PID */ + case 0x1001: /* ZPR */ + case 0x1002: /* TLBX */ + case 0x1003: /* TLBLO */ + case 0x1004: /* TLBHI */ + case 0x1005: /* TLBSX */ + { + TCGv_i32 tmp_ext = tcg_const_i32(arg->e); + TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7); - sr &= 7; - tmp_sr = tcg_const_i32(sr); - if (to) { - gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); - } else { - gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr); + gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src); + tcg_temp_free_i32(tmp_reg); + tcg_temp_free_i32(tmp_ext); } - tcg_temp_free_i32(tmp_sr); - tcg_temp_free_i32(tmp_ext); - return; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs); + return true; } + dc->cpustate_changed = 1; + return true; +#endif +} + +static bool trans_mfs(DisasContext *dc, arg_mfs *arg) +{ + TCGv_i32 dest = reg_for_write(dc, arg->rd); + + if (arg->e) { + switch (arg->rs) { + case SR_EAR: + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_extrh_i64_i32(dest, t64); + tcg_temp_free_i64(t64); + } + return true; +#ifndef CONFIG_USER_ONLY + case 0x1003: /* TLBLO */ + /* Handled below. */ + break; +#endif + case 0x2006 ... 0x2009: + /* High bits of PVR6-9 not implemented. */ + tcg_gen_movi_i32(dest, 0); + return true; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid extended mfs reg 0x%x\n", arg->rs); + return true; + } + } + + switch (arg->rs) { + case SR_PC: + tcg_gen_movi_i32(dest, dc->base.pc_next); + break; + case SR_MSR: + msr_read(dc, dest); + break; + case SR_EAR: + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_extrl_i64_i32(dest, t64); + tcg_temp_free_i64(t64); + } + break; + case SR_ESR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, esr)); + break; + case SR_FSR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, fsr)); + break; + case SR_BTR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, btr)); + break; + case SR_EDR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, edr)); + break; + case 0x800: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, slr)); + break; + case 0x802: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, shr)); + break; + +#ifndef CONFIG_USER_ONLY + case 0x1000: /* PID */ + case 0x1001: /* ZPR */ + case 0x1002: /* TLBX */ + case 0x1003: /* TLBLO */ + case 0x1004: /* TLBHI */ + case 0x1005: /* TLBSX */ + { + TCGv_i32 tmp_ext = tcg_const_i32(arg->e); + TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7); + + gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg); + tcg_temp_free_i32(tmp_reg); + tcg_temp_free_i32(tmp_ext); + } + break; #endif - if (to) { - switch (sr) { - case SR_PC: - break; - case SR_MSR: - msr_write(dc, cpu_R[dc->ra]); - break; - case SR_EAR: - { - TCGv_i64 t64 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); - tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)); - tcg_temp_free_i64(t64); - } - break; - case SR_ESR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, esr)); - break; - case SR_FSR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, fsr)); - break; - case SR_BTR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, btr)); - break; - case SR_EDR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, edr)); - break; - case 0x800: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, slr)); - break; - case 0x802: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, shr)); - break; - default: - cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr); - break; - } - } else { - switch (sr) { - case SR_PC: - tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); - break; - case SR_MSR: - msr_read(dc, cpu_R[dc->rd]); - break; - case SR_EAR: - { - TCGv_i64 t64 = tcg_temp_new_i64(); - tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); - if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); - } else { - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); - } - tcg_temp_free_i64(t64); - } - break; - case SR_ESR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, esr)); - break; - case SR_FSR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, fsr)); - break; - case SR_BTR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, btr)); - break; - case SR_EDR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, edr)); - break; - case 0x800: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, slr)); - break; - case 0x802: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, shr)); - break; - case 0x2000 ... 0x200c: - rn = sr & 0xf; - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, pvr.regs[rn])); - break; - default: - cpu_abort(cs, "unknown mfs reg %x\n", sr); - break; - } - } - - if (dc->rd == 0) { - tcg_gen_movi_i32(cpu_R[0], 0); + case 0x2000 ... 0x200c: + tcg_gen_ld_i32(dest, cpu_env, + offsetof(CPUMBState, pvr.regs[arg->rs - 0x2000])); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid mfs reg 0x%x\n", arg->rs); + break; } + return true; } static void do_rti(DisasContext *dc) @@ -1593,7 +1596,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} }; From patchwork Mon Aug 31 16:05:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248816 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3462643ilg; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 ++++ target/microblaze/translate.c | 64 ++++++++++++++++++++++++++-------- 2 files changed, 55 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 43c9e16819..fb0f0e6838 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -159,6 +159,9 @@ flt 010110 ..... ..... ----- 0101 000 0000 @typea0 fint 010110 ..... ..... ----- 0110 000 0000 @typea0 fsqrt 010110 ..... ..... 00000 0111 000 0000 @typea0 +get 011011 rd:5 00000 0 ctrl:5 000000 imm:4 +getd 010011 rd:5 00000 rb:5 0 ctrl:5 00000 + idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea @@ -201,6 +204,9 @@ pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea +put 011011 00000 ra:5 1 ctrl:5 000000 imm:4 +putd 010011 00000 ra:5 rb:5 1 ctrl:5 00000 + rsub 000001 ..... ..... ..... 000 0000 0000 @typea rsubc 000011 ..... ..... ..... 000 0000 0000 @typea rsubk 000101 ..... ..... ..... 000 0000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 582f5a1577..2c87d671ae 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1560,33 +1560,68 @@ static void dec_null(DisasContext *dc) } /* Insns connected to FSL or AXI stream attached devices. */ -static void dec_stream(DisasContext *dc) +static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl) { TCGv_i32 t_id, t_ctrl; - int ctrl; if (trap_userspace(dc, true)) { - return; + return true; } t_id = tcg_temp_new_i32(); - if (dc->type_b) { - tcg_gen_movi_i32(t_id, dc->imm & 0xf); - ctrl = dc->imm >> 10; + if (rb) { + tcg_gen_andi_i32(t_id, cpu_R[rb], 0xf); } else { - tcg_gen_andi_i32(t_id, cpu_R[dc->rb], 0xf); - ctrl = dc->imm >> 5; + tcg_gen_movi_i32(t_id, imm); } t_ctrl = tcg_const_i32(ctrl); - - if (dc->rd == 0) { - gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); - } else { - gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); - } + gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl); tcg_temp_free_i32(t_id); tcg_temp_free_i32(t_ctrl); + return true; +} + +static bool trans_get(DisasContext *dc, arg_get *arg) +{ + return do_get(dc, arg->rd, 0, arg->imm, arg->ctrl); +} + +static bool trans_getd(DisasContext *dc, arg_getd *arg) +{ + return do_get(dc, arg->rd, arg->rb, 0, arg->ctrl); +} + +static bool do_put(DisasContext *dc, int ra, int rb, int imm, int ctrl) +{ + TCGv_i32 t_id, t_ctrl; + + if (trap_userspace(dc, true)) { + return true; + } + + t_id = tcg_temp_new_i32(); + if (rb) { + tcg_gen_andi_i32(t_id, cpu_R[rb], 0xf); + } else { + tcg_gen_movi_i32(t_id, imm); + } + + t_ctrl = tcg_const_i32(ctrl); + gen_helper_put(t_id, t_ctrl, reg_for_read(dc, ra)); + tcg_temp_free_i32(t_id); + tcg_temp_free_i32(t_ctrl); + return true; +} + +static bool trans_put(DisasContext *dc, arg_put *arg) +{ + return do_put(dc, arg->ra, 0, arg->imm, arg->ctrl); +} + +static bool trans_putd(DisasContext *dc, arg_putd *arg) +{ + return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl); } static struct decoder_info { @@ -1596,7 +1631,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} }; From patchwork Mon Aug 31 16:05:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248819 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3463261ilg; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All instructions have been convered. Issue sigill if decodetree does not match. Remove argument decode from DisasContext. Remove microblaze-decode.h. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/microblaze-decode.h | 59 ---------------------- target/microblaze/translate.c | 73 +-------------------------- 2 files changed, 1 insertion(+), 131 deletions(-) delete mode 100644 target/microblaze/microblaze-decode.h -- 2.25.1 diff --git a/target/microblaze/microblaze-decode.h b/target/microblaze/microblaze-decode.h deleted file mode 100644 index 17b2f29fff..0000000000 --- a/target/microblaze/microblaze-decode.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * MicroBlaze insn decoding macros. - * - * Copyright (c) 2009 Edgar E. Iglesias - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#ifndef TARGET_MICROBLAZE_MICROBLAZE_DECODE_H -#define TARGET_MICROBLAZE_MICROBLAZE_DECODE_H - -/* Convenient binary macros. */ -#define HEX__(n) 0x##n##LU -#define B8__(x) ((x&0x0000000FLU)?1:0) \ - + ((x&0x000000F0LU)?2:0) \ - + ((x&0x00000F00LU)?4:0) \ - + ((x&0x0000F000LU)?8:0) \ - + ((x&0x000F0000LU)?16:0) \ - + ((x&0x00F00000LU)?32:0) \ - + ((x&0x0F000000LU)?64:0) \ - + ((x&0xF0000000LU)?128:0) -#define B8(d) ((unsigned char)B8__(HEX__(d))) - -/* Decode logic, value and mask. */ -#define DEC_ADD {B8(00000000), B8(00110001)} -#define DEC_SUB {B8(00000001), B8(00110001)} -#define DEC_AND {B8(00100001), B8(00110101)} -#define DEC_XOR {B8(00100010), B8(00110111)} -#define DEC_OR {B8(00100000), B8(00110111)} -#define DEC_BIT {B8(00100100), B8(00111111)} -#define DEC_MSR {B8(00100101), B8(00111111)} - -#define DEC_BARREL {B8(00010001), B8(00110111)} -#define DEC_MUL {B8(00010000), B8(00110111)} -#define DEC_DIV {B8(00010010), B8(00110111)} -#define DEC_FPU {B8(00010110), B8(00111111)} - -#define DEC_LD {B8(00110000), B8(00110100)} -#define DEC_ST {B8(00110100), B8(00110100)} -#define DEC_IMM {B8(00101100), B8(00111111)} - -#define DEC_BR {B8(00100110), B8(00110111)} -#define DEC_BCC {B8(00100111), B8(00110111)} -#define DEC_RTS {B8(00101101), B8(00111111)} - -#define DEC_STREAM {B8(00010011), B8(00110111)} - -#endif diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2c87d671ae..8f69ca50b2 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -24,7 +24,6 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" -#include "microblaze-decode.h" #include "exec/cpu_ldst.h" #include "exec/helper-gen.h" #include "exec/translator.h" @@ -65,13 +64,7 @@ typedef struct DisasContext { bool r0_set; /* Decoder. */ - int type_b; - uint32_t ir; uint32_t ext_imm; - uint8_t opcode; - uint8_t rd, ra, rb; - uint16_t imm; - unsigned int cpustate_changed; unsigned int tb_flags; unsigned int tb_flags_to_set; @@ -82,8 +75,6 @@ typedef struct DisasContext { /* Immediate branch-taken destination, or -1 for indirect. */ uint32_t jmp_dest; - - int abort_at_next_insn; } DisasContext; static int typeb_imm(DisasContext *dc, int x) @@ -184,21 +175,6 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } -static int32_t dec_alu_typeb_imm(DisasContext *dc) -{ - tcg_debug_assert(dc->type_b); - return typeb_imm(dc, (int16_t)dc->imm); -} - -static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) -{ - if (dc->type_b) { - tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); - return &cpu_imm; - } - return &cpu_R[dc->rb]; -} - static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { if (likely(reg != 0)) { @@ -1549,16 +1525,6 @@ static void do_rte(DisasContext *dc) dc->tb_flags &= ~DRTE_FLAG; } -static void dec_null(DisasContext *dc) -{ - if (trap_illegal(dc, true)) { - return; - } - qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", - (uint32_t)dc->base.pc_next, dc->opcode); - dc->abort_at_next_insn = 1; -} - /* Insns connected to FSL or AXI stream attached devices. */ static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl) { @@ -1624,40 +1590,6 @@ static bool trans_putd(DisasContext *dc, arg_putd *arg) return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl); } -static struct decoder_info { - struct { - uint32_t bits; - uint32_t mask; - }; - void (*dec)(DisasContext *dc); -} decinfo[] = { - {{0, 0}, dec_null} -}; - -static void old_decode(DisasContext *dc, uint32_t ir) -{ - int i; - - dc->ir = ir; - - /* bit 2 seems to indicate insn type. */ - dc->type_b = ir & (1 << 29); - - dc->opcode = EXTRACT_FIELD(ir, 26, 31); - dc->rd = EXTRACT_FIELD(ir, 21, 25); - dc->ra = EXTRACT_FIELD(ir, 16, 20); - dc->rb = EXTRACT_FIELD(ir, 11, 15); - dc->imm = EXTRACT_FIELD(ir, 0, 15); - - /* Large switch for all insns. */ - for (i = 0; i < ARRAY_SIZE(decinfo); i++) { - if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { - decinfo[i].dec(dc); - break; - } - } -} - static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); @@ -1667,7 +1599,6 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; dc->cpustate_changed = 0; - dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; @@ -1724,7 +1655,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) ir = cpu_ldl_code(env, dc->base.pc_next); if (!decode(dc, ir)) { - old_decode(dc, ir); + trap_illegal(dc, true); } if (dc->r0) { @@ -1764,8 +1695,6 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); - assert(!dc->abort_at_next_insn); - if (dc->base.is_jmp == DISAS_NORETURN) { /* We have already exited the TB. */ return; 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[209.51.188.17]) by mx.google.com with ESMTPS id 125si8779392ybk.264.2020.08.31.09.35.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:35:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Eq2G/QjM"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmmF-0004os-LF for patch@linaro.org; Mon, 31 Aug 2020 12:35:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmLS-0006sj-R1 for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:46 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:46618) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmLR-0006Bh-3m for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:46 -0400 Received: by mail-pl1-x642.google.com with SMTP id k13so3225923plk.13 for ; Mon, 31 Aug 2020 09:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NFMrG515781fPkhuV8GqRES+jyHXpSFNJfiQ1prWFi4=; b=Eq2G/QjMwh1Lud9/DfzphAKW/OOoMT9096Ls4XhI0plD82Ti/L9FE6SxHlUEzXllmo OAZqmCFsmiFpU3PTjLwvduWtSMh4gxca9SPyA6Qastx2hZgkgFF2KO03ybOMCKxNO+xM w4hQ/YaBPYADuNKL962McDeBV9+bnNjt4V8R7uGv3uUWNL8GZgPVu7SgAzSPV41fdDP2 LDs69udQczV0lIic5dEWKggEE4cWkd/G+Nt5tkYHz6rjueBbQcX1a1oQxB9+epP3YOwF TXMQCgd+7UQOzrljVY4co3dQbGKuB4kdxw0whpm3FRIYBdS6OJ6XmnAE+9DlKMiVHa74 0vqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NFMrG515781fPkhuV8GqRES+jyHXpSFNJfiQ1prWFi4=; b=nUS0oTFDaWVNTH52Ut4x5kmKD+u84mVX37HmZnLzyhSVess2SAaAy/KveS4RjHqbNy RLvSpt1erv9KFyM4YqgeOZiE3QssikgEUH2qlkeuS24pamwqq9nTuKThvyOdCCdwMg0i waQC4pXcifd3UpAJn4IE0J98c7x4FhptEzfKHHBP5/Jg9KPRecbMb7v4KAyMRuQJnzj6 UC/TnGMVRPqbINnxiQdxlCh4ta5Xam7imabZBAtoGkCSHuMK+cnym5GT1DUFcO1QOneO X/sk666TX7Jx6fOGcfM3Wg8Ki4JLPYaHyTJDopo6tLQQ2C1nKy0DTGXt1mJVCHCL9Mo/ a5jw== X-Gm-Message-State: AOAM5308vdKXFhVTXNpDFeqe5+79L7PdVm8YF7fzAOarw9ROx67W/zH1 YSevufG6bav+ofiR6tBl7KSjF4v5RqnLmA== X-Received: by 2002:a17:90a:2b88:: with SMTP id u8mr76295pjd.37.1598890063437; Mon, 31 Aug 2020 09:07:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 74/76] target/microblaze: Remove cpu_R[0] Date: Mon, 31 Aug 2020 09:05:59 -0700 Message-Id: <20200831160601.833692-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not initialize cpu_R[0], as this should be totally unused. The cpu_for_read and cpu_for_write functions use a local temp. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8f69ca50b2..8c287457a9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1842,7 +1842,13 @@ void mb_tcg_init(void) static const struct { TCGv_i32 *var; int ofs; char name[8]; } i32s[] = { - R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), + /* + * Note that r0 is handled specially in reg_for_read + * and reg_for_write. Nothing should touch cpu_R[0]. + * Leave that element NULL, which will assert quickly + * inside the tcg generator functions. + */ + R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), From patchwork Mon Aug 31 16:06:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248825 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3467772ilg; Mon, 31 Aug 2020 09:43:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwmrJdq+z/A9bFcvPFzBLU74wjtU/w+y/Jwl9p9VrWacHl7gDDYo+3uNlrV5guHmcu9yY7n X-Received: by 2002:a25:244a:: with SMTP id k71mr3584615ybk.504.1598892190013; Mon, 31 Aug 2020 09:43:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598892190; cv=none; d=google.com; s=arc-20160816; b=CXfjdjQLm3SuhTYkwDrSXvc/4Di6KoECdhbJ9Pl6vis96U4dALGpuMS+E/VTQN/Uqk vxEi/IUuK0kSu/ofO3klZXNieedxPAvK6Hba4ynwdYT1IhBxt3dHUh9j9r1kJhjiAi2w v1scHkSDKqY4oJ0gQAzqIY7i8KRLHqIqBHdnax6MAC920hB0+26/Kw58SFDrGYJIiHdZ H6QlabGns70FDiLdCv8fsBf11RqTyJuHgogNKOwy5n/ruLZikFWlaFHRASTyU5HUStOt GXmnvTp0jG5pkoWmyDFMGwcXs3+kRfval60SOogGSpsCdwJMXUB2e7J5ihficiNOBe+Y c6RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b/gvE9gRrBdUc3JON5McXpRJVtB1reGxqOBY4wQzJOY=; b=awSUy5BmAvDEKCplWuL9gzdVn65IcbyHb6y6lKrZDTdcCDad/TCZOEX1jrG0TiJ35D r2dJlpNM4l1BrONRLcgtkJTklQtOyLjkrAWAAnFHBFLERExjQI+Z/TfIBjUiTgt+86yE eu9MjFBzYbxtfDZyzG9YGEgNyt9XONObD4hSnjHOI+Hi3fsiGwJK7Reh/L2QV5k2aHsi IUZoBzIaqYm5tOeQ+7BsBXPCC3Jbfj2GNbmiILSWMmZXOP+TD2HTNAkIqJXzQdFm1kin QEm6UO9yF2fGujp8cpaFS2dT5gqjk1hvPKm+NQEiNWNemc2+f5FvAG/AVpheHbkAiOiT TpUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oTjhePcC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The mmu_read, mmu_write, get, and put helpers do not touch the general registers, or any of the other variables managed by tcg. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 3980fba797..f740835fcb 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -21,11 +21,11 @@ DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_3(mmu_read, i32, env, i32, i32) -DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32) #endif DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_2(get, i32, i32, i32) -DEF_HELPER_3(put, void, i32, i32, i32) +DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32) +DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32) From patchwork Mon Aug 31 16:06:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248820 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3463507ilg; Mon, 31 Aug 2020 09:36:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz58CqLDDmO/rK902BeSqoQn2nhK7M70OZj9VL5Kcaa+h3LJ195PAENKIMYtSOL+KZIxOXg X-Received: by 2002:a25:e80e:: with SMTP id k14mr3799522ybd.16.1598891806336; Mon, 31 Aug 2020 09:36:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598891806; cv=none; d=google.com; s=arc-20160816; b=Lsv9c2vp/oNGY9Coxr6sdye2aVD2o8whYR3UouK7vMMs380zV4+Grkrdydr+Fd+l1n AcGGQRBym8ssCKRmBcwrMSJKjHEoETBYKPzPPG4Sw9AFbocKlh2hKWFun4u/kmLgJB/l 4/dlPa5dRGiAf3DOQUaIuPoRv5WW/e0jLcXEhgZ5M1DLtpZqwOD+3ABrGqVSjZ34L3iJ gpJ/69yUqvGzQFtyWuTbfxHOHNd/z5FEVHHKZpmMnTQsSQk67+f2oPdiAfVDo1ffKpvX aKcpy5d8v9F+rYn975RkfV/KudBRi9t+AWPQhBmTHSeTfi0UYkMiBMj7J7ivEdyHbE4S YbXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1WdUOJWGCdcV9QIGGOS0y70LT85NGsncqmvGoqTi8AE=; b=JwxjJFaZTxdoU7LGa6qAprwy9aAGvIdELScH/B5VesrOzdzwrHAy6bW7KqrAHIHG3w cJQ3HBCs8H109nnp3awVGUyiPW3XJyUph+YzIcaFfOmI+g4h67CZiVk3nHOzV9UtW1BP Rpo4kpTMlaHgxPWTKOdEQZz79f2YQXLKirLLDl0d0cVFmwFsvSXEnovc0/O5lTHruR/k vopN2wgby3sL8loeTcLdBLb6MY9oEXyUv8o8ihwTHYj6lLSBF8C3p5yRrAhDx+6UF2Y6 UMSRaRVYiG0/zI0lNe7GQD3NvNNKvsuSpeg+hGKLJjGpZvfbL4hwH9osET8bfPFTy7Ty l3+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e69b8CsJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t4si993865ybi.422.2020.08.31.09.36.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:36:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e69b8CsJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmnV-0007PF-Q5 for patch@linaro.org; Mon, 31 Aug 2020 12:36:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34886) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmLW-00072n-Mx for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:50 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:34142) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmLU-0006CK-OU for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:07:50 -0400 Received: by mail-pg1-x544.google.com with SMTP id i10so846115pgk.1 for ; Mon, 31 Aug 2020 09:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1WdUOJWGCdcV9QIGGOS0y70LT85NGsncqmvGoqTi8AE=; b=e69b8CsJeYkWnBKvekJVHEOqMk9y1E4fM/sL+A12hFC5kyXMEE4NYTB9HkSwooL6Z1 tuIJCTBcW9Fn6CF1UGzNux4+Q/kpIcCjBW0025jOvaepFCcRdpnuDsh8/asu0GrEj+Zx CjW6ji916SXGhWbeHNjoQLdICCwiNcSRVrI7WJmtJeOb8/yeKu0V8EeRTlX2fRv/aU3P GjC4kfEMqWK/f/reTysvW86vO1n7PJ0sLRUGOdzCppqiLBWZRbYR2lSB7GYvxurAqKQ4 IYWCWsI2YI+QesbKQkCRdiV4g3u3vPdWJqignyDN9nCS0jYrNiBYoWpzl4882ji7bDkS G+XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1WdUOJWGCdcV9QIGGOS0y70LT85NGsncqmvGoqTi8AE=; b=OoDKvVwxZt5PukGYZMMWA7E0RI16UHW4swXM+VovC2pHcOQNxGIYoIIAXOPjsDPwfq fMGerLys+PvZ7Bv3Ao3qcraMvHkV66HzDDQcyW5btw6IYzfRNBIJ8uG57vKh5oHVGG8r gxFXAj4rixH/zJ/5ZDduCpnAqDfJ4WeLcSCM/mLaAzc6XMKpZ0NdQdMrE2uIv0Q7NuHN sThQ8CG5K8pFj9y+yLvumFr/CvILSDsFyhFht4chUH4jvIEOqnBMsOoxPaNeCsAvMv/n t6ssf/DMF/uLTCSUcpYCC8tGLnV/LGYR8AX9iMdKP3kaovJoko77Dy3XX8Gwy1tQtT90 eMjA== X-Gm-Message-State: AOAM532lPc5eQgWuXdmCx8reWTLbRaTH54jBY3pK4K43uh/FV3wJL3O4 pRYYNqHW+lb+//xKc+x7XtWtYzcHWGXGxA== X-Received: by 2002:a65:6882:: with SMTP id e2mr1803507pgt.290.1598890065867; Mon, 31 Aug 2020 09:07:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:07:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 76/76] target/microblaze: Reduce linux-user address space to 32-bit Date: Mon, 31 Aug 2020 09:06:01 -0700 Message-Id: <20200831160601.833692-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" User-space programs cannot use the 64-bit lwea/swea instructions. We can improve code generation and runtime by restricting the user-only address space to 32-bit. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu-param.h | 15 +++++++++++++++ target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/translate.c | 28 +++++++++++++++++++++++++++- 4 files changed, 45 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 4abbc62d50..4d8297fa94 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -8,9 +8,24 @@ #ifndef MICROBLAZE_CPU_PARAM_H #define MICROBLAZE_CPU_PARAM_H 1 +/* + * While system mode can address up to 64 bits of address space, + * this is done via the lea/sea instructions, which are system-only + * (as they also bypass the mmu). + * + * We can improve the user-only experience by only exposing 32 bits + * of address space. + */ +#ifdef CONFIG_USER_ONLY +#define TARGET_LONG_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#else #define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 +#endif + /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 #define NB_MMU_MODES 3 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 4298f242a6..d11b6fa995 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint32_t pc; uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ - uint64_t ear; + target_ulong ear; uint32_t esr; uint32_t fsr; uint32_t btr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 1667822fb7..48547385b0 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -303,8 +303,8 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, iflags = cpu->env.iflags; qemu_log_mask(CPU_LOG_INT, - "Unaligned access addr=" TARGET_FMT_lx - " pc=%x iflags=%x\n", addr, cpu->env.pc, iflags); + "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n", + (target_ulong)addr, cpu->env.pc, iflags); esr = ESR_EC_UNALIGNED_DATA; if (likely(iflags & ESR_ESS_FLAG)) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8c287457a9..a377818b5e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -687,6 +687,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) return ret; } +#ifndef CONFIG_USER_ONLY static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) { int addr_size = dc->cpu->cfg.addr_size; @@ -712,6 +713,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) } return ret; } +#endif static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) @@ -776,8 +778,12 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +#endif } static bool trans_lbui(DisasContext *dc, arg_typeb *arg) @@ -803,8 +809,12 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +#endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) @@ -830,8 +840,12 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +#endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) @@ -910,8 +924,12 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +#endif } static bool trans_sbi(DisasContext *dc, arg_typeb *arg) @@ -937,8 +955,12 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +#endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) @@ -964,8 +986,12 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +#endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) @@ -1818,7 +1844,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n" - "ear=0x%016" PRIx64 " slr=0x%x shr=0x%x\n", + "ear=0x" TARGET_FMT_lx " slr=0x%x shr=0x%x\n", env->esr, env->fsr, env->btr, env->edr, env->ear, env->slr, env->shr);