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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not attempting to use a single cross-compiler for both big-endian and little-endian at this time. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- tests/tcg/configure.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 7d714f902a..598a50cd4f 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -94,7 +94,7 @@ for target in $target_list; do xtensa|xtensaeb) arches=xtensa ;; - alpha|cris|hppa|i386|lm32|m68k|openrisc|riscv64|s390x|sh4|sparc64) + alpha|cris|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64) arches=$target ;; *) From patchwork Fri Aug 28 14:18:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248512 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1123987ilg; Fri, 28 Aug 2020 07:21:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFZiLve6NPwXEoAcHPlhR82Aerlf7M4c4YET82yJyzklLbvMHWf5aJM+M2+IpYkfDQFre+ X-Received: by 2002:a25:d497:: with SMTP id m145mr2659157ybf.484.1598624488693; Fri, 28 Aug 2020 07:21:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624488; cv=none; d=google.com; s=arc-20160816; b=hr7kS4whfL0t/XkWdnmxC0KiWjQLdUi+Q7rpHXsB+fIZXFrUD3SBcC7cHUcIBmFj7n BALE0hnwCLGCEHIWtUdnt5loPy4xOxVhs/W1pKf58v9IBWVspi4IDT1ZzDHECclMphYs OvIn4zZoxdkuDSPqs7DP7FUKEidbrSzuEAyLezXxkKBRXTGlZDkW5w/pGVkL5h3u471Z /VwmxATg/S4YdEHFFmR9h4PI/ZaJlzeuuIlzNWsaEr8PiVueNzsxV/0xwzbliXeZn1MF po+KKbmMerJmoVAhVH5exCkuM+5RCgriKZ9yrcLdiBGX0NeO/TN/B7lBJl4mYxN2sDXr M05A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LfqpuF2wNDM0fswn7p/0qMKThcYJi8mNAXbQlEHPUSw=; b=qXo/k3zSK3Psjndan4KS54X2rpwU7BR4ZwMpcg0rfwMi9k+90jU2ovJvXSrNdNwmeG W355GsGMaxPrtCGXTk7h/8RoajD24bZE3tyDCt8hOxcQ1tnHknYHctAxRkNlzYm2LFBe OYW5YEwBn+jwV7wGX2WAzauolTCI4UnAnER67MS7CAA5n7XhfVltt3ufa9JAE2+Q5p/t NNx/xZRbPf7JVKHNJRvdBSssvfdvIYCKznWsDhyn3DUonPMnWbzxt+GAnNIBFpd6/Y5E hdR//jg/XxwT/jU4u38hmxMu5jIre8rZJ0dMKe4R977a7eVsy3uwDY/0Q5bVSlup8sWc jgEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=peFYGHyy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is optional in ISO C, and not all cpus provide it. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- tests/tcg/multiarch/float_convs.c | 2 ++ tests/tcg/multiarch/float_madds.c | 2 ++ 2 files changed, 4 insertions(+) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/tests/tcg/multiarch/float_convs.c b/tests/tcg/multiarch/float_convs.c index 47e24b8b16..e9be75c2d5 100644 --- a/tests/tcg/multiarch/float_convs.c +++ b/tests/tcg/multiarch/float_convs.c @@ -30,7 +30,9 @@ float_mapping round_flags[] = { #ifdef FE_DOWNWARD { FE_DOWNWARD, "downwards" }, #endif +#ifdef FE_TOWARDZERO { FE_TOWARDZERO, "to zero" } +#endif }; static void print_input(float input) diff --git a/tests/tcg/multiarch/float_madds.c b/tests/tcg/multiarch/float_madds.c index eceb4ae38b..e422608ccd 100644 --- a/tests/tcg/multiarch/float_madds.c +++ b/tests/tcg/multiarch/float_madds.c @@ -29,7 +29,9 @@ float_mapping round_flags[] = { #ifdef FE_DOWNWARD { FE_DOWNWARD, "downwards" }, #endif +#ifdef FE_TOWARDZERO { FE_TOWARDZERO, "to zero" } +#endif }; From patchwork Fri Aug 28 14:18:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248517 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1125612ilg; Fri, 28 Aug 2020 07:23:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw8cQuzrFkGca9eqpZkl242hfHYDodw6PAPAiRNIDAe6p2SG508ULuUJdNSxLYpw8y33TQS X-Received: by 2002:a25:d486:: with SMTP id m128mr2655297ybf.188.1598624600992; Fri, 28 Aug 2020 07:23:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624600; cv=none; d=google.com; s=arc-20160816; b=JATX6OGw5Yn65WIv+thBmnR2amdYxFHb00VrdbkWaY8Dm6Rm+kyiAd3oOe92DNstke aKxYBYvONg6zMdwci7WeEOPv/d/1IE7rNGlA6CjTvNelXazCsksy9rFru0IK+RWR+g3o IJzQGTfERNrJQg332kbZkqti+uOUm+uffpf/cEP64ymwaHkn7lnyEJxZvCgoJzn3DvKU exvnF95F2CDsjujDMSjm62JYBZ8iHUs9zCN078CZP3jw4RlRM8TDY3m2cj75ZcIyT9pR nN0x1CoMFYvGuVdPQB+5A2iDNKw6SfttiK9colw+acVShsPbrAB4o7C+csUuCpRajIfS 0bog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4/yFPag8qdnd69lG7PXq/hNxrp/qSy4kCl2N10yso4g=; b=VXQuEXmCHeY7sb0x80yTWyBMwjzKXc+cNJr3+l3YVnzTseXmZubWWV+BFmSYf3Q3iz SiPKOWRCpWZCwx5q5S9qtneXWPtdOCYTpOeAeayIaBqtvnBhRke8FDENEgFUdWk2yshC Ph0nlYnqB4oA056i8DVCNwuovODeIo6bDWNiN1wtL3nquE5n7kFJIHtUyAeojZQjv7yQ MQNKkNt1O0+0MFyD3V6NRLQkG/Iet4p/0AKYNGsNcWytobmVR+F0QxV7TLSv+vUfVAg/ uGBXCqrgOlTViny5fuoXKBYJzeq8ezqnsqq/z17c+MXoIt2GarmwtdT4j9lKbWbArGpQ YB+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dEvb7744; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c6si912273ybk.112.2020.08.28.07.23.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:23:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dEvb7744; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfHk-0006P7-DU for patch@linaro.org; Fri, 28 Aug 2020 10:23:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfE9-0007pO-OR for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:37 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:36186) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfE8-00051p-Ao for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:37 -0400 Received: by mail-pg1-x541.google.com with SMTP id p37so532242pgl.3 for ; Fri, 28 Aug 2020 07:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4/yFPag8qdnd69lG7PXq/hNxrp/qSy4kCl2N10yso4g=; b=dEvb7744QiX0jYi3LW2PeIb24gLmK98aD/jOZEaUvsYDgiSJd+DE7LNiDEtSzsw0OT TLcoCtVqxPTXzyggpo8Tm4pKY5OwNKGQgbwiBD36fK3v2/zVpCMF5iO8CbiBQfsBstv9 iUcD8wcxzr7j/68ubvICK/uCP/msDES7DcTaftFRuhWBav+qasz75owl5Ud3kiUQqGla 8tkLIpeXzyLMsBHdMivvy2b+2V994NkqGwy9IxCn7obW6iODzXm1wr6Zwpr0OjP8l2Du 0cvS3Xk1V0up+ThE/4O5/PeS3IuKAtcQYutBVuh72z4VRIwH3RRbCdmCau1HOkNYnNvE Do4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4/yFPag8qdnd69lG7PXq/hNxrp/qSy4kCl2N10yso4g=; b=FG8CdySAqKjTiN2HWmZY4Qz2+nvBmrjWYNcY6EcVyCeVup4CoPJaTd538xdSQ2hKWZ NBnvyRXoOw48+ERjn39Lax1wFPkWHQpunSNSt0qVemd3qGiL1ZytFp5IQsclWEw9pFBf TLIP7t2me8vThmt+L+Sbgsqd4AocTEOBeJSbB0GOMNg/RF0/WQccEOa+lRbtObYobeJv 38eHYUNH+Wy4OywdMWxHdZD2rM7E36pmdupYJhRJH2tMY4z1FdE3nF9tF+GQqsTcco8S H/2ziF71G2owEZEhC9uG++uaccrfFqlJs9n7GpFMCCFuGgmrO16qFpZKoBynLyhtnp7x 6g6Q== X-Gm-Message-State: AOAM532R7EeJ5bkYMg0UPCGNjWDYLNEPLy70PmnvKu+nCY9B22PDOnUv fTKZ4NOEScRoqep3cqntrfm7U14hcfFUIg== X-Received: by 2002:a63:4a1d:: with SMTP id x29mr1452626pga.317.1598624374751; Fri, 28 Aug 2020 07:19:34 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:19:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/76] tests/tcg: Do not require FE_* exception bits Date: Fri, 28 Aug 2020 07:18:16 -0700 Message-Id: <20200828141929.77854-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Define anything that is missing as 0, so that flags & FE_FOO is false for any missing FOO. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- tests/tcg/multiarch/float_helpers.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/tests/tcg/multiarch/float_helpers.h b/tests/tcg/multiarch/float_helpers.h index 6337bc66c1..309f3f4bf1 100644 --- a/tests/tcg/multiarch/float_helpers.h +++ b/tests/tcg/multiarch/float_helpers.h @@ -8,6 +8,23 @@ #include +/* Some hosts do not have support for all of these; not required by ISO C. */ +#ifndef FE_OVERFLOW +#define FE_OVERFLOW 0 +#endif +#ifndef FE_UNDERFLOW +#define FE_UNDERFLOW 0 +#endif +#ifndef FE_DIVBYZERO +#define FE_DIVBYZERO 0 +#endif +#ifndef FE_INEXACT +#define FE_INEXACT 0 +#endif +#ifndef FE_INVALID +#define FE_INVALID 0 +#endif + /* Number of constants in each table */ int get_num_f16(void); int get_num_f32(void); From patchwork Fri Aug 28 14:18:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248508 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1122692ilg; Fri, 28 Aug 2020 07:19:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxQlNkzkgnMI6OvbQCZnlMmVCFZ5rfnWZU7aDypbL8cQsh5oCsx09Q17quYdrCuR8i7ycDG X-Received: by 2002:a25:80d3:: with SMTP id c19mr2745751ybm.13.1598624392098; Fri, 28 Aug 2020 07:19:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624392; cv=none; d=google.com; s=arc-20160816; b=XaMNtoSBYzO/5f8q32iVge5WbP8pxw+PhUcU++67fbhI0Vw3qZ5QNz4wMKWRk7INZf QnfAZHZgFgFPlBYAPWCjghiCP+0cqkAgZA97cQ39iGJffzzWqY9tOQPjwT52N5gA5ipl kuamFGxFtvm/5WdVlUZI4G/zs44YFvDO1Du5jrYkrYreFT1BX6OQpoq/MSqwsMC8Lw/9 r4L+4Vax5x8rv+HVYfb5iSgqoNprooMc7HjpfzVpYxkmzucluCe3K1Aeda+VPLPcxKjy rLwGGjtoWMf3oWXhblVUm6DVkcQV8BV0iXLdpMQWelTetuDg42jSgoR4MfK11UYqGgDd JG8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6qPmiblB+ZyNN9MP1YkeatmcIUSnXTMdD0ACsae5YvQ=; b=yt5YCzf1DOgQUo6dU1mJp8sepRBXOOhfqAox0R7cGVNgeuXUWnWoNj1ZkrUf07DzuF fMxyMEHOW4Rqp8ngLHEHMrqk17Nl43zFWsKMta4DfQYd7Ea0UH8khF5JKTK917zApd1O yiJnl2RGwKEoVSt3B+eoCFWjZ8OCptrmrIrwvkVh/ebrEnd+iCS4+JxaHtLHDpx409ZZ eB5CvE5dtk8FbaqBPFxMRfjREDRPdrPoqWtGYNWyBkflreB0QyWNbsJPXwerfMWCzWbS A3U/kKQVRPGkK1dm7C+fcK1Df6Xzr2udPiIDcbv8Vvi5tLI49DrZU5wvtAKHRnCpo29u RW7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kw1IDEoT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y8si1077610ybr.217.2020.08.28.07.19.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:19:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kw1IDEoT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfEN-0007vS-FS for patch@linaro.org; Fri, 28 Aug 2020 10:19:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEB-0007sV-PG for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:39 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:35130) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfE9-00052j-Tc for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:39 -0400 Received: by mail-pl1-x641.google.com with SMTP id a8so533892plm.2 for ; Fri, 28 Aug 2020 07:19:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6qPmiblB+ZyNN9MP1YkeatmcIUSnXTMdD0ACsae5YvQ=; b=Kw1IDEoTe6DpgIJU2sBcZtyV5KriRp/bVegwRHloievWliYSBEY3zZcCtjT1RUaIfR HCMSiPsTGFgV/35Nvjw3wCV21zCDKyd58f51qpfH7geoAXfgOL4s0MPmTcHcRaKtcFsy kMPLUbcHTj9AGDBVA2v65lM09AN/wxNdJpospBcfrkRw1TdG4ygevocluhc4+A6Yc/8N f7B9sgTAOgT/oSUMNGJpXVWWvIaGAcxcDxaobakVnE/BhrDlKnd7+8HmLOMrNYsTHAtl Pdv9g8rP9KHKibWHNNO9r/WtpzxizZn9ZkfNJxB5mtpFB+QU0o4rd2JHLorEyjMNK0GM Z+tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6qPmiblB+ZyNN9MP1YkeatmcIUSnXTMdD0ACsae5YvQ=; b=diLRf36WHgqWrMZ4lla3j41KvRPSSR97UhQn6Q/ZcSNRvR2juJbWNWMC8J9OELNv48 c8DQhjCURT7+MeOPa2e3A5wm6NbuO5JDarE7nGpu6rrkvRvkVKO4JIyyTfNI7tyb9jX4 OSOAjGQ/qOCD/IGsluKeTPnAAWe5kC7Doo76NPDvvJ+lmSwLc9HwhhQQy3YqL92go2Rc YK6V3ECOwK2t5Yd613OQMDMuPqlc8o+N635MbDn5v+0lU56ivhEWWQu0TqdKhZ8hhRoh k+wmsaLREAbsn4dPUn9cFG8BwWsVR0BUKKr39Qhqk0lQyRzaFj9pwyxBbWCIsTaPrfes ELmQ== X-Gm-Message-State: AOAM5313MhajQFZAnaJo/RZaHxVh09v6AcP2H8/9lvBzTap1/xq/wWUV psi+ua+vLOpqpeFyaYQjoSythgfR6Vh/iQ== X-Received: by 2002:a17:90a:af82:: with SMTP id w2mr1432843pjq.185.1598624375949; Fri, 28 Aug 2020 07:19:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:19:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/76] target/microblaze: Tidy gdbstub Date: Fri, 28 Aug 2020 07:18:17 -0700 Message-Id: <20200828141929.77854-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use an enumeration for the gdb register mapping. Use one switch statement for the entire dispatch. Drop sreg_map and simply enumerate those cases explicitly. Force r0 to have value 0 and ignore writes. Signed-off-by: Richard Henderson --- target/microblaze/gdbstub.c | 193 +++++++++++++++++++----------------- 1 file changed, 101 insertions(+), 92 deletions(-) -- 2.25.1 diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 73e8973597..e65ec051a5 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -21,58 +21,80 @@ #include "cpu.h" #include "exec/gdbstub.h" +/* + * GDB expects SREGs in the following order: + * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. + * + * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't + * map them to anything and return a value of 0 instead. + */ + +enum { + GDB_PC = 32 + 0, + GDB_MSR = 32 + 1, + GDB_EAR = 32 + 2, + GDB_ESR = 32 + 3, + GDB_FSR = 32 + 4, + GDB_BTR = 32 + 5, + GDB_PVR0 = 32 + 6, + GDB_PVR11 = 32 + 17, + GDB_EDR = 32 + 18, + GDB_SLR = 32 + 25, + GDB_SHR = 32 + 26, +}; + int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUClass *cc = CPU_GET_CLASS(cs); CPUMBState *env = &cpu->env; - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything and return a value of 0 instead. - */ - static const uint8_t sreg_map[6] = { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; + uint32_t val; - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { - return gdb_get_reg32(mem_buf, env->regs[n]); - } else { - n -= 32; - switch (n) { - case 0 ... 5: - return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]); - /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -= 6; - return gdb_get_reg32(mem_buf, env->pvr.regs[n]); - case 18: - return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]); - /* Other SRegs aren't modeled, so report a value of 0 */ - case 19 ... 24: - return gdb_get_reg32(mem_buf, 0); - case 25: - return gdb_get_reg32(mem_buf, env->slr); - case 26: - return gdb_get_reg32(mem_buf, env->shr); - default: - return 0; - } + if (n > cc->gdb_num_core_regs) { + return 0; } + + switch (n) { + case 1 ... 31: + val = env->regs[n]; + break; + case GDB_PC: + val = env->sregs[SR_PC]; + break; + case GDB_MSR: + val = env->sregs[SR_MSR]; + break; + case GDB_EAR: + val = env->sregs[SR_EAR]; + break; + case GDB_ESR: + val = env->sregs[SR_ESR]; + break; + case GDB_FSR: + val = env->sregs[SR_FSR]; + break; + case GDB_BTR: + val = env->sregs[SR_BTR]; + break; + case GDB_PVR0 ... GDB_PVR11: + /* PVR12 is intentionally skipped */ + val = env->pvr.regs[n - GDB_PVR0]; + break; + case GDB_EDR: + val = env->sregs[SR_EDR]; + break; + case GDB_SLR: + val = env->slr; + break; + case GDB_SHR: + val = env->shr; + break; + default: + /* Other SRegs aren't modeled, so report a value of 0 */ + val = 0; + break; + } + return gdb_get_reg32(mem_buf, val); } int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) @@ -82,60 +104,47 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) CPUMBState *env = &cpu->env; uint32_t tmp; - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything. - */ - static const uint8_t sreg_map[6] = { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; - if (n > cc->gdb_num_core_regs) { return 0; } tmp = ldl_p(mem_buf); - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { + switch (n) { + case 1 ... 31: env->regs[n] = tmp; - } else { - n -= 32; - switch (n) { - case 0 ... 5: - env->sregs[sreg_map[n]] = tmp; - break; + break; + case GDB_PC: + env->sregs[SR_PC] = tmp; + break; + case GDB_MSR: + env->sregs[SR_MSR] = tmp; + break; + case GDB_EAR: + env->sregs[SR_EAR] = tmp; + break; + case GDB_ESR: + env->sregs[SR_ESR] = tmp; + break; + case GDB_FSR: + env->sregs[SR_FSR] = tmp; + break; + case GDB_BTR: + env->sregs[SR_BTR] = tmp; + break; + case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -= 6; - env->pvr.regs[n] = tmp; - break; - /* Only EDR is modeled in these indeces, so ignore the rest */ - case 18: - env->sregs[SR_EDR] = tmp; - break; - case 25: - env->slr = tmp; - break; - case 26: - env->shr = tmp; - break; - } + env->pvr.regs[n - GDB_PVR0] = tmp; + break; + case GDB_EDR: + env->sregs[SR_EDR] = tmp; + break; + case GDB_SLR: + env->slr = tmp; + break; + case GDB_SHR: + env->shr = tmp; + break; } return 4; } From patchwork Fri Aug 28 14:18:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248511 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1123966ilg; Fri, 28 Aug 2020 07:21:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzrH5Sxhr556cRFBtkMHPlz0rx8ZQ7ThIKBnuJXW1rwIm1lAR2ZcIZHJDdDyQGevwz+vOmY X-Received: by 2002:a25:cb07:: with SMTP id b7mr2740051ybg.268.1598624487013; Fri, 28 Aug 2020 07:21:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624487; cv=none; d=google.com; s=arc-20160816; b=dp+TMfkvig6HSMlp2QxKvx5SSgXn9AHChZMp3Fwdm5k7tXkEatunRT8faDzDJ89/Eo LTu1unyaw3lQWDtE2w7rc+p0KA1vgvK0e5HoN/9klVTwE5HEAEKG3ON3y+TARm3DdKs+ 3a/wOC70IAMr4tyGMpd6g0HFMjk9zC742bTWXjm49vYH/KiuA71D2Ehc9xm6QWjfC3qW IJkhvqsRNkoCllmoQMiopBqTAFVXxQ/Ib8AlvwHGqFNR6clVC48CsnaI5kIeIxYB/Ej8 N90z1rlGVAT76HnaVXvdbqF8zjavtZibFwW5voz4cKxY/pk15c+FWJ5mdMtge9LEgXB6 qO2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4OXLnCdYVi2j43Kppbpt72ljKyfNbleLew6fTqAwaaE=; b=Y/GLXkiTcO1tX6UtM9jyAwPI6UG6J/8G0WvlWPu1MB7VszxUhE6mphc7L5gyhd/GjH Pozt2ytmYWOe7yGoDLWFvDM3sI0N5mIvbkvdQSb3G8bn2M8xi+2sVxJxjx5buRPr+6L3 VsOzagfDZZCkvy9f7LL0yvzrgnHK/eHhxUT1owVSjxdw9CNTB1MkxO2naR52QSOnM8R+ 6q7gzuPD361esqaC5R46e41d9soxf8yPagPIqW62kYC6Uxd7K6xEnLKnYLzfU1iYIAus EUvlg18K/c84qju+p3Rw9Qwq6sB3wlm5AYm0YhYrzCBgaQfB9RED+7CgWxKGDebcZKQs UuTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hmdPJAKP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin eliminating the sregs array in favor of individual members. Does not correct the width of pc, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 ++- linux-user/microblaze/cpu_loop.c | 12 +++++------ linux-user/microblaze/signal.c | 8 ++++---- target/microblaze/cpu.c | 4 ++-- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 34 ++++++++++++++++---------------- target/microblaze/mmu.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 10 +++++++--- 9 files changed, 42 insertions(+), 37 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a31134b65c..d1f91bb318 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -236,6 +236,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; + uint64_t pc; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ @@ -351,7 +352,7 @@ typedef MicroBlazeCPU ArchCPU; static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { - *pc = env->sregs[SR_PC]; + *pc = env->pc; *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 3e0a7f730b..3c693086f4 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -51,7 +51,7 @@ void cpu_loop(CPUMBState *env) case EXCP_BREAK: /* Return address is 4 bytes after the call. */ env->regs[14] += 4; - env->sregs[SR_PC] = env->regs[14]; + env->pc = env->regs[14]; ret = do_syscall(env, env->regs[12], env->regs[5], @@ -63,7 +63,7 @@ void cpu_loop(CPUMBState *env) 0, 0); if (ret == -TARGET_ERESTARTSYS) { /* Wind back to before the syscall. */ - env->sregs[SR_PC] -= 4; + env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->regs[3] = ret; } @@ -73,13 +73,13 @@ void cpu_loop(CPUMBState *env) * not a userspace-usable register, as the kernel may clobber it * at any point.) */ - env->regs[14] = env->sregs[SR_PC]; + env->regs[14] = env->pc; break; case EXCP_HW_EXCP: - env->regs[17] = env->sregs[SR_PC] + 4; + env->regs[17] = env->pc + 4; if (env->iflags & D_FLAG) { env->sregs[SR_ESR] |= 1 << 12; - env->sregs[SR_PC] -= 4; + env->pc -= 4; /* FIXME: if branch was immed, replay the imm as well. */ } @@ -165,5 +165,5 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->regs[29] = regs->r29; env->regs[30] = regs->r30; env->regs[31] = regs->r31; - env->sregs[SR_PC] = regs->pc; + env->pc = regs->pc; } diff --git a/linux-user/microblaze/signal.c b/linux-user/microblaze/signal.c index 80950c2181..b4eeef4673 100644 --- a/linux-user/microblaze/signal.c +++ b/linux-user/microblaze/signal.c @@ -87,7 +87,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUMBState *env) __put_user(env->regs[29], &sc->regs.r29); __put_user(env->regs[30], &sc->regs.r30); __put_user(env->regs[31], &sc->regs.r31); - __put_user(env->sregs[SR_PC], &sc->regs.pc); + __put_user(env->pc, &sc->regs.pc); } static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env) @@ -124,7 +124,7 @@ static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env) __get_user(env->regs[29], &sc->regs.r29); __get_user(env->regs[30], &sc->regs.r30); __get_user(env->regs[31], &sc->regs.r31); - __get_user(env->sregs[SR_PC], &sc->regs.pc); + __get_user(env->pc, &sc->regs.pc); } static abi_ulong get_sigframe(struct target_sigaction *ka, @@ -188,7 +188,7 @@ void setup_frame(int sig, struct target_sigaction *ka, env->regs[7] = frame_addr += offsetof(typeof(*frame), uc); /* Offset of 4 to handle microblaze rtid r14, 0 */ - env->sregs[SR_PC] = (unsigned long)ka->_sa_handler; + env->pc = (unsigned long)ka->_sa_handler; unlock_user_struct(frame, frame_addr, 1); return; @@ -228,7 +228,7 @@ long do_sigreturn(CPUMBState *env) restore_sigcontext(&frame->uc.tuc_mcontext, env); /* We got here through a sigreturn syscall, our path back is via an rtb insn so setup r14 for that. */ - env->regs[14] = env->sregs[SR_PC]; + env->regs[14] = env->pc; unlock_user_struct(frame, frame_addr, 0); return -TARGET_QEMU_ESIGRETURN; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 51e5c85b10..bde9992535 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -79,7 +79,7 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - cpu->env.sregs[SR_PC] = value; + cpu->env.pc = value; } static bool mb_cpu_has_work(CPUState *cs) @@ -117,7 +117,7 @@ static void mb_cpu_reset(DeviceState *dev) /* Disable stack protector. */ env->shr = ~0; - env->sregs[SR_PC] = cpu->cfg.base_vectors; + env->pc = cpu->cfg.base_vectors; #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e65ec051a5..9ea31f8d2f 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -59,7 +59,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->regs[n]; break; case GDB_PC: - val = env->sregs[SR_PC]; + val = env->pc; break; case GDB_MSR: val = env->sregs[SR_MSR]; @@ -115,7 +115,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->regs[n] = tmp; break; case GDB_PC: - env->sregs[SR_PC] = tmp; + env->pc = tmp; break; case GDB_MSR: env->sregs[SR_MSR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ab2ceeb055..5c392deea4 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -35,7 +35,7 @@ void mb_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; env->res_addr = RES_ADDR_NONE; - env->regs[14] = env->sregs[SR_PC]; + env->regs[14] = env->pc; } bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -126,7 +126,7 @@ void mb_cpu_do_interrupt(CPUState *cs) return; } - env->regs[17] = env->sregs[SR_PC] + 4; + env->regs[17] = env->pc + 4; env->sregs[SR_ESR] &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ @@ -145,15 +145,15 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_EAR], + env->pc, env->sregs[SR_EAR], env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; + env->pc = cpu->cfg.base_vectors + 0x20; break; case EXCP_MMU: - env->regs[17] = env->sregs[SR_PC]; + env->regs[17] = env->pc; env->sregs[SR_ESR] &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ @@ -169,7 +169,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "bimm exception at pc=%" PRIx64 " " "iflags=%x\n", - env->sregs[SR_PC], env->iflags); + env->pc, env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } @@ -188,10 +188,10 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=%" PRIx64 " ear=%" PRIx64 " " "iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); + env->pc, env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; + env->pc = cpu->cfg.base_vectors + 0x20; break; case EXCP_IRQ: @@ -209,14 +209,14 @@ void mb_cpu_do_interrupt(CPUState *cs) { const char *sym; - sym = lookup_symbol(env->sregs[SR_PC]); + sym = lookup_symbol(env->pc); if (sym && (!strcmp("netif_rx", sym) || !strcmp("process_backlog", sym))) { qemu_log( "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags, + env->pc, env->sregs[SR_MSR], t, env->iflags, sym); log_cpu_state(cs, 0); @@ -226,14 +226,14 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); + env->pc, env->sregs[SR_MSR], t, env->iflags); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ | MSR_UM | MSR_IE); env->sregs[SR_MSR] |= t; - env->regs[14] = env->sregs[SR_PC]; - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10; + env->regs[14] = env->pc; + env->pc = cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; @@ -245,17 +245,17 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); + env->pc, env->sregs[SR_MSR], t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; if (cs->exception_index == EXCP_HW_BREAK) { - env->regs[16] = env->sregs[SR_PC]; + env->regs[16] = env->pc; env->sregs[SR_MSR] |= MSR_BIP; - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18; + env->pc = cpu->cfg.base_vectors + 0x18; } else - env->sregs[SR_PC] = env->btarget; + env->pc = env->btarget; break; default: cpu_abort(cs, "unhandled exception type=%d\n", diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 6763421ba2..3f403b567b 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -251,7 +251,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%" PRIx64 "\n", - i, env->sregs[SR_PC]); + i, env->pc); env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f3b17a95b3..2deef32740 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -75,7 +75,7 @@ void helper_debug(CPUMBState *env) { int i; - qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]); + qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a96cb21d96..9f6815cc1f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1805,7 +1805,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", - env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); + env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", @@ -1868,7 +1868,11 @@ void mb_tcg_init(void) offsetof(CPUMBState, regs[i]), regnames[i]); } - for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) { + + cpu_SR[SR_PC] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + + for (i = 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); @@ -1878,5 +1882,5 @@ void mb_tcg_init(void) void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, target_ulong *data) { - env->sregs[SR_PC] = data[0]; + env->pc = data[0]; } From patchwork Fri Aug 28 14:18:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248513 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1124046ilg; Fri, 28 Aug 2020 07:21:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy72FrYuFiXCHnktLkaxH0Ih6g0F62uMafRs4aKjKt/4r2WZNpTylh15lOTyaY4QC3JFy8W X-Received: by 2002:a25:6908:: with SMTP id e8mr3186958ybc.83.1598624491840; Fri, 28 Aug 2020 07:21:31 -0700 (PDT) ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of MSR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 7 ++--- target/microblaze/cpu.c | 4 +-- target/microblaze/gdbstub.c | 4 +-- target/microblaze/helper.c | 49 +++++++++++++++++------------------ target/microblaze/op_helper.c | 22 ++++++++-------- target/microblaze/translate.c | 14 +++++----- 6 files changed, 51 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d1f91bb318..36de61d9f9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -237,6 +237,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint64_t pc; + uint64_t msr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ @@ -355,7 +356,7 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | - (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); + (env->msr & (MSR_UM | MSR_VM | MSR_EE)); } #if !defined(CONFIG_USER_ONLY) @@ -370,11 +371,11 @@ static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) MicroBlazeCPU *cpu = env_archcpu(env); /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { return MMU_NOMMU_IDX; } - if (env->sregs[SR_MSR] & MSR_UM) { + if (env->msr & MSR_UM) { return MMU_USER_IDX; } return MMU_KERNEL_IDX; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bde9992535..0eac068570 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -121,9 +121,9 @@ static void mb_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ - env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; + env->msr = MSR_EE | MSR_IE | MSR_VM | MSR_UM; #else - env->sregs[SR_MSR] = 0; + env->msr = 0; mmu_init(&env->mmu); env->mmu.c_mmu = 3; env->mmu.c_mmu_tlb_access = 3; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 9ea31f8d2f..e4c4936a7a 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -62,7 +62,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pc; break; case GDB_MSR: - val = env->sregs[SR_MSR]; + val = env->msr; break; case GDB_EAR: val = env->sregs[SR_EAR]; @@ -118,7 +118,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pc = tmp; break; case GDB_MSR: - env->sregs[SR_MSR] = tmp; + env->msr = tmp; break; case GDB_EAR: env->sregs[SR_EAR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5c392deea4..a18314540f 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -117,7 +117,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); -/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ +/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; switch (cs->exception_index) { case EXCP_HW_EXCP: @@ -136,11 +136,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |= t; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |= t; /* Exception in progress. */ - env->sregs[SR_MSR] |= MSR_EIP; + env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " @@ -179,11 +179,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |= t; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |= t; /* Exception in progress. */ - env->sregs[SR_MSR] |= MSR_EIP; + env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, "exception at pc=%" PRIx64 " ear=%" PRIx64 " " @@ -195,11 +195,11 @@ void mb_cpu_do_interrupt(CPUState *cs) break; case EXCP_IRQ: - assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))); - assert(env->sregs[SR_MSR] & MSR_IE); + assert(!(env->msr & (MSR_EIP | MSR_BIP))); + assert(env->msr & MSR_IE); assert(!(env->iflags & D_FLAG)); - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; #if 0 #include "disas/disas.h" @@ -216,7 +216,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log( "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->pc, env->sregs[SR_MSR], t, env->iflags, + env->pc, env->msr, t, env->iflags, sym); log_cpu_state(cs, 0); @@ -226,11 +226,10 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->pc, env->sregs[SR_MSR], t, env->iflags); + env->pc, env->msr, t, env->iflags); - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ - | MSR_UM | MSR_IE); - env->sregs[SR_MSR] |= t; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); + env->msr |= t; env->regs[14] = env->pc; env->pc = cpu->cfg.base_vectors + 0x10; @@ -241,18 +240,18 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->pc, env->sregs[SR_MSR], t, env->iflags); + env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |= t; - env->sregs[SR_MSR] |= MSR_BIP; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |= t; + env->msr |= MSR_BIP; if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->pc; - env->sregs[SR_MSR] |= MSR_BIP; + env->msr |= MSR_BIP; env->pc = cpu->cfg.base_vectors + 0x18; } else env->pc = env->btarget; @@ -293,8 +292,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) CPUMBState *env = &cpu->env; if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->sregs[SR_MSR] & MSR_IE) - && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) + && (env->msr & MSR_IE) + && !(env->msr & (MSR_EIP | MSR_BIP)) && !(env->iflags & (D_FLAG | IMM_FLAG))) { cs->exception_index = EXCP_IRQ; mb_cpu_do_interrupt(cs); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 2deef32740..3668382d36 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,14 +78,14 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, - (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (bool)(env->sregs[SR_MSR] & MSR_EIP), - (bool)(env->sregs[SR_MSR] & MSR_IE)); + (env->msr & MSR_UM) ? "user" : "kernel", + (env->msr & MSR_UMS) ? "user" : "kernel", + (bool)(env->msr & MSR_EIP), + (bool)(env->msr & MSR_IE)); for (i = 0; i < 32; i++) { qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); if ((i + 1) % 4 == 0) @@ -135,15 +135,15 @@ static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) MicroBlazeCPU *cpu = env_archcpu(env); if (b == 0) { - env->sregs[SR_MSR] |= MSR_DZ; + env->msr |= MSR_DZ; - if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) { + if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { env->sregs[SR_ESR] = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; } - env->sregs[SR_MSR] &= ~MSR_DZ; + env->msr &= ~MSR_DZ; return 1; } @@ -192,7 +192,7 @@ static void update_fpu_flags(CPUMBState *env, int flags) } if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) - && (env->sregs[SR_MSR] & MSR_EE)) { + && (env->msr & MSR_EE)) { raise_fpu_exception(env); } } @@ -437,7 +437,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr, if (mask == 3) { env->sregs[SR_ESR] |= 1 << 11; } - if (!(env->sregs[SR_MSR] & MSR_EE)) { + if (!(env->msr & MSR_EE)) { return; } helper_raise_exception(env, EXCP_HW_EXCP); @@ -484,7 +484,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, env = &cpu->env; cpu_restore_state(cs, retaddr, true); - if (!(env->sregs[SR_MSR] & MSR_EE)) { + if (!(env->msr & MSR_EE)) { return; } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9f6815cc1f..9f2dcd82cd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,16 +1809,16 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", - env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", env->btaken, env->btarget, - (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (bool)(env->sregs[SR_MSR] & MSR_EIP), - (bool)(env->sregs[SR_MSR] & MSR_IE)); + (env->msr & MSR_UM) ? "user" : "kernel", + (env->msr & MSR_UMS) ? "user" : "kernel", + (bool)(env->msr & MSR_EIP), + (bool)(env->msr & MSR_IE)); for (i = 0; i < 12; i++) { qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); if ((i + 1) % 4 == 0) { @@ -1871,8 +1871,10 @@ void mb_tcg_init(void) cpu_SR[SR_PC] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + cpu_SR[SR_MSR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - for (i = 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Fri Aug 28 14:18:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248515 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1125099ilg; Fri, 28 Aug 2020 07:22:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyFMnAtcZg83JcxE+2QdyjjvulBABRkqX+6x90D0J2+B2Zc7sMkKrQPdq5Jm518nOO7KK1x X-Received: by 2002:a25:4b47:: with SMTP id y68mr2472829yba.89.1598624570573; Fri, 28 Aug 2020 07:22:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624570; cv=none; d=google.com; s=arc-20160816; b=CgS07bXgC+f/SpUaMs97mMlz+5n2CpZM6LJc77mDhaDc2PuKDCdeTEdBSGnLGFVQvU OsWXLNwVsbmff7etbD0pfPXHcclyG8lp8rVzFtbglK/CRyvaPny5XDPQbqELQa1mIQpA umw9qFcjyT7nvwU3zkWHEJC9UxZnDUXjbY+JR42/jmgoORDU8TJZw4G6h4recg7KbOBB PoT6wXmsMmXSg69D3Vtq7VXX+wWtJ1Gl0nGG8/l6QRzihMXT12/g5Vs5ZXrH2DL3ud0u JR+tnlwx477o0uDpT8hcZu+H2++lUuoRRbIrm0f9PL4CiHuZaToiwrdiICbbvYi0icOJ wVxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3AKOFIW3VCEZ6h4ggmUpiB5wdoa5LhPs+jftJ9b2SfM=; b=bBIXqp6hsLqIoyYl43+L7gPsz3rYnfhh5cXq7pbT6TCT+PqensHia09zgXFsc512Nx GC+TghVMqF3rAx9KgJQMs9eVR6hLL9zUs5jewDKZlJUOfvR09xj/f6SAk/WrqsgVEVjR r6PjfHj7vMg53AhSvHZ5CIn5MNBi+88Lt8P2OgrL96fDFFESbtpgHc9+VwHB/E2XNTzd KzLpuX1C9RzinpIl4bn749qXGkUiR5qp8d6auXi5yYj3BFrkt4YdzdvH9cVF1L4K3Z7N jPpfhxTdn8wNS5sSY7dhE/kmQGyKz9PC6bQtNk34FRPdBG9uNg/qX9DlXbSXg0XJO+eT 0PuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sIga6H4G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 6 +++--- target/microblaze/op_helper.c | 8 ++++---- target/microblaze/translate.c | 6 ++++-- 5 files changed, 14 insertions(+), 11 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 36de61d9f9..c9035b410e 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -238,6 +238,7 @@ struct CPUMBState { uint32_t regs[32]; uint64_t pc; uint64_t msr; + uint64_t ear; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e4c4936a7a..e33a613efe 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -65,7 +65,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->msr; break; case GDB_EAR: - val = env->sregs[SR_EAR]; + val = env->ear; break; case GDB_ESR: val = env->sregs[SR_ESR]; @@ -121,7 +121,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->msr = tmp; break; case GDB_EAR: - env->sregs[SR_EAR] = tmp; + env->ear = tmp; break; case GDB_ESR: env->sregs[SR_ESR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a18314540f..afe9634781 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -85,7 +85,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", mmu_idx, address); - env->sregs[SR_EAR] = address; + env->ear = address; switch (lu.err) { case ERR_PROT: env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; @@ -145,7 +145,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", - env->pc, env->sregs[SR_EAR], + env->pc, env->ear, env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); @@ -188,7 +188,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=%" PRIx64 " ear=%" PRIx64 " " "iflags=%x\n", - env->pc, env->sregs[SR_EAR], env->iflags); + env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->pc = cpu->cfg.base_vectors + 0x20; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 3668382d36..5bacd29663 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, @@ -431,7 +431,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr, "unaligned access addr=" TARGET_FMT_lx " mask=%x, wr=%d dr=r%d\n", addr, mask, wr, dr); - env->sregs[SR_EAR] = addr; + env->ear = addr; env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ | (dr & 31) << 5; if (mask == 3) { @@ -450,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); - env->sregs[SR_EAR] = addr; + env->ear = addr; env->sregs[SR_ESR] = ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } @@ -488,7 +488,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, return; } - env->sregs[SR_EAR] = addr; + env->ear = addr; if (access_type == MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { env->sregs[SR_ESR] = ESR_EC_INSN_BUS; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9f2dcd82cd..62747b02f3 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->ear, env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " @@ -1873,8 +1873,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_SR[SR_MSR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + cpu_SR[SR_EAR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); - for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Fri Aug 28 14:18:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248509 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1122774ilg; Fri, 28 Aug 2020 07:19:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwZDfGxbOR0BKn6HytmT5I0pdqbU6R/Dk+IsZUr3xeAmmI6byqX9Aw+RophRVSh8OQ9hdBr X-Received: by 2002:a25:7491:: with SMTP id p139mr2882309ybc.293.1598624398562; Fri, 28 Aug 2020 07:19:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624398; cv=none; d=google.com; s=arc-20160816; b=oHSr25NQPeAOdxFZLXS12Z3Ir6NWmvYEBqhk2/K9uaz1v2aRT9aVN7QeOxoSy6SQAE adtljtUb0pyAiO70N6e3ZSfoVd1gxJHftDf03LqF56mTywB4LGHiRMnDZkc3iyoUHZ5j wbsZlAAtR60SkLQv7kx69oBI2qFnV3pRJZ+x3enNRqbIchB+BElaExWUA8FCuMFPAJGj y37cD5m6Vc7upuhl31YSCY1KnzlnUVNxQIsYfOsV7naQJbz5kkRn9xbp2ESM3Kh0jUvl goIcipp6xwelJDVuJxOnm1sbYsyDRQ/l0j8qsFUC0LuJ9ppKME1ew9ysX7bq/o/RW9s+ 1vWg== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of ESR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 6 +++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 18 +++++++++--------- target/microblaze/op_helper.c | 17 ++++++++--------- target/microblaze/translate.c | 6 ++++-- 6 files changed, 27 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c9035b410e..7d94af43ed 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,6 +239,7 @@ struct CPUMBState { uint64_t pc; uint64_t msr; uint64_t ear; + uint64_t esr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 3c693086f4..c10e3e0261 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -78,14 +78,14 @@ void cpu_loop(CPUMBState *env) case EXCP_HW_EXCP: env->regs[17] = env->pc + 4; if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |= 1 << 12; + env->esr |= 1 << 12; env->pc -= 4; /* FIXME: if branch was immed, replay the imm as well. */ } env->iflags &= ~(IMM_FLAG | D_FLAG); - switch (env->sregs[SR_ESR] & 31) { + switch (env->esr & 31) { case ESR_EC_DIVZERO: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; @@ -107,7 +107,7 @@ void cpu_loop(CPUMBState *env) break; default: fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n", - env->sregs[SR_ESR] & ESR_EC_MASK); + env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); break; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e33a613efe..05e22f233d 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -68,7 +68,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->ear; break; case GDB_ESR: - val = env->sregs[SR_ESR]; + val = env->esr; break; case GDB_FSR: val = env->sregs[SR_FSR]; @@ -124,7 +124,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->ear = tmp; break; case GDB_ESR: - env->sregs[SR_ESR] = tmp; + env->esr = tmp; break; case GDB_FSR: env->sregs[SR_FSR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index afe9634781..ea290be780 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -88,12 +88,12 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, env->ear = address; switch (lu.err) { case ERR_PROT: - env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; - env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + env->esr = access_type == MMU_INST_FETCH ? 17 : 16; + env->esr |= (access_type == MMU_DATA_STORE) << 10; break; case ERR_MISS: - env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 19 : 18; - env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + env->esr = access_type == MMU_INST_FETCH ? 19 : 18; + env->esr |= (access_type == MMU_DATA_STORE) << 10; break; default: abort(); @@ -127,11 +127,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } env->regs[17] = env->pc + 4; - env->sregs[SR_ESR] &= ~(1 << 12); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |= 1 << 12 ; + env->esr |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; } @@ -146,7 +146,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", env->pc, env->ear, - env->sregs[SR_ESR], env->iflags); + env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->pc = cpu->cfg.base_vectors + 0x20; @@ -155,11 +155,11 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] = env->pc; - env->sregs[SR_ESR] &= ~(1 << 12); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); - env->sregs[SR_ESR] |= 1 << 12 ; + env->esr |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; /* Reexecute the branch. */ diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 5bacd29663..f01cf9be64 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, @@ -138,7 +138,7 @@ static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) env->msr |= MSR_DZ; if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { - env->sregs[SR_ESR] = ESR_EC_DIVZERO; + env->esr = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; @@ -166,7 +166,7 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) /* raise FPU exception. */ static void raise_fpu_exception(CPUMBState *env) { - env->sregs[SR_ESR] = ESR_EC_FPU; + env->esr = ESR_EC_FPU; helper_raise_exception(env, EXCP_HW_EXCP); } @@ -432,10 +432,9 @@ void helper_memalign(CPUMBState *env, target_ulong addr, " mask=%x, wr=%d dr=r%d\n", addr, mask, wr, dr); env->ear = addr; - env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ - | (dr & 31) << 5; + env->esr = ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) << 5; if (mask == 3) { - env->sregs[SR_ESR] |= 1 << 11; + env->esr |= 1 << 11; } if (!(env->msr & MSR_EE)) { return; @@ -451,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); env->ear = addr; - env->sregs[SR_ESR] = ESR_EC_STACKPROT; + env->esr = ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } } @@ -491,12 +490,12 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, env->ear = addr; if (access_type == MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] = ESR_EC_INSN_BUS; + env->esr = ESR_EC_INSN_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } else { if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] = ESR_EC_DATA_BUS; + env->esr = ESR_EC_DATA_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 62747b02f3..411c7b6e49 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " @@ -1875,8 +1875,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_SR[SR_EAR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); + cpu_SR[SR_ESR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); - for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Fri Aug 28 14:18:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248519 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1126620ilg; Fri, 28 Aug 2020 07:24:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzmowd9HD7g2jPvF58jlRa1jUFzggu7S1ieVXJAYczUSBaH5qmhQYLjvTNBGS1wnbRdK/os X-Received: by 2002:a25:7141:: with SMTP id m62mr2650750ybc.443.1598624675684; Fri, 28 Aug 2020 07:24:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624675; cv=none; d=google.com; s=arc-20160816; b=rKkYQsIPKFjpSMf1W1AInpQRC/7WRiciDDl890L2miB0s0VdeSAmf3jSXCL+0Vd6id CChoUs3o/OTNnSQeyKjtev3RzMqAiBz5pK8n9A6ogFCCmvwV+HJqz36xfmdJDuh3pD1M MClzT1ZejA5qaN0ugX/XWnW0i+Lk9QitAB2fzGLiP2m5B4aMBMUll9QHQ8ecNyh+n844 RqfsoW8qVAZdzG5xvOxUBdIkXgH1kPjkcpcFz8nTRa1Ny3kd13u6IVt0KH8LFNFVdXgo qSag9QtWNKIJj+TZ6chZkBWYzPEVitVD07uIgLrjq/pdUULYajmKFELOw45Too1VoIaV sRag== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of FSR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 4 ++-- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/op_helper.c | 8 ++++---- target/microblaze/translate.c | 6 ++++-- 5 files changed, 13 insertions(+), 10 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7d94af43ed..bcafef99b0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -240,6 +240,7 @@ struct CPUMBState { uint64_t msr; uint64_t ear; uint64_t esr; + uint64_t fsr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index c10e3e0261..da5e98b784 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env) case ESR_EC_FPU: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; - if (env->sregs[SR_FSR] & FSR_IO) { + if (env->fsr & FSR_IO) { info.si_code = TARGET_FPE_FLTINV; } - if (env->sregs[SR_FSR] & FSR_DZ) { + if (env->fsr & FSR_DZ) { info.si_code = TARGET_FPE_FLTDIV; } info._sifields._sigfault._addr = 0; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 05e22f233d..2634ce49fc 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -71,7 +71,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->esr; break; case GDB_FSR: - val = env->sregs[SR_FSR]; + val = env->fsr; break; case GDB_BTR: val = env->sregs[SR_BTR]; @@ -127,7 +127,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->esr = tmp; break; case GDB_FSR: - env->sregs[SR_FSR] = tmp; + env->fsr = tmp; break; case GDB_BTR: env->sregs[SR_BTR] = tmp; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f01cf9be64..ae57d45536 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -175,19 +175,19 @@ static void update_fpu_flags(CPUMBState *env, int flags) int raise = 0; if (flags & float_flag_invalid) { - env->sregs[SR_FSR] |= FSR_IO; + env->fsr |= FSR_IO; raise = 1; } if (flags & float_flag_divbyzero) { - env->sregs[SR_FSR] |= FSR_DZ; + env->fsr |= FSR_DZ; raise = 1; } if (flags & float_flag_overflow) { - env->sregs[SR_FSR] |= FSR_OF; + env->fsr |= FSR_OF; raise = 1; } if (flags & float_flag_underflow) { - env->sregs[SR_FSR] |= FSR_UF; + env->fsr |= FSR_UF; raise = 1; } if (raise diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 411c7b6e49..c58c49ea8f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1810,7 +1810,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags, env->sregs[SR_FSR], + env->debug, env->imm, env->iflags, env->fsr, env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", @@ -1877,8 +1877,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_SR[SR_ESR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); + cpu_SR[SR_FSR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); - for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Fri Aug 28 14:18:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248521 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1127196ilg; Fri, 28 Aug 2020 07:25:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxK9HoB8uLS8HV+tAxmqlYPgWwPt/LbSdENJPFIJsdfIAvSaDN5wwe/rbeU7VqcszRhftQS X-Received: by 2002:a25:7611:: with SMTP id r17mr2645624ybc.183.1598624719845; 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[209.51.188.17]) by mx.google.com with ESMTPS id 135si1056111ybd.363.2020.08.28.07.25.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:25:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u2meYQFb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfJf-0002XI-89 for patch@linaro.org; Fri, 28 Aug 2020 10:25:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEK-0008CW-8h for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:48 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:38247) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEI-00054M-FX for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:47 -0400 Received: by mail-pf1-x441.google.com with SMTP id d22so737862pfn.5 for ; Fri, 28 Aug 2020 07:19:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uVRyTVQxo8OjLoh4LZ/et66lNRgcRHaSjjoCMlpw+SQ=; b=u2meYQFbUWxfteHLzcUK2AZ+zWuwExI34OSwejQpg43VgXpZxmEkwh6lXqUd5IcncH 186aItOpJximDBd/aavgaWqQJitu3q9b3WKJZkfQb+gpMdf+BCDu6VSdhrPIHvsV0Un9 ekYBxK55Mr/gLV+/Zfpi+yJ2NVbvtS6uBUb7/nGkoQodj3BwCRT1iLflKQE96Mzku5AL IB33QVw/LE/3i+TR1Pz3wDElws4i7QwGikuRXD1fOc1yQq17A7c1kWTqRQa4S5H1Nrql 223rF8QIe6WkdyN8D5YNP48Tu+61zPrOrYB0PW/3W4FI4j/VjVtx+QnWTDi3Ds+unJu1 oeXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uVRyTVQxo8OjLoh4LZ/et66lNRgcRHaSjjoCMlpw+SQ=; b=toGHx/B9v45rLgY8jD5n7U9IT6jTIp08u2mcgYoRgAub88GXhz3cuvmWB/HnGRtBJf sHkR/gF+sxpHH+q8h2N3z4sBTlfh31H4QT2iIB735E0LNkZGspKkCwXFis8tgU9R9fgg vGbWyBRfztar+Hnfigfxnumvguml3U/wOzpvlI02gD9SvkkpJmvwNgZDbzW0+AcM4VOF c9dRrLXYznTlQ2tEYNnXla1aQOsZ6KTjSc7yquqQAjEKQ9qWFAGMQ182SeQciclfI0XN 7NsN0IvmFQHqui3ihyHrR27HObbdzeQ6Refr2VyZbPrVCEzCO2kaAdUh93lrSeOiExZK QpdA== X-Gm-Message-State: AOAM533GohZUGC/9CU/nbzn0rM29gNsK5ppiAsEeF3MUrsa0mLjP8s+B CGjUuy5Q2MUuGsDNrpkcwLrLUPoRNXB0WQ== X-Received: by 2002:a63:8543:: with SMTP id u64mr1425085pgd.350.1598624384601; Fri, 28 Aug 2020 07:19:44 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.19.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:19:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 10/76] target/microblaze: Split out BTR from env->sregs Date: Fri, 28 Aug 2020 07:18:23 -0700 Message-Id: <20200828141929.77854-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of BTR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 4 ++-- target/microblaze/translate.c | 6 ++++-- 4 files changed, 9 insertions(+), 6 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index bcafef99b0..deddb47abb 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,6 +241,7 @@ struct CPUMBState { uint64_t ear; uint64_t esr; uint64_t fsr; + uint64_t btr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 2634ce49fc..cde8c169bf 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -74,7 +74,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->fsr; break; case GDB_BTR: - val = env->sregs[SR_BTR]; + val = env->btr; break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ @@ -130,7 +130,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->fsr = tmp; break; case GDB_BTR: - env->sregs[SR_BTR] = tmp; + env->btr = tmp; break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ea290be780..b240dc76f6 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -132,7 +132,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { env->esr |= 1 << 12 ; - env->sregs[SR_BTR] = env->btarget; + env->btr = env->btarget; } /* Disable the MMU. */ @@ -160,7 +160,7 @@ void mb_cpu_do_interrupt(CPUState *cs) if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); env->esr |= 1 << 12 ; - env->sregs[SR_BTR] = env->btarget; + env->btr = env->btarget; /* Reexecute the branch. */ env->regs[17] -= 4; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c58c49ea8f..469e1f103a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1811,7 +1811,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, - env->sregs[SR_BTR]); + env->btr); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", env->btaken, env->btarget, @@ -1879,8 +1879,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); cpu_SR[SR_FSR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); + cpu_SR[SR_BTR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Fri Aug 28 14:18:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248524 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1128490ilg; Fri, 28 Aug 2020 07:27:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxEPpHcD4um6CRM9GhYOwjtZoOprsOAuotm4ivEBs+TwXb4nwXiRafg6DymfwtUgy/Doogw X-Received: by 2002:a25:2314:: with SMTP id j20mr2718284ybj.508.1598624823292; Fri, 28 Aug 2020 07:27:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624823; cv=none; d=google.com; s=arc-20160816; b=QURNeljylb1nOlDCF0de7iDtFzowXaiA7V3auVjK40YevFeKd6tmt2y6LzckgiQRur yIsM44meEck/x/NkFIXy39DFsh/gPRNAJrFJqpzMdvhZIrEVI1/bB+DKulIuODyW18B9 fwRQFCaNkkczYiHvn61TQ4Oui25jqkLrxosICIXzVev89aaWiQVzgOLAh1cJy0w1QFwS KLVx1yFnpqp3rGFW+2YpDQYefT+Nd0T0cO0V4jT5/V97L1pfv6IK8gj53WEVW53WoHln 3NaHNUsQ5Jy0Zflvr2mqpZIqnskyq92sBOrGFcvL6tg6CIzBtlTJzknB3PJUiUCAVZEd RlOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kxuKPEsnkZdfVwCBdweXYlcCCLoCz5+CGJqBlv/VqWk=; b=KsI7jjY2DSblBjRViCirscdfvNpkyagIB9GNc9p93e072iiwkW/m8aYaF7Myhbtt4D 3RGZcCQEVeDzD4UHzY5jUD/bjUgu+3j0RVhp+/1aJqCe2wxwTfjIpsz2tr+ewfLy1a3A TLYxufj4lj2f8FPO/+TCTx0hxMLgCfiTfPz1bVY8nc9OWhxlwQKXlqJcdLXoReEfEmd9 h8vOHuP5TSGVqqplXKkTP6qXOxeCuPJHC18+1G442FMBzY3/WWrtzwAimdtH4Cp5l20N 3XKMayCwMdDywT2ykuo6aXLGv0HtvWerkqO1CaxS6CmNlxxugCfHMFW8TWwU03RQxsjR 5b5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J5WX9nTT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Finish eliminating the sregs array in favor of individual members. Does not correct the width of EDR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/elfload.c | 9 ++++++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/translate.c | 16 +++------------- 4 files changed, 12 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index deddb47abb..610ddfb719 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint64_t esr; uint64_t fsr; uint64_t btr; - uint64_t sregs[14]; + uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index fe9dfe795d..bbfb665321 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1032,9 +1032,12 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env (*regs)[pos++] = tswapreg(env->regs[i]); } - for (i = 0; i < 6; i++) { - (*regs)[pos++] = tswapreg(env->sregs[i]); - } + (*regs)[pos++] = tswapreg(env->pc); + (*regs)[pos++] = tswapreg(env->msr); + (*regs)[pos++] = 0; + (*regs)[pos++] = tswapreg(env->ear); + (*regs)[pos++] = 0; + (*regs)[pos++] = tswapreg(env->esr); } #endif /* TARGET_MICROBLAZE */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index cde8c169bf..9cba9d2215 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -81,7 +81,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pvr.regs[n - GDB_PVR0]; break; case GDB_EDR: - val = env->sregs[SR_EDR]; + val = env->edr; break; case GDB_SLR: val = env->slr; @@ -137,7 +137,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pvr.regs[n - GDB_PVR0] = tmp; break; case GDB_EDR: - env->sregs[SR_EDR] = tmp; + env->edr = tmp; break; case GDB_SLR: env->slr = tmp; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 469e1f103a..7d307e6b48 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -103,12 +103,6 @@ static const char *regnames[] = "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", }; -static const char *special_regnames[] = -{ - "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr", - "sr8", "sr9", "sr10", "rbtr", "sr12", "redr" -}; - static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1828,7 +1822,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) /* Registers that aren't modeled are reported as 0 */ qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " - "rtlblo=0 rtlbhi=0\n", env->sregs[SR_EDR]); + "rtlblo=0 rtlbhi=0\n", env->edr); qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); @@ -1881,12 +1875,8 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_SR[SR_BTR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - - for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) { - cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUMBState, sregs[i]), - special_regnames[i]); - } + cpu_SR[SR_EDR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Fri Aug 28 14:18:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248527 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1129250ilg; Fri, 28 Aug 2020 07:27:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyV09J1T8twIWWssvJLz1APxKKOlXePN5H0RCkaXDI567fMFR/PD+Of3Zw7Mj2GSb1Cg9kK X-Received: by 2002:a25:cccf:: with SMTP id l198mr3018569ybf.100.1598624878527; Fri, 28 Aug 2020 07:27:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624878; cv=none; d=google.com; s=arc-20160816; b=SCrki0ZPoaOErIvpLGJzaIQtAPUQ5oGLui5LXE0YrHdGYBzOsJT/JZo8xH5tUQ+4PL jME0sYVUMdpfrDYBhlFD3Z4U/+Q5XRibiN3xhqxWYzuezqynJbC3DqLgVIYnhZgW7iJE kRw5XDUQuK8xJkB8QdvEOqqs60oBbiTucjFzAQ3pmO0fI+mWJtSwX1D3n+Zu+fMs+dXL QHCH/vMIisqCbtjpVKJt9vx9fvDAnPBR9bqDLNUnnw/VLhcCZJDRoxHNwIuLXyqbWUwL 56DNb3VM1qNjF/2VfgDK9gpFjqFe960f88T3irdUxDtnSp1wu/LeFJ2/th5oGLagxFlT XbLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mWZxIEkP4nZuOtJzfgZGg0mAj4EW15ubIN08DOn/YHw=; b=1BnBLeZSCiNnpy6IbtzfEveNfEtsJaHC0ZsVhXNNo22aYuugTOmpndBWKfNpAj5uuN SX5OzmOrOkelxuU+NpOrR7AniN9StyTAq0zcDPQnhtwBOYJwrriRK9uwpx05yeeKB77B YulB85luaRL3Q8luyA3r3PRIaiYPPHlZKPU2NK+8eik8kHlIqKdxdaIcwrkj/6BfJVjm JEtecYaRteLWM5JnhlvQVqkXwp7oGh/HTzoPnCykbbXnrIC39Iva0A4jSgy/MJTzoQJw XN+Uhg3Fv0zJYp24HMLtEXm/oLtyJZ/4LckLUFcCAwxyYLRGhAbfdDF1LdfZkA8B6e9y vy1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j7EtJ6H1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Similar to splitting the sregs array, this will allow further fixes and cleanups. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 106 +++++++++++++++++++++------------- 1 file changed, 65 insertions(+), 41 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7d307e6b48..19d7b8abfd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -55,7 +55,13 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; -static TCGv_i64 cpu_SR[14]; +static TCGv_i64 cpu_pc; +static TCGv_i64 cpu_msr; +static TCGv_i64 cpu_ear; +static TCGv_i64 cpu_esr; +static TCGv_i64 cpu_fsr; +static TCGv_i64 cpu_btr; +static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i64 env_btarget; @@ -117,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) TCGv_i32 tmp = tcg_const_i32(index); t_sync_flags(dc); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; @@ -136,17 +142,17 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); } else { - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(d, cpu_msr); tcg_gen_shri_i32(d, d, 31); } @@ -159,8 +165,8 @@ static void write_carry(DisasContext *dc, TCGv_i32 v) TCGv_i64 t0 = tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t0, v); /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); - tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); + tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1); + tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1); tcg_temp_free_i64(t0); } @@ -180,7 +186,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -196,7 +202,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -431,7 +437,7 @@ static void dec_xor(DisasContext *dc) static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(d, cpu_msr); } static inline void msr_write(DisasContext *dc, TCGv_i32 v) @@ -443,8 +449,8 @@ static inline void msr_write(DisasContext *dc, TCGv_i32 v) /* PVR bit is not writable. */ tcg_gen_extu_i32_i64(t, v); tcg_gen_andi_i64(t, t, ~MSR_PVR); - tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); - tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); + tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR); + tcg_gen_or_i64(cpu_msr, cpu_msr, t); tcg_temp_free_i64(t); } @@ -503,7 +509,7 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_pc, dc->pc + 4); dc->is_jmp = DISAS_UPDATE; return; } @@ -535,15 +541,25 @@ static void dec_msr(DisasContext *dc) if (to) { LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); switch (sr) { - case 0: + case SR_PC: break; - case 1: + case SR_MSR: msr_write(dc, cpu_R[dc->ra]); break; case SR_EAR: + tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); + break; case SR_ESR: + tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]); + break; case SR_FSR: - tcg_gen_extu_i32_i64(cpu_SR[sr], cpu_R[dc->ra]); + tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); + break; + case SR_BTR: + tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); + break; + case SR_EDR: + tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], @@ -561,22 +577,30 @@ static void dec_msr(DisasContext *dc) LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); switch (sr) { - case 0: + case SR_PC: tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); break; - case 1: + case SR_MSR: msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); - break; + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); + } else { + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); } + break; case SR_ESR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr); + break; case SR_FSR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); + break; case SR_BTR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); + break; case SR_EDR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -749,7 +773,7 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t0, cpu_msr); tcg_gen_andi_i32(t0, t0, MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { @@ -995,7 +1019,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); tcg_temp_free_i32(t0); @@ -1115,7 +1139,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1169,7 +1193,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false) TCGv_i64 tmp_zero = tcg_const_i64(0); tcg_gen_extu_i32_i64(tmp_btaken, env_btaken); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_SR[SR_PC], + tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tmp_btaken, tmp_zero, pc_true, pc_false); @@ -1253,7 +1277,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_pc, dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1309,7 +1333,7 @@ static inline void do_rti(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_ori_i32(t1, t1, MSR_IE); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1327,7 +1351,7 @@ static inline void do_rtb(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_andi_i32(t1, t1, ~MSR_BIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1346,7 +1370,7 @@ static inline void do_rte(DisasContext *dc) t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_ori_i32(t1, t1, MSR_EE); tcg_gen_andi_i32(t1, t1, ~MSR_EIP); tcg_gen_shri_i32(t0, t1, 1); @@ -1401,7 +1425,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU); + tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; @@ -1652,7 +1676,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_debug(); } #endif @@ -1730,7 +1754,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); sync_jmpstate(dc); } else npc = dc->jmp_pc; @@ -1740,7 +1764,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); } t_sync_flags(dc); @@ -1748,7 +1772,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1863,19 +1887,19 @@ void mb_tcg_init(void) regnames[i]); } - cpu_SR[SR_PC] = + cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); - cpu_SR[SR_MSR] = + cpu_msr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_SR[SR_EAR] = + cpu_ear = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); - cpu_SR[SR_ESR] = + cpu_esr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_SR[SR_FSR] = + cpu_fsr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); - cpu_SR[SR_BTR] = + cpu_btr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - cpu_SR[SR_EDR] = + cpu_edr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } From patchwork Fri Aug 28 14:18:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248516 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1125241ilg; Fri, 28 Aug 2020 07:22:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyj7TnFapbwv/1/UVZunztwij+45YNU231rr0urbecLdz5N2Gbl2Yr32GUEwBa1QV4mOCFS X-Received: by 2002:a25:4c84:: with SMTP id z126mr2462528yba.369.1598624577235; Fri, 28 Aug 2020 07:22:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624577; cv=none; d=google.com; s=arc-20160816; b=G+KAxzp5KTiwraNMtwsP/bW+5xsskLt8px68vMF80VvWVfKd32DgeC5/l/jSDrwILr 5mvocUDt/G0IylZ5+mNP+vOJ3e57WDP4Dh46oqgGKSEo7owCn03aWFcTh73jD7132wPG pcMLPW9KT7lADf8Dvl5rqVM6888QMZ0+Xs7y7bS1mi/EtYfrnkGh/srbCxqDebWD+e8k RfLDDij/goM3E3Q1g9haANSkWj1hdEFNQLoT/T2UOMdBd15/x7IK5ssjgcBoaEHjdEnM giqxtwOmci22ciHAxLZ0w9VTMSxqBODEAV2C31PvL2GwB1BxKjgmGgEOE8VF6bcQJ+Hl nSGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rsRB0RZxqoK3N2gzIw0qX54Gonb1t6EonRXZar2I/Yw=; b=z8USdKqg7CcMuBgZ0Daabmx+x5jnY4A2+Ydsq4PMG/bMWimrEI0Ql+i0o/yFuvSazC AUl5KIqrxwW2E/hnn91c7Wf8Hi8bXPqjGqz7ZjdKO/PQR+KAjg3dwRsubiosOUlbt6ZQ ddhF6TGWMbTvxoh4ToY3tVMf77q7k2OeKd3lSqsuu0jNlbc74RIJxf2BF9iQ4PlA27Qy 5S/NtNdt0TSw3d9jMbwNCgWgSOmSmYHrOOsRAaQ0y1Jfof6Jd85QFakn7vtgM20CoVAS tlJwXiSE1sVeRj2X6WHCahbnxVhsJq6aWY0C3QTNht4gYHA+/gPmg4AUUrfHlNFj7Iia k7lg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PhYOaq9i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The program counter is only 32-bits wide. Do not use a 64-bit type to represent it. Since they are so closely related, fix btarget at the same time. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/helper.c | 16 +++---- target/microblaze/mmu.c | 4 +- target/microblaze/op_helper.c | 4 +- target/microblaze/translate.c | 78 ++++++++++++++--------------------- 5 files changed, 43 insertions(+), 63 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 610ddfb719..f4c3c09b09 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -231,12 +231,12 @@ typedef struct CPUMBState CPUMBState; struct CPUMBState { uint32_t debug; uint32_t btaken; - uint64_t btarget; + uint32_t btarget; uint32_t bimm; uint32_t imm; uint32_t regs[32]; - uint64_t pc; + uint32_t pc; uint64_t msr; uint64_t ear; uint64_t esr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b240dc76f6..b95617a81a 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -143,7 +143,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, - "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " + "hw exception at pc=%x ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", env->pc, env->ear, env->esr, env->iflags); @@ -167,8 +167,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* was the branch immprefixed?. */ if (env->bimm) { qemu_log_mask(CPU_LOG_INT, - "bimm exception at pc=%" PRIx64 " " - "iflags=%x\n", + "bimm exception at pc=%x iflags=%x\n", env->pc, env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); @@ -186,8 +185,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, - "exception at pc=%" PRIx64 " ear=%" PRIx64 " " - "iflags=%x\n", + "exception at pc=%x ear=%" PRIx64 " iflags=%x\n", env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); @@ -224,8 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " - "iflags=%x\n", + "interrupt at pc=%x msr=%" PRIx64 " %x iflags=%x\n", env->pc, env->msr, t, env->iflags); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); @@ -242,9 +239,8 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & D_FLAG)); t = (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, - "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " - "iflags=%x\n", - env->pc, env->msr, t, env->iflags); + "break at pc=%x msr=%" PRIx64 " %x iflags=%x\n", + env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->msr |= t; diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 3f403b567b..6e583d78d9 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -250,8 +250,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) if (rn == MMU_R_TLBHI) { if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) qemu_log_mask(LOG_GUEST_ERROR, - "invalidating index %x at pc=%" PRIx64 "\n", - i, env->pc); + "invalidating index %x at pc=%x\n", + i, env->pc); env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index ae57d45536..fdf706a723 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -75,12 +75,12 @@ void helper_debug(CPUMBState *env) { int i; - qemu_log("PC=%" PRIx64 "\n", env->pc); + qemu_log("PC=%08x\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); - qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", + qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 19d7b8abfd..72783c1d8a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -55,7 +55,7 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; -static TCGv_i64 cpu_pc; +static TCGv_i32 cpu_pc; static TCGv_i64 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i64 cpu_esr; @@ -64,7 +64,7 @@ static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; -static TCGv_i64 env_btarget; +static TCGv_i32 cpu_btarget; static TCGv_i32 env_iflags; static TCGv env_res_addr; static TCGv_i32 env_res_val; @@ -123,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) TCGv_i32 tmp = tcg_const_i32(index); t_sync_flags(dc); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; @@ -142,10 +142,10 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_i64(cpu_pc, dest); + tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); } else { - tcg_gen_movi_i64(cpu_pc, dest); + tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } @@ -509,7 +509,7 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i64(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); dc->is_jmp = DISAS_UPDATE; return; } @@ -850,7 +850,7 @@ static inline void sync_jmpstate(DisasContext *dc) tcg_gen_movi_i32(env_btaken, 1); } dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i64(env_btarget, dc->jmp_pc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } } @@ -1019,7 +1019,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); tcg_temp_free_i32(t0); @@ -1139,7 +1139,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1187,18 +1187,15 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, } } -static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false) +static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) { - TCGv_i64 tmp_btaken = tcg_temp_new_i64(); - TCGv_i64 tmp_zero = tcg_const_i64(0); + TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_extu_i32_i64(tmp_btaken, env_btaken); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, - tmp_btaken, tmp_zero, + tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, + env_btaken, zero, pc_true, pc_false); - tcg_temp_free_i64(tmp_btaken); - tcg_temp_free_i64(tmp_zero); + tcg_temp_free_i32(zero); } static void dec_setup_dslot(DisasContext *dc) @@ -1229,14 +1226,12 @@ static void dec_bcc(DisasContext *dc) if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - tcg_gen_movi_i64(env_btarget, dc->pc + offset); + tcg_gen_movi_i32(cpu_btarget, dc->pc + offset); dc->jmp = JMP_DIRECT_CC; dc->jmp_pc = dc->pc + offset; } else { dc->jmp = JMP_INDIRECT; - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); } @@ -1277,7 +1272,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i64(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1303,7 +1298,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_INDIRECT; if (abs) { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) t_gen_raise_exception(dc, EXCP_BREAK); @@ -1321,9 +1316,7 @@ static void dec_br(DisasContext *dc) dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); } else { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } } } @@ -1387,7 +1380,6 @@ static inline void do_rte(DisasContext *dc) static void dec_rts(DisasContext *dc) { unsigned int b_bit, i_bit, e_bit; - TCGv_i64 tmp64; i_bit = dc->ir & (1 << 21); b_bit = dc->ir & (1 << 22); @@ -1413,13 +1405,7 @@ static void dec_rts(DisasContext *dc) dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(env_btaken, 1); - - tmp64 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_extu_i32_i64(tmp64, cpu_R[dc->ra]); - tcg_gen_add_i64(env_btarget, env_btarget, tmp64); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); - tcg_temp_free_i64(tmp64); + tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } static int dec_check_fpuv2(DisasContext *dc) @@ -1676,7 +1662,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_debug(); } #endif @@ -1718,10 +1704,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) dc->tb_flags &= ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp == JMP_INDIRECT) { - TCGv_i64 tmp_pc = tcg_const_i64(dc->pc); - eval_cond_jmp(dc, env_btarget, tmp_pc); - tcg_temp_free_i64(tmp_pc); - + TCGv_i32 tmp_pc = tcg_const_i32(dc->pc); + eval_cond_jmp(dc, cpu_btarget, tmp_pc); + tcg_temp_free_i32(tmp_pc); dc->is_jmp = DISAS_JUMP; } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); @@ -1754,7 +1739,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); sync_jmpstate(dc); } else npc = dc->jmp_pc; @@ -1764,7 +1749,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); } t_sync_flags(dc); @@ -1772,7 +1757,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1822,7 +1807,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) return; } - qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", + qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " @@ -1830,8 +1815,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, env->btr); - qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " - "eip=%d ie=%d\n", + qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", @@ -1869,7 +1853,7 @@ void mb_tcg_init(void) env_imm = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); - env_btarget = tcg_global_mem_new_i64(cpu_env, + cpu_btarget = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btarget), "btarget"); env_btaken = tcg_global_mem_new_i32(cpu_env, @@ -1888,7 +1872,7 @@ void mb_tcg_init(void) } cpu_pc = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_ear = From patchwork Fri Aug 28 14:18:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248520 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1126718ilg; Fri, 28 Aug 2020 07:24:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyXm+WL3PeUszSAXshzCFS/COyvAR8sHXGH4vEJ/JDCWYfcB6didOvGvxXxU86Miqo7WjHK X-Received: by 2002:a25:afd0:: with SMTP id d16mr2910705ybj.177.1598624683546; Fri, 28 Aug 2020 07:24:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624683; cv=none; d=google.com; s=arc-20160816; b=JeoISbm3Pshruk7hWVjbzJK1kj91ur3UZEuLKv3eW+o4SN/ZEhKrqUEDu1RbFw7CoV PDA8xYq0u7DdgmFlPBaOBWFzRdUY3htfBy9FuEG0BJty0H5mEWOuGZPSGcBB/CWZaNyy 10bac+nwT+DsQKVqbHBiYYTmwKHji/9+ZhZJC8Zi/rljlUmP1Qs4s3QS/ceZxhhrG/dX efeoimSTRb55nZnjtmYwJxBpKNjsc/a0C7tk7wgabvlOMJSYNVFWzP4TJBfB4qiE39Li lrlyvT5yIfSvK9D6HhrGAjoy9OoDyDH7JSEqla9azJrgOMZ5OJFSrewbENqwhOgfG47T /r1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vLvNC5AlBnMMj5Xypoodm2v5NfVH1pHkbk/5dT3fkns=; b=oFz7vsnwSCjMW420tzaTUHTYyHKKv1Ecaol0tVdMqsgoZn4tz7SyLscyT41Fr7mPHh gqFVfRUPv9LhGlayQiAzxM3yTTskUW/sypsHNu658Icr0LQDvVfgJmLGbyW5ohipBYuZ HkAkvolhJK8W4+40E3hejcFOeJCu15iv5G8fhRbdjcnPhQ7QY+j7yvV/lIy+n1E7HdQk iypIHYrLLUfUswkRi4ce5HI2vCdxdZgu4tNc4LFpLVMwoC7ThiPyQ4OYJmrfTIqlIKQQ xFcsjhtbfDJPakkS5BSllVta25g1e7QfIZdTt+ZxTPij3nZVeIfNi42YbtSJKmui7Ayi Wsfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IBi7kfQq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The machine status register is only 32-bits wide. Do not use a 64-bit type to represent it. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 38 ++++++++++++----------------------- 4 files changed, 17 insertions(+), 29 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f4c3c09b09..019e5dfa26 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -237,7 +237,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint32_t pc; - uint64_t msr; + uint32_t msr; uint64_t ear; uint64_t esr; uint64_t fsr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b95617a81a..af79091fd2 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%x msr=%" PRIx64 " %x iflags=%x\n", + "interrupt at pc=%x msr=%x %x iflags=%x\n", env->pc, env->msr, t, env->iflags); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); @@ -239,7 +239,7 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & D_FLAG)); t = (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, - "break at pc=%x msr=%" PRIx64 " %x iflags=%x\n", + "break at pc=%x msr=%x %x iflags=%x\n", env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index fdf706a723..a7f6cb71f1 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 72783c1d8a..0e71e7ed01 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,7 +56,7 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; -static TCGv_i64 cpu_msr; +static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i64 cpu_esr; static TCGv_i64 cpu_fsr; @@ -152,8 +152,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_msr); - tcg_gen_shri_i32(d, d, 31); + tcg_gen_shri_i32(d, cpu_msr, 31); } /* @@ -162,12 +161,9 @@ static void read_carry(DisasContext *dc, TCGv_i32 d) */ static void write_carry(DisasContext *dc, TCGv_i32 v) { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(t0, v); /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1); - tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1); - tcg_temp_free_i64(t0); + tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1); + tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1); } static void write_carryi(DisasContext *dc, bool carry) @@ -437,21 +433,14 @@ static void dec_xor(DisasContext *dc) static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_msr); + tcg_gen_mov_i32(d, cpu_msr); } static inline void msr_write(DisasContext *dc, TCGv_i32 v) { - TCGv_i64 t; - - t = tcg_temp_new_i64(); dc->cpustate_changed = 1; - /* PVR bit is not writable. */ - tcg_gen_extu_i32_i64(t, v); - tcg_gen_andi_i64(t, t, ~MSR_PVR); - tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR); - tcg_gen_or_i64(cpu_msr, cpu_msr, t); - tcg_temp_free_i64(t); + /* PVR bit is not writable, and is never set. */ + tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR); } static void dec_msr(DisasContext *dc) @@ -773,8 +762,7 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_extrl_i64_i32(t0, cpu_msr); - tcg_gen_andi_i32(t0, t0, MSR_CC); + tcg_gen_andi_i32(t0, cpu_msr, MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); @@ -1326,7 +1314,7 @@ static inline void do_rti(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_ori_i32(t1, t1, MSR_IE); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1344,7 +1332,7 @@ static inline void do_rtb(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_andi_i32(t1, t1, ~MSR_BIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1363,7 +1351,7 @@ static inline void do_rte(DisasContext *dc) t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_ori_i32(t1, t1, MSR_EE); tcg_gen_andi_i32(t1, t1, ~MSR_EIP); tcg_gen_shri_i32(t0, t1, 1); @@ -1809,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_fprintf(f, "rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, @@ -1874,7 +1862,7 @@ void mb_tcg_init(void) cpu_pc = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_ear = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = From patchwork Fri Aug 28 14:18:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248523 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1128199ilg; Fri, 28 Aug 2020 07:26:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwWzMfd4KtShcrp1QrlcAGylfEUcJg8Jy92WTTfuakYs3eB5WypADkU9T4+ge8voxgIrllU X-Received: by 2002:a25:410f:: with SMTP id o15mr2852917yba.328.1598624801325; Fri, 28 Aug 2020 07:26:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624801; cv=none; d=google.com; s=arc-20160816; b=z2cq9HHWGTVJbWCcxLarIwNrkXoVbpOwpjmFeuPXiYumbllP1uO2KZBPGuA5QF98cg r5xTguWejpqVpKqgnkELsknk5Z6BCu7IlqifPfyPWSUgFh2+U4HqaW+VMy4fYFspN1Zn 49gtbwZ4KLGYGUN9AOJXQWIiJT5Yl6TB0LEVQcV1g98rK1HJ7BMpKintg4GEWynbyXzp k3Sz72jRcGtwPmvHe3+nurzaS/yZqP3Pz6aervaTQrrkEddtjjWP5YyVbGyGm0a/ed9f wu3OSZtL1lKz1SqfzMkKxm6AWOSQP3eP+KYhikoYLmtHI7OYHkA9p+9J1Wf6z407B2Xy OC/g== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 16 ++++++++-------- 5 files changed, 12 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 019e5dfa26..aaac0c9a6c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,7 +239,7 @@ struct CPUMBState { uint32_t pc; uint32_t msr; uint64_t ear; - uint64_t esr; + uint32_t esr; uint64_t fsr; uint64_t btr; uint64_t edr; diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index da5e98b784..3de99ea311 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -106,7 +106,7 @@ void cpu_loop(CPUMBState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; default: - fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n", + fprintf(stderr, "Unhandled hw-exception: 0x%x\n", env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index af79091fd2..b2373f6a23 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -144,7 +144,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%x ear=%" PRIx64 " " - "esr=%" PRIx64 " iflags=%x\n", + "esr=%x iflags=%x\n", env->pc, env->ear, env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index a7f6cb71f1..dc2bec0c99 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_log("rmsr=%x resr=%x rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0e71e7ed01..f63aae6de9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,7 +58,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; -static TCGv_i64 cpu_esr; +static TCGv_i32 cpu_esr; static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; @@ -182,7 +182,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -198,7 +198,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -539,7 +539,7 @@ static void dec_msr(DisasContext *dc) tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); break; case SR_ESR: - tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]); + tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); @@ -580,7 +580,7 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr); + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); @@ -1399,7 +1399,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU); + tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; @@ -1797,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, @@ -1866,7 +1866,7 @@ void mb_tcg_init(void) cpu_ear = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); cpu_fsr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr = From patchwork Fri Aug 28 14:18:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248531 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1131067ilg; Fri, 28 Aug 2020 07:30:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRS/Ax4h84UvHsxzycJE+qQvcm+MdGr4OEKsRvvwwX4qXaz1eCSgp5vyaW2YF8ibRsSxeD X-Received: by 2002:a25:2fcc:: with SMTP id v195mr2687477ybv.119.1598625026161; Fri, 28 Aug 2020 07:30:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625026; cv=none; d=google.com; s=arc-20160816; b=bHh06HjVlzZZBWD0rh9xP94HpBqTAh7hjSQCWGuGxQ0pDrQO1g4llRz+6z8Ds+qry+ rVB3x158lo6ej6bvLruBlTJH+OQaUo+Kr6hDqKSH2aLBBeIHyAkTraWjFDCv5kg1hI7t nxrAWuHrddiUkUPPXgfunhIUBZPj+Fwk9Lk6/kWVV4+7emQMjjAQtgH2o9ud03jZ7j2O rb8j0hiQJkLRahlLbpD6/RhPUXj2Hhmn6CoRpny4pan8Q4HkQRoBjm9U9mO6C4Oi0+WW JuJKpmLx/Np63rcYqEg7iJOb/WX+paP787NpACann+l5Olj+e2wAygzSFzKo/BKwyve0 +agg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rMh4Sqcir06bVXs74gHMdeUNg4a+HHCVID7KGWDrg3A=; b=M5hkgt3GF0XkFoQ0Pw2DZ94vVrZdFZxfAwPIfDrhU2tHn7VqL0cwKW/HVI4CP+jlVM gs1a3Hzuu58Yb0+ANUMQeM9HJxSE5MPuR0F/z4CvJsD3SeFS3uMAPfuQJCmj1EjTlU06 JWfLSpcfw/Tfb7TfPZC2ggg02dTMM9LROERWaUN0mxYSmfqm6EBd1G4pAoWW9sgqyjrX Vi4DBSq3WMKNKW17tN4iFFKd9GdaCJetaaOY5/784AvY5zvILPSUgpQbRsLOSP/uKFcx jSOs6rnntvGKPYB3ZaTOW4jYBWUFolJCvq60BRrRKav4metBUHQ1DHnZ/peSWMxJkKDL qKyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iBbq5da3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_fsr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index aaac0c9a6c..34177f9b28 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -240,7 +240,7 @@ struct CPUMBState { uint32_t msr; uint64_t ear; uint32_t esr; - uint64_t fsr; + uint32_t fsr; uint64_t btr; uint64_t edr; float_status fp_status; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f63aae6de9..3fc2feda3d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; @@ -542,7 +541,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: - tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); @@ -583,7 +583,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); @@ -1798,7 +1799,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " + "debug=%x imm=%x iflags=%x fsr=%x " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, @@ -1867,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_fsr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr = From patchwork Fri Aug 28 14:18:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248514 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1124534ilg; Fri, 28 Aug 2020 07:22:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTt8hB9IHRvRv1kTGpLQwfVEWtmr3QiQRyEBt3ZVG7dQ1Z+m/TGpb5lppKbH2eSwQvNDez X-Received: by 2002:a25:c6cd:: with SMTP id k196mr2746951ybf.318.1598624529428; Fri, 28 Aug 2020 07:22:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624529; cv=none; d=google.com; s=arc-20160816; b=jDLE6xsnpeRtXfMKV3CzB/AH9OoXSa4RoIsZw97NsiP8s5VItAAn7FW8mbI//SiGW7 foOHu0ocyHRKnOsSfsP5j8Vr2dhe8oX22Eb5LMXcPpwPLZ1IdYUkhSVug+xcoiRHLDyn TE8evcidk8wTYaaSogekxdNy+kyteDum81EicUvRQ1H1G7HDZCNdQRKFKC9sL7OnNq6s Fiw1aiONTbD/NK5TqpyuYedw8qfloI++3fSbLNsXrx73LH63xkMVoyEqtjWQUaoBk7Ib 57RMADTrz/CUymaXsm5W+jt9z6YZf81+N51h59H5FAPY7cvaC3pJwbiCQP10nVDx3tEd YUEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AF5wUNj1rfWDk74W8hKW9/y1FLbHGsX9t+9rRKYsDAE=; b=uV0yyl2C/ZQoX6VX0V60rxnYUFMVFgyipBWl//zFcAI3cGEJ5O8kjHK+wHrHfWUQN9 azFEV8NTXw26oVPGhKlfDY/YWMTuh3BZh/IBLPwVwaAd7DfBrHQbcuNCsU1qIis5dT43 hI0hI9xegiA+0QYjZcvlj35kLZtgInOKm1WrLX223m+MCOOCMUZXl7lGxBSnHtQps1We cDVepudZqmPx3vVShvpZbjA89UhCQUYjVkuBRcZXGVr6eClUTjDHY8fJDxuyHm+NIfQB t78YPOiV4NfvGUzDofdF/oGshbb1Z6vOtUqPvKE52cW+3aiuDF6ALXesYRsbRZB5bjPf IJ+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cSJPLrm9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y83si1055805yby.351.2020.08.28.07.22.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:22:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cSJPLrm9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfGa-0004eB-RX for patch@linaro.org; Fri, 28 Aug 2020 10:22:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51088) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfET-00007u-3j for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:57 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:52175) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfER-000561-CS for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:56 -0400 Received: by mail-pj1-x1043.google.com with SMTP id ds1so564759pjb.1 for ; Fri, 28 Aug 2020 07:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AF5wUNj1rfWDk74W8hKW9/y1FLbHGsX9t+9rRKYsDAE=; b=cSJPLrm9GteLmp/zHcYXBP7RJR7B23j4r/EiC/h2x4srhE/XJSzyKYIm2vuVNjWSg+ vbqASILIB4TCQd6fuelOKhjCYpFZ170/obWyZNCxPEv5Z6bGpC3i/91BfafuJi33fMGi t5X2WnEW7RYHhzWjgpZAw9YzX3V1lflRQ28FtSYtbFiW3qCB3NU0XLbfm2vNHpH1Sj2A rDfNqk9uKagyhmCflNQeuiZP9rWXXwrNJ6U7WlITLS9fzRYLC2tlopXG9pXFyL0jNeaz Ubk3M/FvWCnTnaLB/AuEbQP6oRuP8OrwJlOvPSwmAl7MPgcI2o7zlnd2n14jApOvtynl 6Hvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AF5wUNj1rfWDk74W8hKW9/y1FLbHGsX9t+9rRKYsDAE=; b=TUUtZn7dUcn00esqgriMbdR4xhkhLKII2oTPYX1VYacOuz3/HnhGOJTyDOSK7QJ2jX bK7TRTd/sb9RlhBqFZ2NAdXmjCTbn/hIZd8VTNR4DEAnILPQt4absFtuTClvqWHDPwJE p0NNqvHi/G3yupWrLodZEqpCEauoS/N/maHzMBZnlv7betWcKxc99S5iL2Wqgwm3YIoC s8PKzVS4MWA5Y7eU/PQPz7rQvaVukkOb7h9wUDw1AWxLWMMpmviHJytA0pzSjxiUevQl x2gUeJg5AKsaF0Qbmb2ho6L/qxKUBFhPGueQS3QUdNUafb0I2H1CkdiI/c8GrruufBuX gWig== X-Gm-Message-State: AOAM531+aOt5eYROoBQQ2PwzEUrQO6lHg8PrD1hKw4Wqz+332mbce9rx d2t3nwtKd/sQcTDmTSPTZB9KADK57KYf2g== X-Received: by 2002:a17:90a:f28a:: with SMTP id fs10mr1331215pjb.219.1598624393664; Fri, 28 Aug 2020 07:19:53 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:19:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 17/76] target/microblaze: Fix width of BTR Date: Fri, 28 Aug 2020 07:18:30 -0700 Message-Id: <20200828141929.77854-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The branch target register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_btr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 12 +++++------- 2 files changed, 6 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 34177f9b28..72f068a5fd 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,7 +241,7 @@ struct CPUMBState { uint64_t ear; uint32_t esr; uint32_t fsr; - uint64_t btr; + uint32_t btr; uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3fc2feda3d..a2bba0fe61 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -545,7 +544,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); @@ -587,7 +587,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); @@ -1799,8 +1800,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%x " - "rbtr=%" PRIx64 "\n", + "debug=%x imm=%x iflags=%x fsr=%x rbtr=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, env->btr); @@ -1868,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_btr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } From patchwork Fri Aug 28 14:18:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248528 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1129984ilg; Fri, 28 Aug 2020 07:28:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxAPaSh6lNX7sbNDYWBoskh2P6lOgL5dX/3AR9G+KGoLuJX+j1W6Ut8HO/Wosu435f30pwd X-Received: by 2002:a25:cb8d:: with SMTP id b135mr2842474ybg.381.1598624938065; Fri, 28 Aug 2020 07:28:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624938; cv=none; d=google.com; s=arc-20160816; b=SDLjJtlL22vtyAo4J8I3U2rDjip9OKb6qlmqjtJaI2geIIi9Gnqw6gofcrYTfVKR6W 2skrvFRBdnRdVS6y9LjbIHc7iV/9fjqtN1+YR2ZvMB8U55Ia2s0xOfZnBd7AZJTt+zUA +2bdNTLdDIRX8IqtomtF+ZZBwr535sfY8E/EOjABHpnkcTzDA/YCkuHZUQa/bW87i+R9 YuRLtvorCx/rstSAoLxbEGiVqb492EciQaUPU6aKZVqr5lNTnVMjW9GciVtAPKNHuE/Y ds0UcjUAfqoxJp+GwLsh9YCM9NtLPutdQtDl/8h060S6jWXx8i5RMPcRAnfpeoD2ArjI dMCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZaIdcAkOSjEufmU2G8vkTG/fvmG7Z2otY+gyeoJlJtY=; b=nZ3t2TgADUdC7/tpFaouVRxA+9svhVH5Ujd/TmaIdQzNnpE9kMvvgUQ3KR1Djla04M zEogCWjfps9fFdHgFgTrpfZmxC7JjZhNdMTeDjOBdGsoCf7K84Q5BUzmnY8yIOg/4vy+ V0H8a+cg6A9hYfQy/+3iY3T0ghygYWoZNMnPGdLldY91+E5wazNV7fOGvYC6bZWF/FEG +qOQvvOF/GgR2gaNYAq1jQHSNVopEXTW9wmcBbmKBzoILI9ABS6wP4bAmP0R4zXXQM72 dkCyW+DYUXrV15q6KXIyvINrTiw/YZtCMCPiy3xgRlGAN7YRzYafrTsntBzYEgAPjGuL lX8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nq4CMsIz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c10si999362ybm.341.2020.08.28.07.28.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:28:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nq4CMsIz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfNB-0008Qv-G0 for patch@linaro.org; Fri, 28 Aug 2020 10:28:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEU-0000Ct-QA for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:58 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:52040) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfET-00056J-2B for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:19:58 -0400 Received: by mail-pj1-x1033.google.com with SMTP id ds1so564784pjb.1 for ; Fri, 28 Aug 2020 07:19:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZaIdcAkOSjEufmU2G8vkTG/fvmG7Z2otY+gyeoJlJtY=; b=Nq4CMsIzS5K26opVUF9V8DXJsA5W+8XBiW2LKu3khEvOhMUvw8rQ0FsI1TgVhJO9sd sBwfqqJD09GJMa1WCLkR8XlnjwxzxjCCQTvwSIIQDPqHgsT5pezT9hM3Oja/kw9bR6tp ezCJU2Gi9RcQ2RIIEyAjSu/qhBBq6JYF4ckhEjd1fUtJMTy/MjxKjOTsgCHx45sOuDzO VWbKBFMjAEsfNipdOwDuocrPww+4im6LJIN2nxVRUAAT2tRkTVGEV0EDmiqQb8EajHpY uqiPbpjiBGdnjqWXXGAFKZVh9kgh6RTNJtQ14R0fsI8fbk/cVQ4JHEfQM1kCneO8kapF JF+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZaIdcAkOSjEufmU2G8vkTG/fvmG7Z2otY+gyeoJlJtY=; b=M1dKhc1l0Z7/iZR3b0E+JRd9rIHrpBxq+zUuPuk2cN7kP3Mk56aX3/+zkZLi+lo0mG 3wtb5ymDtcfPFXFcSk4Hb7RfvNHyh3phYyHT9lc860uUBkhbYAOM4uW6SM5UO7fJPNOF W/Xp4f2q1aJiuP6IgYnwzEeztSiqjEW0SxHmFQszPNFnyMsFcRTkYC2A7qHhwhewORop LAYjmn1hnYaow/LZgUelOTGG4luRPHi1RgHwi3/+v8xTS2RY2qgwvQCp31NTcU8daDiQ 8/TUUD61K71FHogwYXARTv/Jtfz2yUOo0gVrNP5JA52IDNZ1Im/9IYHwoKqt0d9WLbar EOlQ== X-Gm-Message-State: AOAM5333dSs3u5CswGaO03lmSFpIvLPm674hKvR7QL9XrkteCBqy2k5X m1rgiYCA1Z85HipQ53zDrEgF+3wJZHv2oQ== X-Received: by 2002:a17:90a:d594:: with SMTP id v20mr1454736pju.227.1598624395285; Fri, 28 Aug 2020 07:19:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.19.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:19:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 18/76] target/microblaze: Fix width of EDR Date: Fri, 28 Aug 2020 07:18:31 -0700 Message-Id: <20200828141929.77854-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception data register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_edr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 72f068a5fd..b88acba12b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint32_t esr; uint32_t fsr; uint32_t btr; - uint64_t edr; + uint32_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a2bba0fe61..a862ac4055 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 cpu_btarget; @@ -548,7 +547,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: - tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, edr)); break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], @@ -591,7 +591,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, edr)); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -1818,7 +1819,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } /* Registers that aren't modeled are reported as 0 */ - qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " + qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " "rtlblo=0 rtlbhi=0\n", env->edr); qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { @@ -1868,8 +1869,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_edr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Fri Aug 28 14:18:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248518 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1125873ilg; Fri, 28 Aug 2020 07:23:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJykdG2Ne/1QW31HZ6cT1TJdNizRugol1cWMglt4FYI1a9ZcwZJ7zUFFsfLkuex/cfNBtBkH X-Received: by 2002:a25:e06:: with SMTP id 6mr2837889ybo.80.1598624619418; Fri, 28 Aug 2020 07:23:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624619; cv=none; d=google.com; s=arc-20160816; b=mLEqvt3CcdyEfY4jrV+ZG/6ihPvOmioiGMFy7xqO3Y/3P3JecQWC4UhtWRPTQGBlW1 UEIGe4ygSdzn/P7sOySjcHHSRt3wOMmzlspSOvqtgGsZ8jSuGkI0ygCgIvUcfZshf5Hj VxlLK37+mgUCgmQXlQLDPhZS2boLSggLlQ7/ewyc48gOi8J50sWZ8EPJONKGJDuLROCX u1WaQhQBYA9JdjcTSajIjGk4j6evXQIaFPe8+m26YEXrjU7QkUVnj1XK7bl4cFsGvCAF 1JHRHH58tLgLkWSNQ8njNoZ2U5MxqIHDUIFRR1rBAaPOSPZ5+Q6HuS5w98zDfevmn0A2 ztIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HaAnpocjYbBqDikM80fgZOEo5h0cDqsU8in/f2nqeSk=; b=KWsq/gj8SmTgVEOPaiD0M13jWVvoHiM8e37BUflggWb+MNtc4pY2LMrfJWEpsPLRBy LjmmSbfXlEq1iNYs7W8dOtK7pdYZ/vgKBIPlttomh7eLHJdUhdQqbDzWfZ5if2oZYNTw mnnwi4DP64eAHuT+oKgFhOf5423RqoR7GbgDOf82xpai5JVwsokm/HoZS+jJsKmBS0ll /w+B4R2AgFE9jnWR7hhl5hCmGcA6TkaJFVGZWIEdHJNQexxHVkBYlAoY6Vtqcp6XcX6Z 7zniecKFg+oP7vCF+RBg8hg836w9OaIR3qWu/QdRKacPqI/9ThH9hA5o3GslLyzNttTP nupg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cLry2Aar; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since cpu_ear is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a862ac4055..f5ca25cead 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,6 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -533,7 +532,12 @@ static void dec_msr(DisasContext *dc) msr_write(dc, cpu_R[dc->ra]); break; case SR_EAR: - tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); + tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_temp_free_i64(t64); + } break; case SR_ESR: tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); @@ -573,10 +577,15 @@ static void dec_msr(DisasContext *dc) msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: - if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); - } else { - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + if (extended) { + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); + } else { + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); + } + tcg_temp_free_i64(t64); } break; case SR_ESR: @@ -1865,8 +1874,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_ear = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); } From patchwork Fri Aug 28 14:18:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248522 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1127497ilg; Fri, 28 Aug 2020 07:25:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzz/TQxTHLtqHoKQ2kmvc0t33hd5AwoXhHf46alJUJLxrI3atvWrrwg8EGs5+W7rYd0UPO4 X-Received: by 2002:a25:2496:: with SMTP id k144mr2526331ybk.24.1598624742314; Fri, 28 Aug 2020 07:25:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624742; cv=none; d=google.com; s=arc-20160816; b=kdcI/F6WSf6ivtApPToj6A02ypEZG0zULJiAYERTNRNGZGXLGSvyCZZNrknEW7EVPc 4HQp3HcP+pIXrsEK7ZkSMv5Phgn7CLySPNhSDbnFzLQZrSVvYJDy84r/e8gzbkUnS/Dw AbEhF5U51J+yaPy4HSsoCPNVOJor1QWPKY9hKLU7a5A+ZXNaKRpLhND+x38UfQzAtcF/ gQ9cCk8L1k8wOmkvs3DpSev05SI4vc9W7TqOC+W6BBvGOZ2PC8Py8nWw+g/nwtrrrV+b BbkPCRY8YnIs9v1ZAw0OGsXTbdFj5NYm7McA00K7NjaWplH/3He5AA1+mIvIWPaknZUR obZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Z4AmITk5w2LQx1h3BHbpZiArbCayMAaSAdvlTGNWCzo=; b=C5KuKfz6wwaSa97jJWJ6vysgtHuA8YdeR0LDJOhGV77icait1GCwj2S51r3/tnTVzb wokyVlytAJhxAttjg0DBHbmUTkdPCwV2PuqJZ9u69jgwkbOG93RX6kMT2S6sDXmASGvf J4prpSl56WD272ORPRVl9pH4ZmvBBaafl+amsS8TypMChPl63HNDkv4kl1DJEEdFzAqQ Vb+s5c//zWZhjpQ6nVCDr8oU2w53PuxiLi4wJ3jLu3miSoarE0fNC8qiN8G+3/jqKPRC GDD7dj4bgcTrFQgMT2N7yFPi3qbOHkCdrpUaQDxIrRXmzfxOqpjKhqhPuUKvzGzo8L0n lANA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WAv9b7bU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out gen_raise_exception which does no cpu state sync. Rename t_gen_raise_exception to gen_raise_exception_sync to emphasize that it does a sync. Create gen_raise_hw_excp to simplify code raising EXCP_HW_EXCP. Since there is now only one use of cpu_esr, perform a store instead and remove the TCG variable. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 62 +++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f5ca25cead..9a00a78b8a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,6 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i32 cpu_esr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 cpu_btarget; @@ -114,17 +113,31 @@ static inline void t_sync_flags(DisasContext *dc) } } -static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) +static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); - t_sync_flags(dc); - tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; } +static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) +{ + t_sync_flags(dc); + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_raise_exception(dc, index); +} + +static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) +{ + TCGv_i32 tmp = tcg_const_i32(esr_ec); + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr)); + tcg_temp_free_i32(tmp); + + gen_raise_exception_sync(dc, EXCP_HW_EXCP); +} + static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { #ifndef CONFIG_USER_ONLY @@ -178,8 +191,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); } return cond; } @@ -194,8 +206,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); } return cond_user; } @@ -540,7 +551,8 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, esr)); break; case SR_FSR: tcg_gen_st_i32(cpu_R[dc->ra], @@ -589,7 +601,8 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, esr)); break; case SR_FSR: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -1258,8 +1271,7 @@ static void dec_br(DisasContext *dc) /* mbar IMM & 16 decodes to sleep. */ if (mbar_imm & 16) { - TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT); - TCGv_i32 tmp_1 = tcg_const_i32(1); + TCGv_i32 tmp_1; LOG_DIS("sleep\n"); @@ -1269,13 +1281,16 @@ static void dec_br(DisasContext *dc) } t_sync_flags(dc); + + tmp_1 = tcg_const_i32(1); tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); - gen_helper_raise_exception(cpu_env, tmp_hlt); - tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); + + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); + + gen_raise_exception(dc, EXCP_HLT); return; } /* Break the TB. */ @@ -1300,14 +1315,15 @@ static void dec_br(DisasContext *dc) tcg_gen_movi_i32(env_btaken, 1); tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { - if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) - t_gen_raise_exception(dc, EXCP_BREAK); + if (!(dc->tb_flags & IMM_FLAG) && + (dc->imm == 8 || dc->imm == 0x18)) { + gen_raise_exception_sync(dc, EXCP_BREAK); + } if (dc->imm == 0) { if (trap_userspace(dc, true)) { return; } - - t_gen_raise_exception(dc, EXCP_DEBUG); + gen_raise_exception_sync(dc, EXCP_DEBUG); } } } else { @@ -1411,8 +1427,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_FPU); } return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; } @@ -1668,8 +1683,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) #endif if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { - t_gen_raise_exception(dc, EXCP_DEBUG); - dc->is_jmp = DISAS_UPDATE; + gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that @@ -1874,8 +1888,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_esr = - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Fri Aug 28 14:18:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248535 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1132329ilg; Fri, 28 Aug 2020 07:31:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJPqntxSSb9P+Xlq/VZZhFwMkNRiwgp3dEEtj9iJY15QTRwA5N29+dbMviUv936gZ7pum9 X-Received: by 2002:a25:4211:: with SMTP id p17mr3089496yba.101.1598625103757; Fri, 28 Aug 2020 07:31:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625103; cv=none; d=google.com; s=arc-20160816; b=oaK6g97o/ZGLERqkMqu+se+WFznIVEqzsxScp0+Fybg+t6XnKllNyIzo+P02PMU9rR I4Jv7rMxbSCILm7ENISFqHmQjR5z+okVwUusdTWEFAltQL6tvfyKr//n9P/q7Cqj3gpb cca4raeVpkopUJIggXoXVS8a2+ULPaNooEkx9wZsJZV/H+faXbU8LQOxVQM8Y48p+BBV D/inzdkW4dUKNKxk9w3TwZSyDA566QVRuNosna288bx35P9Vv8tBxjKafUxKNXey5DZQ Z8J/WsSE41tLkRLEXM/GkCxdcDWGwhMyqYtbaCI6acVB/yfpUa+/9lWIzSQijlYx31dL jBeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=45kd/bFobWQBgRWzCCV4KKe4PH1pZqfnSM8e41v0zaE=; b=M9Byu+u+a7SH6zVMyOf5EHMbMBR1cZTCiZqtZOUNk2SkOy5+fO3iudNPp0RO8x2IR0 mmxs7VjuPXsOO8IhIy7GK0L6DFgxxZPsedoMHnhc2BgZkxAQ3BAdaetltQ2snPGyp2S8 8Z62mx19HiluRrs4cNu1VWBDoMswX0/uJhICxrqCZsKL1BA1uDpgdYPwrTMsY9kiJZZH SXJG0BzpED2LXSbVHngDXMw3gO4O9CTtBqJARNzRtrQVHTn7EMZfgdrOpB8YdmRBSvj2 oiNfVBpoaUCVASdL8Xo7M7YJAIQjCmdUxZbMrggVh/yae8RveMisVihnzIx26MnYl7FY 8d5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PUA5pzzC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will allow tcg to remove any dead code that might follow an exception. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 2f8bdea22b..820711366d 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,4 +1,4 @@ -DEF_HELPER_2(raise_exception, void, env, i32) +DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_1(debug, void, env) DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) From patchwork Fri Aug 28 14:18:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248539 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1134322ilg; Fri, 28 Aug 2020 07:33:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyE6x8QjZjg2WQinSFZCoCLlMpikQX3I5xJISR2YK7Tzh3VXZNG+Dc120gpCQV6+bd2jFtq X-Received: by 2002:a25:6c86:: with SMTP id h128mr2655268ybc.115.1598625234633; Fri, 28 Aug 2020 07:33:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625234; cv=none; d=google.com; s=arc-20160816; b=JVD8XPp+WWwURGcl8YpCsrYUBENdvFmKA1BtiIvDWXNQJxlbBpvQ6yzfPQAP/2PlPX NUCcgEGFZGKEdhErFLIbvQhKXBr70eoMoUM5ddom2pik5c8m03zLBE38WmH+DmjeETcU OHguKHZ7Jwxz1SVYhR+QS7eIDGepKW70UMnJr58/sNcHKFquTmMwdNqwtUqx+WCD4QEp 9sf0f5kupWcf7Vk/0FphnE7NrgsdpV8EJMg5Ox/D7SUEyaxkGMkv0TlSlmcEta26OnEM 6iNKmp90diiIUShOoX7VaETjTwyynNZwqfsgxgLvvSR+GytL0ga7zjoDxBbXe2RVudas nw6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lL2TV9fvxAuHwerQiahLV44CD3Djc67HSq2e2+fPjhU=; b=ZUPmmCN38YuEHsh6t1ZeTfhZii/UiaDWKZQBoTmVM0dGWpZL75DU5h2reZzEAJ1d6R 66gP9EY/C+q+wxUIuV6Z/1D7LdGXTYPJh0YSr4wvsUDsNqlUTdoCOH6Z8EMrxuHStZ35 jug0o03CrubjQaGfAe6nuTZWm9crpqOc40ZR0aoUynh5ICyZ9vAdLBOq/d822yNgHGTo JfJsa/WqqD5jriCq9ye2SbqNe+w4JfG7Mgck3+NcLVyU30ir5VnDDQpG6y8KwfMBirDt 6SaIbcPLFeqOGZx8BY7dl7FhNhKOsj9PnC982+RPYoNgn0j/ERdhUniAlsiHRao6WCcE QCdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h2uppks3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x5si1079199ybl.171.2020.08.28.07.33.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:33:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h2uppks3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfRy-0001gA-2J for patch@linaro.org; Fri, 28 Aug 2020 10:33:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEa-0000Sf-Nb for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:04 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:40437) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEY-00056q-Fn for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:04 -0400 Received: by mail-pf1-x443.google.com with SMTP id c142so665850pfb.7 for ; Fri, 28 Aug 2020 07:20:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lL2TV9fvxAuHwerQiahLV44CD3Djc67HSq2e2+fPjhU=; b=h2uppks3xwpxy0Qhl+Zy4+9XnKx24TIktbuQqHcf6HqhMTz/3UKyZSw5JE/AgmRAtJ gIE67Kdgf9GNjlpuT/lp4RKDjVJAQYnUjAWjo5ebClujJiifUMAfAmlT5+L4jvGFr7Ns wlzONaiDg0n/UXDVsgdlF1qHcaj7cO0Wo83jxwWb3OAp5Y3r9+rR4WIU09pQsDQfOePx Q6KUXZw2LQKY2J4kHACfH32SAJccXpjPdQ1m6BqFHltXy8rBgMWr6HSePGS7ddRYMxBC L4/Bc8Gg5aLXWU5rEvZFaoIwjE1Fq+HwIgfs5Nv44LvxuPKa4VLKNe+mjrRMEDcxgM9R qwKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lL2TV9fvxAuHwerQiahLV44CD3Djc67HSq2e2+fPjhU=; b=njCYbhvnn9jw1m7+PZuzawpkpkIRJE8PcA1WO27rZCmxiShEKmt5/cjPW3aUPn6Xli FuXG/JfOl4MwiO0/mnOBG+h2DS/EjtEw+DqCRIhfRWGfe9AhXnTF1uGssdBJY+YTNrVd 6KeERiO80w+WzYyL0vrYfY2Ns1cLd1Zp7X2zAl9Q1MhSuuINpOFsPD2s2XLU1/VUXKCO DP5mfioL+d9QfyUXQfk2KpyvczRn6HbRs/hBk9KPrbNHUX8R3H3CKeR8j6/fl1jTM7/Z oSg5ZqPWBbBMBDF80X/JiR3Cdm9+PtVpKhL+fxSaQKiJhKzTZSXw8NkQyFhVbBTFKaSf M09g== X-Gm-Message-State: AOAM530iPzeHwd2J4Rzx1Uuxx4mUZMZP66qxPFyj9IuZOnXJNNgI6UlS QcS48xOm4e+h/9aVAuW4ciIcvr0aJJeVEA== X-Received: by 2002:a63:50c:: with SMTP id 12mr1426504pgf.173.1598624400550; Fri, 28 Aug 2020 07:20:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.19.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:19:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 22/76] target/microblaze: Remove helper_debug and env->debug Date: Fri, 28 Aug 2020 07:18:35 -0700 Message-Id: <20200828141929.77854-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not used, and seems redundant with -d cpu. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 - target/microblaze/helper.h | 1 - target/microblaze/op_helper.c | 23 ----------------------- target/microblaze/translate.c | 16 ++-------------- 4 files changed, 2 insertions(+), 39 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b88acba12b..7708c9a3d3 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -229,7 +229,6 @@ typedef struct CPUMBState CPUMBState; #define STREAM_NONBLOCK (1 << 4) struct CPUMBState { - uint32_t debug; uint32_t btaken; uint32_t btarget; uint32_t bimm; diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 820711366d..9309142f8d 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_1(debug, void, env) DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) DEF_HELPER_2(cmpu, i32, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index dc2bec0c99..d79202c3f8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -71,29 +71,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -void helper_debug(CPUMBState *env) -{ - int i; - - qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%x resr=%x rear=%" PRIx64 " " - "debug[%x] imm=%x iflags=%x\n", - env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags); - qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", - env->btaken, env->btarget, - (env->msr & MSR_UM) ? "user" : "kernel", - (env->msr & MSR_UMS) ? "user" : "kernel", - (bool)(env->msr & MSR_EIP), - (bool)(env->msr & MSR_IE)); - for (i = 0; i < 32; i++) { - qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); - if ((i + 1) % 4 == 0) - qemu_log("\n"); - } - qemu_log("\n\n"); -} - static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) { uint32_t cout = 0; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9a00a78b8a..ecfa6b86a4 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -53,7 +53,6 @@ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ -static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; @@ -1675,13 +1674,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) tcg_gen_insn_start(dc->pc); num_insns++; -#if SIM_COMPAT - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_debug(); - } -#endif - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in @@ -1824,10 +1816,9 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%x rbtr=%x\n", + "imm=%x iflags=%x fsr=%x rbtr=%x\n", env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags, env->fsr, - env->btr); + env->imm, env->iflags, env->fsr, env->btr); qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", @@ -1857,9 +1848,6 @@ void mb_tcg_init(void) { int i; - env_debug = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, debug), - "debug0"); env_iflags = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, iflags), "iflags"); From patchwork Fri Aug 28 14:18:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248543 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1135539ilg; Fri, 28 Aug 2020 07:35:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx2K1g0ubM6i/x/RYWMy68OEw1zu38rO9K7D0EaoUeAlFHiB0ArDdCZizLp64UPk9AU0R8C X-Received: by 2002:a25:dc4b:: with SMTP id y72mr2708696ybe.197.1598625314891; Fri, 28 Aug 2020 07:35:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625314; cv=none; d=google.com; s=arc-20160816; b=FvZ+mpbtSUzAKQoeq3WsLdLYNB1+I8f4moV8Kmx2nroqiiqLMTeUUux8URNim6Yqm2 RBx+cAeI6DTM0/wjaA9SkWzKEBuvr/w0zbYxW9hsBKzTOX8cfGUxEjMpU13VEYM15SRs THvbXE2oNPNc4QRcLx/kwuQfIArhyE8MInChONZuM3kO04QxkP0gCyIDrlKB9LHX0a3Y RwoX/G1hYjwYriYtf0Ffb0MlR33k1z8FVhaeyQuWcSrq3jN6ODBXTVDp0HRaqv03E+FU e36EiL0IMhlMLhFKgJGYMVoUVsGuniADXJIE4YPcmI7q2vrApMZ/oB6CdX1BDW4TqFXG hkZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Xvkn3g2mPXtRTX9S6LWMZSG9zfZ6Smrj8vu/NEKgNeA=; b=MqnTrH408T+pchDsINYPAscSNxpGZHdulgPEPzsHjL3txLq734Pz3qhTBEvqYgMEv3 sc1GfF73Vnz8yj0ukgdzpb+4r5wuoR0ZNuv63stLGTa8n0B5PNPmOdIE/cGQ5OP+j6Nz tzRkl2Jpye4lUXms1nA1cxPDYRQm3bMMMCxXqhSHVyjJi4XeoNJWDaAMr7G5YxcNOt7u Vwxxq0jlxN6Wj9jp4Zn2y7uPDMnnswPbPk4LjmbMK5p3wgxv7PIlJikyaRr+rnPYaE46 xgnFDIR8jW5D67sYAalDFPrqLF8Ey1SP8mZPpxoYA7m9k9yvphir4wp+DW8TWWOuO/PG eyAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vNrH2eFf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is cpu_imm, cpu_btaken, cpu_iflags, cpu_res_addr and cpu_res_val. It is standard for these file-scope globals to begin with cpu_*. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 54 +++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ecfa6b86a4..9aa63ddcc5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,12 +56,12 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i32 env_imm; -static TCGv_i32 env_btaken; +static TCGv_i32 cpu_imm; +static TCGv_i32 cpu_btaken; static TCGv_i32 cpu_btarget; -static TCGv_i32 env_iflags; -static TCGv env_res_addr; -static TCGv_i32 env_res_val; +static TCGv_i32 cpu_iflags; +static TCGv cpu_res_addr; +static TCGv_i32 cpu_res_val; #include "exec/gen-icount.h" @@ -107,7 +107,7 @@ static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ if (dc->tb_flags != dc->synced_flags) { - tcg_gen_movi_i32(env_iflags, dc->tb_flags); + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); dc->synced_flags = dc->tb_flags; } } @@ -222,10 +222,10 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_i32(env_imm, env_imm, dc->imm); + tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm); else - tcg_gen_movi_i32(env_imm, (int32_t)((int16_t)dc->imm)); - return &env_imm; + tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm)); + return &cpu_imm; } else return &cpu_R[dc->rb]; } @@ -859,7 +859,7 @@ static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); } dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); @@ -869,7 +869,7 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { LOG_DIS("imm %x\n", dc->imm << 16); - tcg_gen_movi_i32(env_imm, (dc->imm << 16)); + tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; } @@ -1040,8 +1040,8 @@ static void dec_load(DisasContext *dc) } if (ex) { - tcg_gen_mov_tl(env_res_addr, addr); - tcg_gen_mov_i32(env_res_val, v); + tcg_gen_mov_tl(cpu_res_addr, addr); + tcg_gen_mov_i32(cpu_res_val, v); } if (dc->rd) { tcg_gen_mov_i32(cpu_R[dc->rd], v); @@ -1103,7 +1103,7 @@ static void dec_store(DisasContext *dc) write_carryi(dc, 1); swx_skip = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, addr, swx_skip); + tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); /* * Compare the value loaded at lwx with current contents of @@ -1111,11 +1111,11 @@ static void dec_store(DisasContext *dc) */ tval = tcg_temp_new_i32(); - tcg_gen_atomic_cmpxchg_i32(tval, addr, env_res_val, + tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val, cpu_R[dc->rd], mem_index, mop); - tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip); + tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); write_carryi(dc, 0); tcg_temp_free_i32(tval); } @@ -1204,7 +1204,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) TCGv_i32 zero = tcg_const_i32(0); tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, - env_btaken, zero, + cpu_btaken, zero, pc_true, pc_false); tcg_temp_free_i32(zero); @@ -1245,7 +1245,7 @@ static void dec_bcc(DisasContext *dc) dc->jmp = JMP_INDIRECT; tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } - eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); + eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } static void dec_br(DisasContext *dc) @@ -1311,7 +1311,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_INDIRECT; if (abs) { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && @@ -1330,7 +1330,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_DIRECT; dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); } else { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } } @@ -1419,7 +1419,7 @@ static void dec_rts(DisasContext *dc) LOG_DIS("rts ir=%x\n", dc->ir); dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } @@ -1722,7 +1722,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) TCGLabel *l1 = gen_new_label(); t_sync_flags(dc); /* Conditional jmp. */ - tcg_gen_brcondi_i32(TCG_COND_NE, env_btaken, 0, l1); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); gen_goto_tb(dc, 1, dc->pc); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); @@ -1848,22 +1848,22 @@ void mb_tcg_init(void) { int i; - env_iflags = tcg_global_mem_new_i32(cpu_env, + cpu_iflags = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, iflags), "iflags"); - env_imm = tcg_global_mem_new_i32(cpu_env, + cpu_imm = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); cpu_btarget = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btarget), "btarget"); - env_btaken = tcg_global_mem_new_i32(cpu_env, + cpu_btaken = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btaken), "btaken"); - env_res_addr = tcg_global_mem_new(cpu_env, + cpu_res_addr = tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); - env_res_val = tcg_global_mem_new_i32(cpu_env, + cpu_res_val = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, res_val), "res_val"); for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { From patchwork Fri Aug 28 14:18:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248548 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1137552ilg; Fri, 28 Aug 2020 07:37:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjQX4HcOVNIAi438GTCkAxvSnWEsQXfQRhiFxbrF9QCP1zRAS68Tt9XmH1ZA1eVk3XAh13 X-Received: by 2002:a05:6902:4af:: with SMTP id r15mr2760587ybs.32.1598625447888; Fri, 28 Aug 2020 07:37:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625447; cv=none; d=google.com; s=arc-20160816; b=FmF4pp8bAPMTWt8iKDfrfR7zYSuBzOs7cItDZ4Lcu1lJPkw+wHZ7svyNS9OifeNSoF CNO1vRyqRutcDtt6g1O/DZ62bMuYtbSOuNlrccsnoYCwxsNQoTkbYXj6GdxboflRgEzj GPlE862o009nn7Pkrw4X5Nbz/Z0nlenVvK5KUo8Xsouib/KNIlgJPAGUnYFT6O06xD3d 9yXs+FKvkHiLdQHOoFXrtj12lwUQQKhNFNX2HxrKpiABrP5bJycI+4CLf26MBJNMAvmX qsANuDpJgvXPAZxPUARzKHl9p9W+1ESZbJis2JJci62H8GOyQ5x2rcx1Qy+Oa3wCF8Jj UQPA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id c204si1053713ybf.366.2020.08.28.07.37.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:37:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="w9NqW6o/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfVP-0008U8-8f for patch@linaro.org; Fri, 28 Aug 2020 10:37:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEd-0000YI-0n for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:07 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:37658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEb-00057A-1P for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:06 -0400 Received: by mail-pg1-x541.google.com with SMTP id 5so529341pgl.4 for ; Fri, 28 Aug 2020 07:20:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7NCItsGikAjoxCQbtrtcdgvM3OCnFXhPqNO+3OzZ5UY=; b=w9NqW6o/d7xpN7WyjF8XV2hXkg3mEhZ/pa4ceYASlCwZvWbQDnG6ThRCKRTCVtxnbJ 7J60iN4D83usBnCCpKMt0eY9olEdUEZGEKoRS3TiZ2Wd+jpJ4T4ZoeSAN3BQydFvZcc9 +H6a45JiryEu2nnEd/OZQDgDV0BDimi7MW5S1HcX9Bq8CjaH39d2lkZyFkdBXEe0TrVh GxsVNDu1DD60pGaqDICGtbHCHv9MFcEM+SPCAw1d2rJtqfLfc7OUwueYpO4vAIis8sw+ TERKySKI8eE7htAJ877GP4N1dEd19FQNOpd4r/Fm/u21BB5ZVTCq5TLhDBMKL0U48dN/ y4lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7NCItsGikAjoxCQbtrtcdgvM3OCnFXhPqNO+3OzZ5UY=; b=jH0GBm1iqAHEgBOnZCLe+kIvEWx9scbr6rU2HNnAT0ApoQuvAhc4JYbO9meFSA7EXh BSrI7qxMwveV5QoqncahWerNj6dYfFEduRNiGYypoZjF5JS+gyjIty0MDTsd87EpXFWc vDA3ZlUPUlg1ldEnveQjZPZ+TqvAomC9u0G7IAVjDWzJav2DUkw8todM2gahuKncc7wQ y0h3Lm0cEYu5dPswqRzBGT98ibCcoUk5B+pvnc650nY2kCN2z/cwwNOyo4bPwlhFlZhT 79fCDl0/C6L0+XQg/pxSjwdHqF7YlvOChohO9Ub/cIpUPC7pqKnH2ODTAtMOtswCatsD nxKg== X-Gm-Message-State: AOAM530BerA4wSargxV4yupIn3N9FnxZZ+puScW1ZMfstEewjWUl+Lrq lvYl6QsxxMHODNzhwopX2+DJXDr8go/m2g== X-Received: by 2002:a63:4c11:: with SMTP id z17mr1408895pga.152.1598624403254; Fri, 28 Aug 2020 07:20:03 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 24/76] target/microblaze: Tidy mb_tcg_init Date: Fri, 28 Aug 2020 07:18:37 -0700 Message-Id: <20200828141929.77854-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All of the tcg globals can be recorded in the same table. Drop the "r" prefix from "rpc" and "rmsr". Obviates the need for regnames[], which was incorrectly not const. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 62 +++++++++++++++-------------------- 1 file changed, 27 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9aa63ddcc5..e709884f2d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -95,14 +95,6 @@ typedef struct DisasContext { int singlestep_enabled; } DisasContext; -static const char *regnames[] = -{ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", -}; - static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1846,36 +1838,36 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) void mb_tcg_init(void) { - int i; +#define R(X) { &cpu_R[X], offsetof(CPUMBState, regs[X]), "r" #X } +#define SP(X) { &cpu_##X, offsetof(CPUMBState, X), #X } - cpu_iflags = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, iflags), - "iflags"); - cpu_imm = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, imm), - "imm"); - cpu_btarget = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, btarget), - "btarget"); - cpu_btaken = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, btaken), - "btaken"); - cpu_res_addr = tcg_global_mem_new(cpu_env, - offsetof(CPUMBState, res_addr), - "res_addr"); - cpu_res_val = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, res_val), - "res_val"); - for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { - cpu_R[i] = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, regs[i]), - regnames[i]); + static const struct { + TCGv_i32 *var; int ofs; char name[8]; + } i32s[] = { + R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), + R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), + R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), + R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), + + SP(pc), + SP(msr), + SP(imm), + SP(iflags), + SP(btaken), + SP(btarget), + SP(res_val), + }; + +#undef R +#undef SP + + for (int i = 0; i < ARRAY_SIZE(i32s); ++i) { + *i32s[i].var = + tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name); } - cpu_pc = - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); - cpu_msr = - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + cpu_res_addr = + tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Fri Aug 28 14:18:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248525 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1128550ilg; Fri, 28 Aug 2020 07:27:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2tjNkMOwAaabMDKjB6oV8HQnE3P78UTKeAh/pKhLyOpYpxXYbLKenWXKmt4LW/WVBPhNM X-Received: by 2002:a25:70c1:: with SMTP id l184mr2801643ybc.241.1598624828265; Fri, 28 Aug 2020 07:27:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624828; cv=none; d=google.com; s=arc-20160816; b=Jn8zEWFRP4cJgsSL2ymiJlyIDjoJPmD1FUU//Vc/Obzay3dWQKkYMoSV4G/mvZpR2L feYJXMTZnPlc2cCXO5tqNGI7nfgP+VZQWTke7mTCxNF3mbE10PD0w4grA/iu7aTIvIFd FMHZh/NEjxFY0C5bJnTzzjdaNNFMOx24yF6+2Kyxpjr0SFbFBb+d61h29VI9hg9ruQxo Czjg0DmcLDBNzd6IF2o2IGHi7bPqOQyp5k0W3ESOn8MU0w7PNj5WY94/xgR3EGX8V69O GZSbyNx1iMPIubK8iuisuTDxCdvHC7wiU1dt//JyWObarw4/M4iRVFMyl5e3KY82AJMS rWlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tvav2yDgl091Kla7AxGkIifdrAi1yowT9YLtoH5uMlM=; b=UItHgKoB86++MmY0JRpZKqa4/ohmxIwzIJH8/yFVXXetkznbywLzQNl194KObeCx+m xjx3NWaCfhJOTFEhcp6JahhyoBJpdjo9M+FtUnQvqreQ1OJKcwsA6BwSKNQYWhEDhYyb tdbGlRd8cjFwYc30+8iCGiICqwP0ndI6fOU3zUTusBgYGWCUXmCL0QFwOblfw+25+2R1 Sd915E5JcJ04YBHE28i5pt/GA2KPh7m7MGqSH+ErfX+7tzkOqgTfSfwTXymMjGWJAP84 M8Hn4TLloMgqwZ8CWpX2cT/a7m3l6VBIWdDrWCJXkLQsg8u7R2QmDtPfyJAElng9FtIB GR2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c7bxIiv5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 135si1059072ybd.363.2020.08.28.07.27.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:27:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c7bxIiv5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfLP-0005zq-Iu for patch@linaro.org; Fri, 28 Aug 2020 10:27:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEf-0000eA-Bf for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:09 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:42409) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEc-00057J-Na for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:09 -0400 Received: by mail-pf1-x441.google.com with SMTP id 17so729988pfw.9 for ; Fri, 28 Aug 2020 07:20:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tvav2yDgl091Kla7AxGkIifdrAi1yowT9YLtoH5uMlM=; b=c7bxIiv55uJTvV7CM3S2ERtZ6aPNhVq4Z0OLfFhAKSlx5dnzd/6p7Tkk2GaUJWYVV7 hSPAO0gdAa6oTbnW+QhUw/TDWrsMmiPRdWjtMApxvejOZ0jlE0h9Itt52acYpIacaMR7 7NUSwxxnsOx1+ScErVMJ+jTWw7/oQCoW6Gx3lzqf5ek8apX8aEdM3waqJDMVpnFLg+Mt ofbo7Advl6BYzQLf3sb94G61JX6QM5Xcuq8bB9xNaLg88JhYA4267fcERck/AmP58gVS qapZ+M76ge9nLTIHSlO3YaM6DQkIbpXNZIhVbXUXA9p013dAGFythezqt9LYTZTtB/ly xC8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tvav2yDgl091Kla7AxGkIifdrAi1yowT9YLtoH5uMlM=; b=YUjd+TK37pyhFkaMpN4e8CTIrSeTCj/CqfVvuAa1vXWhFaOgu+qmESuGxpUHZAf0WU 4vJgI0xeOQ0AJoDImx3CdzvQN+OIg8IzdnEIhJ0tuvb3+a5WMZs18igTNLwNS0NBfpou SX2kZ12ihUMEK56j9O+TgvyLkCt2mo+qEThgKEFqIomjZ2GOGScRI9itxOA4MOuG4iS4 LCFtdUZ/GPUUn7aylMHLFqcdkTbhgdy2dC2u5bDr1lqCbgyXg8WskWYNthwXjcjiIEob 17BNmKGycGPumLvL48Mw/QszwdCGJw05amQr2kEJmeWFQGEiiuf0PzaKhcHgTYXZ3PBB vhAw== X-Gm-Message-State: AOAM5330zQQo5nIpHxCzjTc3CYM5p8EWiSNpkLbi2j0GgC4rJHR6G04F 4UHjzh5diKldBgOGek4fMvNysNTeSa/LmQ== X-Received: by 2002:a05:6a00:1688:: with SMTP id k8mr1414318pfc.33.1598624404483; Fri, 28 Aug 2020 07:20:04 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 25/76] target/microblaze: Split out MSR[C] to its own variable Date: Fri, 28 Aug 2020 07:18:38 -0700 Message-Id: <20200828141929.77854-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Having the MSR[C] bit separate will improve arithmetic that operates on the carry bit. Having mb_cpu_read_msr() populate MSR[CC] will prevent the carry copy not matching the carry bit. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 19 +++++++- linux-user/elfload.c | 2 +- target/microblaze/cpu.c | 4 +- target/microblaze/gdbstub.c | 4 +- target/microblaze/helper.c | 58 +++++++++++----------- target/microblaze/translate.c | 91 +++++++++++------------------------ 6 files changed, 82 insertions(+), 96 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7708c9a3d3..7066878ac7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -236,7 +236,8 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint32_t pc; - uint32_t msr; + uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ + uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ uint64_t ear; uint32_t esr; uint32_t fsr; @@ -327,6 +328,22 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +static inline uint32_t mb_cpu_read_msr(const CPUMBState *env) +{ + /* Replicate MSR[C] to MSR[CC]. */ + return env->msr | (env->msr_c * (MSR_C | MSR_CC)); +} + +static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) +{ + env->msr_c = (val >> 2) & 1; + /* + * Clear both MSR[C] and MSR[CC] from the saved copy. + * MSR_PVR is not writable and is always clear. + */ + env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR); +} + void mb_tcg_init(void); /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero diff --git a/linux-user/elfload.c b/linux-user/elfload.c index bbfb665321..98af4fe7e0 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1033,7 +1033,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env } (*regs)[pos++] = tswapreg(env->pc); - (*regs)[pos++] = tswapreg(env->msr); + (*regs)[pos++] = tswapreg(mb_cpu_read_msr(env)); (*regs)[pos++] = 0; (*regs)[pos++] = tswapreg(env->ear); (*regs)[pos++] = 0; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 0eac068570..1eabf5cc3f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -121,9 +121,9 @@ static void mb_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ - env->msr = MSR_EE | MSR_IE | MSR_VM | MSR_UM; + mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); #else - env->msr = 0; + mb_cpu_write_msr(env, 0); mmu_init(&env->mmu); env->mmu.c_mmu = 3; env->mmu.c_mmu_tlb_access = 3; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 9cba9d2215..08d6a0e807 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -62,7 +62,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pc; break; case GDB_MSR: - val = env->msr; + val = mb_cpu_read_msr(env); break; case GDB_EAR: val = env->ear; @@ -118,7 +118,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pc = tmp; break; case GDB_MSR: - env->msr = tmp; + mb_cpu_write_msr(env, tmp); break; case GDB_EAR: env->ear = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b2373f6a23..9a95456401 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -112,12 +112,11 @@ void mb_cpu_do_interrupt(CPUState *cs) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; - uint32_t t; + uint32_t t, msr = mb_cpu_read_msr(env); /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); -/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; switch (cs->exception_index) { case EXCP_HW_EXCP: @@ -136,11 +135,12 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->msr & (MSR_VM | MSR_UM)) << 1; - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |= t; + t = (msr & (MSR_VM | MSR_UM)) << 1; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; /* Exception in progress. */ - env->msr |= MSR_EIP; + msr |= MSR_EIP; + mb_cpu_write_msr(env, msr); qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%x ear=%" PRIx64 " " @@ -178,11 +178,12 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->msr & (MSR_VM | MSR_UM)) << 1; - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |= t; + t = (msr & (MSR_VM | MSR_UM)) << 1; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; /* Exception in progress. */ - env->msr |= MSR_EIP; + msr |= MSR_EIP; + mb_cpu_write_msr(env, msr); qemu_log_mask(CPU_LOG_INT, "exception at pc=%x ear=%" PRIx64 " iflags=%x\n", @@ -193,11 +194,11 @@ void mb_cpu_do_interrupt(CPUState *cs) break; case EXCP_IRQ: - assert(!(env->msr & (MSR_EIP | MSR_BIP))); - assert(env->msr & MSR_IE); + assert(!(msr & (MSR_EIP | MSR_BIP))); + assert(msr & MSR_IE); assert(!(env->iflags & D_FLAG)); - t = (env->msr & (MSR_VM | MSR_UM)) << 1; + t = (msr & (MSR_VM | MSR_UM)) << 1; #if 0 #include "disas/disas.h" @@ -212,21 +213,20 @@ void mb_cpu_do_interrupt(CPUState *cs) && (!strcmp("netif_rx", sym) || !strcmp("process_backlog", sym))) { - qemu_log( - "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->pc, env->msr, t, env->iflags, - sym); + qemu_log("interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", + env->pc, msr, t, env->iflags, sym); log_cpu_state(cs, 0); } } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%x msr=%x %x iflags=%x\n", - env->pc, env->msr, t, env->iflags); + "interrupt at pc=%x msr=%x %x iflags=%x\n", + env->pc, msr, t, env->iflags); - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); - env->msr |= t; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); + msr |= t; + mb_cpu_write_msr(env, msr); env->regs[14] = env->pc; env->pc = cpu->cfg.base_vectors + 0x10; @@ -237,20 +237,22 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); - t = (env->msr & (MSR_VM | MSR_UM)) << 1; + t = (msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=%x msr=%x %x iflags=%x\n", - env->pc, env->msr, t, env->iflags); + env->pc, msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |= t; - env->msr |= MSR_BIP; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; + msr |= MSR_BIP; if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->pc; - env->msr |= MSR_BIP; + msr |= MSR_BIP; env->pc = cpu->cfg.base_vectors + 0x18; - } else + } else { env->pc = env->btarget; + } + mb_cpu_write_msr(env, msr); break; default: cpu_abort(cs, "unhandled exception type=%d\n", diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e709884f2d..0c9b4ffa5a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,6 +56,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; +static TCGv_i32 cpu_msr_c; static TCGv_i32 cpu_imm; static TCGv_i32 cpu_btaken; static TCGv_i32 cpu_btarget; @@ -150,30 +151,6 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) } } -static void read_carry(DisasContext *dc, TCGv_i32 d) -{ - tcg_gen_shri_i32(d, cpu_msr, 31); -} - -/* - * write_carry sets the carry bits in MSR based on bit 0 of v. - * v[31:1] are ignored. - */ -static void write_carry(DisasContext *dc, TCGv_i32 v) -{ - /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1); - tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1); -} - -static void write_carryi(DisasContext *dc, bool carry) -{ - TCGv_i32 t0 = tcg_temp_new_i32(); - tcg_gen_movi_i32(t0, carry); - write_carry(dc, t0); - tcg_temp_free_i32(t0); -} - /* * Returns true if the insn an illegal operation. * If exceptions are enabled, an exception is raised. @@ -243,11 +220,7 @@ static void dec_add(DisasContext *dc) if (c) { /* c - Add carry into the result. */ - cf = tcg_temp_new_i32(); - - read_carry(dc, cf); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free_i32(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); } } return; @@ -257,21 +230,15 @@ static void dec_add(DisasContext *dc) /* Extract carry. */ cf = tcg_temp_new_i32(); if (c) { - read_carry(dc, cf); + tcg_gen_mov_i32(cf, cpu_msr_c); } else { tcg_gen_movi_i32(cf, 0); } + gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); if (dc->rd) { - TCGv_i32 ncf = tcg_temp_new_i32(); - gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - write_carry(dc, ncf); - tcg_temp_free_i32(ncf); - } else { - gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - write_carry(dc, cf); } tcg_temp_free_i32(cf); } @@ -309,11 +276,7 @@ static void dec_sub(DisasContext *dc) if (c) { /* c - Add carry into the result. */ - cf = tcg_temp_new_i32(); - - read_carry(dc, cf); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free_i32(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); } } return; @@ -324,7 +287,7 @@ static void dec_sub(DisasContext *dc) cf = tcg_temp_new_i32(); na = tcg_temp_new_i32(); if (c) { - read_carry(dc, cf); + tcg_gen_mov_i32(cf, cpu_msr_c); } else { tcg_gen_movi_i32(cf, 1); } @@ -332,16 +295,10 @@ static void dec_sub(DisasContext *dc) /* d = b + ~a + c. carry defaults to 1. */ tcg_gen_not_i32(na, cpu_R[dc->ra]); + gen_helper_carry(cpu_msr_c, na, *(dec_alu_op_b(dc)), cf); if (dc->rd) { - TCGv_i32 ncf = tcg_temp_new_i32(); - gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf); tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - write_carry(dc, ncf); - tcg_temp_free_i32(ncf); - } else { - gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf); - write_carry(dc, cf); } tcg_temp_free_i32(cf); tcg_temp_free_i32(na); @@ -429,16 +386,26 @@ static void dec_xor(DisasContext *dc) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } -static inline void msr_read(DisasContext *dc, TCGv_i32 d) +static void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_mov_i32(d, cpu_msr); + TCGv_i32 t; + + /* Replicate the cpu_msr_c boolean into the proper bit and the copy. */ + t = tcg_temp_new_i32(); + tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC); + tcg_gen_or_i32(d, cpu_msr, t); + tcg_temp_free_i32(t); } -static inline void msr_write(DisasContext *dc, TCGv_i32 v) +static void msr_write(DisasContext *dc, TCGv_i32 v) { dc->cpustate_changed = 1; - /* PVR bit is not writable, and is never set. */ - tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR); + + /* Install MSR_C. */ + tcg_gen_extract_i32(cpu_msr_c, v, 2, 1); + + /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */ + tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } static void dec_msr(DisasContext *dc) @@ -778,8 +745,8 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_i32(t0, cpu_msr, MSR_CC); - write_carry(dc, cpu_R[dc->ra]); + tcg_gen_shli_i32(t0, cpu_msr_c, 31); + tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); @@ -792,8 +759,7 @@ static void dec_bit(DisasContext *dc) /* srl. */ LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); - /* Update carry. Note that write carry only looks at the LSB. */ - write_carry(dc, cpu_R[dc->ra]); + tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { if (op == 0x41) tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); @@ -1042,7 +1008,7 @@ static void dec_load(DisasContext *dc) if (ex) { /* lwx */ /* no support for AXI exclusive so always clear C */ - write_carryi(dc, 0); + tcg_gen_movi_i32(cpu_msr_c, 0); } tcg_temp_free(addr); @@ -1093,7 +1059,7 @@ static void dec_store(DisasContext *dc) /* swx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - write_carryi(dc, 1); + tcg_gen_movi_i32(cpu_msr_c, 1); swx_skip = gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); @@ -1108,7 +1074,7 @@ static void dec_store(DisasContext *dc) mop); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); - write_carryi(dc, 0); + tcg_gen_movi_i32(cpu_msr_c, 0); tcg_temp_free_i32(tval); } @@ -1851,6 +1817,7 @@ void mb_tcg_init(void) SP(pc), SP(msr), + SP(msr_c), SP(imm), SP(iflags), SP(btaken), From patchwork Fri Aug 28 14:18:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248532 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1131272ilg; Fri, 28 Aug 2020 07:30:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy0sj/xs7ifxl1yC7IfoAOl47q+kqYqoYnhSajTwbu2/4RnaTqTXRLHzNawtZTayfFMmvJd X-Received: by 2002:a25:6d86:: with SMTP id i128mr2718619ybc.61.1598625038986; Fri, 28 Aug 2020 07:30:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625038; cv=none; d=google.com; s=arc-20160816; b=EFHqOONWDhEbnz95JvIhIjYyesepyT+u57OWtCM8JPUeeWfYo8hIq+AO4nqfeUrB+a gbZPKhCDlbiYp7Jal+bCfUcUrhutZVmdRaAkWmYu0ru1oSQsLXrHMo/oyRSjPRO4Evue /E257g0UU9E+LTCg7RZ+0Rdq/HfMh4jIf4LHEDm7JOvrTCyCpuoxGF7P35luYPhY9CQn MakZ30Qu/jiEXCIB4PzM4Q26GCLjlWBYkyFgpycm3xnOz5kgqZO1NX3KFcRRak0pdipZ bw/YaYptGQP6DjE3Ia9Fnbu6D/0LxOvMj0MUT3tn8gD6k8Wojm2DR7oduDyJF1OppVYZ QKOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qXpLGSkTUh0l6cihbLBx2yxjRuaY4I2Cb0zQBnRmSlQ=; b=LZvQE6pHJ4ZZrcTOLFgC6TLc/aP3dIbU+F0fz3jHP70WOUT7HCekJR+AU6n4iv7hJ+ 1PrfLy0YpS4g6fl+ZDXfo0GvYg6iFqihAO6Jd1X7WZUi+FN1+90w9Q6YS1cdf5w94Nq6 JjzxG3qi70isGGndmTA421kGHbo8MLjUdwkvJG/VQxMW/VaWDFQGu8Ds9Ja6AcpXy+ti rIGP2GteYT8sYEr6kCvDB76jWX6vSbIS0sbp48BKPpuPTVa+xhkEXWJKq41JgtGjM7q7 hAMEotFk0MaAxBaDoN5DPeuB1Fhv69U1yVZ03muUYc6RB93z0e5COT1/LWRkvHbqv4j6 t+5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KakpYYKH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 5si1075004yba.67.2020.08.28.07.30.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:30:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KakpYYKH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfOo-0003Kp-F8 for patch@linaro.org; Fri, 28 Aug 2020 10:30:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51240) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEg-0000g3-5g for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:10 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:46879) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEd-00057Q-C1 for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:09 -0400 Received: by mail-pf1-x444.google.com with SMTP id t185so722716pfd.13 for ; Fri, 28 Aug 2020 07:20:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qXpLGSkTUh0l6cihbLBx2yxjRuaY4I2Cb0zQBnRmSlQ=; b=KakpYYKHmGmteDL+lHFlX6zCH1S5uw1naqWSrBkmncYx9YNjZUHkJf0O6F0NaqGtq/ qpINusx8ffqduxH6T4W5/KPQVrbsDB+k42r7KEIb5zG1sRzVMsegundBYK/NpOacHdru aZVQCi1FgAK5iY45pHAIJ8tzQBNt9y1k+DDa02Pwthxj0fwT715/n8wwIJunw/onVk6F ChgwfUvNu3ZuNSWd/iIHueCF8rO5Lz3hhwmd1nWRJo7vIf4Gokg4eK7IK1BWpPnW1WeZ ZrtXKLBcF1TMKueGv/Tfprg3eWrD4yGaT3S2bhyGcEapITfAr5JeNsLBy3lO9c9urpeA Lxbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qXpLGSkTUh0l6cihbLBx2yxjRuaY4I2Cb0zQBnRmSlQ=; b=d4UAu8LphhwpAVgD8MFJq1uw9B0fVSoFQ8IkIMRhE8Smdw5H/QuRgJUPRnA1jBlZAM ImjgDuZvfrNXfrsp36HFUXBL5oxo2gH6CwIVx6Eg7p1Csf0qluHapGruYwH8Q35XNRyA /ecTUp0GJctUzeCgnKs5kcP0WPYqlxQlHRhMM/sTB0ekZ57OsCyhHFvU5408FKaaAG02 oLS9VTmieGh7KKz3jxkK1zEcRwBbNW2uT2Utclp8BauleRMHSYS7NjZTRKr880LdT3hU Kw+u3E/PvPm3a3nZJNMREDbWd6CMJ9gbWh2O7LMHq8FbFfck6SjdNrQ27RtBrtmgI8qQ lffw== X-Gm-Message-State: AOAM533bOJL1a0DMZP7Rl1yj6S8Job0ArrZr7IUxSW/yf4IiPEKoxATb AdNi76MDqs7BGFF+JxZ3IH1S3XqEwVdMFg== X-Received: by 2002:a65:524b:: with SMTP id q11mr1455199pgp.372.1598624405567; Fri, 28 Aug 2020 07:20:05 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 26/76] target/microblaze: Use DISAS_NORETURN Date: Fri, 28 Aug 2020 07:18:39 -0700 Message-Id: <20200828141929.77854-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both exceptions and gen_goto_tb do not return. Use the official DISAS_NORETURN enumerator for this case. This eliminates all use of DISAS_TB_JUMP. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0c9b4ffa5a..53ca0bfb38 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -51,7 +51,6 @@ /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ -#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; @@ -111,7 +110,7 @@ static void gen_raise_exception(DisasContext *dc, uint32_t index) gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; } static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) @@ -149,6 +148,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } + dc->is_jmp = DISAS_NORETURN; } /* @@ -1675,7 +1675,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); gen_goto_tb(dc, 0, dc->jmp_pc); - dc->is_jmp = DISAS_TB_JUMP; } else if (dc->jmp == JMP_DIRECT_CC) { TCGLabel *l1 = gen_new_label(); t_sync_flags(dc); @@ -1684,8 +1683,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) gen_goto_tb(dc, 1, dc->pc); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); - - dc->is_jmp = DISAS_TB_JUMP; } break; } @@ -1717,7 +1714,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } t_sync_flags(dc); - if (unlikely(cs->singlestep_enabled)) { + if (dc->is_jmp == DISAS_NORETURN) { + /* nothing more to generate */ + } else if (unlikely(cs->singlestep_enabled)) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { @@ -1730,16 +1729,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) case DISAS_NEXT: gen_goto_tb(dc, 1, npc); break; - default: case DISAS_JUMP: case DISAS_UPDATE: /* indicate that the hash table must be used to find the next TB */ tcg_gen_exit_tb(NULL, 0); break; - case DISAS_TB_JUMP: - /* nothing more to generate */ - break; + default: + g_assert_not_reached(); } } gen_tb_end(tb, num_insns); From patchwork Fri Aug 28 14:18:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248536 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1133195ilg; Fri, 28 Aug 2020 07:32:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwvgQdiSA3PBtsH/ht1X6aw1pw/SobEre9Nasy4ueJxZyUYDoHo/N53EhFwaYkBdsXzQpvE X-Received: by 2002:a25:5384:: with SMTP id h126mr2993608ybb.374.1598625157941; Fri, 28 Aug 2020 07:32:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625157; cv=none; d=google.com; s=arc-20160816; b=wliqwoYFWFEhf53Pr8eY9GfpaInGP/uhgPAS9CnmE+oatxBO2kpNT0Rcw95nMYMJ8v qja+xUfd0ysfC0j8QcAJStxbYdPBAu4d2mMoDMAcxS/HDRoVW6gxsa4+NAK0szlBVuqH 4G+8Sj5TD1MCZK2DdFJHee+crT9KDzrp5k1aYDxiPOEBm+ixHRGEo9+KkytBwxNnY/4f Vk70D6CphVww7XbuUxLCWo1JwlnDbIQAG5b34rhLsdvi/V4xVK6ZtiOipzmJNK+WBVgC C+ztXhuAG7CQD/eXnkWBQNstu+UfYg7vrekSCTVwqCzhc5Xfog0lZJ2Z5HKNANApS0di VXTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vRHfeWYe4t2JOdjOnGDnZu1tFFPEQawCvJ5AdLU8/XA=; b=TC8xGxsZLhHhWf34Tm8j9K6BB/2JUnyKezXLGnrwdJERBZg4jnAS+OOSJBxLYGbHZW kX6FUbRikGwcO1aYQneXwd3hQt4vGoTnOaePZZJ3N9Rr4tzpgFrqQ0K9Ri7r8iSeEMk8 mihJSnfZRdt6wu6FojoiK1u5szalI4g//QliTeR3GzL8bHB4PbPX0raPoVcgUb/sQrWp hAUAX8DzGN7QacQx02HNYrw0vwZkQv3PLGtJdaDmTtQ2mKCDtOFABXfnd3pcDPXy83/k zCov/mqH22zO7bLd66KLF5UZNKOgDYXs0gt4AiId0XFHRb0JsBnoICilZ4B5i06DPecc crtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rtuKips1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o7si993795ybg.411.2020.08.28.07.32.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:32:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rtuKips1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfQj-0006nN-CS for patch@linaro.org; Fri, 28 Aug 2020 10:32:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEg-0000iC-Vm for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:10 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:40439) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEe-00057Z-8Z for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:10 -0400 Received: by mail-pf1-x443.google.com with SMTP id c142so665981pfb.7 for ; Fri, 28 Aug 2020 07:20:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vRHfeWYe4t2JOdjOnGDnZu1tFFPEQawCvJ5AdLU8/XA=; b=rtuKips1AicN7F+yu6Abird5Dw9NJ+XNSA6KmwmrE+vIxCpsLTksrjjv9CimaqhzeY pvMxWeA1jpIFogWa+/6sRqLmtuG1lFYXKfEOP7WxpZALHz1/EQwsC/epWwflNsQRqq49 C5CeIH6nP9fAwrQmVwWQaWczXI3FCx9tl+2U2UXVhhQ5Xba88KvdaHJ/Pu1xuyMKpPNR 9GdudkB1+FgkI+Yc++LTvN9Ph5Ajq4YbMpkFbYVvDIPK53mgczvWZclLvOrn+dYAe6DJ VXCqwQY/dMiW5k9XXrs1QTBDFaaU4z/9XvpH+HgzaXhD+ma7YjKqE3k932qz0SUtl5wT hQ2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vRHfeWYe4t2JOdjOnGDnZu1tFFPEQawCvJ5AdLU8/XA=; b=V86YnEaS9bJ0tPi5NCkaNRhclxXOP1jCdVBjUUBqUb+eSajuVHtzk13Z4iEHVdFI5T 3RPRVjNiqXRoB5FMfT1cfOef2o8VGyaSvwPdh6Evm99HZ5vwgUI67yT9fOMVyzFeuV6V xwFnjjwxBImy5HdcDAkJT2dM+2PMGSuYLcWxD8n59D1CFYeJMbqyyeAbBkGhUtLp4kru 9PTTygykbHFct3reu5YqMBra/G8hFY1VjaKDz2ueSXHOE02f4CyPiQPyqNSdishLnh9n 5eTvKvHTjcJaCsE9ivrOlTtE6WgxuUekYQl/PnOzkbNxL3vWNtxMWpLWTpzioeH/Is+v CQuQ== X-Gm-Message-State: AOAM530wdGFh+pCPWJ9h7R4NFStNjVfXGrPEpqZXgOt5SL1dtw7akAZO dBVm3/8kDFuWLeLXk6vFXDT244jg2rEMyA== X-Received: by 2002:aa7:810f:: with SMTP id b15mr1424581pfi.293.1598624406682; Fri, 28 Aug 2020 07:20:06 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 27/76] target/microblaze: Check singlestep_enabled in gen_goto_tb Date: Fri, 28 Aug 2020 07:18:40 -0700 Message-Id: <20200828141929.77854-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not use goto_tb if we're single-stepping. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Edgar E. Iglesias diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 53ca0bfb38..7d5b96c38b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -140,7 +140,12 @@ static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { - if (use_goto_tb(dc, dest)) { + if (dc->singlestep_enabled) { + TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); + tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + gen_helper_raise_exception(cpu_env, tmp); + tcg_temp_free_i32(tmp); + } else if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); From patchwork Fri Aug 28 14:18:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248551 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1138316ilg; Fri, 28 Aug 2020 07:38:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwfhvBKge+Dj+T7roJj90iQOR84WTcnJSvk6sCbok7ZrPN7XNaGdDyuV5kCw6ZxgdIFGRak X-Received: by 2002:a25:1f42:: with SMTP id f63mr3072311ybf.217.1598625510529; Fri, 28 Aug 2020 07:38:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625510; cv=none; d=google.com; s=arc-20160816; b=1F6SCwnPU/AnKLxFHkFFM2gMr17P2rWIqV9uhbzC5Mrwk1rYNrv+VKvkLopJ99hrLP gOPPRyE5Xt7U+ZTiXmTZ1mrTCy9ltfl0tq08D0u8Ah9inlwFGnL3IZVcnhYcdwNGQ0tw 7sUiiwhdq+mP2z9cxhERfYQvR84w+voOVxHiorDibPMleZQJtxKSFoXgFgMLsXpDRRfM 4i+5w4Ylkdktk+PtmF1k7+G5Xx/qgn9TNa1q/OMcUU/odHNyHF/BBB+cu8F8cGDr9bxz OvX5TMiyOs47u5pfz4pnQZhkO1ZTjrbU8zl+WZGuak25v7ro7XGBccB0DGD/1fYU8zxu 679Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kv9Q2CNP0xNdIj9IWSGlA1oMnFfXI9CS46hFWNSGG9w=; b=hMkMTnHqGk7mAH6TT3gs2GePTL6f+d2XVO+An2bEVA/KAMoEgX5LSJZp1qMoOQOFG7 DwLb8vKVV6C6iivM8486eqFQThKUqiB2krTLXj2Ksr4dnhoPBbxb8hKmc7mr2NU4HFEA cw/YWKsan+swMxGvsXpUc+GV32ctahv0AqeuS6gRl2dZKNvW7J2/8Sz8Axk3c6cCUozQ hM4PWMNHmVx0HUBeO6ZcWjjzWQHbcW6pcByHwUdbVrjRspMrWQ11P2SWbRkzmknOfxZm a8SrJg6Rims97+tKiNmTc21bUsjDVjGbVhhkM3VggxTgQDHXeBQouvXzLL2XWEnDgimv iNsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ja3VBGZi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 8si1058090ybq.230.2020.08.28.07.38.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:38:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ja3VBGZi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfWP-0003SD-UD for patch@linaro.org; Fri, 28 Aug 2020 10:38:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51270) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEi-0000mO-Pu for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:12 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:37150) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEg-00057n-5B for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:12 -0400 Received: by mail-pf1-x42f.google.com with SMTP id x143so741728pfc.4 for ; Fri, 28 Aug 2020 07:20:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kv9Q2CNP0xNdIj9IWSGlA1oMnFfXI9CS46hFWNSGG9w=; b=ja3VBGZiZN6wLe3q3D2MgdvHPXkhLGcQC3GQsMQ7lPzls3KSuzNYUtNV8/mTa7ei6N yRQGnx66bzzWJEDt/weKilCSAaQ3WdgcxFTst62WxctkrH0mohfBHzgUZhMGsqd94Zxp KewEzWoJ3zm2JByuFy3SuAQR3NONKuuAsLY0ElW3nuZgWNj/XD6HSyol2iJfnEArnLBX 4W9eYBmPfHgz5leeXHXR+KaEWF7ODp2U69/AydoW62vVfi7RfhMnTWVg+m8prn7xxyOv jUZ+nvzx05UpTzwo6cM+Sbfblr/ePrUPxauOo2cesae6CBzj+M+H0QiLq8Db3s6CrY3C Q+dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kv9Q2CNP0xNdIj9IWSGlA1oMnFfXI9CS46hFWNSGG9w=; b=iUAVfahEZL1jh2dK4wcLVIphknUCcwzWA/9rJH7bUC7W1IxhgATfUOQUplCwY4KdlB FWMD0xa2Wc2g0diHxL+aZYIRg6CNj3r/EB69eyHZo+NFQT+53Fwo/6WRj9AFA0O5gHc/ F0f7W9pFHiKhPS3txxJFJPKunEF97gOPsoL5VUgv60861xdPfYsD6i8gq7ObiWeN5UDV crrBM3RIECEd1ixVP0eLcPlnXj1ovZ0LTt+VIGns71AeVwcv/N0leqEheuNTzpVuLCjv mZmJnkGDmI8r5l0V6uEZ8t81lUraPYrMISJb0p8U+mwiVd+Q/3vVz6lWEjSnRZ/Jau0Z YAxw== X-Gm-Message-State: AOAM532uTji42T0Ng2GAjkNIIgJaXI1TSCRb/rpCkDxnGQcuRqZEYVna xQQ1WK7na9aP5Zagj7g7VI07wA4Ry49oQQ== X-Received: by 2002:aa7:8c42:: with SMTP id e2mr1452633pfd.181.1598624408177; Fri, 28 Aug 2020 07:20:08 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 28/76] target/microblaze: Convert to DisasContextBase Date: Fri, 28 Aug 2020 07:18:41 -0700 Message-Id: <20200828141929.77854-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Part one of conversion to the generic translator_loop is to use the DisasContextBase and the members therein. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 104 +++++++++++++++++----------------- 1 file changed, 52 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7d5b96c38b..45b1555f85 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -67,8 +67,8 @@ static TCGv_i32 cpu_res_val; /* This is the state at translation time. */ typedef struct DisasContext { + DisasContextBase base; MicroBlazeCPU *cpu; - uint32_t pc; /* Decoder. */ int type_b; @@ -81,7 +81,6 @@ typedef struct DisasContext { unsigned int delayed_branch; unsigned int tb_flags, synced_flags; /* tb dependent flags. */ unsigned int clear_imm; - int is_jmp; #define JMP_NOJMP 0 #define JMP_DIRECT 1 @@ -91,8 +90,6 @@ typedef struct DisasContext { uint32_t jmp_pc; int abort_at_next_insn; - struct TranslationBlock *tb; - int singlestep_enabled; } DisasContext; static inline void t_sync_flags(DisasContext *dc) @@ -110,13 +107,13 @@ static void gen_raise_exception(DisasContext *dc, uint32_t index) gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; } static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) { t_sync_flags(dc); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_raise_exception(dc, index); } @@ -132,7 +129,7 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); + return (dc->base.pc_first & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); #else return true; #endif @@ -140,20 +137,20 @@ static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { - if (dc->singlestep_enabled) { + if (dc->base.singlestep_enabled) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i32(cpu_pc, dest); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); } else if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb(dc->tb, n); + tcg_gen_exit_tb(dc->base.tb, n); } else { tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; } /* @@ -468,8 +465,8 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); - dc->is_jmp = DISAS_UPDATE; + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); + dc->base.is_jmp = DISAS_UPDATE; return; } @@ -546,7 +543,7 @@ static void dec_msr(DisasContext *dc) switch (sr) { case SR_PC: - tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); break; case SR_MSR: msr_read(dc, cpu_R[dc->rd]); @@ -813,7 +810,7 @@ static void dec_bit(DisasContext *dc) break; default: cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", - dc->pc, op, dc->rd, dc->ra, dc->rb); + (uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->rb); break; } } @@ -994,7 +991,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); tcg_temp_free_i32(t0); @@ -1114,7 +1111,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1201,12 +1198,12 @@ static void dec_bcc(DisasContext *dc) if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - tcg_gen_movi_i32(cpu_btarget, dc->pc + offset); + tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset); dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->pc + offset; + dc->jmp_pc = dc->base.pc_next + offset; } else { dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); } eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } @@ -1250,7 +1247,7 @@ static void dec_br(DisasContext *dc) +offsetof(CPUState, halted)); tcg_temp_free_i32(tmp_1); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); gen_raise_exception(dc, EXCP_HLT); return; @@ -1270,7 +1267,7 @@ static void dec_br(DisasContext *dc) dec_setup_dslot(dc); } if (link && dc->rd) - tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); dc->jmp = JMP_INDIRECT; if (abs) { @@ -1291,10 +1288,10 @@ static void dec_br(DisasContext *dc) } else { if (dec_alu_op_b_is_small_imm(dc)) { dc->jmp = JMP_DIRECT; - dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); + dc->jmp_pc = dc->base.pc_next + (int32_t)((int16_t)dc->imm); } else { tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); } } } @@ -1459,7 +1456,8 @@ static void dec_fpu(DisasContext *dc) qemu_log_mask(LOG_UNIMP, "unimplemented fcmp fpu_insn=%x pc=%x" " opc=%x\n", - fpu_insn, dc->pc, dc->opcode); + fpu_insn, (uint32_t)dc->base.pc_next, + dc->opcode); dc->abort_at_next_insn = 1; break; } @@ -1489,7 +1487,7 @@ static void dec_fpu(DisasContext *dc) default: qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" " opc=%x\n", - fpu_insn, dc->pc, dc->opcode); + fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode); dc->abort_at_next_insn = 1; break; } @@ -1500,7 +1498,8 @@ static void dec_null(DisasContext *dc) if (trap_illegal(dc, true)) { return; } - qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode); + qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", + (uint32_t)dc->base.pc_next, dc->opcode); dc->abort_at_next_insn = 1; } @@ -1610,19 +1609,20 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) pc_start = tb->pc; dc->cpu = cpu; - dc->tb = tb; org_flags = dc->synced_flags = dc->tb_flags = tb->flags; - dc->is_jmp = DISAS_NEXT; dc->jmp = 0; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); if (dc->delayed_branch) { dc->jmp = JMP_INDIRECT; } - dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->base.pc_first = pc_start; + dc->base.pc_next = pc_start; + dc->base.singlestep_enabled = cs->singlestep_enabled; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; + dc->base.is_jmp = DISAS_NEXT; + dc->base.tb = tb; if (pc_start & 3) { cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); @@ -1634,31 +1634,31 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) gen_tb_start(tb); do { - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->base.pc_next); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - dc->pc += 4; + dc->base.pc_next += 4; break; } /* Pretty disas. */ - LOG_DIS("%8.8x:\t", dc->pc); + LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next); if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } dc->clear_imm = 1; - decode(dc, cpu_ldl_code(env, dc->pc)); + decode(dc, cpu_ldl_code(env, dc->base.pc_next)); if (dc->clear_imm) dc->tb_flags &= ~IMM_FLAG; - dc->pc += 4; + dc->base.pc_next += 4; if (dc->delayed_branch) { dc->delayed_branch--; @@ -1673,10 +1673,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) dc->tb_flags &= ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp == JMP_INDIRECT) { - TCGv_i32 tmp_pc = tcg_const_i32(dc->pc); + TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); eval_cond_jmp(dc, cpu_btarget, tmp_pc); tcg_temp_free_i32(tmp_pc); - dc->is_jmp = DISAS_JUMP; + dc->base.is_jmp = DISAS_JUMP; } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); gen_goto_tb(dc, 0, dc->jmp_pc); @@ -1685,26 +1685,26 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) t_sync_flags(dc); /* Conditional jmp. */ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); - gen_goto_tb(dc, 1, dc->pc); + gen_goto_tb(dc, 1, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); } break; } } - if (cs->singlestep_enabled) { + if (dc->base.singlestep_enabled) { break; } - } while (!dc->is_jmp && !dc->cpustate_changed + } while (!dc->base.is_jmp && !dc->cpustate_changed && !tcg_op_buf_full() && !singlestep - && (dc->pc - page_start < TARGET_PAGE_SIZE) + && (dc->base.pc_next - page_start < TARGET_PAGE_SIZE) && num_insns < max_insns); - npc = dc->pc; + npc = dc->base.pc_next; if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { - dc->is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_UPDATE; tcg_gen_movi_i32(cpu_pc, npc); sync_jmpstate(dc); } else @@ -1712,25 +1712,25 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } /* Force an update if the per-tb cpu state has changed. */ - if (dc->is_jmp == DISAS_NEXT + if (dc->base.is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { - dc->is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_UPDATE; tcg_gen_movi_i32(cpu_pc, npc); } t_sync_flags(dc); - if (dc->is_jmp == DISAS_NORETURN) { + if (dc->base.is_jmp == DISAS_NORETURN) { /* nothing more to generate */ } else if (unlikely(cs->singlestep_enabled)) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); - if (dc->is_jmp != DISAS_JUMP) { + if (dc->base.is_jmp != DISAS_JUMP) { tcg_gen_movi_i32(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); } else { - switch(dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, npc); break; @@ -1746,7 +1746,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } gen_tb_end(tb, num_insns); - tb->size = dc->pc - pc_start; + tb->size = dc->base.pc_next - pc_start; tb->icount = num_insns; #ifdef DEBUG_DISAS @@ -1755,7 +1755,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) && qemu_log_in_addr_range(pc_start)) { FILE *logfile = qemu_log_lock(); qemu_log("--------------\n"); - log_target_disas(cs, pc_start, dc->pc - pc_start); + log_target_disas(cs, pc_start, dc->base.pc_next - pc_start); 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Part two of conversion to the generic translator_loop. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 289 ++++++++++++++++++---------------- 1 file changed, 149 insertions(+), 140 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 45b1555f85..6a9710d76d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1595,172 +1595,181 @@ static inline void decode(DisasContext *dc, uint32_t ir) } } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) +static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { - CPUMBState *env = cs->env_ptr; - MicroBlazeCPU *cpu = env_archcpu(env); - uint32_t pc_start; - struct DisasContext ctx; - struct DisasContext *dc = &ctx; - uint32_t page_start, org_flags; - uint32_t npc; - int num_insns; + DisasContext *dc = container_of(dcb, DisasContext, base); + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + int bound; - pc_start = tb->pc; dc->cpu = cpu; - org_flags = dc->synced_flags = dc->tb_flags = tb->flags; - - dc->jmp = 0; + dc->synced_flags = dc->tb_flags = dc->base.tb->flags; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); - if (dc->delayed_branch) { - dc->jmp = JMP_INDIRECT; - } - dc->base.pc_first = pc_start; - dc->base.pc_next = pc_start; - dc->base.singlestep_enabled = cs->singlestep_enabled; + dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; - dc->base.is_jmp = DISAS_NEXT; - dc->base.tb = tb; - if (pc_start & 3) { - cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); + bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + dc->base.max_insns = MIN(dc->base.max_insns, bound); +} + +static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs) +{ +} + +static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) +{ + tcg_gen_insn_start(dcb->pc_next); +} + +static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcb, DisasContext, base); + + gen_raise_exception_sync(dc, EXCP_DEBUG); + + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + dc->base.pc_next += 4; + return true; +} + +static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc = container_of(dcb, DisasContext, base); + CPUMBState *env = cs->env_ptr; + + /* TODO: This should raise an exception, not terminate qemu. */ + if (dc->base.pc_next & 3) { + cpu_abort(cs, "Microblaze: unaligned PC=%x\n", + (uint32_t)dc->base.pc_next); } - page_start = pc_start & TARGET_PAGE_MASK; - num_insns = 0; + dc->clear_imm = 1; + decode(dc, cpu_ldl_code(env, dc->base.pc_next)); + if (dc->clear_imm) { + dc->tb_flags &= ~IMM_FLAG; + } + dc->base.pc_next += 4; - gen_tb_start(tb); - do - { - tcg_gen_insn_start(dc->base.pc_next); - num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { - gen_raise_exception_sync(dc, EXCP_DEBUG); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next += 4; - break; + if (dc->delayed_branch && --dc->delayed_branch == 0) { + if (dc->tb_flags & DRTI_FLAG) { + do_rti(dc); } - - /* Pretty disas. */ - LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next); - - if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); + if (dc->tb_flags & DRTB_FLAG) { + do_rtb(dc); } - - dc->clear_imm = 1; - decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) - dc->tb_flags &= ~IMM_FLAG; - dc->base.pc_next += 4; - - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - if (dc->tb_flags & DRTI_FLAG) - do_rti(dc); - if (dc->tb_flags & DRTB_FLAG) - do_rtb(dc); - if (dc->tb_flags & DRTE_FLAG) - do_rte(dc); - /* Clear the delay slot flag. */ - dc->tb_flags &= ~D_FLAG; - /* If it is a direct jump, try direct chaining. */ - if (dc->jmp == JMP_INDIRECT) { - TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); - dc->base.is_jmp = DISAS_JUMP; - } else if (dc->jmp == JMP_DIRECT) { - t_sync_flags(dc); - gen_goto_tb(dc, 0, dc->jmp_pc); - } else if (dc->jmp == JMP_DIRECT_CC) { - TCGLabel *l1 = gen_new_label(); - t_sync_flags(dc); - /* Conditional jmp. */ - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); - gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); - gen_goto_tb(dc, 0, dc->jmp_pc); - } - break; - } + if (dc->tb_flags & DRTE_FLAG) { + do_rte(dc); } - if (dc->base.singlestep_enabled) { - break; - } - } while (!dc->base.is_jmp && !dc->cpustate_changed - && !tcg_op_buf_full() - && !singlestep - && (dc->base.pc_next - page_start < TARGET_PAGE_SIZE) - && num_insns < max_insns); - - npc = dc->base.pc_next; - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->tb_flags & D_FLAG) { - dc->base.is_jmp = DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); - sync_jmpstate(dc); - } else - npc = dc->jmp_pc; + /* Clear the delay slot flag. */ + dc->tb_flags &= ~D_FLAG; + dc->base.is_jmp = DISAS_JUMP; } - /* Force an update if the per-tb cpu state has changed. */ - if (dc->base.is_jmp == DISAS_NEXT - && (dc->cpustate_changed || org_flags != dc->tb_flags)) { + /* Force an exit if the per-tb cpu state has changed. */ + if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) { dc->base.is_jmp = DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); } - t_sync_flags(dc); +} + +static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc = container_of(dcb, DisasContext, base); + + assert(!dc->abort_at_next_insn); if (dc->base.is_jmp == DISAS_NORETURN) { - /* nothing more to generate */ - } else if (unlikely(cs->singlestep_enabled)) { - TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); - - if (dc->base.is_jmp != DISAS_JUMP) { - tcg_gen_movi_i32(cpu_pc, npc); - } - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - gen_goto_tb(dc, 1, npc); - break; - case DISAS_JUMP: - case DISAS_UPDATE: - /* indicate that the hash table must be used - to find the next TB */ - tcg_gen_exit_tb(NULL, 0); - break; - default: - g_assert_not_reached(); - } + /* We have already exited the TB. */ + return; } - gen_tb_end(tb, num_insns); - tb->size = dc->base.pc_next - pc_start; - tb->icount = num_insns; + t_sync_flags(dc); + if (dc->tb_flags & D_FLAG) { + sync_jmpstate(dc); + dc->jmp = JMP_NOJMP; + } + switch (dc->base.is_jmp) { + case DISAS_TOO_MANY: + assert(dc->jmp == JMP_NOJMP); + gen_goto_tb(dc, 0, dc->base.pc_next); + return; + + case DISAS_UPDATE: + assert(dc->jmp == JMP_NOJMP); + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; + + case DISAS_JUMP: + switch (dc->jmp) { + case JMP_INDIRECT: + { + TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); + eval_cond_jmp(dc, cpu_btarget, tmp_pc); + tcg_temp_free_i32(tmp_pc); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + } + return; + + case JMP_DIRECT_CC: + { + TCGLabel *l1 = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + gen_goto_tb(dc, 1, dc->base.pc_next); + gen_set_label(l1); + } + /* fall through */ + + case JMP_DIRECT: + gen_goto_tb(dc, 0, dc->jmp_pc); + return; + } + /* fall through */ + + default: + g_assert_not_reached(); + } +} + +static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) +{ #ifdef DEBUG_DISAS #if !SIM_COMPAT - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - FILE *logfile = qemu_log_lock(); - qemu_log("--------------\n"); - log_target_disas(cs, pc_start, dc->base.pc_next - pc_start); - qemu_log_unlock(logfile); - } + qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); + log_target_disas(cs, dcb->pc_first, dcb->tb->size); #endif #endif - assert(!dc->abort_at_next_insn); +} + +static const TranslatorOps mb_tr_ops = { + .init_disas_context = mb_tr_init_disas_context, + .tb_start = mb_tr_tb_start, + .insn_start = mb_tr_insn_start, + .breakpoint_check = mb_tr_breakpoint_check, + .translate_insn = mb_tr_translate_insn, + .tb_stop = mb_tr_tb_stop, + .disas_log = mb_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns) +{ + DisasContext dc; + translator_loop(&mb_tr_ops, &dc.base, cpu, tb, max_insns); } void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) From patchwork Fri Aug 28 14:18:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248558 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1140700ilg; Fri, 28 Aug 2020 07:41:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwebO7GcwPaaot37NKzmKA28eDWjenj3wx2tcC8M+KayrUUBPEFcbzkuY+JvKJEvGpFbwL6 X-Received: by 2002:a25:db49:: with SMTP id g70mr2477363ybf.155.1598625691933; Fri, 28 Aug 2020 07:41:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625691; cv=none; d=google.com; s=arc-20160816; b=O0JP+umHalo93K9Np/5XRi3kriOimhmUVOUEratpGb0VWJY1CLMtDZjRGo4hJzN6tF G5ciLXKyDWcr0THu0fOwP3BkcdZleJjNzbYsuVulX5jrD1AhD9xEAtbUaslqh5APfMBY 01Fh0tHYCng+yb+5dTfOglxaet1sAPca0bTOlAgOtW0I3zeE/7PKa0iB8N3iQi5ZnOln HThQ+VwO5wxbBHc7ybGytW38ZqVXQ71EpJUaZbyLuqCuadcsgkbjpxe/iM8aYXxYE4hn n5PGBVUay/+P7w0LrBlkDu1xQrVZh4f5IZ5E9o/UN1wQVyY+0ykCoJdGQpCBaa7A7+N/ 6dzA== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6a9710d76d..a90e56a17f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -34,10 +34,9 @@ #include "exec/log.h" -#define SIM_COMPAT 0 #define DISAS_GNU 1 #define DISAS_MB 1 -#if DISAS_MB && !SIM_COMPAT +#if DISAS_MB # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) #else # define LOG_DIS(...) do { } while (0) @@ -1749,11 +1748,9 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) { #ifdef DEBUG_DISAS -#if !SIM_COMPAT qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); log_target_disas(cs, dcb->pc_first, dcb->tb->size); #endif -#endif } static const TranslatorOps mb_tr_ops = { From patchwork Fri Aug 28 14:18:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248526 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1128663ilg; Fri, 28 Aug 2020 07:27:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxf5l6P7Pj09p+ZN5wL295kLedf7UmgbyqglkNpWm03StmYfan0j7+4j/fubh8yToXSMshE X-Received: by 2002:a25:8b07:: with SMTP id i7mr2858827ybl.39.1598624834812; Fri, 28 Aug 2020 07:27:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624834; cv=none; d=google.com; s=arc-20160816; b=qD7ZeaYe0zgxJFqe+BR6dFuUz7odP1AKImoQFtDkFDhSkQzIDba/u4ZET9OGOR8bym v5t7oMD8R/4Fvf6KinDt0WFEad+B/bf2+NupU0komqVJktxWSVqNkc5OhSIccUjQqiPk 3j76ydXuOi29H7gVdow5viv571pgX7gkooE6kX4aAkDovT829cMrsJQlN743LWyKyIol GrVqU7rerUVBcR5kFUr6lOHJZAjkzIiPQJhAV9GCjMVddmrA7QRSGmbWO+PtY1Iu0/KC rzmIdffSLiW38BZug+0s2WT53Bwllr4PxbIzmpEY1PhIPD5XhtuTEPng+effGwPQ1YAY +OMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Vc1/n0PAMq2ruFSCbPStrg/chGbNzuC4FGRX/oeXBs0=; b=Y3prRUVKCJsD4doAlBBIBvAM70hFJBNFWvfEPqOQpYDbYy2JNM9Lr/lHfsxv6NGOdJ +d2xnCsBzhRdyZpTsjWGmxfsaZ8hKuz6Hg7ehVH6oIYHNNPROXOHy7S+1OYp9U3jsjkt CQWc06mQU+Mh8UqFqP8dXywoa6CPIyo8u8IaWWCcS+sMSPOtkXqTSDaQBwnZVMUWeRj0 qpDFVJe3mFaVg3vfYEbDpwDL0UgAb41dHiwH95yf/f9rn3YhGiKJDbDC2PNtGordrxno 8e0HmEVWHyA0z7QZ9K4FJWHAEF1xVtd/aH7thnH7rg7RowgvZH//TVX2PeCzMPk3wazJ YnSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S6NGo0a0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is never used. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 1 - 1 file changed, 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a90e56a17f..6757720776 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -34,7 +34,6 @@ #include "exec/log.h" -#define DISAS_GNU 1 #define DISAS_MB 1 #if DISAS_MB # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) From patchwork Fri Aug 28 14:18:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248538 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1133947ilg; Fri, 28 Aug 2020 07:33:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyg0ttOTCrsIMuggb+QniCzUtliLETnH6ICXXl5LJaFH3r+rqujOhDxn0NbXfe17IXIN2it X-Received: by 2002:a25:a143:: with SMTP id z61mr2921398ybh.468.1598625209078; Fri, 28 Aug 2020 07:33:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625209; cv=none; d=google.com; s=arc-20160816; b=JfRnD8o5E1zXR9deemdQD0Bd/02WWliSC8XZJXtQOe0BIOxQRAglSyN+bi1IVEMUmv 8nT4aMPmQBBdOIyVbWJVgJ9aZYFYQiWRNcj2KFfheOX9Dh7v9aehvQKOQag+M0eIjmpI YikXfLGdsUeP6WlasmQneY13oEwLM1A5HYF9oNVhBYXk8dCC+HJXqIAAAqM3m0I/OcuD A+v+J/bDSYlm7dKmnxEzlFE/P5rqOK8HHEqYEleB1vhsjRFoCtA9wa4LPTnYXMtx2sd2 XWQ9txLY1vT5LyA7lJipagSKiDD2ujIokqf2ZYVf40ZF7iIdO1vhtjntPpkkGtXssBP3 G3DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b/4g1T+WE9RDnuv3IAKyPSAVgdbvulTxnio8bcXmxqI=; b=BTUnHs/wUxbZzGjaTGp0psn3oet/WGiV+gOtqbjR9FfV8Ob59Sef9ZQ+geZsD6mBDm GlejpCvcaoIQVuNTCVIYtxqtexm5q3PA+kQl7YXwcYJJoLGpHlZ5M2rJcjWBheClGz0v k2I6PcpMnXBM8DpLW6k4l5x36Umot8IJSl9yWHDhqARg6yWNAQkbodFQ1WzAR9tq0oas Qhupd6wF029NEiLSArTAJiO4mnvapOl79U/p0PYMXPaO/hBFqYE06Tv1+nRh9mWy9MPN 97yjxQiaeeRwIcyKQaQVbzdDmqnMx3LUfPnH1AuN9EqOM8wSxgnivT+PSBqFsJxmBuwE 5PAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hMyYKG6i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s91si933998ybi.418.2020.08.28.07.33.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:33:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hMyYKG6i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfRY-00084R-CQ for patch@linaro.org; Fri, 28 Aug 2020 10:33:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEr-00011t-Mg for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:21 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:37203) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEk-0005A7-Tf for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:21 -0400 Received: by mail-pl1-x644.google.com with SMTP id c15so532455plq.4 for ; Fri, 28 Aug 2020 07:20:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b/4g1T+WE9RDnuv3IAKyPSAVgdbvulTxnio8bcXmxqI=; b=hMyYKG6iT0h/SFFlVYPd9MK/4bGQ8pub5C8qdGVH5s5Mo3MwXa6BIfcS9qTpt0+rdM 3id2GW0GADLz0+KI26LMWUFraqWSeit4Mfg3qymldd2kUyRnNfHUrx52TcKgqMqN2XIB q6rLQlglQEU1XOWPB70N90+6CDTF+wFIfVdmpODFwrPe7WcfGALEACr2nniBUgBzXGrz oQ7Kn2W8GoDzoWmDn76vWGpZ4hb8Ijddw7iVBNZc4eWR0AvaNBhcL4j6oL9YYeBGIkTG TilM5EfjgRtFcUu6AQ8xB0ignvvnTaz6IpUqDFITVJhoneXrx5a4RR0RvX9hnz/SfnIS Iglw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b/4g1T+WE9RDnuv3IAKyPSAVgdbvulTxnio8bcXmxqI=; b=lRAT3W5QwSdVtU8HMetuP2eIzuzF7Y+SUIRd5gPyebxkNEL+d9wipjFKuVRlsgbME6 UH/loZXgmcnjMR3h+07S9kpuPUiRPawhcYbUoiq4szzSURl43WGktDWUA7hGgos6HBDy xuF3EDaP7rToa4TtErj1EF6q3O+nojK2A7j377yI9BcSt85I3m4MYjuOMXwEw3xEtp2O zc71RoSjajv3MZpHDXW4KPutXV2L8csLF3BFmNBSgNytcSZpMXVyRkccQ/rbIQSVv/Ph a5be4tZNlwp1DfD2byKd+VOaCgx7pDXqLJNjT9jVeGeD99nYeRklvHdPJV739MP+6IjF wlNg== X-Gm-Message-State: AOAM530CbcOsSrQuYhoJl+iNaievwcuAzlQ5nsWwxkqfZMYpwDbP8gF8 tGMLuMVPNIG4Ff/Jp634MYmDbBrIPtvuMA== X-Received: by 2002:a17:902:76cb:: with SMTP id j11mr1477125plt.29.1598624413102; Fri, 28 Aug 2020 07:20:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 32/76] target/microblaze: Remove empty D macros Date: Fri, 28 Aug 2020 07:18:45 -0700 Message-Id: <20200828141929.77854-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is never used in op_helper.c and translate.c. There are two trivial uses in helper.c which can be improved by always logging MMU_EXCP to CPU_LOG_INT. Signed-off-by: Richard Henderson --- target/microblaze/helper.c | 11 ++++------- target/microblaze/op_helper.c | 2 -- target/microblaze/translate.c | 2 -- 3 files changed, 4 insertions(+), 11 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 9a95456401..f8e2ca12a9 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,8 +24,6 @@ #include "qemu/host-utils.h" #include "exec/log.h" -#define D(x) - #if defined(CONFIG_USER_ONLY) void mb_cpu_do_interrupt(CPUState *cs) @@ -155,10 +153,13 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] = env->pc; + qemu_log_mask(CPU_LOG_INT, + "MMU exception at pc=%x iflags=%x ear=%" PRIx64 "\n", + env->pc, env->iflags, env->ear); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); env->esr |= 1 << 12 ; env->btr = env->btarget; @@ -166,14 +167,10 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[17] -= 4; /* was the branch immprefixed?. */ if (env->bimm) { - qemu_log_mask(CPU_LOG_INT, - "bimm exception at pc=%x iflags=%x\n", - env->pc, env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } } else if (env->iflags & IMM_FLAG) { - D(qemu_log("IMM_FLAG set at exception\n")); env->regs[17] -= 4; } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index d79202c3f8..decdca0fd8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -26,8 +26,6 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" -#define D(x) - void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { int test = ctrl & STREAM_TEST; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6757720776..860859324a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -41,8 +41,6 @@ # define LOG_DIS(...) do { } while (0) #endif -#define D(x) - #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) From patchwork Fri Aug 28 14:18:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248530 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1130035ilg; Fri, 28 Aug 2020 07:29:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxq6UKkdAqYB951XjmST/ZmHwHrNuTOs6ZfcK/5/7UGAJSswogY8w7YEPX70md+xXdKvZZ/ X-Received: by 2002:a25:6e54:: with SMTP id j81mr2733697ybc.194.1598624941850; Fri, 28 Aug 2020 07:29:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624941; cv=none; d=google.com; s=arc-20160816; b=oG27vGnxXBe6c4/e8wpPfw7S9pWg1GQwBv3dGt8JRKmr7p4jpwzTm4qI0VnLkWeTKS sBLBofvH8kKwailAStofG8wVLDVNsvgcEJjQ/WtEGEXMTSWuvveEWaEA3cNQ3sUnx80W jkFzksenUToQqwN2goVFcBUBi8R+ztIUdKTe8jvUtAl+oF6NZpaBi6DvqXH96/YRCswl ZN/JncIBQM6jdSYbtT5L5JLi2zgtVHIwxBSJtcFge37fROXd8DgnfisQlsenkc78dSrR r4tf8GwkzBg0HeWr3vCahCuFEA+3a7rnlbWXEzvo+6wDThyUohP74iO+ne+trtRW/gjn gpDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KOp/91/a2BIVMe1u/E83L0OjODEkWinQdZcmcUxF1f8=; b=JIaBuuA7LQNisQeyzwYY+WGF9Tw9WMram1LzEPhZvlZIkba2zVSTxmlgXAv5zRFWG4 vAKxCFXPWzyv9MVc9Q/DFtg34986559J3wkhz988KCV2JRmzwzdolGaCCDQIY8gmU0Kw m+jCCRh1/hBRCpnuDc2SWgeAvQw5svxI45iyCN5Z/5PrRRvV4EWISXnNHuY6pRHjJJ0H /pFc7YQOa/Krmb+3Q8ns10gIddgcojIN5e7RGE33PcB2RU+No9x1jCGrvqbI5CiH1fjX uxUEL/xuB+I2KLEq/lxZUCzs88agFUt8cCwhil7m+JCZrn6v29Ww2I2aEP/EAgUYESDe CD8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ksnZScMT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also remove the related defines, DISAS_MB and DEBUG_DISAS. Rely on print_insn_microblaze. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 78 +---------------------------------- 1 file changed, 1 insertion(+), 77 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 860859324a..133ec24870 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -33,14 +33,6 @@ #include "trace-tcg.h" #include "exec/log.h" - -#define DISAS_MB 1 -#if DISAS_MB -# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) -#else -# define LOG_DIS(...) do { } while (0) -#endif - #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) @@ -205,10 +197,6 @@ static void dec_add(DisasContext *dc) k = dc->opcode & 4; c = dc->opcode & 2; - LOG_DIS("add%s%s%s r%d r%d r%d\n", - dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "", - dc->rd, dc->ra, dc->rb); - /* Take care of the easy cases first. */ if (k) { /* k - keep carry, no need to update MSR. */ @@ -252,7 +240,6 @@ static void dec_sub(DisasContext *dc) cmp = (dc->imm & 1) && (!dc->type_b) && k; if (cmp) { - LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir); if (dc->rd) { if (u) gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); @@ -262,9 +249,6 @@ static void dec_sub(DisasContext *dc) return; } - LOG_DIS("sub%s%s r%d, r%d r%d\n", - k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb); - /* Take care of the easy cases first. */ if (k) { /* k - keep carry, no need to update MSR. */ @@ -314,19 +298,16 @@ static void dec_pattern(DisasContext *dc) switch (mode) { case 0: /* pcmpbf. */ - LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 2: - LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); } break; case 3: - LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); @@ -349,7 +330,6 @@ static void dec_and(DisasContext *dc) } not = dc->opcode & (1 << 1); - LOG_DIS("and%s\n", not ? "n" : ""); if (!dc->rd) return; @@ -367,7 +347,6 @@ static void dec_or(DisasContext *dc) return; } - LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm); if (dc->rd) tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } @@ -379,7 +358,6 @@ static void dec_xor(DisasContext *dc) return; } - LOG_DIS("xor r%d\n", dc->rd); if (dc->rd) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } @@ -433,9 +411,6 @@ static void dec_msr(DisasContext *dc) if (clrset) { bool clr = extract32(dc->ir, 16, 1); - LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", - dc->rd, dc->imm); - if (!dc->cpu->cfg.use_msr_instr) { /* nop??? */ return; @@ -478,7 +453,6 @@ static void dec_msr(DisasContext *dc) sr &= 7; tmp_sr = tcg_const_i32(sr); - LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); if (to) { gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); } else { @@ -491,7 +465,6 @@ static void dec_msr(DisasContext *dc) #endif if (to) { - LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); switch (sr) { case SR_PC: break; @@ -535,8 +508,6 @@ static void dec_msr(DisasContext *dc) break; } } else { - LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); - switch (sr) { case SR_PC: tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); @@ -609,7 +580,6 @@ static void dec_mul(DisasContext *dc) subcode = dc->imm & 3; if (dc->type_b) { - LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); return; } @@ -622,21 +592,17 @@ static void dec_mul(DisasContext *dc) tmp = tcg_temp_new_i32(); switch (subcode) { case 0: - LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 1: - LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 2: - LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 3: - LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; default: @@ -652,7 +618,6 @@ static void dec_div(DisasContext *dc) unsigned int u; u = dc->imm & 2; - LOG_DIS("div\n"); if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { return; @@ -688,10 +653,6 @@ static void dec_barrel(DisasContext *dc) imm_w = extract32(dc->imm, 6, 5); imm_s = extract32(dc->imm, 0, 5); - LOG_DIS("bs%s%s%s r%d r%d r%d\n", - e ? "e" : "", - s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); - if (e) { if (imm_w + imm_s > 32 || imm_w == 0) { /* These inputs have an undefined behavior. */ @@ -742,7 +703,6 @@ static void dec_bit(DisasContext *dc) /* src. */ t0 = tcg_temp_new_i32(); - LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); tcg_gen_shli_i32(t0, cpu_msr_c, 31); tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { @@ -755,8 +715,6 @@ static void dec_bit(DisasContext *dc) case 0x1: case 0x41: /* srl. */ - LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { if (op == 0x41) @@ -766,11 +724,9 @@ static void dec_bit(DisasContext *dc) } break; case 0x60: - LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra); tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x61: - LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra); tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x64: @@ -778,12 +734,10 @@ static void dec_bit(DisasContext *dc) case 0x74: case 0x76: /* wdc. */ - LOG_DIS("wdc r%d\n", dc->ra); trap_userspace(dc, true); break; case 0x68: /* wic. */ - LOG_DIS("wic r%d\n", dc->ra); trap_userspace(dc, true); break; case 0xe0: @@ -796,12 +750,10 @@ static void dec_bit(DisasContext *dc) break; case 0x1e0: /* swapb */ - LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra); tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x1e2: /*swaph */ - LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra); tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); break; default: @@ -824,7 +776,6 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { - LOG_DIS("imm %x\n", dc->imm << 16); tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; @@ -928,10 +879,6 @@ static void dec_load(DisasContext *dc) return; } - LOG_DIS("l%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", - ex ? "x" : "", - ea ? "ea" : ""); - t_sync_flags(dc); addr = tcg_temp_new(); compute_ldst_addr(dc, ea, addr); @@ -1039,9 +986,6 @@ static void dec_store(DisasContext *dc) trap_userspace(dc, ea); - LOG_DIS("s%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", - ex ? "x" : "", - ea ? "ea" : ""); t_sync_flags(dc); /* If we get a fault on a dslot, the jmpstate better be in sync. */ sync_jmpstate(dc); @@ -1184,7 +1128,6 @@ static void dec_bcc(DisasContext *dc) cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); - LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm); dc->delayed_branch = 1; if (dslot) { @@ -1217,8 +1160,6 @@ static void dec_br(DisasContext *dc) if (mbar == 2 && dc->imm == 4) { uint16_t mbar_imm = dc->rd; - LOG_DIS("mbar %d\n", mbar_imm); - /* Data access memory barrier. */ if ((mbar_imm & 2) == 0) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); @@ -1228,8 +1169,6 @@ static void dec_br(DisasContext *dc) if (mbar_imm & 16) { TCGv_i32 tmp_1; - LOG_DIS("sleep\n"); - if (trap_userspace(dc, true)) { /* Sleep is a privileged instruction. */ return; @@ -1253,11 +1192,6 @@ static void dec_br(DisasContext *dc) return; } - LOG_DIS("br%s%s%s%s imm=%x\n", - abs ? "a" : "", link ? "l" : "", - dc->type_b ? "i" : "", dslot ? "d" : "", - dc->imm); - dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); @@ -1363,16 +1297,12 @@ static void dec_rts(DisasContext *dc) dec_setup_dslot(dc); if (i_bit) { - LOG_DIS("rtid ir=%x\n", dc->ir); dc->tb_flags |= DRTI_FLAG; } else if (b_bit) { - LOG_DIS("rtbd ir=%x\n", dc->ir); dc->tb_flags |= DRTB_FLAG; } else if (e_bit) { - LOG_DIS("rted ir=%x\n", dc->ir); dc->tb_flags |= DRTE_FLAG; - } else - LOG_DIS("rts ir=%x\n", dc->ir); + } dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(cpu_btaken, 1); @@ -1505,9 +1435,6 @@ static void dec_stream(DisasContext *dc) TCGv_i32 t_id, t_ctrl; int ctrl; - LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put", - dc->type_b ? "" : "d", dc->imm); - if (trap_userspace(dc, true)) { return; } @@ -1565,7 +1492,6 @@ static inline void decode(DisasContext *dc, uint32_t ir) int i; dc->ir = ir; - LOG_DIS("%8.8x\t", dc->ir); if (ir == 0) { trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); @@ -1744,10 +1670,8 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) { -#ifdef DEBUG_DISAS qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); log_target_disas(cs, dcb->pc_first, dcb->tb->size); -#endif } static const TranslatorOps mb_tr_ops = { From patchwork Fri Aug 28 14:18:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248533 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1131448ilg; Fri, 28 Aug 2020 07:30:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMLjk+r7Oqa/HMaPCnj1zuGz4hw3Y8bECuwy1qZ2JRfn0oXNM/hlXxgN/jnlVnATpRBThc X-Received: by 2002:a25:7341:: with SMTP id o62mr3007853ybc.305.1598625050774; Fri, 28 Aug 2020 07:30:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625050; cv=none; d=google.com; s=arc-20160816; b=lxSR/n35r6bm/WB4Ztqqt591STzTeXgAxQKF+dnzlwfy1rSVH4SZzj46ig6N6NaSCY ejzp7sz4zdx0lkPJFhtYhAfh7wPrBlqdNCcR7jCJgDwbD4WEScqet2q6muXvfHFXb+Zn qW+vkVRgCmYlvWsdM5s9dFUcJ19b6P6idsgoj6cTIj3/tvFDG7IGP+F9iO/8RRaOUTHr WqbXBmNiDfm5G3EYj2/15O4JDVGffD5pqGUpDruNS8NM0igF8IWfj+5xgEoAKekggUob vfCBf9XaEZurp3cxvRUVcGnru+cC9lOq2NPiIlf2RDL5jqkJIpvOc8373xV787yldAjC u24w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wse7zD0pJo6WjEez5LvLZIudG6q/fbgb3bbbGW9ilgU=; b=h5L2zCxkrmpzmBsIdTcIwvruoELSGUO+dDwMVOEGMMLKvtWsao+OWbMqxX+N2euxkv BTNWOY8ApuVFUqHyXzwMA3OgLkjFonSDcCCFMSMZFM1S2lLLd4jFOSDAylq4+/iGUpfa FC2qyzyYpUDgviEmxqyX5kvYVwd20XQPOOA0CR7/3S3FzLXbNRG3GdVK1KKaewK0MNSc k1Bwqvf2AVs9r40rUWV4Pp2+2nUDTxbxLJGSOefODZbo+XiZ+/Fare+xijHO0F9a/wPi RlJ6X1l53jAcFPZ+WJzPdHcOMjAivggDA1h3U3X74iWuUZhvx0bu+e9NthUuNgCcp2ej 8DNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JTtHd001; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c3si1124710ybb.352.2020.08.28.07.30.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:30:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JTtHd001; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44934 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfOz-0004Yw-W3 for patch@linaro.org; Fri, 28 Aug 2020 10:30:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51394) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEr-00010l-1W for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:21 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:44612) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEn-0005Bh-5l for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:20 -0400 Received: by mail-pl1-x636.google.com with SMTP id q3so519699pls.11 for ; Fri, 28 Aug 2020 07:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wse7zD0pJo6WjEez5LvLZIudG6q/fbgb3bbbGW9ilgU=; b=JTtHd001fmseF2x8ueeXUqRoww9p2zSHOGlRcOTohLKFRLMLAGUPSs3Ji3e7PgtyEc GEIhJ8HeJpCT0G596HhCoxvee7+xpnOltXzwW1v9xbEKQzWQG9PwISSYCeSHg97FvmqH XGouX4YMs2Kv1FvnxTx0OF9c7GlpOqg67U69IuIAmc0GStImTKmUldlT8hdCIhe+iIyK 9exMY2FWun8Dtfx9wHVFVH4Q7pzz9D6rNjGlttBirrxO1Wtz4vx5jWcwV+6MmS770Dbs 8oiFByfTG5HFxgR4ic+uA7plpMnLSuiRXhoUGrKUSrAuJZqXIa6vdeZ0ncVZehhFxTL4 OvCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wse7zD0pJo6WjEez5LvLZIudG6q/fbgb3bbbGW9ilgU=; b=V1KgVeVL9t5Zz1uWHMD6H1rpzWR0K24akbo4Lp/nYjfsBsV3xulL2StQIMHPQztPG0 q8zCmWrVt56QAm0vtLH4oNgAR29ezd69LX98TrV/OF8MxNMUMDYkeXe/MLXvgrjq1VBN 0UyRsENx2aZH0XQyHRBGINqSpYpE6P5tpqnN0TEm56io1X+VY1ZnKAj4vec+Fewgke/r 6XCcWpLxIxhIBVqylFkjDPo/pJ6+VYGBT7cZdG+weARdWaVeIWeAJef8E83bNOr4M32W BnSIbmQ1/0dQGMPvXFFy9S00WB7YF83gOvWCGD29mZyS8+3HsNLeEYr7WMaw4fDtenLw Qe/g== X-Gm-Message-State: AOAM531bXElZ92KCmLLtwqcI/iEeleuH6V40AY+Uk1YU9fEYKW8I2vKC xFtCMHvNW3WsFvrTls/0TW2Wj51tcrm9KA== X-Received: by 2002:a17:90a:ad48:: with SMTP id w8mr1393761pjv.179.1598624415335; Fri, 28 Aug 2020 07:20:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 34/76] target/microblaze: Ensure imm constant is always available Date: Fri, 28 Aug 2020 07:18:47 -0700 Message-Id: <20200828141929.77854-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 111 ++++++++++++++++++++-------------- 2 files changed, 67 insertions(+), 46 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7066878ac7..013858b8e0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -374,9 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { *pc = env->pc; - *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & (MSR_UM | MSR_VM | MSR_EE)); + *cs_base = (*flags & IMM_FLAG ? env->imm : 0); } #if !defined(CONFIG_USER_ONLY) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 133ec24870..65ce8f3cd6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -61,6 +61,7 @@ typedef struct DisasContext { /* Decoder. */ int type_b; uint32_t ir; + uint32_t ext_imm; uint8_t opcode; uint8_t rd, ra, rb; uint16_t imm; @@ -169,24 +170,23 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } -/* True if ALU operand b is a small immediate that may deserve - faster treatment. */ -static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) +static int32_t dec_alu_typeb_imm(DisasContext *dc) { - /* Immediate insn without the imm prefix ? */ - return dc->type_b && !(dc->tb_flags & IMM_FLAG); + tcg_debug_assert(dc->type_b); + if (dc->tb_flags & IMM_FLAG) { + return dc->ext_imm | dc->imm; + } else { + return (int16_t)dc->imm; + } } static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { - if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm); - else - tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm)); + tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); return &cpu_imm; - } else - return &cpu_R[dc->rb]; + } + return &cpu_R[dc->rb]; } static void dec_add(DisasContext *dc) @@ -776,14 +776,14 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { - tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); + dc->ext_imm = dc->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; } static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) { - bool extimm = dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ bool stackprot = false; TCGv_i32 t32; @@ -836,11 +836,7 @@ static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) } /* Immediate. */ t32 = tcg_temp_new_i32(); - if (!extimm) { - tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm); - } else { - tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); - } + tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); tcg_gen_extu_i32_tl(t, t32); tcg_temp_free_i32(t32); @@ -1134,15 +1130,13 @@ static void dec_bcc(DisasContext *dc) dec_setup_dslot(dc); } - if (dec_alu_op_b_is_small_imm(dc)) { - int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - - tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset); + if (dc->type_b) { dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->base.pc_next + offset; + dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } @@ -1192,38 +1186,63 @@ static void dec_br(DisasContext *dc) return; } + if (abs && link && !dslot) { + if (dc->type_b) { + /* BRKI */ + uint32_t imm = dec_alu_typeb_imm(dc); + if (trap_userspace(dc, imm != 8 && imm != 0x18)) { + return; + } + } else { + /* BRK */ + if (trap_userspace(dc, true)) { + return; + } + } + } + dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); } - if (link && dc->rd) + if (link && dc->rd) { tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); + } - dc->jmp = JMP_INDIRECT; if (abs) { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); - if (link && !dslot) { - if (!(dc->tb_flags & IMM_FLAG) && - (dc->imm == 8 || dc->imm == 0x18)) { + if (dc->type_b) { + uint32_t dest = dec_alu_typeb_imm(dc); + + dc->jmp = JMP_DIRECT; + dc->jmp_pc = dest; + tcg_gen_movi_i32(cpu_btarget, dest); + if (link && !dslot) { + switch (dest) { + case 8: + case 0x18: + gen_raise_exception_sync(dc, EXCP_BREAK); + break; + case 0: + gen_raise_exception_sync(dc, EXCP_DEBUG); + break; + } + } + } else { + dc->jmp = JMP_INDIRECT; + tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); + if (link && !dslot) { gen_raise_exception_sync(dc, EXCP_BREAK); } - if (dc->imm == 0) { - if (trap_userspace(dc, true)) { - return; - } - gen_raise_exception_sync(dc, EXCP_DEBUG); - } } + } else if (dc->type_b) { + dc->jmp = JMP_DIRECT; + dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { - if (dec_alu_op_b_is_small_imm(dc)) { - dc->jmp = JMP_DIRECT; - dc->jmp_pc = dc->base.pc_next + (int32_t)((int16_t)dc->imm); - } else { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); - } + dc->jmp = JMP_INDIRECT; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } + tcg_gen_movi_i32(cpu_btaken, 1); } static inline void do_rti(DisasContext *dc) @@ -1529,6 +1548,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; + dc->ext_imm = dc->base.tb->cs_base; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1573,8 +1593,9 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->clear_imm = 1; decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) { + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; + tcg_gen_discard_i32(cpu_imm); } dc->base.pc_next += 4; From patchwork Fri Aug 28 14:18:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248542 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1134818ilg; Fri, 28 Aug 2020 07:34:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZp8+Xr2VyAEsNWlneEdyMf5h8M0uKHAGGL9jIZ2Uqo7dlFx6aYzxyPqmcGRd4BtGtrywA X-Received: by 2002:a25:3803:: with SMTP id f3mr2723419yba.470.1598625267182; Fri, 28 Aug 2020 07:34:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625267; cv=none; d=google.com; s=arc-20160816; b=uipFdLlFwpD8878Q3hLNmXaT5bEpIbAhCc2GzLG2l5MCSeUmdHaROY76+sCa/62pnK 1/V8VglGMDdkhjdDm6OXaTsCAuQNl/Upag114s3q8s3z6EyaqeAyIm4OXwKhjSYVcom+ jzxlXWbPX1mqQGMYMpzSByzr7pGlxpTlhzAxkcx3xk95wZiO/UckIrjJARmi4ykb2Lj3 td1LEHOXcQ810ehNU4T+Jbl22rsS87MlvGNStUOA7j779Oh8w6xGGYcHMdN4oof6t9Nd yW7XcGFcaYcbB8ahHx7CIXWFpi/tdAZoo/rXT2xUwcdE1RNxwvDzPxZlP4LS3JFlvMwl dDDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+kEx0UptQCrtmnph6sgV6tFoh7UCNGXW3aCpI+f1tQA=; b=oCEMK4JI8s05YDamzExysEOfAMYQRcRZMRyLjFCXxFteOEZ5WuU/2/+ufMrxd3nI48 iZiyAqfBviCqY92oPr9nv+AeGDDhObyNPrT7FxlMrkOQOOejaZRjp3vM1Zib7jLtq4cZ uCGP8zfLUY3ph7yE7MZ0hNYRge3eTO8+OB7RQFmHH5pOKg2EUZ6Qc6NCkBHsbmtMouG0 r1NPDyd662HiNF/DG51w00IBAR37ufIt0ww2r+PJSCePw3jBOjdEMMY0FOJs4ZyOstWT vJOAcm2UE38HhH0ET8RLS4zcN4N6rGzMBXOAGiV26xjnPdlzMSnlTC0muRa6ty4Q/Qgz vpRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="YomxZ/Dh"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c204si1048433ybf.366.2020.08.28.07.34.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:34:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="YomxZ/Dh"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfSU-00035d-Jm for patch@linaro.org; Fri, 28 Aug 2020 10:34:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51410) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEr-00012a-Vq for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:23 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:46935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEo-0005Bu-7E for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:21 -0400 Received: by mail-pl1-x643.google.com with SMTP id k13so513714plk.13 for ; Fri, 28 Aug 2020 07:20:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+kEx0UptQCrtmnph6sgV6tFoh7UCNGXW3aCpI+f1tQA=; b=YomxZ/DhDeUWnSe05DJ+fB7yPF1bZJ0rpB3bsxUT3XCdcvfOmXZQDqK5rg3zkXz9mZ /i8qziZJKBy0NqI09elc8x02O3K5VbKybNQtVKzHu3dTrTozRQla80GkmIYA1ACegXSO souu71kuNybTiQd+C+lRszFqH+uctoQzyirGAHHzSl3EDnIjY2dPIs6g5ABGzoMAM6Y1 tFfPIy8MPAZPk+Ffr0YqE1QUvHyyRfE67IE1szgaLJkcLmge9OG3k6iDsiYtWWb5qFXc y3gIoW6+sx6YitiDXZq3bbSb6h3HAzTjEDr6UYCTL+CLqSUzd+vkRVv8YN+1tI96gzIM 5M9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+kEx0UptQCrtmnph6sgV6tFoh7UCNGXW3aCpI+f1tQA=; b=snw/BJxKvcg0sq4RMb7zZKKfu3NTa6d7ww8OERFfB8ZdI3FE98YMrxITP2W+XoNqCU T4/tNbnFXZpLC5zrbR1ZPyXoZ83O1qhfxPA6JWrXSfyrYvIM4bHBl7iDg9l7zSrVbdCR orjkmlkWDu32kxAlEC8lR3aKe+JXPB+pZ/iGMiL4d/xEDXBMEAWg8R66a2EjOjRJAzbO U419IhBFjsyJgbNc+rLabym0iPt1LHhpEGhm+eolkf3IEcFGnlojsEyhyYvx2dl1k9DV 91udEBYGBxzZ2rqXfrQQpl7CwWGx70OdJ9zZykMRJAzQo/Yh02Is1Y4geqf0oOH+msS9 KoNA== X-Gm-Message-State: AOAM530ZKwD084Z0ndZK71ZYtd0AEaTSq7FuEMotvzzfk/KJ8YPOi2WT w32KZndLrZJ9rc1X1cXqdoPbLY3h8pA2uQ== X-Received: by 2002:a17:902:748c:: with SMTP id h12mr1496665pll.316.1598624416492; Fri, 28 Aug 2020 07:20:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 35/76] target/microblaze: Add decodetree infrastructure Date: Fri, 28 Aug 2020 07:18:48 -0700 Message-Id: <20200828141929.77854-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The new interface is a stub that recognizes no instructions. It falls back to the old decoder for all instructions. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 18 ++++++++++++++++++ target/microblaze/translate.c | 11 +++++++++-- target/microblaze/meson.build | 3 +++ 3 files changed, 30 insertions(+), 2 deletions(-) create mode 100644 target/microblaze/insns.decode -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode new file mode 100644 index 0000000000..1ed9ca0731 --- /dev/null +++ b/target/microblaze/insns.decode @@ -0,0 +1,18 @@ +# +# MicroBlaze instruction decode definitions. +# +# Copyright (c) 2020 Richard Henderson +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 65ce8f3cd6..e624093745 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -81,6 +81,9 @@ typedef struct DisasContext { int abort_at_next_insn; } DisasContext; +/* Include the auto-generated decoder. */ +#include "decode-insns.c.inc" + static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1506,7 +1509,7 @@ static struct decoder_info { {{0, 0}, dec_null} }; -static inline void decode(DisasContext *dc, uint32_t ir) +static void old_decode(DisasContext *dc, uint32_t ir) { int i; @@ -1584,6 +1587,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); CPUMBState *env = cs->env_ptr; + uint32_t ir; /* TODO: This should raise an exception, not terminate qemu. */ if (dc->base.pc_next & 3) { @@ -1592,7 +1596,10 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) } dc->clear_imm = 1; - decode(dc, cpu_ldl_code(env, dc->base.pc_next)); + ir = cpu_ldl_code(env, dc->base.pc_next); + if (!decode(dc, ir)) { + old_decode(dc, ir); + } if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; tcg_gen_discard_i32(cpu_imm); diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index b8fe4afe61..639c3f73a8 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -1,4 +1,7 @@ +gen = decodetree.process('insns.decode') + microblaze_ss = ss.source_set() +microblaze_ss.add(gen) microblaze_ss.add(files( 'cpu.c', 'gdbstub.c', From patchwork Fri Aug 28 14:18:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248544 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1135602ilg; Fri, 28 Aug 2020 07:35:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwSYkej1mDDmASxRbFlMI5irFJBLiB9zvRLztIGpv+htbokPRHPqUCRKhpGGKQEwqs/h7Gu X-Received: by 2002:a25:b290:: with SMTP id k16mr2728669ybj.389.1598625319181; Fri, 28 Aug 2020 07:35:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625319; cv=none; d=google.com; s=arc-20160816; b=GsY5fg66MS0XavWBt2C4YRVogREgVQTvVm/QA93rRl9Nal/n0Qw4bcMF4V6+0jxW6C 65NuZH9yc/QZ9hLFFQOks+HAle1gLeLwTRnZCr52W8YXtcDtDSr7QSqB1Rc+32Q4iI4c kCxynmSFzxQ2Hs3Fh97WU9qZfQhT1w6USv0N1JW1NvQy2CIRmLjsF/bfcQHMlKi+ifko Z9uwFCOalhISxLID09F3xD00Y4iy735/OtauUKtmxskhEtePyDqvHvKw9yoTn5tt76Fq Tg0rrMKPXWhdm3Gt6qmDu5ekstLw8Ux806Pc1dfhgp9gFZYzy8ipIuq5i2aWbM7j8roB +VAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xYtpy93DxsUkXiRzI3kpBRzzV+FuhgtgLCBh7eVcN9c=; b=oi5WMnZjIyVfLNtUUVkoA35/js4ijkXAs3pUebVsgA4PF1l6ZFvbgaZAiq5xRX9XO0 gpaw+zDP2zQA2y8n8nStclPzRPrexvLRCbZ/Bkf8+7Q+toxTg/4DX/4KEj+D38ZyICPW 4Q6D5hybuy1BVOrX0WZdebVk2MafrYwbnArU8IUMd2OmXLCHb98xwsy/cUtW9U+T0YkG yr1yeggi5whDfTafIHc+xJQbJFdevuNP3arb1O4TqKY4l86VLLs2+O3hINuZ0x6PPLe5 GeoYwQ11RxwcPQ+RTHW80r5iGX5TUBQSq2nR9FlSINdaGyyczO66e68JyH3z/lwcUmgL dnaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QdWz2WsA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Adds infrastrucure for translation of instructions, which could not be added before their first use. Cache a temporary which represents r0 as the immediate 0 value, or a sink. Move the special case of opcode_0_illegal from old_decode() into decodetree as well, lest this get interpreted as add. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 24 ++++ target/microblaze/translate.c | 197 ++++++++++++++++++++++++++------- 2 files changed, 178 insertions(+), 43 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 1ed9ca0731..5f289a446c 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -16,3 +16,27 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +&typea rd ra rb +&typeb rd ra imm + +# Include any IMM prefix in the value reported. +%extimm 0:s16 !function=typeb_imm + +@typea ...... rd:5 ra:5 rb:5 ... .... .... &typea +@typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm + +### + +{ + zero 000000 00000 00000 00000 000 0000 0000 + add 000000 ..... ..... ..... 000 0000 0000 @typea +} +addc 000010 ..... ..... ..... 000 0000 0000 @typea +addk 000100 ..... ..... ..... 000 0000 0000 @typea +addkc 000110 ..... ..... ..... 000 0000 0000 @typea + +addi 001000 ..... ..... ................ @typeb +addic 001010 ..... ..... ................ @typeb +addik 001100 ..... ..... ................ @typeb +addikc 001110 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e624093745..de822bd7b7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; + TCGv_i32 r0; + bool r0_set; + /* Decoder. */ int type_b; uint32_t ir; @@ -81,6 +84,14 @@ typedef struct DisasContext { int abort_at_next_insn; } DisasContext; +static int typeb_imm(DisasContext *dc, int x) +{ + if (dc->tb_flags & IMM_FLAG) { + return deposit32(dc->ext_imm, 0, 16, x); + } + return x; +} + /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -176,11 +187,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) static int32_t dec_alu_typeb_imm(DisasContext *dc) { tcg_debug_assert(dc->type_b); - if (dc->tb_flags & IMM_FLAG) { - return dc->ext_imm | dc->imm; - } else { - return (int16_t)dc->imm; - } + return typeb_imm(dc, (int16_t)dc->imm); } static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) @@ -192,44 +199,146 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) return &cpu_R[dc->rb]; } -static void dec_add(DisasContext *dc) +static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { - unsigned int k, c; - TCGv_i32 cf; - - k = dc->opcode & 4; - c = dc->opcode & 2; - - /* Take care of the easy cases first. */ - if (k) { - /* k - keep carry, no need to update MSR. */ - /* If rd == r0, it's a nop. */ - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - - if (c) { - /* c - Add carry into the result. */ - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); - } + if (likely(reg != 0)) { + return cpu_R[reg]; + } + if (!dc->r0_set) { + if (dc->r0 == NULL) { + dc->r0 = tcg_temp_new_i32(); } - return; + tcg_gen_movi_i32(dc->r0, 0); + dc->r0_set = true; + } + return dc->r0; +} + +static TCGv_i32 reg_for_write(DisasContext *dc, int reg) +{ + if (likely(reg != 0)) { + return cpu_R[reg]; + } + if (dc->r0 == NULL) { + dc->r0 = tcg_temp_new_i32(); + } + return dc->r0; +} + +static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, rb; + + if (arg->rd == 0 && !side_effects) { + return true; } - /* From now on, we can assume k is zero. So we need to update MSR. */ - /* Extract carry. */ - cf = tcg_temp_new_i32(); - if (c) { - tcg_gen_mov_i32(cf, cpu_msr_c); - } else { - tcg_gen_movi_i32(cf, 0); + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + rb = reg_for_read(dc, arg->rb); + fn(rd, ra, rb); + return true; +} + +static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects, + void (*fni)(TCGv_i32, TCGv_i32, int32_t)) +{ + TCGv_i32 rd, ra; + + if (arg->rd == 0 && !side_effects) { + return true; } - gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + fni(rd, ra, arg->imm); + return true; +} + +static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, imm; + + if (arg->rd == 0 && !side_effects) { + return true; } - tcg_temp_free_i32(cf); + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + imm = tcg_const_i32(arg->imm); + + fn(rd, ra, imm); + + tcg_temp_free_i32(imm); + return true; +} + +#define DO_TYPEA(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ + { return do_typea(dc, a, SE, FN); } + +#define DO_TYPEBI(NAME, SE, FNI) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_imm(dc, a, SE, FNI); } + +#define DO_TYPEBV(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_val(dc, a, SE, FN); } + +/* No input carry, but output carry. */ +static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + + tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero); + + tcg_temp_free_i32(zero); +} + +/* Input and output carry. */ +static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero); + tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(zero); +} + +/* Input carry, but no output carry. */ +static void gen_addkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_add_i32(out, ina, inb); + tcg_gen_add_i32(out, out, cpu_msr_c); +} + +DO_TYPEA(add, true, gen_add) +DO_TYPEA(addc, true, gen_addc) +DO_TYPEA(addk, false, tcg_gen_add_i32) +DO_TYPEA(addkc, true, gen_addkc) + +DO_TYPEBV(addi, true, gen_add) +DO_TYPEBV(addic, true, gen_addc) +DO_TYPEBI(addik, false, tcg_gen_addi_i32) +DO_TYPEBV(addikc, true, gen_addkc) + +static bool trans_zero(DisasContext *dc, arg_zero *arg) +{ + /* If opcode_0_illegal, trap. */ + if (dc->cpu->cfg.opcode_0_illegal) { + trap_illegal(dc, true); + return true; + } + /* + * Otherwise, this is "add r0, r0, r0". + * Continue to trans_add so that MSR[C] gets cleared. + */ + return false; } static void dec_sub(DisasContext *dc) @@ -1488,7 +1597,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_ADD, dec_add}, {DEC_SUB, dec_sub}, {DEC_AND, dec_and}, {DEC_XOR, dec_xor}, @@ -1515,12 +1623,6 @@ static void old_decode(DisasContext *dc, uint32_t ir) dc->ir = ir; - if (ir == 0) { - trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); - /* Don't decode nop/zero instructions any further. */ - return; - } - /* bit 2 seems to indicate insn type. */ dc->type_b = ir & (1 << 29); @@ -1552,6 +1654,8 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; + dc->r0 = NULL; + dc->r0_set = false; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1600,6 +1704,13 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) if (!decode(dc, ir)) { old_decode(dc, ir); } + + if (dc->r0) { + tcg_temp_free_i32(dc->r0); + dc->r0 = NULL; + dc->r0_set = false; + } + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; tcg_gen_discard_i32(cpu_imm); From patchwork Fri Aug 28 14:18:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248562 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1141869ilg; Fri, 28 Aug 2020 07:43:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjaJdXPeXmh/vZR9YGwSY+KHBY1Gq0g3wxHvU9oL8ujGsOZUsIMg9pUmrpn5MbcjtMCTqn X-Received: by 2002:a25:7310:: with SMTP id o16mr2913065ybc.415.1598625781382; Fri, 28 Aug 2020 07:43:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625781; cv=none; d=google.com; s=arc-20160816; b=bLh5cJRGuKpQ9nIMms/gYzhtMuG0nwfXzb9ICJP91VILhwBeiWKw9Py3jGcXhb7CA3 /gLRwzOBTWGQOJTJCZYnqSZYyePCA1izSM3JxkfF9j7YXb/oBqcWmSmYk0VO62vqgOG5 P4otJuKt1IEDaJnhfcMoqDn9mogAT71jTH8Kj92glHipk7LP1d9Tv3TpxrjnAXAgxIYW xUQcP6NLV4vGvA3VlLg+bFUzOz4/YRSf76EI7E/w/K3BCWjB27QYBeMDasm0ox6xsels SAx/XD54ksPPi/Ug8BVgs70tWjEVqmrC/HOrch097XwoV+NObvDT62ZIbtfw+0P8vJaw Oj4g== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use tcg_gen_add2_i32 for computing carry. This removes the last use of helper_carry, so remove that. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 1 - target/microblaze/insns.decode | 13 ++++ target/microblaze/op_helper.c | 16 ----- target/microblaze/translate.c | 110 ++++++++++++++++----------------- 4 files changed, 65 insertions(+), 75 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 9309142f8d..988abf7661 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) DEF_HELPER_2(cmpu, i32, i32, i32) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 5f289a446c..a611cc83a7 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -40,3 +40,16 @@ addi 001000 ..... ..... ................ @typeb addic 001010 ..... ..... ................ @typeb addik 001100 ..... ..... ................ @typeb addikc 001110 ..... ..... ................ @typeb + +cmp 000101 ..... ..... ..... 000 0000 0001 @typea +cmpu 000101 ..... ..... ..... 000 0000 0011 @typea + +rsub 000001 ..... ..... ..... 000 0000 0000 @typea +rsubc 000011 ..... ..... ..... 000 0000 0000 @typea +rsubk 000101 ..... ..... ..... 000 0000 0000 @typea +rsubkc 000111 ..... ..... ..... 000 0000 0000 @typea + +rsubi 001001 ..... ..... ................ @typeb +rsubic 001011 ..... ..... ................ @typeb +rsubik 001101 ..... ..... ................ @typeb +rsubikc 001111 ..... ..... ................ @typeb diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index decdca0fd8..9bb6a2ad76 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,17 +69,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) -{ - uint32_t cout = 0; - - if ((b == ~0) && cin) - cout = 1; - else if ((~0 - a) < (b + cin)) - cout = 1; - return cout; -} - uint32_t helper_cmp(uint32_t a, uint32_t b) { uint32_t t; @@ -100,11 +89,6 @@ uint32_t helper_cmpu(uint32_t a, uint32_t b) return t; } -uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) -{ - return compute_carry(a, b, cf); -} - static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { MicroBlazeCPU *cpu = env_archcpu(env); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index de822bd7b7..0e7d24ddca 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -327,6 +327,58 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) +DO_TYPEA(cmp, false, gen_helper_cmp) +DO_TYPEA(cmpu, false, gen_helper_cmpu) + +/* No input carry, but output carry. */ +static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_msr_c, inb, ina); + tcg_gen_sub_i32(out, inb, ina); +} + +/* Input and output carry. */ +static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_not_i32(tmp, ina); + tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero); + tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); + + tcg_temp_free_i32(zero); + tcg_temp_free_i32(tmp); +} + +/* No input or output carry. */ +static void gen_rsubk(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_sub_i32(out, inb, ina); +} + +/* Input carry, no output carry. */ +static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 nota = tcg_temp_new_i32(); + + tcg_gen_not_i32(nota, ina); + tcg_gen_add_i32(out, inb, nota); + tcg_gen_add_i32(out, out, cpu_msr_c); + + tcg_temp_free_i32(nota); +} + +DO_TYPEA(rsub, true, gen_rsub) +DO_TYPEA(rsubc, true, gen_rsubc) +DO_TYPEA(rsubk, false, gen_rsubk) +DO_TYPEA(rsubkc, true, gen_rsubkc) + +DO_TYPEBV(rsubi, true, gen_rsub) +DO_TYPEBV(rsubic, true, gen_rsubc) +DO_TYPEBV(rsubik, false, gen_rsubk) +DO_TYPEBV(rsubikc, true, gen_rsubkc) + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -341,63 +393,6 @@ static bool trans_zero(DisasContext *dc, arg_zero *arg) return false; } -static void dec_sub(DisasContext *dc) -{ - unsigned int u, cmp, k, c; - TCGv_i32 cf, na; - - u = dc->imm & 2; - k = dc->opcode & 4; - c = dc->opcode & 2; - cmp = (dc->imm & 1) && (!dc->type_b) && k; - - if (cmp) { - if (dc->rd) { - if (u) - gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - else - gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - } - return; - } - - /* Take care of the easy cases first. */ - if (k) { - /* k - keep carry, no need to update MSR. */ - /* If rd == r0, it's a nop. */ - if (dc->rd) { - tcg_gen_sub_i32(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); - - if (c) { - /* c - Add carry into the result. */ - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); - } - } - return; - } - - /* From now on, we can assume k is zero. So we need to update MSR. */ - /* Extract carry. And complement a into na. */ - cf = tcg_temp_new_i32(); - na = tcg_temp_new_i32(); - if (c) { - tcg_gen_mov_i32(cf, cpu_msr_c); - } else { - tcg_gen_movi_i32(cf, 1); - } - - /* d = b + ~a + c. carry defaults to 1. */ - tcg_gen_not_i32(na, cpu_R[dc->ra]); - - gen_helper_carry(cpu_msr_c, na, *(dec_alu_op_b(dc)), cf); - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - } - tcg_temp_free_i32(cf); - tcg_temp_free_i32(na); -} - static void dec_pattern(DisasContext *dc) { unsigned int mode; @@ -1597,7 +1592,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_SUB, dec_sub}, {DEC_AND, dec_and}, {DEC_XOR, dec_xor}, {DEC_OR, dec_or}, From patchwork Fri Aug 28 14:18:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248563 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1142616ilg; Fri, 28 Aug 2020 07:43:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBQyNk+j+dOVaDF1Vpp9YA5lM2BqPkCVrsQfyc0UjSDYY0wt0/9ULR/C39k9M5+Wab+gQP X-Received: by 2002:a25:5384:: with SMTP id h126mr3062025ybb.374.1598625833547; Fri, 28 Aug 2020 07:43:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625833; cv=none; d=google.com; s=arc-20160816; b=ba8a+SZPfTuCuWb1yvupVl+C25xB1po0oZ85pt+2sNZjFgiqv4FO4GoUKIneQqj3/6 2EaEPKIp74xWTADczaxpLCJOWz/QzagWVJBjCrc2BLCHMw4Fl7MFdwcYrqpIaznnGmr/ YwLcXyfVloIFg7hU4kpyZWgQXJ9qrGHVAq9TCvDfM2vOr92HP9xnx+pqIJqhBzeamjl4 BD/XfAdEf57Q+wwlzPcn14y013Y82GfOUsczSrz+RR246ZhwTlMDMVjAYtPjmlenoRxg pstUJNluYHsbgWP1PObq4tEKGjaoQfCzP7vl7qsqVR+iuLmXZ8+Q2vKnIAwUkB0jw3jW VOaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1/Hy6AwnddO7FgH8pQmMPkXmEttwqr8LltORKFA3Vts=; b=G9aPE82lrIhhlD9B78MfnRTJ13yosDHf5TppIEuU2B0M968pKFCyYOclyxzgY7zSBU 5jfESDNotf6CacsKJMMXeHynoV0NZPRVhnYx+PbrcGWTlNNW5gG+46zbhsvybJjU1cG3 u4UC1r0qovFlvn8kE0prrX3JmhEXi6ArlZPTZ1yv5Sqcdx/KJ8wHBaWXXY2SJWggB8KC pO5W+SSmALaLXADRHCJT220pXGEhtARsp2W4lvOqELiHGug1ZW8FX39+vH5Gf/cBNlw+ sf3GfmdoaKKBQ2bD5Eblfwl0x6Z9mkel7T9hhVChCDBINVuVxivekWoSeov28Cjj3Cnr mJmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mKjpcga4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d5si1119062ybk.135.2020.08.28.07.43.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:43:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mKjpcga4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfbd-0006YJ-1a for patch@linaro.org; Fri, 28 Aug 2020 10:43:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEu-00015D-G4 for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:24 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:35132) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEr-0005EX-M9 for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:24 -0400 Received: by mail-pg1-x542.google.com with SMTP id g29so534807pgl.2 for ; Fri, 28 Aug 2020 07:20:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1/Hy6AwnddO7FgH8pQmMPkXmEttwqr8LltORKFA3Vts=; b=mKjpcga4kNQpWS9DBD8HwW1uQUEGbJ6wTgVRaXAmWo9lct7BiyVxHQ656wLnSBOXwi CfrTt0FgBo9gVp44hJyZaVWKhaYGZzoZ8aOl4Hw3xR1KkmqSq5q8YeqGhC6vRmWzZ5as W1Cbn9EGU/KYD/tYZCcOyqRijccMbADMFN12hKfUudoQF8i3mI69S5LrA3QI1qc4LVEc DAhzbeqMsap9dS/xFPXo/kRgsk1s1C1+htQIqoqk4hrMNmp+PciB4Ff2kOEHMYQxmXHZ zA96tZ0qnIfZUpISialJzYVInFbiWQjEd3apV3AD3Jzgp44KZ919fSQMJpUYAZ4+0aAY kutw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1/Hy6AwnddO7FgH8pQmMPkXmEttwqr8LltORKFA3Vts=; b=pyFEJX97wpQA4w94FXolNo1rpewrudUTWAT8jUJAm0lo4/2FM21r6vvn/subW1Xw0F eWPFKyP+1NnrqFRL4pIAB13786ydahfBZJvdN2ZG4zp1+/xJ646vrsYi/e1Z0ZXkew4B cew0kq2TlaEoxhFFK76MH7ruqMqnDXvS/nyHh81/7AKauS4e0g7xVXJ6HTq55SIxY0ie zw9gWt4M/hswde3qftGTRFZBsNv512wurupSb/Jylw4ADh5ZASKg9irXMA3vn3hjEj46 pv/GHMBvzJAno/qrF4wYftoK+I0FbZeTMpUN7KgRUFCfL1pWmR/YkFdkz3xfWBsg+a9M ZzFA== X-Gm-Message-State: AOAM533gw29LMLkikStj7pu68yUa92we9Vc7ojYEpGJFr4kPeiEtTqLm RpY8wCZGiBpTach0NlBXIOF7p0mCVXU8KQ== X-Received: by 2002:a63:547:: with SMTP id 68mr1404422pgf.327.1598624419880; Fri, 28 Aug 2020 07:20:19 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 38/76] target/microblaze: Implement cmp and cmpu inline Date: Fri, 28 Aug 2020 07:18:51 -0700 Message-Id: <20200828141929.77854-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are simple enough operations; we do not need to call an out-of-line helper. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 -- target/microblaze/op_helper.c | 20 -------------------- target/microblaze/translate.c | 24 ++++++++++++++++++++++-- 3 files changed, 22 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 988abf7661..6f7f96421f 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,6 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_2(cmp, i32, i32, i32) -DEF_HELPER_2(cmpu, i32, i32, i32) DEF_HELPER_3(divs, i32, env, i32, i32) DEF_HELPER_3(divu, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 9bb6a2ad76..f976d112eb 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,26 +69,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -uint32_t helper_cmp(uint32_t a, uint32_t b) -{ - uint32_t t; - - t = b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t = (t & 0x7fffffff) | (b & 0x80000000); - return t; -} - -uint32_t helper_cmpu(uint32_t a, uint32_t b) -{ - uint32_t t; - - t = b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t = (t & 0x7fffffff) | (a & 0x80000000); - return t; -} - static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { MicroBlazeCPU *cpu = env_archcpu(env); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0e7d24ddca..8da477457d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -327,8 +327,28 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) -DO_TYPEA(cmp, false, gen_helper_cmp) -DO_TYPEA(cmpu, false, gen_helper_cmpu) +static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt = tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt = tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +DO_TYPEA(cmp, false, gen_cmp) +DO_TYPEA(cmpu, false, gen_cmpu) /* No input carry, but output carry. */ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) From patchwork Fri Aug 28 14:18:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248546 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1136742ilg; Fri, 28 Aug 2020 07:36:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxirCfObxRwa4sk6mZicH7hC7nYSY/2u2NqnJAzuQJzgtXutqAV4iKPv6tno/OgHSepQz0y X-Received: by 2002:a25:3b0d:: with SMTP id i13mr2830468yba.314.1598625396176; Fri, 28 Aug 2020 07:36:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625396; cv=none; d=google.com; s=arc-20160816; b=Om5ubQ1bSGMQS+XIlt39/7SgTJEqmt+dbWkEzesyqbBs/OwwmXJSC+vvgN93PjWpGK wjqxCTkjIWwgU3W18LZOXSBmY8urCgxujxMgpx65fU5sSN1+kpavaSgr072UQ9xfAme4 oWz8irzRfa0R2cSzA2IQSlQ8rWkuGx6tdiEm4vzXNmdysbB2UyatLRZmW+L8dE8Q2ret 5Q64oKyPeRg6KUQbyCKmp0y7lNWua29+OJdVOAMsb+EiMS04NdsXPbhqO/N1cw8YdUg3 jrsb21kNzPkVxMwAMnLB0ok/03bgf/6b2JI6lZdO5Kdz03ASz5MnASmtEIi5/lXBWG5q Yc2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wXHheAujwG3J7OkJDdVOIKAESxqo8RAwt5jkuy5HApE=; b=kru8vdKwmTXjW+3paJ3BdE9RF51Yv68vA9xFRQCNTSF4zAsaCFsCPqTh9rkygfdyrQ A18srrHVY4WgVM0LYbFVb0ErU6LJc6RPw9ymbOFFhZcL29wJzwsO8R7122bTWAxVBvye yLrNmJn2HG3/Gc5YJVZ57rsMidLvZ/4pkHQKnQsdF4WraiXjvsWfoLiLKqOKVAIGEcqo l85LpTkEJBg7lynwrhJYd8Gzj8B/0XGLvzCE8s5AnRiXeUXsCnWE3tUjFo3o7eL9Aj49 cT6KKhnrkKxr/7nX+kmbVnO3hVeYkebYcZ34YruL5OzTuJ59ELEpSKdVngWZfswnxg4T 20Gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rRcLMnk0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 4 ++ target/microblaze/translate.c | 67 +++++++++------------------------- 2 files changed, 22 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index a611cc83a7..16519f05dc 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -44,6 +44,10 @@ addikc 001110 ..... ..... ................ @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea +pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea +pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea + rsub 000001 ..... ..... ..... 000 0000 0000 @typea rsubc 000011 ..... ..... ..... 000 0000 0000 @typea rsubk 000101 ..... ..... ..... 000 0000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8da477457d..7ebf0e1e7d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -279,6 +279,10 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ { return do_typea(dc, a, SE, FN); } +#define DO_TYPEA_CFG(NAME, CFG, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ + { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } + #define DO_TYPEBI(NAME, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } @@ -350,6 +354,20 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); +} + +static void gen_pcmpne(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_NE, out, ina, inb); +} + +DO_TYPEA_CFG(pcmpbf, use_pcmp_instr, false, gen_helper_pcmpbf) +DO_TYPEA_CFG(pcmpeq, use_pcmp_instr, false, gen_pcmpeq) +DO_TYPEA_CFG(pcmpne, use_pcmp_instr, false, gen_pcmpne) + /* No input carry, but output carry. */ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { @@ -413,49 +431,10 @@ static bool trans_zero(DisasContext *dc, arg_zero *arg) return false; } -static void dec_pattern(DisasContext *dc) -{ - unsigned int mode; - - if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { - return; - } - - mode = dc->opcode & 3; - switch (mode) { - case 0: - /* pcmpbf. */ - if (dc->rd) - gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - if (dc->rd) { - tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - } - break; - case 3: - if (dc->rd) { - tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - } - break; - default: - cpu_abort(CPU(dc->cpu), - "unsupported pattern insn opcode=%x\n", dc->opcode); - break; - } -} - static void dec_and(DisasContext *dc) { unsigned int not; - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - not = dc->opcode & (1 << 1); if (!dc->rd) @@ -469,22 +448,12 @@ static void dec_and(DisasContext *dc) static void dec_or(DisasContext *dc) { - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - if (dc->rd) tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } static void dec_xor(DisasContext *dc) { - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - if (dc->rd) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } From patchwork Fri Aug 28 14:18:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248529 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1129986ilg; Fri, 28 Aug 2020 07:28:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx5+Zq0L3OhRbvXIlteuEvxqtMreQAIfshoQug5sQhJCkElVlDR9XALo2rrT9a4hQL99dIf X-Received: by 2002:a25:84cd:: with SMTP id x13mr2607958ybm.425.1598624938171; Fri, 28 Aug 2020 07:28:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598624938; cv=none; d=google.com; s=arc-20160816; b=vuC2QGZgF9/vaZN6dC4YXyW955OehnFrZq48kcrW7LGFzZFbb2IUxh7pzDZIKCKlct bLzoQ9eBWKsxtechKhXe564R3NBmy52WZJy1X9K7Dxr2uM+zdiU5TvmpjYDxkwTUOcbp NDHO+6keZUVpvnpg0cCAIBR1tPJaTrwiudsMC5z8TJatbXlCCKlGGtoeKGklHFxbsj/z a4UlR8/jmvMLw9itbI1KA/dOGw0UUAvCTjrkLfoonBximWCzZNLnukBYRWR5HozMrWwr MdvkoN4YwMmBp2NaojBe33aa77pkF3tS+nNTJfVLsJN6JCWcP5LhU5ctoq6kEQu8EbHo AC8A== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id k131si1071901ybk.460.2020.08.28.07.28.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:28:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lregl2ax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36272 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfNB-0000yw-I4 for patch@linaro.org; Fri, 28 Aug 2020 10:28:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEv-00018z-W1 for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:26 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:36198) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEt-0005Ew-W3 for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:25 -0400 Received: by mail-pf1-x432.google.com with SMTP id m8so744209pfh.3 for ; Fri, 28 Aug 2020 07:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sHORevIojNYxQS1WYiF9QC1vlWbeSRb2UpS9N98vWv0=; b=Lregl2axj9rCEZ++cE/qehPTB7GrkWZWUUmBa4fefTa1RnfeveWawY2v8S4NgZGgMg 2/nXvD8rPuMKe+mRRdxfN+0ufYdAgtpboDG2YRYHJsYy/Zp0Z+12ispbgzWw/+SWXohV S8ieiDXVbAZcEvTXtu+IsB9ngoPcoRNhwMpjIWrhK8iAxJbwNSQkEBJuko5KkUGBApg3 h1gKxEq+tbt5bHTXzlPNYlMCWMFaHXXfSGu6fr/Nvf5QNyDnC9c6VvoeeKBmoTDvLIgv 3ebVbXfl8ZBqKk3Mk38Oivv0ZuXRtqv4Mz9u1bj7QfWIWDq0JkYbzBPIU5o7Hhqdh5WX AQ5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sHORevIojNYxQS1WYiF9QC1vlWbeSRb2UpS9N98vWv0=; b=IVoetTvnpr34PFg25rRDgBxxYsDy8vSRDDGidCEYGAFttyUztH5ehiMCLgYaiN8Y4P Fr/6hzi1GF0fqoV57aBdJPWyOFeVRj9kMKeemKzgRgPQjx4pGK3ohPNLg09ITnfLeLJM P4wlQU3b/ROA2437aDg7bCbVwHuc+gVT11dDq/tm3cxPBk/I7mp0oryy67pY0jhjaYq4 KYCVqOcdYG+uG2tQ+RFlrCPXolV6tkBejOhnPzBMGBA5q73nlGiAbvjAPM6ivs+EA3gT jrSjYeiYY9VIPMKiH47BcKs1FsK6rIB40nMEfMq33relkSJB6YxUuK4287cG047qF+Ii 1n5A== X-Gm-Message-State: AOAM5308NZh0KmF8pAKi3AYRblKA/3lRwOfEDlYgyPntypqKWTHGOLXw obUuMQFZboL9aDOoN+SuOg571Vg3NPN5hA== X-Received: by 2002:a05:6a00:14d0:: with SMTP id w16mr1478201pfu.39.1598624422182; Fri, 28 Aug 2020 07:20:22 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 40/76] target/microblaze: Convert dec_and, dec_or, dec_xor to decodetree Date: Fri, 28 Aug 2020 07:18:53 -0700 Message-Id: <20200828141929.77854-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 12 +++++++++ target/microblaze/translate.c | 46 ++++++++++++---------------------- 2 files changed, 28 insertions(+), 30 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 16519f05dc..93bd51c78b 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -41,9 +41,18 @@ addic 001010 ..... ..... ................ @typeb addik 001100 ..... ..... ................ @typeb addikc 001110 ..... ..... ................ @typeb +and 100001 ..... ..... ..... 000 0000 0000 @typea +andi 101001 ..... ..... ................ @typeb + +andn 100011 ..... ..... ..... 000 0000 0000 @typea +andni 101011 ..... ..... ................ @typeb + cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +or 100000 ..... ..... ..... 000 0000 0000 @typea +ori 101000 ..... ..... ................ @typeb + pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea @@ -57,3 +66,6 @@ rsubi 001001 ..... ..... ................ @typeb rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb + +xor 100010 ..... ..... ..... 000 0000 0000 @typea +xori 101010 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7ebf0e1e7d..a143f17e9d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -331,6 +331,16 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) +static void gen_andni(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + tcg_gen_andi_i32(out, ina, ~imm); +} + +DO_TYPEA(and, false, tcg_gen_and_i32) +DO_TYPEBI(andi, false, tcg_gen_andi_i32) +DO_TYPEA(andn, false, tcg_gen_andc_i32) +DO_TYPEBI(andni, false, gen_andni) + static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 lt = tcg_temp_new_i32(); @@ -354,6 +364,9 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +DO_TYPEA(or, false, tcg_gen_or_i32) +DO_TYPEBI(ori, false, tcg_gen_ori_i32) + static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); @@ -417,6 +430,9 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) +DO_TYPEA(xor, false, tcg_gen_xor_i32) +DO_TYPEBI(xori, false, tcg_gen_xori_i32) + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -431,33 +447,6 @@ static bool trans_zero(DisasContext *dc, arg_zero *arg) return false; } -static void dec_and(DisasContext *dc) -{ - unsigned int not; - - not = dc->opcode & (1 << 1); - - if (!dc->rd) - return; - - if (not) { - tcg_gen_andc_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - } else - tcg_gen_and_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - -static void dec_or(DisasContext *dc) -{ - if (dc->rd) - tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - -static void dec_xor(DisasContext *dc) -{ - if (dc->rd) - tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - static void msr_read(DisasContext *dc, TCGv_i32 d) { TCGv_i32 t; @@ -1581,9 +1570,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_AND, dec_and}, - {DEC_XOR, dec_xor}, - {DEC_OR, dec_or}, {DEC_BIT, dec_bit}, {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, From patchwork Fri Aug 28 14:18:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248547 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1137134ilg; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 77 ++++++++++++++-------------------- 2 files changed, 37 insertions(+), 46 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 93bd51c78b..1a2e22e44a 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -50,6 +50,12 @@ andni 101011 ..... ..... ................ @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +mul 010000 ..... ..... ..... 000 0000 0000 @typea +mulh 010000 ..... ..... ..... 000 0000 0001 @typea +mulhu 010000 ..... ..... ..... 000 0000 0011 @typea +mulhsu 010000 ..... ..... ..... 000 0000 0010 @typea +muli 011000 ..... ..... ................ @typeb + or 100000 ..... ..... ..... 000 0000 0000 @typea ori 101000 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a143f17e9d..617e208583 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -287,6 +287,10 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } +#define DO_TYPEBI_CFG(NAME, CFG, SE, FNI) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return dc->cpu->cfg.CFG && do_typeb_imm(dc, a, SE, FNI); } + #define DO_TYPEBV(NAME, SE, FN) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_val(dc, a, SE, FN); } @@ -364,6 +368,33 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_muls2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +static void gen_mulhu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mulu2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +static void gen_mulhsu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mulsu2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +DO_TYPEA_CFG(mul, use_hw_mul, false, tcg_gen_mul_i32) +DO_TYPEA_CFG(mulh, use_hw_mul >= 2, false, gen_mulh) +DO_TYPEA_CFG(mulhu, use_hw_mul >= 2, false, gen_mulhu) +DO_TYPEA_CFG(mulhsu, use_hw_mul >= 2, false, gen_mulhsu) +DO_TYPEBI_CFG(muli, use_hw_mul, false, tcg_gen_muli_i32) + DO_TYPEA(or, false, tcg_gen_or_i32) DO_TYPEBI(ori, false, tcg_gen_ori_i32) @@ -652,51 +683,6 @@ static void dec_msr(DisasContext *dc) } } -/* Multiplier unit. */ -static void dec_mul(DisasContext *dc) -{ - TCGv_i32 tmp; - unsigned int subcode; - - if (trap_illegal(dc, !dc->cpu->cfg.use_hw_mul)) { - return; - } - - subcode = dc->imm & 3; - - if (dc->type_b) { - tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - return; - } - - /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ - if (subcode >= 1 && subcode <= 3 && dc->cpu->cfg.use_hw_mul < 2) { - /* nop??? */ - } - - tmp = tcg_temp_new_i32(); - switch (subcode) { - case 0: - tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 1: - tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 3: - tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - default: - cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); - break; - } - tcg_temp_free_i32(tmp); -} - /* Div unit. */ static void dec_div(DisasContext *dc) { @@ -1579,7 +1565,6 @@ static struct decoder_info { {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_FPU, dec_fpu}, - {DEC_MUL, dec_mul}, {DEC_DIV, dec_div}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, From patchwork Fri Aug 28 14:18:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248534 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1131819ilg; Fri, 28 Aug 2020 07:31:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxQ2ftNzOswXMdq/nlO3EmtNUEMpot0EZjij0aVX4/a8o966A+fkt1D0EqjuMeQM0PYpGtH X-Received: by 2002:a25:4251:: with SMTP id p78mr2702596yba.306.1598625071434; Fri, 28 Aug 2020 07:31:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625071; cv=none; d=google.com; s=arc-20160816; b=Ftx6cwE3nM66OHM6IVh+hgiAY9exblszSqeNA7rAUyfXWTmejb4xosbbBjSsGkZ9Db twUE+BUZ+uVAFH1R6OcSFUXlxCkErNOcPMr29GoOpAhXaX8sJVTOD18ntBd5LkmK6osk zA5QfgDlHEvLwFNYTLZblWfbcj2Klb/RxLSWTjPs0/BWVRE01aX948T18KcFQlD5Ku3T 1HqvewSK8CybKoW+b8luN8b0TT4y81ou8pdFoNqNofuUUlgmN8wSFyJPpTfbH9iSPxqq 2IY2Qoeiipf/Vn+HJUsC14CMnhVykM8nrBK6wFhli90ZRK1Q5Fzv/wbmFuq1J2XjQneB Oi2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hr7Ho+g+bgpcDeEBrTLXrsm1Zc/M5hF3iPitiFsO4bo=; b=yD2KbLuuK6u5z4hpQnjJ9HrbV3BDV16hiab7gYVzCF1Lgx0nk8N510wGXiWS5//D1w X087GrFRIzEF0S3JdAZXKsyI4dYSxPUzFNdEsAgR2/ZIUeARWzphf5x2Nr9vmezQI8d7 fkmkHbhUIKpKxhOMKT7VyizKOaW251NbnN8+a/Zb9OzhWO9Aefx9GkCfVM1DF1McL9/7 Mk6sn6IhAC1c1KCAtuno0G3Ke3jv33BrI8Y/aFw0b6jqYn0OmT1ZDc4EoafkQHrf0CSn zp141PUd6XVkakOtHaT/Rr8TjPJVd5O7OfSUywFh0rFetcWGRYDMSNNFc2UDHcVmqWw0 MPtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rCJEAKQ5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 195si1084950ybe.452.2020.08.28.07.31.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:31:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rCJEAKQ5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfPK-0004LU-Sw for patch@linaro.org; Fri, 28 Aug 2020 10:31:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51498) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfEy-0001FU-Bx for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:28 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:38255) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEw-0005FI-Ar for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:28 -0400 Received: by mail-pf1-x443.google.com with SMTP id d22so738830pfn.5 for ; Fri, 28 Aug 2020 07:20:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hr7Ho+g+bgpcDeEBrTLXrsm1Zc/M5hF3iPitiFsO4bo=; b=rCJEAKQ5k22P/Ge7NP5z3Ds4h2F1hJsdAZ7l8B7wB3PYZVJ+QaZIDEEj8qrXEy2pdZ gT/5qf+6V96BqpRo7rYybQQ2Xq8wWV/HDpaPUCBXkokxAqcPMvur/dytBuPhh+x6viO6 lTK0kL0cCpNW6ToKD+cD0bkhMcY3fdRE1h2lGO/6RP0iUhZj1QtZY6KYTMuCwq1pGprW NikGe5cPWcEXJSvEwL1r0PUtpRvR1MIkJPJ014cU1h9aqihiBE9kI+RS2axscdB49Jml ZnoMp3l2lp0BiHbBCmWe4wFUjnCAwKntJQZcnoawBpwvjSirYp6B1c8uR5dXZz6lXv61 1vXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hr7Ho+g+bgpcDeEBrTLXrsm1Zc/M5hF3iPitiFsO4bo=; b=dWlL2Y9eHfpJhFyo8iOIYZ5J8qc00RMSfGu69w8cpeEykeu3cMDB0e77KcmfVuILZE iqmf0Wc0d9QdJmWmQY27NUmeNasR/f9rIGrseBAL4ZKBy2etV/rlj5Cz+/X4jja9fKOk 8ejXfS3pOYKfZDvxHtNxakFgBJZFdZEYxfvGgrC/2td9i4fvTVoge9Y4kxCKPEausMae cJob9CyPBWFbIrXSkwFOeuMK5skZwi/+VyvthWRpL5fUChPWK99ZwTG6PyPmwsCuYVWI tj7sJc8MsS41RbIar4NRzqRBuoWHe5WeqYPZqieeBb/hz2hmpkIPQKmnKF9vUutb+Gdz A36A== X-Gm-Message-State: AOAM531kKCvD0htVuTSzjjMqOr7iuhM6MjvUkAogFaqDEvTCX7Owz/Up cuT4n+TPTUSGxs2qZZUMZ7qDsvwskH0RbQ== X-Received: by 2002:a63:fc4b:: with SMTP id r11mr1401780pgk.342.1598624424664; Fri, 28 Aug 2020 07:20:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 42/76] target/microblaze: Convert dec_div to decodetree Date: Fri, 28 Aug 2020 07:18:55 -0700 Message-Id: <20200828141929.77854-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 +++ target/microblaze/translate.c | 35 +++++++++++++--------------------- 2 files changed, 16 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 1a2e22e44a..b2dcbdf784 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -50,6 +50,9 @@ andni 101011 ..... ..... ................ @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +idiv 010010 ..... ..... ..... 000 0000 0000 @typea +idivu 010010 ..... ..... ..... 000 0000 0010 @typea + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 617e208583..9763b9d77c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -368,6 +368,19 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + gen_helper_divs(out, cpu_env, inb, ina); +} + +static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + gen_helper_divu(out, cpu_env, inb, ina); +} + +DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) +DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) + static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp = tcg_temp_new_i32(); @@ -683,27 +696,6 @@ static void dec_msr(DisasContext *dc) } } -/* Div unit. */ -static void dec_div(DisasContext *dc) -{ - unsigned int u; - - u = dc->imm & 2; - - if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { - return; - } - - if (u) - gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), - cpu_R[dc->ra]); - else - gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), - cpu_R[dc->ra]); - if (!dc->rd) - tcg_gen_movi_i32(cpu_R[dc->rd], 0); -} - static void dec_barrel(DisasContext *dc) { TCGv_i32 t0; @@ -1565,7 +1557,6 @@ static struct decoder_info { {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_FPU, dec_fpu}, - {DEC_DIV, dec_div}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} From patchwork Fri Aug 28 14:18:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248550 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1137623ilg; Fri, 28 Aug 2020 07:37:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyyAjRO0/2X2+q+7Ykc3a7xeX40hK+alKFKlBn1okRqtEXwQpWCbVuA7MYB7uxTasv03Nkz X-Received: by 2002:a25:ab0f:: with SMTP id u15mr2942004ybi.7.1598625455995; Fri, 28 Aug 2020 07:37:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625455; cv=none; d=google.com; s=arc-20160816; b=kBGTKjdnH5PpGDeMTgaa/Npmqd4NtpgJdNXMAuZWgysk2LY/JdRJGY4oqZW2ZZ0yca 6RZh/cJt0sFYjWHcVR/Bu6s/w3h78aQz126kJ+/V9wh728I/cGfpK7GnRgpBYycOPXSO EsgT4J4943O88opRxfU/aH+nEeKNYzLSCuZQURvVailjWVErhhDLyoaVW4FWC5IMEyHb o/zUq5Yx1/uQNoi81sWGG84b1bmHEsAe2pX+oVt58VtAYJ8vyAMDDNh9jKvsLe08izno fkuCHjCwCdd3B9Ol2cAHZpE5pUxZXIA7Rgg+LFqW0VrgAtjfuyEsUlqJY81G6VwSrpDd tR8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bQC2NsHcUulzW6D5RhH+hzBIgYR+xbZNPdmPEiO9k08=; b=lzAbqPdJPPjCSCfby5Ek1MJBc5FoVekXls1Xv6v3NeI3AetEIXeNn0HF1/m9Dci5mC ik3jd3ve1sHCFdltBYdpeNL+8BESUnz/ieOY1acDSo5elKhDPSqwEy4eNSPKWtRV9SCe p5UN0zBXwT1K5n1X9wrPBi23yVbz9hU6oC70Tsetxiit+RIF4Ji08gtmPQAhKwSqhm27 QEnr1LOWOyXEROLovLg19MRzEBy6lxDhqmQYImfhLp3y2fJJkn8s4n8L69SsQqZIo1+I YH57SSW4mDZ3xcaIailExA18hjlV8Trnr/048yiM9m4fKBaAN+mnHwpU/RCTrxYAKR9Q Mg2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zg0juVRQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s82si1162282ybb.75.2020.08.28.07.37.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:37:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zg0juVRQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfVX-0001Qu-Eg for patch@linaro.org; Fri, 28 Aug 2020 10:37:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfF0-0001IK-4n for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:30 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:39263) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEx-0005FT-Ms for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:29 -0400 Received: by mail-pj1-x1043.google.com with SMTP id s2so565405pjr.4 for ; Fri, 28 Aug 2020 07:20:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bQC2NsHcUulzW6D5RhH+hzBIgYR+xbZNPdmPEiO9k08=; b=zg0juVRQKbAqwIFtI3G83o+nuPOMDKq6hl5qrzV0gCIOSK5KXRue36QcRz9aLOiwtD aZq/hhprqlcky0GGAoOHd40WCZE1AL9SOuXMlidt/aElwSHW3TaoOvARsY+kweBnnHH/ +AJXRZzbRjlPfdAe8K22PuXZ/U15eThQiN+u8K28xiuspGRAR20iufSG1alQqZL1LAB1 ATDy6zxtvzrsWueFkiGDKG4K3c68yOMuEJDDKWhjcCZo9pdbeyh8Sl23ToNlBvYj2D3Q yfsV8cwoxGsnTVBBVU/gSau62LQg8Zd8JnjTz4q/euIa1aLxt+51N94MhgVuxMaLSq4X 8QhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bQC2NsHcUulzW6D5RhH+hzBIgYR+xbZNPdmPEiO9k08=; b=YYrqnuwAhRj0rcYZMxGojmHxvcOqYQDfIJsm9PKQd8Xk+1bYSidFm8xQwPGXBZ8+pR 336IFGYqUt/moVkf4HmNzH1E6nsUmvK+6a+x3XletejV1Wv50jwNo+O+asWxT9pi8Djj WCv+kNQSU3XvLc8+4qSxNzWCGonIblU1nycPEDyCmv1EULNBTSlPqLyOggmSKPcorMMg DQkdyj2nUHx7H4OGDzzyg0rrwt1/pdNgWF/8FKrqR04LtisHKHx7In7/SwrZYewmORQ0 3tBFMDIFCo+giMDq/fihOk5KAwIk6//cPoly6FMeAXjdB2NRXqlslNy5a2jYCSbQB4hp 02BA== X-Gm-Message-State: AOAM5313r0qfC37t2WErBAHCv2nkiQl0nf9isxBeHUJb2tB7wsQak9Bh u/m45Viz2s1wD4bp8r7aRgNhdXJlV7CJUg== X-Received: by 2002:a17:902:690a:: with SMTP id j10mr1541600plk.155.1598624426000; Fri, 28 Aug 2020 07:20:26 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 43/76] target/microblaze: Unwind properly when raising divide-by-zero Date: Fri, 28 Aug 2020 07:18:56 -0700 Message-Id: <20200828141929.77854-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Restore the correct pc when raising divide-by-zero. Also, the MSR[DZO] bit is sticky -- it is not cleared with a successful divide. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 4 ++-- target/microblaze/op_helper.c | 23 ++++++++++++----------- 2 files changed, 14 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 6f7f96421f..79e1e8ecc7 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,7 +1,7 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_3(divs, i32, env, i32, i32) -DEF_HELPER_3(divu, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_3(fadd, i32, env, i32, i32) DEF_HELPER_3(frsub, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f976d112eb..d99d98051a 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,26 +69,27 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) +static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t ra) { - MicroBlazeCPU *cpu = env_archcpu(env); - - if (b == 0) { + if (unlikely(b == 0)) { env->msr |= MSR_DZ; - if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { + if ((env->msr & MSR_EE) && + env_archcpu(env)->cfg.div_zero_exception) { + CPUState *cs = env_cpu(env); + env->esr = ESR_EC_DIVZERO; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); } - return 0; + return false; } - env->msr &= ~MSR_DZ; - return 1; + return true; } uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(env, a, b)) { + if (!check_divz(env, a, b, GETPC())) { return 0; } return (int32_t)a / (int32_t)b; @@ -96,7 +97,7 @@ uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(env, a, b)) { + if (!check_divz(env, a, b, GETPC())) { return 0; } return a / b; From patchwork Fri Aug 28 14:18:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248537 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1133861ilg; Fri, 28 Aug 2020 07:33:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyYXtv52HL4cFj2TU+DritVYcuijp3PvJeJhDqksTsnNGk/by4vpCiqDHu9mqFfcTCiOmqX X-Received: by 2002:a25:2d13:: with SMTP id t19mr2861757ybt.113.1598625203762; Fri, 28 Aug 2020 07:33:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625203; cv=none; d=google.com; s=arc-20160816; b=IGGe2ECqAlHqcXc/Y7iXV79FB7wI9bHmSAW8OJvs3keZl7ZKJ4cqZ1fYZ+41ffTDqA RjpKOtdrOXy/bLzt3tlk7e/e8FnEJWSE0XZ3XvGVw/PGnCFyeDiexgepnlyVeLB3GirT LGpoOng1FFrXad/G9/ccgIPpHRufdyJDKnUtpbyYAwkJLnHM5QFRVuCh/stkvIlkY7OC Psg7Wr7uaHB3Y81XzxhVV5kT9GXPnPnH7bs8KyZTNrxoocdx4sHWMC/8HJgFqdmCucQj LoAkUpCkfnBZ/MuBg3tGigW+2PoD3FVclAvwmpGndhaA0NZUwwgKZyJtKSHQb1dwMeCh xsbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1p89rcIKDhUfhg0SSJdukaxV9RnhP+FGLvdyYS/byGA=; b=FroIslIF4WKcu9j1XorpbUdKlDyLl4kkX1xZYOls22CSEx/dJh29xezSjcmFOPbajQ YJn9b7fS9xzwO8fBoTsPeWvC4vKTpJqIVNDrYtBKBmg53xAekWqdeSt6UVVPE5j4vtfK vN8nXVreSB1e+fK/Ft8F/GGQXg/zmykSyhTHEBEji8fipvAyNyk8XrckalPp/SNLyJX1 v6YDFrojLn2xBwYwOF/goxLu1aM9ByemCqQ5DQC4XgB1WmGynwUAVvwnvupmCgdVAwRt E3jT6wb/w5ujgr3UuiDgKLU88jkO0Y1yVPN5oWPKT4PEia7j1Ol2kRKtr0m2Tu/nvc6X 2zNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xvl+iwyy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o62si1143119yba.223.2020.08.28.07.33.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:33:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xvl+iwyy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52542 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfRT-0007oD-71 for patch@linaro.org; Fri, 28 Aug 2020 10:33:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfF1-0001L1-Gr for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:31 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:37665) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfEz-0005Fh-0E for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:31 -0400 Received: by mail-pg1-x543.google.com with SMTP id 5so529903pgl.4 for ; Fri, 28 Aug 2020 07:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1p89rcIKDhUfhg0SSJdukaxV9RnhP+FGLvdyYS/byGA=; b=xvl+iwyy7Eqqh0JdouKjIBuUXBqRtjv8faafuGiE2W1ERpLhlQEG207kaYqDdeidz4 mLswnYfbW8vX2No6xReDxgU5lFiNxeSyXJY0+HN/Xx3DFJzibMJhypfrs9rQUv2/wicJ fiDCnYtvZgES55g4VDr6y6HJesuAkGcJktfFOY6ehwGSSi79mvI23aAktw5E/zftbAK1 4+ps22nYABxuvoN4YtCYzrB2pwPS2RLA0s+Z4aTbRsD+8Zii7+Sr2ZMY3OBwzN1dQkss XrofVr0uhX/UNI62JoWpFHYMd+Yw9DrJIpi2p5P26zmaNhh1cmpxcWAruZTt1jddfnRs EMwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1p89rcIKDhUfhg0SSJdukaxV9RnhP+FGLvdyYS/byGA=; b=ZPxIeIdTCxU5Tt3V24hKHsITMn7c/l/gt+/aQ26pO0751byMKASTCRvT+/+sAevDII 8w9Kf/wA25Y7Jdr/Wp+Csl5d/q3avekw5yOaXgoUMPzVHtWCg5YzIDCYMzEDIxnZYKYe M9IU8sNxwBNVkXnrRoG2HmcybHBmvdvFNK/ByEbkL6etV1tfPXBnrkwkVgPdy2ptZCl2 Z+2K1ChqFz+XqnBnC01G3C0pKBUu4kg8gsMXFKvgPXSx6sRw9YRedvYO3MsiA3RQ7yDO o4HtC5ThK8AD2d46Y0qFGVGrCKOjaOq3wINwjQ2suRPefrCVcew/jafR99IEteMefRJN qmkQ== X-Gm-Message-State: AOAM5314j401gdGimXSirI/8y8jOxtvFCFbsXWLwA+M4UL0Zr54BP1c4 78evS0uYSr4C3zZht9ZurH0R6f7KmmyAMw== X-Received: by 2002:a62:5a87:: with SMTP id o129mr1474669pfb.204.1598624427177; Fri, 28 Aug 2020 07:20:27 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 44/76] target/microblaze: Convert dec_bit to decodetree Date: Fri, 28 Aug 2020 07:18:57 -0700 Message-Id: <20200828141929.77854-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 +++++ target/microblaze/translate.c | 148 +++++++++++++++++---------------- 2 files changed, 95 insertions(+), 73 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index b2dcbdf784..d265e36044 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -17,6 +17,7 @@ # License along with this library; if not, see . # +&typea0 rd ra &typea rd ra rb &typeb rd ra imm @@ -26,6 +27,9 @@ @typea ...... rd:5 ra:5 rb:5 ... .... .... &typea @typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm +# Officially typea, but with rb==0, which is not used. +@typea0 ...... rd:5 ra:5 ................ &typea0 + ### { @@ -47,6 +51,8 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +clz 100100 ..... ..... 00000 000 1110 0000 @typea0 + cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea @@ -76,5 +82,19 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +sext8 100100 ..... ..... 00000 000 0110 0000 @typea0 +sext16 100100 ..... ..... 00000 000 0110 0001 @typea0 + +sra 100100 ..... ..... 00000 000 0000 0001 @typea0 +src 100100 ..... ..... 00000 000 0010 0001 @typea0 +srl 100100 ..... ..... 00000 000 0100 0001 @typea0 + +swapb 100100 ..... ..... 00000 001 1110 0000 @typea0 +swaph 100100 ..... ..... 00000 001 1110 0010 @typea0 + +# Cache operations have no effect in qemu: discard the arguments. +wdic 100100 00000 ----- ----- -00 -11- 01-0 # wdc +wdic 100100 00000 ----- ----- 000 0110 1000 # wic + xor 100010 ..... ..... ..... 000 0000 0000 @typea xori 101010 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9763b9d77c..2d57f76548 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -241,6 +241,21 @@ static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, return true; } +static bool do_typea0(DisasContext *dc, arg_typea0 *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra; + + if (arg->rd == 0 && !side_effects) { + return true; + } + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + fn(rd, ra); + return true; +} + static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects, void (*fni)(TCGv_i32, TCGv_i32, int32_t)) { @@ -283,6 +298,14 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } +#define DO_TYPEA0(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ + { return do_typea0(dc, a, SE, FN); } + +#define DO_TYPEA0_CFG(NAME, CFG, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ + { return dc->cpu->cfg.CFG && do_typea0(dc, a, SE, FN); } + #define DO_TYPEBI(NAME, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } @@ -345,6 +368,13 @@ DO_TYPEBI(andi, false, tcg_gen_andi_i32) DO_TYPEA(andn, false, tcg_gen_andc_i32) DO_TYPEBI(andni, false, gen_andni) +static void gen_clz(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_clzi_i32(out, ina, 32); +} + +DO_TYPEA0_CFG(clz, use_pcmp_instr, false, gen_clz) + static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 lt = tcg_temp_new_i32(); @@ -474,6 +504,51 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) +DO_TYPEA0(sext8, false, tcg_gen_ext8s_i32) +DO_TYPEA0(sext16, false, tcg_gen_ext16s_i32) + +static void gen_sra(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_sari_i32(out, ina, 1); +} + +static void gen_src(TCGv_i32 out, TCGv_i32 ina) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_mov_i32(tmp, cpu_msr_c); + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_extract2_i32(out, ina, tmp, 1); + + tcg_temp_free_i32(tmp); +} + +static void gen_srl(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_shri_i32(out, ina, 1); +} + +DO_TYPEA0(sra, false, gen_sra) +DO_TYPEA0(src, false, gen_src) +DO_TYPEA0(srl, false, gen_srl) + +static void gen_swaph(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_rotri_i32(out, ina, 16); +} + +DO_TYPEA0(swapb, false, tcg_gen_bswap32_i32) +DO_TYPEA0(swaph, false, gen_swaph) + +static bool trans_wdic(DisasContext *dc, arg_wdic *a) +{ + /* Cache operations are nops: only check for supervisor mode. */ + trap_userspace(dc, true); + return true; +} + DO_TYPEA(xor, false, tcg_gen_xor_i32) DO_TYPEBI(xori, false, tcg_gen_xori_i32) @@ -754,78 +829,6 @@ static void dec_barrel(DisasContext *dc) } } -static void dec_bit(DisasContext *dc) -{ - CPUState *cs = CPU(dc->cpu); - TCGv_i32 t0; - unsigned int op; - - op = dc->ir & ((1 << 9) - 1); - switch (op) { - case 0x21: - /* src. */ - t0 = tcg_temp_new_i32(); - - tcg_gen_shli_i32(t0, cpu_msr_c, 31); - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); - if (dc->rd) { - tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); - } - tcg_temp_free_i32(t0); - break; - - case 0x1: - case 0x41: - /* srl. */ - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); - if (dc->rd) { - if (op == 0x41) - tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - else - tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - } - break; - case 0x60: - tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x61: - tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x64: - case 0x66: - case 0x74: - case 0x76: - /* wdc. */ - trap_userspace(dc, true); - break; - case 0x68: - /* wic. */ - trap_userspace(dc, true); - break; - case 0xe0: - if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { - return; - } - if (dc->cpu->cfg.use_pcmp_instr) { - tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); - } - break; - case 0x1e0: - /* swapb */ - tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x1e2: - /*swaph */ - tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); - break; - default: - cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", - (uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->rb); - break; - } -} - static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { @@ -1548,7 +1551,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BIT, dec_bit}, {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, {DEC_ST, dec_store}, From patchwork Fri Aug 28 14:18:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248553 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1139377ilg; Fri, 28 Aug 2020 07:39:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwIG7CNW11xQHohvOODAixIoYvV3biP2HzV6oGQrj0SWIYKLNHlsjza0a2TMPyLm+GY1Yxr X-Received: by 2002:a25:d917:: with SMTP id q23mr2675554ybg.450.1598625589300; Fri, 28 Aug 2020 07:39:49 -0700 (PDT) ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 ++++++ target/microblaze/translate.c | 125 +++++++++++++++++---------------- 2 files changed, 86 insertions(+), 59 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index d265e36044..4644defbfe 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -30,6 +30,15 @@ # Officially typea, but with rb==0, which is not used. @typea0 ...... rd:5 ra:5 ................ &typea0 +# Officially typeb, but any immediate extension is unused. +@typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb + +# For convenience, extract the two imm_w/imm_s fields, then pack +# them back together as "imm". Doing this makes it easiest to +# match the required zero at bit 5. +%ieimm 6:5 0:5 +@typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=%ieimm + ### { @@ -51,6 +60,17 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +bsrl 010001 ..... ..... ..... 000 0000 0000 @typea +bsra 010001 ..... ..... ..... 010 0000 0000 @typea +bsll 010001 ..... ..... ..... 100 0000 0000 @typea + +bsrli 011001 ..... ..... 00000 000000 ..... @typeb_bs +bsrai 011001 ..... ..... 00000 010000 ..... @typeb_bs +bslli 011001 ..... ..... 00000 100000 ..... @typeb_bs + +bsefi 011001 ..... ..... 01000 .....0 ..... @typeb_ie +bsifi 011001 ..... ..... 10000 .....0 ..... @typeb_ie + clz 100100 ..... ..... 00000 000 1110 0000 @typea0 cmp 000101 ..... ..... ..... 000 0000 0001 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2d57f76548..964525f75e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -368,6 +368,72 @@ DO_TYPEBI(andi, false, tcg_gen_andi_i32) DO_TYPEA(andn, false, tcg_gen_andc_i32) DO_TYPEBI(andni, false, gen_andni) +static void gen_bsra(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_sar_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_shr_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_shl_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsefi(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + /* Note that decodetree has extracted and reassembled imm_w/imm_s. */ + int imm_w = extract32(imm, 5, 5); + int imm_s = extract32(imm, 0, 5); + + if (imm_w + imm_s > 32 || imm_w == 0) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", + imm_w, imm_s); + } else { + tcg_gen_extract_i32(out, ina, imm_s, imm_w); + } +} + +static void gen_bsifi(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + /* Note that decodetree has extracted and reassembled imm_w/imm_s. */ + int imm_w = extract32(imm, 5, 5); + int imm_s = extract32(imm, 0, 5); + int width = imm_w - imm_s + 1; + + if (imm_w < imm_s) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", + imm_w, imm_s); + } else { + tcg_gen_deposit_i32(out, out, ina, imm_s, width); + } +} + +DO_TYPEA_CFG(bsra, use_barrel, false, gen_bsra) +DO_TYPEA_CFG(bsrl, use_barrel, false, gen_bsrl) +DO_TYPEA_CFG(bsll, use_barrel, false, gen_bsll) + +DO_TYPEBI_CFG(bsrai, use_barrel, false, tcg_gen_sari_i32) +DO_TYPEBI_CFG(bsrli, use_barrel, false, tcg_gen_shri_i32) +DO_TYPEBI_CFG(bslli, use_barrel, false, tcg_gen_shli_i32) + +DO_TYPEBI_CFG(bsefi, use_barrel, false, gen_bsefi) +DO_TYPEBI_CFG(bsifi, use_barrel, false, gen_bsifi) + static void gen_clz(TCGv_i32 out, TCGv_i32 ina) { tcg_gen_clzi_i32(out, ina, 32); @@ -771,64 +837,6 @@ static void dec_msr(DisasContext *dc) } } -static void dec_barrel(DisasContext *dc) -{ - TCGv_i32 t0; - unsigned int imm_w, imm_s; - bool s, t, e = false, i = false; - - if (trap_illegal(dc, !dc->cpu->cfg.use_barrel)) { - return; - } - - if (dc->type_b) { - /* Insert and extract are only available in immediate mode. */ - i = extract32(dc->imm, 15, 1); - e = extract32(dc->imm, 14, 1); - } - s = extract32(dc->imm, 10, 1); - t = extract32(dc->imm, 9, 1); - imm_w = extract32(dc->imm, 6, 5); - imm_s = extract32(dc->imm, 0, 5); - - if (e) { - if (imm_w + imm_s > 32 || imm_w == 0) { - /* These inputs have an undefined behavior. */ - qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", - imm_w, imm_s); - } else { - tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w); - } - } else if (i) { - int width = imm_w - imm_s + 1; - - if (imm_w < imm_s) { - /* These inputs have an undefined behavior. */ - qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", - imm_w, imm_s); - } else { - tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra], - imm_s, width); - } - } else { - t0 = tcg_temp_new_i32(); - - tcg_gen_mov_i32(t0, *(dec_alu_op_b(dc))); - tcg_gen_andi_i32(t0, t0, 31); - - if (s) { - tcg_gen_shl_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } else { - if (t) { - tcg_gen_sar_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } else { - tcg_gen_shr_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } - } - tcg_temp_free_i32(t0); - } -} - static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { @@ -1551,7 +1559,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, {DEC_ST, dec_store}, {DEC_IMM, dec_imm}, From patchwork Fri Aug 28 14:18:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248554 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1139400ilg; Fri, 28 Aug 2020 07:39:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7oKcZa73smZ6jFs4Iiu2+LpTXwBswZQxYpOW+2LktW0dXtrx+XK+YNckc02hhqAr4bRrN X-Received: by 2002:a25:f42:: with SMTP id 63mr2978859ybp.348.1598625591185; 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[209.51.188.17]) by mx.google.com with ESMTPS id 72si1111803ybf.295.2020.08.28.07.39.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:39:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="mlqP/lXH"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfXi-0004uH-Kr for patch@linaro.org; Fri, 28 Aug 2020 10:39:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfF3-0001N9-0S for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:33 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:42414) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfF1-0005G1-8b for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:32 -0400 Received: by mail-pf1-x441.google.com with SMTP id 17so730586pfw.9 for ; Fri, 28 Aug 2020 07:20:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UD6YQPwqrNk8aVHv/Pbf8iTSNfjWSSiBgehdYJhx7tU=; b=mlqP/lXHcJ+i+A0RZwyKXETVs2fnnodznLFd7sZOKCkABHtOqDlWQk6TUShhqlfUeS uONuvkmvFSuZJB0VJ2PkeQg9UbdzsWvB1ISLVg8vxhiTj4cDRb3t6Ef9AjWQIvuhxeA/ 65quXobR3U4w+PX2rHGp9tdXL0met06OTLU42kDUCdkFvsgsJd9DxI0PIUT+DAT4edOK SyBlLz6FdJ7nLVkBJRVfZNHGLZoHI7WlPe8RuUoSeUMZ1c3Ks2ia9ERVwk1u/ipg3fjP 1kZHcJdp5OGY5o3+HAjRQTs/5eGtQDhT5e1sznFd+TvtFtdQDgCSckNBwIxE1dd11Qcf 7JIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UD6YQPwqrNk8aVHv/Pbf8iTSNfjWSSiBgehdYJhx7tU=; b=kzsZTgkTM8x5u6wxR2sNdMnhvFKOXe6IdIwK4zJTje/D3FRGYt/rxRzDVR7SkNhvmP u/FOvfk8GoYYaR88S3kK9Dks/b6flXbM17CZ4fe/DfvUxNFXl67xnOcpcGitHwn/IyXY aq13/BU21l6lJocPtqYYa945lNYOuArXAqguoRv8w/DxuVHpYUA36LqsHrmSPiBjLadO nfXaEq89vtp85O8EaMQwKc4qz6Rpsb9JCLnsQZi1NlHBdFNCQfrh1sJJjbrMFirYbMxN UnTZISHxxTY3ZvPX1gNUV3nOcR0XhtYx5Ifne4qxPaqSTeKmcuZR3JZ8AD15x2IZ1zyv g54w== X-Gm-Message-State: AOAM532CcnrnwyLx8gGbkZu+926gZfRF4bt70c8aRJ9h2+V7AgwjMabi 2GBO/lLSVMqzV+PFc1S36Xu9u14HZYsBnQ== X-Received: by 2002:a62:17d5:: with SMTP id 204mr1474738pfx.109.1598624429658; Fri, 28 Aug 2020 07:20:29 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 46/76] target/microblaze: Convert dec_imm to decodetree Date: Fri, 28 Aug 2020 07:18:59 -0700 Message-Id: <20200828141929.77854-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 2 ++ target/microblaze/translate.c | 18 +++++++++--------- 2 files changed, 11 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 4644defbfe..ad15c16f9b 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -79,6 +79,8 @@ cmpu 000101 ..... ..... ..... 000 0000 0011 @typea idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea +imm 101100 00000 00000 imm:16 + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 964525f75e..54de136a16 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -477,6 +477,15 @@ static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) +static bool trans_imm(DisasContext *dc, arg_imm *arg) +{ + dc->ext_imm = arg->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); + dc->tb_flags |= IMM_FLAG; + dc->clear_imm = 0; + return true; +} + static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp = tcg_temp_new_i32(); @@ -848,14 +857,6 @@ static inline void sync_jmpstate(DisasContext *dc) } } -static void dec_imm(DisasContext *dc) -{ - dc->ext_imm = dc->imm << 16; - tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags |= IMM_FLAG; - dc->clear_imm = 0; -} - static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) { /* Should be set to true if r1 is used by loadstores. */ @@ -1561,7 +1562,6 @@ static struct decoder_info { } decinfo[] = { {DEC_LD, dec_load}, {DEC_ST, dec_store}, - {DEC_IMM, dec_imm}, {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, From patchwork Fri Aug 28 14:19:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248541 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1134759ilg; Fri, 28 Aug 2020 07:34:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzTTLaOKuim/R5PI2A7K06UA+5eMEDehPpqhc6NqnojBudj9mDQejMpm5vRUu4GPVmaeRfA X-Received: by 2002:a25:fc22:: with SMTP id v34mr2628294ybd.393.1598625263071; Fri, 28 Aug 2020 07:34:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625263; cv=none; d=google.com; s=arc-20160816; b=Ti8DJSq+eCAmtHmo2tOfi7IbSgIEaZeUYdueFvp88FcoG3Mm7VNbesYoL+QjNzAq/u AdTb7nCWvR1eZ9A+/cAW5XQa3CzD1fM9snmASYvtyByyT+wocFveTMiDe+KregH/31Nb EgXHvrUcpXOI8j+kt0C+Dlv+GHv3W4EMuxz8egOEhbyUXsdgk4YwYRhOtazHEftD3W3K oDycLJuE6gw6DCCeZmPHM292vZkfNVDTTiXgFzTkDBtJJEV2Thezn7z9y5JrFdDGj4M9 GI5UUy2cFb4Qg2X9AoY7mJSDACFPeKYObYH4q4EUJBA7GXU/iW7eRrweJcVuylu3TZHx 0iCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ANk/oixShuAbduJtUrJKl+/8XzjLIjdJC9lFbwLzidk=; b=kUuG2JIEwbA9LHJjdbmZZhfkQLhPYELliD+UyqfkyDIQA3jsqyQLLavVgg27US+qMz P3Ns758apeNaYtMtZ/lNWSwelf27CF7AT4e1z3qgE5SvLkngnX+wyps2DWuZZwW8tGO2 rM8glFnHuGClMNK9HmsKS8WNJnGlK9ecv5b8C/Gf1im4dj4m+AjPuRG0lAB3tcez9/ZK 5F9The0cuGtP/COM/qFAoW3XDL5oR7iVr201lvsJUkrxnEFaqlBA+h+pe1JS8cIDWJeY gYVXuHcaP1u1HTEUF+/oocbtEGYxYSdXjAY/phfmmcGeCF//1eFEC6C7Ry2PsyVNn+pO XzIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LzKrsEC3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The current dec_check_fpuv2 test, raising an FPU exception for an unimplemented instruction, appears to be contradictory to the manual. Drop that and merely check use_fpu == 2. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 19 +++++ target/microblaze/translate.c | 152 +++++++++------------------------ 2 files changed, 60 insertions(+), 111 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index ad15c16f9b..87e8f5679b 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -76,6 +76,25 @@ clz 100100 ..... ..... 00000 000 1110 0000 @typea0 cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +fadd 010110 ..... ..... ..... 0000 000 0000 @typea +frsub 010110 ..... ..... ..... 0001 000 0000 @typea +fmul 010110 ..... ..... ..... 0010 000 0000 @typea +fdiv 010110 ..... ..... ..... 0011 000 0000 @typea +fcmp_un 010110 ..... ..... ..... 0100 000 0000 @typea +fcmp_lt 010110 ..... ..... ..... 0100 001 0000 @typea +fcmp_eq 010110 ..... ..... ..... 0100 010 0000 @typea +fcmp_le 010110 ..... ..... ..... 0100 011 0000 @typea +fcmp_gt 010110 ..... ..... ..... 0100 100 0000 @typea +fcmp_ne 010110 ..... ..... ..... 0100 101 0000 @typea +fcmp_ge 010110 ..... ..... ..... 0100 110 0000 @typea + +# Note that flt and fint, unlike fsqrt, are documented as having the RB +# operand which is unused. So allow the field to be non-zero but discard +# the value and treat as 2-operand insns. +flt 010110 ..... ..... ----- 0101 000 0000 @typea0 +fint 010110 ..... ..... ----- 0110 000 0000 @typea0 +fsqrt 010110 ..... ..... 00000 0111 000 0000 @typea0 + idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 54de136a16..72541905ec 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -318,6 +318,14 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_val(dc, a, SE, FN); } +#define ENV_WRAPPER2(NAME, HELPER) \ + static void NAME(TCGv_i32 out, TCGv_i32 ina) \ + { HELPER(out, cpu_env, ina); } + +#define ENV_WRAPPER3(NAME, HELPER) \ + static void NAME(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) \ + { HELPER(out, cpu_env, ina, inb); } + /* No input carry, but output carry. */ static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { @@ -464,6 +472,39 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +ENV_WRAPPER3(gen_fadd, gen_helper_fadd) +ENV_WRAPPER3(gen_frsub, gen_helper_frsub) +ENV_WRAPPER3(gen_fmul, gen_helper_fmul) +ENV_WRAPPER3(gen_fdiv, gen_helper_fdiv) +ENV_WRAPPER3(gen_fcmp_un, gen_helper_fcmp_un) +ENV_WRAPPER3(gen_fcmp_lt, gen_helper_fcmp_lt) +ENV_WRAPPER3(gen_fcmp_eq, gen_helper_fcmp_eq) +ENV_WRAPPER3(gen_fcmp_le, gen_helper_fcmp_le) +ENV_WRAPPER3(gen_fcmp_gt, gen_helper_fcmp_gt) +ENV_WRAPPER3(gen_fcmp_ne, gen_helper_fcmp_ne) +ENV_WRAPPER3(gen_fcmp_ge, gen_helper_fcmp_ge) + +DO_TYPEA_CFG(fadd, use_fpu, true, gen_fadd) +DO_TYPEA_CFG(frsub, use_fpu, true, gen_frsub) +DO_TYPEA_CFG(fmul, use_fpu, true, gen_fmul) +DO_TYPEA_CFG(fdiv, use_fpu, true, gen_fdiv) +DO_TYPEA_CFG(fcmp_un, use_fpu, true, gen_fcmp_un) +DO_TYPEA_CFG(fcmp_lt, use_fpu, true, gen_fcmp_lt) +DO_TYPEA_CFG(fcmp_eq, use_fpu, true, gen_fcmp_eq) +DO_TYPEA_CFG(fcmp_le, use_fpu, true, gen_fcmp_le) +DO_TYPEA_CFG(fcmp_gt, use_fpu, true, gen_fcmp_gt) +DO_TYPEA_CFG(fcmp_ne, use_fpu, true, gen_fcmp_ne) +DO_TYPEA_CFG(fcmp_ge, use_fpu, true, gen_fcmp_ge) + +ENV_WRAPPER2(gen_flt, gen_helper_flt) +ENV_WRAPPER2(gen_fint, gen_helper_fint) +ENV_WRAPPER2(gen_fsqrt, gen_helper_fsqrt) + +DO_TYPEA0_CFG(flt, use_fpu >= 2, true, gen_flt) +DO_TYPEA0_CFG(fint, use_fpu >= 2, true, gen_fint) +DO_TYPEA0_CFG(fsqrt, use_fpu >= 2, true, gen_fsqrt) + +/* Does not use ENV_WRAPPER3, because arguments are swapped as well. */ static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { gen_helper_divs(out, cpu_env, inb, ina); @@ -1403,116 +1444,6 @@ static void dec_rts(DisasContext *dc) tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } -static int dec_check_fpuv2(DisasContext *dc) -{ - if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - gen_raise_hw_excp(dc, ESR_EC_FPU); - } - return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; -} - -static void dec_fpu(DisasContext *dc) -{ - unsigned int fpu_insn; - - if (trap_illegal(dc, !dc->cpu->cfg.use_fpu)) { - return; - } - - fpu_insn = (dc->ir >> 7) & 7; - - switch (fpu_insn) { - case 0: - gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 1: - gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 2: - gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 3: - gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 4: - switch ((dc->ir >> 4) & 7) { - case 0: - gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 1: - gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 3: - gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 4: - gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 5: - gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 6: - gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - default: - qemu_log_mask(LOG_UNIMP, - "unimplemented fcmp fpu_insn=%x pc=%x" - " opc=%x\n", - fpu_insn, (uint32_t)dc->base.pc_next, - dc->opcode); - dc->abort_at_next_insn = 1; - break; - } - break; - - case 5: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - case 6: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - case 7: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - default: - qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" - " opc=%x\n", - fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode); - dc->abort_at_next_insn = 1; - break; - } -} - static void dec_null(DisasContext *dc) { if (trap_illegal(dc, true)) { @@ -1565,7 +1496,6 @@ static struct decoder_info { {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, - {DEC_FPU, dec_fpu}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} From patchwork Fri Aug 28 14:19:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248556 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1140445ilg; Fri, 28 Aug 2020 07:41:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyc0vfRUw72Y/915ESy3dNLjtVsr4XvsHw4inXyw2SKZYibLhHktCZjEMTIOXzioY6BwkZ0 X-Received: by 2002:a25:6612:: with SMTP id a18mr3166931ybc.267.1598625667894; Fri, 28 Aug 2020 07:41:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625667; cv=none; d=google.com; s=arc-20160816; b=GSRHzK8nTbLXOiJi+UQn2vl2/k6K1y/PBVcG/KGJDoVFNk5KZQMrrkANLRUxYikR3u yYZGG74M4Z2eKI80pktwDq5s6w2K7z9hDVWo1yNa5FlD+cuvmooXmozZ6WHhBSgZh6s4 rx6JM/txP6n4FohrC1jddNuMvXrvtOoMqqY/cke7MOOEXeMmzlTr9Pe4RL4nZFcPqyfN qTfEW5aOMSfQ0C6xzsf0T454idbXdatdhMhMUUOkegEV/ZdAvRTUjuPJsv5qjL8Y5bcZ F7VMSNTNpD353e+8q3y6JCsSls0R0Ul20UpEw4Li2BFVXKgeDli3z+MzlYfIQyu4bmQW EAtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5Gx/7ND2enUqh97byGs4EhjEjQPx9quOoqiJMUHgOSo=; b=PGgb5ghIIv7Zdex98u+YstpSnGsuWu3nwdt8x+oIfK8t+fGMplBkP0xBhWpcdmZ4Lk iJgk8ArI8U7DG9EOPxTyq8eq0AVmYGMT4px0KLNTXQmG3/lckvPdtvbBrgWnS4pikoWu 5VelOJWHBC8pAgYYcQCrlDGtQo8XFgqcwDbdqFc72/r3JDZC0yPbQbJDe+hh00gMzuoQ sH8PVhGb8MQRsC8a4tOfkoYpv5w1OkylERKOoe59AfaIJ+N2I7dxvObekcNg6fKnoSCU 3cULAyTrE8N19beImCR3jOGZPMAKgGwgmSBtuzstE1KjvRmlsMWvCHqp+nUvd31iQ0VC JCXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qA5mw518; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Restore the correct PC when an exception must be raised. Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 37 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index d99d98051a..2c59d4492d 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -104,13 +104,16 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) } /* raise FPU exception. */ -static void raise_fpu_exception(CPUMBState *env) +static void raise_fpu_exception(CPUMBState *env, uintptr_t ra) { + CPUState *cs = env_cpu(env); + env->esr = ESR_EC_FPU; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); } -static void update_fpu_flags(CPUMBState *env, int flags) +static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) { int raise = 0; @@ -133,7 +136,7 @@ static void update_fpu_flags(CPUMBState *env, int flags) if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) && (env->msr & MSR_EE)) { - raise_fpu_exception(env); + raise_fpu_exception(env, ra); } } @@ -148,7 +151,7 @@ uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) fd.f = float32_add(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -162,7 +165,7 @@ uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; fd.f = float32_sub(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -176,7 +179,7 @@ uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; fd.f = float32_mul(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -191,7 +194,7 @@ uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; fd.f = float32_div(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -206,7 +209,7 @@ uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) if (float32_is_signaling_nan(fa.f, &env->fp_status) || float32_is_signaling_nan(fb.f, &env->fp_status)) { - update_fpu_flags(env, float_flag_invalid); + update_fpu_flags(env, float_flag_invalid, GETPC()); r = 1; } @@ -229,7 +232,7 @@ uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; r = float32_lt(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -245,7 +248,7 @@ uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; r = float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -261,7 +264,7 @@ uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = float32_le(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; @@ -277,7 +280,7 @@ uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = float32_lt(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -291,7 +294,7 @@ uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -306,7 +309,7 @@ uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = !float32_lt(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -330,7 +333,7 @@ uint32_t helper_fint(CPUMBState *env, uint32_t a) fa.l = a; r = float32_to_int32(fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return r; } @@ -344,7 +347,7 @@ uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) fa.l = a; fd.l = float32_sqrt(fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that FSR is no longer a tcg global temp, we can say that the fpu helpers do not write to tcg temps. All temps are read implicitly by the fpu exception path. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 79e1e8ecc7..64816c89e1 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -3,21 +3,21 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) -DEF_HELPER_3(fadd, i32, env, i32, i32) -DEF_HELPER_3(frsub, i32, env, i32, i32) -DEF_HELPER_3(fmul, i32, env, i32, i32) -DEF_HELPER_3(fdiv, i32, env, i32, i32) -DEF_HELPER_2(flt, i32, env, i32) -DEF_HELPER_2(fint, i32, env, i32) -DEF_HELPER_2(fsqrt, i32, env, i32) +DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(frsub, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_2(flt, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_2(fint, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_2(fsqrt, TCG_CALL_NO_WG, i32, env, i32) -DEF_HELPER_3(fcmp_un, i32, env, i32, i32) -DEF_HELPER_3(fcmp_lt, i32, env, i32, i32) -DEF_HELPER_3(fcmp_eq, i32, env, i32, i32) -DEF_HELPER_3(fcmp_le, i32, env, i32, i32) -DEF_HELPER_3(fcmp_gt, i32, env, i32, i32) -DEF_HELPER_3(fcmp_ne, i32, env, i32, i32) -DEF_HELPER_3(fcmp_ge, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_un, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_lt, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_eq, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_le, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_gt, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) #if !defined(CONFIG_USER_ONLY) From patchwork Fri Aug 28 14:19:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248561 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1141873ilg; Fri, 28 Aug 2020 07:43:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxMoqduao2llBB4NS5TqUHGAjrd1s2PHyY4RMVlbAF4X4ITccBNoQGLwELnybvDGIvVZXTt X-Received: by 2002:a25:1f44:: with SMTP id f65mr3043836ybf.438.1598625781717; Fri, 28 Aug 2020 07:43:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625781; cv=none; d=google.com; s=arc-20160816; b=meP1JaZ90RGWwv5lOf0ikWyu6yKO4OoWYgVNhhF1BvobEolYNp44m4RKBUkkDvTNzm IGzYriKdh2pSyQzG7q7QBrRkxHr10wQBk2NDUv1XxVO8zQUB0mJcYPSm7KIe+xxygMsy wC4hndvxUeWNSNr2qKeEGMf9NrjITUkUJXBWBO7DiUkHTv3iRurr+OxCngko+l9Ixtlk epaViYfKlSBPhP75ta0LxPlKkT4vL/RmBOgLqtUUJC3vTK0oLLU2Cl1XOZcQs1dgNipb qTDDYTIemv4AS7my7rFYmWmzTsFh2M3+E4BABne5b0iZiwMLtKKiatHr4SHDJ8wL0/pE vpvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NRLeu0duKzKFzn8XTETT/ccAhISS+EWPP5zocKzGJT0=; b=xRx2AasfivnBReMiL/fhYgYZkaDG7Ii731OASo877YrWK5iDo45QiHHX1jTrxNd5SX t9mLA+KUrBjqr/ZN/fBWx+nHI0BOgbjeUBF8KqDELnR0A36XUoR7rUmQ/Wuw4JT/a4u3 D30uPH1Ns19zgFKkLRpo7X/DR4Rn2ntgt58iT9adc+I+gr6ccKMVBFqRuGLSP4Yog8eo o33G0qsY81dDUf1uKDdj5WjUeuoh6kF7gZxJSNDtyijj/bg7CJNYULTt8+XOZesZY1qq 6RWq4KC2S1vn6uiEWXZN+H4rY2sDcb6MF7dKZyPNLb8dwD0XFlvOLNJG7vvnErI6ocWz VwIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PnPZbre5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g26si1013896ybe.40.2020.08.28.07.43.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:43:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PnPZbre5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfan-0003GJ-30 for patch@linaro.org; Fri, 28 Aug 2020 10:43:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFB-0001aO-2t for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:41 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:33819) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfF6-0005HM-B4 for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:40 -0400 Received: by mail-pg1-x541.google.com with SMTP id i10so536426pgk.1 for ; Fri, 28 Aug 2020 07:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NRLeu0duKzKFzn8XTETT/ccAhISS+EWPP5zocKzGJT0=; b=PnPZbre5EAruWNThBF09eEr6vSA3daKHXbZEIrItDwVgFDlcRwDKIvRIsiOpya+QyI qmIolpx1uWJ8tMukgZ1/dGgWlQrKCctn/4+GcRD1WG8g0PCw3XxP+Qo8nhWmqiGiHsWV qphQjZvNKFC5frJKO6E5lkZzwOHadgqdB9unSmMKggJ2O/zMrLbCBZ9OaJzAuk/eQjbf HTPRb8dM+0AGeAJqds2S9fLLHYeVGuefBV0ajCQ764jIH1yABbucnM+nVk+W9E0kWeUc j8BrnQbQge2S5nyE/Yg6VD438cuaCFF2tuys4dNAw4di8vNBOX8ZGj1jEa9XAQ/DYJ6K R8ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NRLeu0duKzKFzn8XTETT/ccAhISS+EWPP5zocKzGJT0=; b=dW16SbXEbJ/OMJu0GKWky58qDQEeyTxPARSdLXLczpeh/gBLWnaEIuff+JHLK4wdHi 8QMxsTswV3unNyBUJssMSBa55G6z/EZ4D7eVESWbVCBo8ud2+Il+qbGmOMn73303kDof OTkbGQAXJYVGVX4G6jdtwC693pBj7y20d0j/XrYCLWCXFDpJSkzAl45IGwFq7riJWsMP m+J8uib6qs7sIDhObQpWDLwdHTU23pcsQ7W6l8TLCh4A+ELE/+a3wl1IGeErz45S977L Z7XJxhKqRfG7bpQ/OfgwjxgYSlhBTbBaCfbravqWjW+2bxwtYFOsDAeHdV59iKFL84NO UIcA== X-Gm-Message-State: AOAM5337wjXbsQ3eiO1LuhhqVr6FcvLcKwDN4yk5wCiayq8jSjG08p5w HTmQe0tpn13MCnuSJWb55iw8wYxkGuyPxw== X-Received: by 2002:a63:e74e:: with SMTP id j14mr1399497pgk.182.1598624434688; Fri, 28 Aug 2020 07:20:34 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 50/76] target/microblaze: Replace MSR_EE_FLAG with MSR_EE Date: Fri, 28 Aug 2020 07:19:03 -0700 Message-Id: <20200828141929.77854-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There's no reason to define MSR_EE_FLAG; we can just use the original MSR_EE define. Document the other flags copied into tb_flags with iflag to reserve those bits. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +++- target/microblaze/translate.c | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 013858b8e0..594501e4e7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -254,7 +254,9 @@ struct CPUMBState { /* Internal flags. */ #define IMM_FLAG 4 -#define MSR_EE_FLAG (1 << 8) +/* MSR_EE (1 << 8) */ +/* MSR_UM (1 << 11) */ +/* MSR_VM (1 << 13) */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 72541905ec..1f6731e0af 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -162,7 +162,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) */ static bool trap_illegal(DisasContext *dc, bool cond) { - if (cond && (dc->tb_flags & MSR_EE_FLAG) + if (cond && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.illegal_opcode_exception) { gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); } @@ -178,7 +178,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) int mem_index = cpu_mmu_index(&dc->cpu->env, false); bool cond_user = cond && mem_index == MMU_USER_IDX; - if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { + if (cond_user && (dc->tb_flags & MSR_EE)) { gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); } return cond_user; From patchwork Fri Aug 28 14:19:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248559 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1141569ilg; Fri, 28 Aug 2020 07:42:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxiSEzKXvRSaasqS2ELXOnuwD4f1qQsiIJGtK5c8l2dEMYySkeH2hehB4pON5O8hpgximzB X-Received: by 2002:a25:5094:: with SMTP id e142mr2744902ybb.99.1598625757380; Fri, 28 Aug 2020 07:42:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625757; cv=none; d=google.com; s=arc-20160816; b=TZ0FyPEgQIwa0PkAXdARgktprmU9V5GXY0c7NJhIll4jcjyGtkKq34e3mwYFcmWExg t/t/HnnEY2nBx7xQrL85btHA6jENiB6q6o03tBuPpOS/2AHFOvW45KeVE/SPlZ5SWnXy CZte2JUmlHMpgamOQ/od3NZE1J2OLHQn3/G+ocs+/QGUC/eiYhKVU+auFZRM0gwKx1mH NHGUzASb+8mVPxQKjYiLJ4kazmDNinMrXbejaXaa5SFbF/NzBMEXOQ+wvjCTf78x26db +Zc1QE55DVXVUS7Jd8HrwDGD9uKvBkE0p0stFO2al7AU8UPD0RlevF1yHZFJeuw80I7B yrYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iiLlNgJrdHfhscp1aVBO6P+kxbA4/R9Ha0WeuU0s3+0=; b=Y9Wjnoyh2SbJVqu+bJSDsGmFsgTCghAL3rU8xR4kqQn2fZo5ltwvyN2nw+6jg9CI36 Vc/w+Qc0BZOxF2cuSMrztbKXNalwH3UiMYPt6WVP4uxacXjoZ/lcLBiAs72FloWl8css FG3MjhxVPhfLXgQZLf8HdnkwxiCJnUVnnf/G5uL2IIq3XllzRP6QSRYSUaLuHHX/z87O SSWlh1WghUXY4TnyKaSiOWk0X7kr0zn4meHz1DqJ5QoskVHwHtHDzeD0V+0K53G3MK9T E9OBQL2PJORYqvQf5w37W26GZdCqfHajHln3uyKbmjZPzWW3/Xq12ekdGMSO/g6cQMpi gfmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X517tc+H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d192si1050494ybf.426.2020.08.28.07.42.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:42:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X517tc+H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfaO-0003EU-Or for patch@linaro.org; Fri, 28 Aug 2020 10:42:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFC-0001bP-VD for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:43 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:52179) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfF7-0005I2-ET for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:42 -0400 Received: by mail-pj1-x1043.google.com with SMTP id ds1so565600pjb.1 for ; Fri, 28 Aug 2020 07:20:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iiLlNgJrdHfhscp1aVBO6P+kxbA4/R9Ha0WeuU0s3+0=; b=X517tc+HzAIdyUpQ/iplzhqDa1de+HN8MW/TrII1EAB47ANYFjK2umcBdntbxUf8zJ sIyXrl3X2wc1OAvUyp+HVKu1ZdgWznU8jm1QD8K42mdyVd0Lz2uT4R5ZCwbj/cogjLU3 iDUBKrLlPJS2dEKp0mUbS671hNKaOb3mPPPq1OWg3vEfBID+L0+RkKp9zOHblLgbZZcV nu0zJXsnYP5/XRucsviWwIKeT7UAQfB0BcQLoXRIxsODa1kX4wWBbVFbj2+syfMzea/G p8JVkoK2qw0aEM6rGnlE8vj4M8+h/4cCVueIMzKAtnfM5pEFnImh68UmTHaDervcpC/j oNcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iiLlNgJrdHfhscp1aVBO6P+kxbA4/R9Ha0WeuU0s3+0=; b=T6wVlR/nhnanSptM3Lz9SPD+YtOWD3azNQU+R9jnzYLfudWBwwHNi8YzX1AFUW8/QC VBoGDTa9KTymA8yTlOFDscwnuPd5iWTeNahNdy6RRWiC1pzAqSQp5783bSIoXVOG3bXH hPUUzY8wWXpMIvYliliZNriStxGlNF2sV6MkPm8ZHelBA8CA6Nup9HwGDsvM1gEMEaDV y81xEHbGOKscXeYsdv47AqXSZ6jeHma8VBsI88HypcZMkHBO5soRjb2YSXD1hHdNYpf7 v39uWyEEEPObaooV0AVp2+UE9MGpFXNvP5roLsnYJHv49OzhV/d5ZYiK+Wursr9PhfCY fHfA== X-Gm-Message-State: AOAM531YBuNjOn9VyRcorax8+8PT1KaUzidPrZngf4tJunI5YE02u9XE GnO2xqRocpp6ZJgxh6NQc4pj50QV7wW/1A== X-Received: by 2002:a17:90b:4d0d:: with SMTP id mw13mr1362668pjb.43.1598624435943; Fri, 28 Aug 2020 07:20:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 51/76] target/microblaze: Cache mem_index in DisasContext Date: Fri, 28 Aug 2020 07:19:04 -0700 Message-Id: <20200828141929.77854-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Ideally, nothing outside the top-level of translation even has access to env. Cache the value in init_disas_context. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 1f6731e0af..a55e110171 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -73,6 +73,7 @@ typedef struct DisasContext { unsigned int delayed_branch; unsigned int tb_flags, synced_flags; /* tb dependent flags. */ unsigned int clear_imm; + int mem_index; #define JMP_NOJMP 0 #define JMP_DIRECT 1 @@ -175,8 +176,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) */ static bool trap_userspace(DisasContext *dc, bool cond) { - int mem_index = cpu_mmu_index(&dc->cpu->env, false); - bool cond_user = cond && mem_index == MMU_USER_IDX; + bool cond_user = cond && dc->mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE)) { gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); @@ -968,7 +968,7 @@ static void dec_load(DisasContext *dc) TCGv addr; unsigned int size; bool rev = false, ex = false, ea = false; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); + int mem_index = dc->mem_index; MemOp mop; mop = dc->opcode & 3; @@ -1077,7 +1077,7 @@ static void dec_store(DisasContext *dc) TCGLabel *swx_skip = NULL; unsigned int size; bool rev = false, ex = false, ea = false; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); + int mem_index = dc->mem_index; MemOp mop; mop = dc->opcode & 3; @@ -1540,6 +1540,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; + dc->mem_index = cpu_mmu_index(&cpu->env, false); bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); From patchwork Fri Aug 28 14:19:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248564 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1142907ilg; Fri, 28 Aug 2020 07:44:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAczWp5iHIoy6WBs43yG1CWwyU57sa2tSmkrmzrhn8xtw5Bq1ydi4YpFH0iCCS+1rRl/Z9 X-Received: by 2002:a25:868b:: with SMTP id z11mr2856223ybk.108.1598625855102; Fri, 28 Aug 2020 07:44:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625855; cv=none; d=google.com; s=arc-20160816; b=PrHzG55SEra+PTdkykrdxYBaItcK1uBWz8ZnFDI/RhJ/gWBOssWE76qC6FCKc4w2WV 9kz0DpQRpN1E/pkWznzZiMtO7AWqNk+tTd33/ItTqvtJ0D7sbrUTaybDVo9SDF+QRy28 vpz1CRdQh5U0Y9nFpv11Y1V+Q+tF/LtgqbCIRw4iOj1drg+f/2WNfZIXpWDUkhBGUoZM foGohyM4G7jn0Ld7/ekhvhhx5JiiBIdqCGXdIRH/eVvsNTlOKh3UMhR4lw98C7gtNBwK 6tVKm35Srz/dpQetIUBHw2ViMbnFXQHZhOAGJ/lv1nLgABbHNt0PRO39nqYbH0WTbRB7 ufJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=R2cuEf3Qt/jcGcIZclz+3Hjy1ReL2CdcRjCqzKw0P3k=; b=zLAtnLv8IwdC3cmfbl8sYe82/i6cK+Vxbli97GD0SBv9KVbfCIDuwueuV2e4e/V/L0 7fxy8q2CXeK4yQPZBumTvPSTdnQ73fpIBYIo6HsuEhu5H/Wy5CmGjHarGM7Nx0zKtTtK MHh3uZGIwI9KX/eacsnVzYxr/VuaECAHNEzKbRmhkWDOofANOLmkehWuSCHplL75Ksb+ /edMeb+QuckwDw1DaQGZVidpdpm9IoUpS3p0vxo7M1hP+nMbB+ihdpihGCYPl0b9zQZg E+Dnw2t9LwpTN1zQ0u8fPRW7xdtxbwjQEyMznEshTjeX7pl7Fn8wXXhhaVl9QBLRuCJJ IHvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vWxvfLJx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Restore the correct PC when an exception must be raised. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 +- target/microblaze/op_helper.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 64816c89e1..a473c1867b 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -26,7 +26,7 @@ DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) #endif DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) -DEF_HELPER_2(stackprot, void, env, tl) +DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_2(get, i32, i32, i32) DEF_HELPER_3(put, void, i32, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 2c59d4492d..a99c467364 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -389,12 +389,16 @@ void helper_memalign(CPUMBState *env, target_ulong addr, void helper_stackprot(CPUMBState *env, target_ulong addr) { if (addr < env->slr || addr > env->shr) { + CPUState *cs = env_cpu(env); + qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); + env->ear = addr; env->esr = ESR_EC_STACKPROT; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, GETPC()); } } From patchwork Fri Aug 28 14:19:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248566 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1143749ilg; Fri, 28 Aug 2020 07:45:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzU71YCle1S0OweAe+C5r5v/HGnNIjNBI1nGX0LGAY+X+FtmSgpgHHRt2uU/EsEf8zLcb1P X-Received: by 2002:a25:5f0b:: with SMTP id t11mr2961119ybb.141.1598625922879; Fri, 28 Aug 2020 07:45:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625922; cv=none; d=google.com; s=arc-20160816; b=WmoQ2iorsiXXzRhXi59OdH2y2eruTaYlDfdFDUI1KZqIapt4PMXAm25i6LFFwWfQ+P mq9Wg2wX7kfkooRuf54SMNmdWuv9Zz7AncE6ttisPOmZd7l7tfSvlik+rg88yoVOmvJQ Pfrgj48GviDCzIrBeZRLbxkMHYhZNLJRJb8k08kuYu+NEZHkAbprSkL2ht6YDx5tAHpv 9v+K/V/ylhk6c0WvbVUgwOWUuSwCDgDui8M1kzqTiHPseFE/olmaWrr5QbRWnFbHsR9C 1l8iKOuGsW1RfNw3VmDCw5I3+/wrKu0X3pKHE0B+rm3r26SP54SIJW22y3xLutht5fZJ XE9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QQQ2WFgIL0ZEv9AAY/hbIBgOjAfsOiOu/hJOwBASNX8=; b=JpmQbVmBrE/MPA0HPzr2/aRfRkrBdbUNKdmIssJsBope9datNNM3REjNpvjIqHTfFs 5MacCJxWhDgwb3TdeF7HQUrAyHrAtTKLgPU+amT0BX956R1gvE0TkZ9rXArDMCCUj7VX FVOmY8QBPifn427lLjQoSlNe5MQbtDk+i3BDsE18v5jLnAJR14cRBsGOXGGZt1y2CKSc ewgbq6AZlStIqIdt5QtOYSGqeoOb2R048npVYfNJZy9zEPA1lxl7FV+OMWhQDNXFMHuk OuHavRA+r0NMNCvZ1WpmPB5q+9E9/EGI/VO5arkBcJhBCZXDFuzW8zmJYmLW3t3X7zC0 6KXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nGd0FEkc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 32 ++ target/microblaze/translate.c | 723 +++++++++++++++++++-------------- 2 files changed, 456 insertions(+), 299 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 87e8f5679b..47b92b9cbc 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -100,6 +100,22 @@ idivu 010010 ..... ..... ..... 000 0000 0010 @typea imm 101100 00000 00000 imm:16 +lbu 110000 ..... ..... ..... 0000 000 0000 @typea +lbur 110000 ..... ..... ..... 0100 000 0000 @typea +lbuea 110000 ..... ..... ..... 0001 000 0000 @typea +lbui 111000 ..... ..... ................ @typeb + +lhu 110001 ..... ..... ..... 0000 000 0000 @typea +lhur 110001 ..... ..... ..... 0100 000 0000 @typea +lhuea 110001 ..... ..... ..... 0001 000 0000 @typea +lhui 111001 ..... ..... ................ @typeb + +lw 110010 ..... ..... ..... 0000 000 0000 @typea +lwr 110010 ..... ..... ..... 0100 000 0000 @typea +lwea 110010 ..... ..... ..... 0001 000 0000 @typea +lwx 110010 ..... ..... ..... 1000 000 0000 @typea +lwi 111010 ..... ..... ................ @typeb + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea @@ -123,6 +139,22 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +sb 110100 ..... ..... ..... 0000 000 0000 @typea +sbr 110100 ..... ..... ..... 0100 000 0000 @typea +sbea 110100 ..... ..... ..... 0001 000 0000 @typea +sbi 111100 ..... ..... ................ @typeb + +sh 110101 ..... ..... ..... 0000 000 0000 @typea +shr 110101 ..... ..... ..... 0100 000 0000 @typea +shea 110101 ..... ..... ..... 0001 000 0000 @typea +shi 111101 ..... ..... ................ @typeb + +sw 110110 ..... ..... ..... 0000 000 0000 @typea +swr 110110 ..... ..... ..... 0100 000 0000 @typea +swea 110110 ..... ..... ..... 0001 000 0000 @typea +swx 110110 ..... ..... ..... 1000 000 0000 @typea +swi 111110 ..... ..... ................ @typeb + sext8 100100 ..... ..... 00000 000 0110 0000 @typea0 sext16 100100 ..... ..... 00000 000 0110 0001 @typea0 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a55e110171..d2baa7db0e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -105,6 +105,17 @@ static inline void t_sync_flags(DisasContext *dc) } } +static inline void sync_jmpstate(DisasContext *dc) +{ + if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { + if (dc->jmp == JMP_DIRECT) { + tcg_gen_movi_i32(cpu_btaken, 1); + } + dc->jmp = JMP_INDIRECT; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + } +} + static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); @@ -668,6 +679,419 @@ static bool trans_wdic(DisasContext *dc, arg_wdic *a) DO_TYPEA(xor, false, tcg_gen_xor_i32) DO_TYPEBI(xori, false, tcg_gen_xori_i32) +static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) +{ + TCGv ret = tcg_temp_new(); + + /* If any of the regs is r0, set t to the value of the other reg. */ + if (ra && rb) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]); + tcg_gen_extu_i32_tl(ret, tmp); + tcg_temp_free_i32(tmp); + } else if (ra) { + tcg_gen_extu_i32_tl(ret, cpu_R[ra]); + } else if (rb) { + tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + } else { + tcg_gen_movi_tl(ret, 0); + } + + if ((ra == 1 || rb == 1) && dc->cpu->cfg.stackprot) { + gen_helper_stackprot(cpu_env, ret); + } + return ret; +} + +static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) +{ + TCGv ret = tcg_temp_new(); + + /* If any of the regs is r0, set t to the value of the other reg. */ + if (ra) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[ra], imm); + tcg_gen_extu_i32_tl(ret, tmp); + tcg_temp_free_i32(tmp); + } else { + tcg_gen_movi_tl(ret, (uint32_t)imm); + } + + if (ra == 1 && dc->cpu->cfg.stackprot) { + gen_helper_stackprot(cpu_env, ret); + } + return ret; +} + +static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) +{ + int addr_size = dc->cpu->cfg.addr_size; + TCGv ret = tcg_temp_new(); + + if (addr_size == 32 || ra == 0) { + if (rb) { + tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + } else { + tcg_gen_movi_tl(ret, 0); + } + } else { + if (rb) { + tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]); + } else { + tcg_gen_extu_i32_tl(ret, cpu_R[ra]); + tcg_gen_shli_tl(ret, ret, 32); + } + if (addr_size < 64) { + /* Mask off out of range bits. */ + tcg_gen_andi_i64(ret, ret, MAKE_64BIT_MASK(0, addr_size)); + } + } + return ret; +} + +static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, + int mem_index, bool rev) +{ + TCGv_i32 v; + MemOp size = mop & MO_SIZE; + + /* + * When doing reverse accesses we need to do two things. + * + * 1. Reverse the address wrt endianness. + * 2. Byteswap the data lanes on the way back into the CPU core. + */ + if (rev) { + if (size > MO_8) { + mop ^= MO_BSWAP; + } + if (size < MO_32) { + tcg_gen_xori_tl(addr, addr, 3 - size); + } + } + + t_sync_flags(dc); + sync_jmpstate(dc); + + /* + * Microblaze gives MMU faults priority over faults due to + * unaligned addresses. That's why we speculatively do the load + * into v. If the load succeeds, we verify alignment of the + * address and if that succeeds we write into the destination reg. + */ + v = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); + + /* TODO: Convert to CPUClass::do_unaligned_access. */ + if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { + TCGv_i32 t0 = tcg_const_i32(0); + TCGv_i32 treg = tcg_const_i32(rd); + TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + gen_helper_memalign(cpu_env, addr, treg, t0, tsize); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); + } + + if (rd) { + tcg_gen_mov_i32(cpu_R[rd], v); + } + + tcg_temp_free_i32(v); + tcg_temp_free(addr); + return true; +} + +static bool trans_lbu(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_lbur(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, true); +} + +static bool trans_lbuea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +} + +static bool trans_lbui(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_lhu(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_lhur(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); +} + +static bool trans_lhuea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +} + +static bool trans_lhui(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_lw(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_lwr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); +} + +static bool trans_lwea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +} + +static bool trans_lwi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_lwx(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + + /* lwx does not throw unaligned access errors, so force alignment */ + tcg_gen_andi_tl(addr, addr, ~3); + + t_sync_flags(dc); + sync_jmpstate(dc); + + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_mov_tl(cpu_res_addr, addr); + tcg_temp_free(addr); + + if (arg->rd) { + tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val); + } + + /* No support for AXI exclusive so always clear C */ + tcg_gen_movi_i32(cpu_msr_c, 0); + return true; +} + +static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, + int mem_index, bool rev) +{ + MemOp size = mop & MO_SIZE; + + /* + * When doing reverse accesses we need to do two things. + * + * 1. Reverse the address wrt endianness. + * 2. Byteswap the data lanes on the way back into the CPU core. + */ + if (rev) { + if (size > MO_8) { + mop ^= MO_BSWAP; + } + if (size < MO_32) { + tcg_gen_xori_tl(addr, addr, 3 - size); + } + } + + t_sync_flags(dc); + sync_jmpstate(dc); + + tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); + + /* TODO: Convert to CPUClass::do_unaligned_access. */ + if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { + TCGv_i32 t1 = tcg_const_i32(1); + TCGv_i32 treg = tcg_const_i32(rd); + TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + /* FIXME: if the alignment is wrong, we should restore the value + * in memory. One possible way to achieve this is to probe + * the MMU prior to the memaccess, thay way we could put + * the alignment checks in between the probe and the mem + * access. + */ + gen_helper_memalign(cpu_env, addr, treg, t1, tsize); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); + } + + tcg_temp_free(addr); + return true; +} + +static bool trans_sb(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_sbr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, true); +} + +static bool trans_sbea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +} + +static bool trans_sbi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_sh(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_shr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); +} + +static bool trans_shea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +} + +static bool trans_shi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_sw(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_swr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); +} + +static bool trans_swea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +} + +static bool trans_swi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_swx(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCGLabel *swx_done = gen_new_label(); + TCGLabel *swx_fail = gen_new_label(); + TCGv_i32 tval; + + t_sync_flags(dc); + sync_jmpstate(dc); + + /* swx does not throw unaligned access errors, so force alignment */ + tcg_gen_andi_tl(addr, addr, ~3); + + /* + * Compare the address vs the one we used during lwx. + * On mismatch, the operation fails. On match, addr dies at the + * branch, but we know we can use the equal version in the global. + * In either case, addr is no longer needed. + */ + tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail); + tcg_temp_free(addr); + + /* + * Compare the value loaded during lwx with current contents of + * the reserved location. + */ + tval = tcg_temp_new_i32(); + + tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, + reg_for_write(dc, arg->rd), + dc->mem_index, MO_TEUL); + + tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); + tcg_temp_free_i32(tval); + + /* Success */ + tcg_gen_movi_i32(cpu_msr_c, 0); + tcg_gen_br(swx_done); + + /* Failure */ + gen_set_label(swx_fail); + tcg_gen_movi_i32(cpu_msr_c, 1); + + gen_set_label(swx_done); + + /* + * Prevent the saved address from working again without another ldx. + * Akin to the pseudocode setting reservation = 0. + */ + tcg_gen_movi_tl(cpu_res_addr, -1); + return true; +} + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -887,303 +1311,6 @@ static void dec_msr(DisasContext *dc) } } -static inline void sync_jmpstate(DisasContext *dc) -{ - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(cpu_btaken, 1); - } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); - } -} - -static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) -{ - /* Should be set to true if r1 is used by loadstores. */ - bool stackprot = false; - TCGv_i32 t32; - - /* All load/stores use ra. */ - if (dc->ra == 1 && dc->cpu->cfg.stackprot) { - stackprot = true; - } - - /* Treat the common cases first. */ - if (!dc->type_b) { - if (ea) { - int addr_size = dc->cpu->cfg.addr_size; - - if (addr_size == 32) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); - return; - } - - tcg_gen_concat_i32_i64(t, cpu_R[dc->rb], cpu_R[dc->ra]); - if (addr_size < 64) { - /* Mask off out of range bits. */ - tcg_gen_andi_i64(t, t, MAKE_64BIT_MASK(0, addr_size)); - } - return; - } - - /* If any of the regs is r0, set t to the value of the other reg. */ - if (dc->ra == 0) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); - return; - } else if (dc->rb == 0) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->ra]); - return; - } - - if (dc->rb == 1 && dc->cpu->cfg.stackprot) { - stackprot = true; - } - - t32 = tcg_temp_new_i32(); - tcg_gen_add_i32(t32, cpu_R[dc->ra], cpu_R[dc->rb]); - tcg_gen_extu_i32_tl(t, t32); - tcg_temp_free_i32(t32); - - if (stackprot) { - gen_helper_stackprot(cpu_env, t); - } - return; - } - /* Immediate. */ - t32 = tcg_temp_new_i32(); - tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); - tcg_gen_extu_i32_tl(t, t32); - tcg_temp_free_i32(t32); - - if (stackprot) { - gen_helper_stackprot(cpu_env, t); - } - return; -} - -static void dec_load(DisasContext *dc) -{ - TCGv_i32 v; - TCGv addr; - unsigned int size; - bool rev = false, ex = false, ea = false; - int mem_index = dc->mem_index; - MemOp mop; - - mop = dc->opcode & 3; - size = 1 << mop; - if (!dc->type_b) { - ea = extract32(dc->ir, 7, 1); - rev = extract32(dc->ir, 9, 1); - ex = extract32(dc->ir, 10, 1); - } - mop |= MO_TE; - if (rev) { - mop ^= MO_BSWAP; - } - - if (trap_illegal(dc, size > 4)) { - return; - } - - if (trap_userspace(dc, ea)) { - return; - } - - t_sync_flags(dc); - addr = tcg_temp_new(); - compute_ldst_addr(dc, ea, addr); - /* Extended addressing bypasses the MMU. */ - mem_index = ea ? MMU_NOMMU_IDX : mem_index; - - /* - * When doing reverse accesses we need to do two things. - * - * 1. Reverse the address wrt endianness. - * 2. Byteswap the data lanes on the way back into the CPU core. - */ - if (rev && size != 4) { - /* Endian reverse the address. t is addr. */ - switch (size) { - case 1: - { - tcg_gen_xori_tl(addr, addr, 3); - break; - } - - case 2: - /* 00 -> 10 - 10 -> 00. */ - tcg_gen_xori_tl(addr, addr, 2); - break; - default: - cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); - break; - } - } - - /* lwx does not throw unaligned access errors, so force alignment */ - if (ex) { - tcg_gen_andi_tl(addr, addr, ~3); - } - - /* If we get a fault on a dslot, the jmpstate better be in sync. */ - sync_jmpstate(dc); - - /* Verify alignment if needed. */ - /* - * Microblaze gives MMU faults priority over faults due to - * unaligned addresses. That's why we speculatively do the load - * into v. If the load succeeds, we verify alignment of the - * address and if that succeeds we write into the destination reg. - */ - v = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); - - if (dc->cpu->cfg.unaligned_exceptions && size > 1) { - TCGv_i32 t0 = tcg_const_i32(0); - TCGv_i32 treg = tcg_const_i32(dc->rd); - TCGv_i32 tsize = tcg_const_i32(size - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_helper_memalign(cpu_env, addr, treg, t0, tsize); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); - } - - if (ex) { - tcg_gen_mov_tl(cpu_res_addr, addr); - tcg_gen_mov_i32(cpu_res_val, v); - } - if (dc->rd) { - tcg_gen_mov_i32(cpu_R[dc->rd], v); - } - tcg_temp_free_i32(v); - - if (ex) { /* lwx */ - /* no support for AXI exclusive so always clear C */ - tcg_gen_movi_i32(cpu_msr_c, 0); - } - - tcg_temp_free(addr); -} - -static void dec_store(DisasContext *dc) -{ - TCGv addr; - TCGLabel *swx_skip = NULL; - unsigned int size; - bool rev = false, ex = false, ea = false; - int mem_index = dc->mem_index; - MemOp mop; - - mop = dc->opcode & 3; - size = 1 << mop; - if (!dc->type_b) { - ea = extract32(dc->ir, 7, 1); - rev = extract32(dc->ir, 9, 1); - ex = extract32(dc->ir, 10, 1); - } - mop |= MO_TE; - if (rev) { - mop ^= MO_BSWAP; - } - - if (trap_illegal(dc, size > 4)) { - return; - } - - trap_userspace(dc, ea); - - t_sync_flags(dc); - /* If we get a fault on a dslot, the jmpstate better be in sync. */ - sync_jmpstate(dc); - /* SWX needs a temp_local. */ - addr = ex ? tcg_temp_local_new() : tcg_temp_new(); - compute_ldst_addr(dc, ea, addr); - /* Extended addressing bypasses the MMU. */ - mem_index = ea ? MMU_NOMMU_IDX : mem_index; - - if (ex) { /* swx */ - TCGv_i32 tval; - - /* swx does not throw unaligned access errors, so force alignment */ - tcg_gen_andi_tl(addr, addr, ~3); - - tcg_gen_movi_i32(cpu_msr_c, 1); - swx_skip = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); - - /* - * Compare the value loaded at lwx with current contents of - * the reserved location. - */ - tval = tcg_temp_new_i32(); - - tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val, - cpu_R[dc->rd], mem_index, - mop); - - tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); - tcg_gen_movi_i32(cpu_msr_c, 0); - tcg_temp_free_i32(tval); - } - - if (rev && size != 4) { - /* Endian reverse the address. t is addr. */ - switch (size) { - case 1: - { - tcg_gen_xori_tl(addr, addr, 3); - break; - } - - case 2: - /* 00 -> 10 - 10 -> 00. */ - /* Force addr into the temp. */ - tcg_gen_xori_tl(addr, addr, 2); - break; - default: - cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); - break; - } - } - - if (!ex) { - tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop); - } - - /* Verify alignment if needed. */ - if (dc->cpu->cfg.unaligned_exceptions && size > 1) { - TCGv_i32 t1 = tcg_const_i32(1); - TCGv_i32 treg = tcg_const_i32(dc->rd); - TCGv_i32 tsize = tcg_const_i32(size - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - /* FIXME: if the alignment is wrong, we should restore the value - * in memory. One possible way to achieve this is to probe - * the MMU prior to the memaccess, thay way we could put - * the alignment checks in between the probe and the mem - * access. - */ - gen_helper_memalign(cpu_env, addr, treg, t1, tsize); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); - } - - if (ex) { - gen_set_label(swx_skip); - } - - tcg_temp_free(addr); -} - static inline void eval_cc(DisasContext *dc, unsigned int cc, TCGv_i32 d, TCGv_i32 a) { @@ -1491,8 +1618,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_LD, dec_load}, - {DEC_ST, dec_store}, {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, From patchwork Fri Aug 28 14:19:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248545 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1136133ilg; Fri, 28 Aug 2020 07:35:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzQe2rfoKJukqMAUgF6CrZg0WvmVBld0kyJTjjR1zQpv0YU/KllU9VcujO2IuMyKL1m6HAg X-Received: by 2002:a25:ae43:: with SMTP id g3mr2801973ybe.459.1598625353847; Fri, 28 Aug 2020 07:35:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625353; cv=none; d=google.com; s=arc-20160816; b=uv4uSVumqqSOuT2qArzskwX8OrDAGLKgt51NpE8himnh27x//bkrUUTcd5InlszUCR KOFJbhOZIY1U/6LbjpmfO3SAVNSMj7KSUahI3pmVS3qVyFh3H9VpVQlT7TlqYmc3moRz YRFl84CumVyvuD37pGGKKh62K+0j+UcwhZ/+Qom5RGJbpOqFpS1N7c1zHAm+ggPdSRSi 5QI3epymlRxzlYkMl8TUHA0ds0XHDzM5yG9LPcxZU9Hikl219BlIdKBKQOEOkCGH0BBD PuV5F4usmXDTlg/ivj5YpeCgz5xEW5E8p83dfGC6leV+5NPYdt3xwmqq1nOp1ueDLAvi dn7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=50E0hW76gnTgLCYM21b2+hcWFagS0hoFg/XoJTnl9H8=; b=XsU3LYvWRPgsgBDXHpELRPMuLprtmksycEgY0K9ZxToxBPi3yTZXfTdJyiinhhjyi8 +iL+hrsigmiRcOQ+q+GPjISVaejNfAaYMTdlOZZ3N+L56+c3WHjmDrYilA7DIHjiFhF7 jLnYezLDgc468bHGzLOTDYsfW2OYHhvrytkW+7q9QvBnny7QfHonMwG7KBtSncavsveD 5c+ZJC9K0wdcsrDyhZkc2QF7HGCIpSs/yGK0WYidupPqy8YAH3MduRt8mhEkUC31pj9x /oeDIvjrZ+auN0X2K9CWuxwkaFsGZgjZMAjkdtWZ5p6srxMTfU68k5Fc2Whul+iFHZMx 4/Ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aMD0vn7Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l4si1234262ybc.52.2020.08.28.07.35.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:35:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aMD0vn7Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfTt-0006J0-6Z for patch@linaro.org; Fri, 28 Aug 2020 10:35:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFF-0001gy-6S for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:45 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:34218) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFC-0005L5-Bl for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:44 -0400 Received: by mail-pl1-x644.google.com with SMTP id v16so539343plo.1 for ; Fri, 28 Aug 2020 07:20:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=50E0hW76gnTgLCYM21b2+hcWFagS0hoFg/XoJTnl9H8=; b=aMD0vn7YXNiI7oXmxipwC3oGnTBSwqApyOeZgc8vZfIwMEgqgpwlzMo3el4S3H2bdG F08uIXSUUsiNOhf12sZhzgvk967B5L476cJGA1Lhs/oEl9Of0RtcpTwiPdy+KyF0EWdS i+CaBvX+D5Iihfh3/6gDr15zBNp9Mvc255+rxeyVz3Lx11t4jYvWTqraIaO7urI1PmIr c7KCdaACYl64BqfkC3Rwklevw/+Yyz2bOayZ8n0OCfGP6bALyld9xqX83g4U/g5uh5Ow wwfeiofDBHhxYXub/4aOkYYFAyyvVYKjyVOsGisHbRJf1+70zsvaEZSpHOsu+SqkSiaC aMpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=50E0hW76gnTgLCYM21b2+hcWFagS0hoFg/XoJTnl9H8=; b=h+wH/bwtRw7ymLex99KqbwCx9OZCqwQja2nqf3yAnzH1LlT+b2VTelnLnGvh7AkFpS 1+Flm4cmEm1RKEL63kRDBRJxfYEm4zeTR412rWlAFmsa7HeI6N7Xh4vhUaYJinqUPCnl Pd2o509AP402Dhdvw1tE0X9ZKRjJsqWUofzWjqz6TT/SUdAewy3Lwj7lwbC0THve4aL8 rJIRKgEa5c8wcJcTPOddRqrZb/fT/g+3DS8dwf0m4NbWgR3JBN0puMg/PaSX4JT4rqxN LrpfE6EkK6lE4Rf8xaOLGhAuuMECXoS+3DnK19iOPdQDdy2oOtumPJh4VdzsVtsVrhXL ngtg== X-Gm-Message-State: AOAM5307r6AIn6SomtIVnRT1TBZF3OKGKXLUbC6X7+6XoK/sI/xCb1bo KD0e81S5rL8lLjchTVLhoii0XVA/Ik/3nA== X-Received: by 2002:a17:902:b60d:: with SMTP id b13mr1490296pls.48.1598624439819; Fri, 28 Aug 2020 07:20:39 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 54/76] target/microblaze: Assert no overlap in flags making up tb_flags Date: Fri, 28 Aug 2020 07:19:07 -0700 Message-Id: <20200828141929.77854-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create MSR_TB_MASK. Use it in cpu_get_tb_cpu_state, and check that IFLAGS_TB_MASK does not overlap. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 594501e4e7..2fc7cf26f1 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -261,8 +261,11 @@ struct CPUMBState { #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) #define D_FLAG (1 << 19) /* Bit in ESR. */ + /* TB dependent CPUMBState. */ #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) +#define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE) + uint32_t iflags; #if !defined(CONFIG_USER_ONLY) @@ -372,12 +375,14 @@ typedef MicroBlazeCPU ArchCPU; #include "exec/cpu-all.h" +/* Ensure there is no overlap between the two masks. */ +QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); + static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { *pc = env->pc; - *flags = (env->iflags & IFLAGS_TB_MASK) | - (env->msr & (MSR_UM | MSR_VM | MSR_EE)); + *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); *cs_base = (*flags & IMM_FLAG ? env->imm : 0); } From patchwork Fri Aug 28 14:19:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248570 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1144771ilg; Fri, 28 Aug 2020 07:46:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJynW4HfcjVLR4IqSRq5mGv3nTbvvRH8BEBzM1rctFhCtXXw1VzXcK4HdntJhffk+bvphwIj X-Received: by 2002:a25:f807:: with SMTP id u7mr2927762ybd.291.1598626005134; Fri, 28 Aug 2020 07:46:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626005; cv=none; d=google.com; s=arc-20160816; b=plEHvN37u/BkOyUTPyWlLxG9nEPBRWunWcJcMvoZc4+j5pzA7z5I/WD1gNtVdcUikT GTsxKnYs7A5GPKmO/pMFwcWbxrZulbXaBxWozUh82DrI+Tca7o+GrNc4qUIGxWFnbJ6C EhCsAawxO7R0/Fz9aQNHH+GFCSjqXedy/TedQWMh9jvdK8HXsXWqS5slTylI6H/oyCy+ oyATV3ivPcSVPjhynxWqDSP037e7+ROq154Q+Y9dEblg99hoFj08XS97J5F6u8W6OXDv gov0VuSZLLsr1laal64q7mKlVf7QLWs7AoSpgCoCDaCAoktqbDSdUgjftJUMfoEutM6T ceHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RISUXOD2AWMs6jP2ZEWVEZMruhXXXQYxncqeH2DRHUM=; b=j4pPylPshMULyL0ZBZYpN0eEqJIVP6krxhlazNmQfppZVd3KA8tNJMC1gGC6xVImkl iqo7buLaf7bYSmx4CpttTuKiEWRaw1H1b0sLxUg0KjM0SXh8J5HnWcORUpP4jO/aBtLJ LFKryg/IVwgztN94UTVxAoHVTe6fMvmR4PRsTNCEiR0Yh8tCNCgkbzE2E2jk8L5lrTyG ADaWDb9QWP4gjmCLG26t2kwVqejaw8Dcn2tDpT1tArCIHDpdPEvDjgtOXYxHWhz20i4I MH7HNOmt25z808q4FDhbDixQbp6QIHXwwuDJi6e6Ni/Y9mGsXl3JNIRqo0CMWqrs2L1Z SPSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dML2YWPG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j188si1136725ybj.477.2020.08.28.07.46.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:46:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dML2YWPG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfeO-0003mg-Jf for patch@linaro.org; Fri, 28 Aug 2020 10:46:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFE-0001gT-UP for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:44 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:39122) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFD-0005LY-2t for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:44 -0400 Received: by mail-pg1-x52d.google.com with SMTP id v15so526369pgh.6 for ; Fri, 28 Aug 2020 07:20:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RISUXOD2AWMs6jP2ZEWVEZMruhXXXQYxncqeH2DRHUM=; b=dML2YWPGGfyZ96nA+IZyV4k8asKs2lC9cWA8MKk5GozgCvzgPF3j4eeTkcJdnkEg// l02WhqmIXytKVqsdqLGMzuoHJgnU+uQewxA2HUvpkuQ380ciUvBuZzdGAqyB6bi22xzA DMQnkqkkjO2WJB+1mpWC9ucMG8XnL7XsRIiredsaIUYkefMnH5XuorPQ74sG/nEbiDV7 4pQAdbazFB6RnCzoBvupFYzuskXX/eNKAqUi4O37Bz/Q+tG54QrvZF1LwHiMAHsw2Dm2 DYF+kbsdxs39W1OZtQLTrJRF8WSsZ9ihcvUgQyi+DHyf6l/PfnJ2XnR/+eLAHwJrpWv0 T2Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RISUXOD2AWMs6jP2ZEWVEZMruhXXXQYxncqeH2DRHUM=; b=tMBHT281D/hW+/L0hmBqZyBrnQB2uT7kgDP8hcm6D3LLpLBOGTzlpwQ3v/kPG9EHWr 6yvcfeh/wfWWoa0O27Y/AY3oasMaIN3tih7ELKlKqc98glsZx96Q4MDaRCHmHcl+s1DR FMWIA9mQfx0CXuFl84K5dW2mBpcLJqjrCdw/Z4/7HBTeYgzFJemQXZ1KLbC1X0bnprUX zT7YkTUZuksve2zFaeJgFakDe31Z5fm32oMFFMCL2SRkzOe85UOhtFfwY7qatqwZDmRg JG4Yjl+JaeA2LwcjpP2hzOeQ43FAk+bjagLUXyeK7A75+eFfYLYewM28h5OrkzHGQYJQ 4fTQ== X-Gm-Message-State: AOAM531Lov0JjkHvrFeEP7cuUi/GFguVaTcCftsfAB1kZ3EHyxZQQ0am sj649wqNetRCzlHjSDLgDFBybRqFiiXADA== X-Received: by 2002:a63:3841:: with SMTP id h1mr1370545pgn.38.1598624441344; Fri, 28 Aug 2020 07:20:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 55/76] target/microblaze: Move bimm to BIMM_FLAG Date: Fri, 28 Aug 2020 07:19:08 -0700 Message-Id: <20200828141929.77854-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It makes sense to keep BIMM with D_FLAG, as they can be written back to iflags at the same time. BIMM_FLAG does not need to be added to IFLAGS_TB_MASK because it does not affect the next TB, only the exception path out of the current TB. Renumber IMM_FLAG, as the value 4 holds no particular significance; pack these two flags at the bottom of the bitfield. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 ++-- target/microblaze/helper.c | 2 +- target/microblaze/translate.c | 12 +++++------- 3 files changed, 8 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 2fc7cf26f1..a5df1fa28f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -231,7 +231,6 @@ typedef struct CPUMBState CPUMBState; struct CPUMBState { uint32_t btaken; uint32_t btarget; - uint32_t bimm; uint32_t imm; uint32_t regs[32]; @@ -253,7 +252,8 @@ struct CPUMBState { uint32_t res_val; /* Internal flags. */ -#define IMM_FLAG 4 +#define IMM_FLAG (1 << 0) +#define BIMM_FLAG (1 << 1) /* MSR_EE (1 << 8) */ /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index f8e2ca12a9..06f4322e09 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -166,7 +166,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* Reexecute the branch. */ env->regs[17] -= 4; /* was the branch immprefixed?. */ - if (env->bimm) { + if (env->iflags & BIMM_FLAG) { env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d2baa7db0e..97a436c8d5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1351,13 +1351,11 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) static void dec_setup_dslot(DisasContext *dc) { - TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)); - - dc->delayed_branch = 2; - dc->tb_flags |= D_FLAG; - - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm)); - tcg_temp_free_i32(tmp); + dc->delayed_branch = 2; + dc->tb_flags |= D_FLAG; + if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + dc->tb_flags |= BIMM_FLAG; + } } static void dec_bcc(DisasContext *dc) From patchwork Fri Aug 28 14:19:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248565 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1142905ilg; Fri, 28 Aug 2020 07:44:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwSucnGIN5I+HCkpKa4cF0LMexbca72Z2HLA2smJkmUBNutwr+sLgMSS7sFsj2i/orGm+1d X-Received: by 2002:a25:5555:: with SMTP id j82mr3114240ybb.125.1598625854956; Fri, 28 Aug 2020 07:44:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625854; cv=none; d=google.com; s=arc-20160816; b=w+VSQmNnOlWz+YLZ/N1wlM1OPFj9pLnN7UBHZu0CUws50660etcWczRfCPU3W1zUvv JWT8YhHRwIrArYU0iOOx8g7B1oZTNCwz2oilIZtH19td2t/gZZ8nsHh1cVpro2IkzdK9 2SNXGfxdNDOuGnBojfcmwOD1AapHYoaMVY5Abn1JZrzZhoeOjvl676LaDGMT2knaBrIj VC09Ehr54tlyQWxAlBRqLYflGXX5JW+fQ/7sgwHfT6SG77/JaaCHFSv6B2GyYdAaiybm PQfHU7KorrYCbLt21qBQ8VKL0J7lTab8QshU3D8AxRgNya/bMdLDWBhVi0ln2lFq/wgI H35w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3LLfQYgaXzGwswhNrhZmalAI0pGPTZAeATntMFf9mBA=; b=JbCwM4FyNiuYCGDtuCCf+GI6YgwVMhjfEiefrRyDVwlyClVkStHikptj+a66XhPO+a gE5cEUoxVEJaKvONeGXE7mufBQ+WiXJn5Dyi7RaYtoClD07mYLmuo7vQL3GsT2VnL42k kMTnCvm600YLq+xtUK56dLcHxevdus0YR8DZ97CfNL5VNrwyneia5umAcE4GSmm9E90R C9pVVkuVGTpFl9nBVjJQ+PtclRKYXV7F3AhQ9X5By5EZ/lJmfb5qCQ9fLBHPmIW74bfr IO54S8C8aU1xmArKHpKbhkP8nLIXBb51oxNY7mUOO0Dx50GVAvjMY53c691ynSZFRwQM S/sA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p8ZolXJM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not call cpu_restore_state when no exception will be delivered. This can lead to inconsistent cpu state. Reported-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index a99c467364..e6dcc79243 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -419,32 +419,33 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - MicroBlazeCPU *cpu; - CPUMBState *env; + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx " physaddr 0x" TARGET_FMT_plx " size %d access type %s\n", addr, physaddr, size, access_type == MMU_INST_FETCH ? "INST_FETCH" : (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE")); - cpu = MICROBLAZE_CPU(cs); - env = &cpu->env; - cpu_restore_state(cs, retaddr, true); if (!(env->msr & MSR_EE)) { return; } - env->ear = addr; if (access_type == MMU_INST_FETCH) { - if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { - env->esr = ESR_EC_INSN_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); + if (!cpu->cfg.iopb_bus_exception) { + return; } + env->esr = ESR_EC_INSN_BUS; } else { - if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { - env->esr = ESR_EC_DATA_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); + if (!cpu->cfg.dopb_bus_exception) { + return; } + env->esr = ESR_EC_DATA_BUS; } + + env->ear = addr; + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, retaddr); } #endif From patchwork Fri Aug 28 14:19:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248574 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1146601ilg; Fri, 28 Aug 2020 07:49:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyuv6eo/2goPsmJcL/1TEKU7KeGY1qDJHatcu6dvUPP45FU3VOma5vS6bcJ3OHRQnQVIQ4G X-Received: by 2002:a25:5f0f:: with SMTP id t15mr3061498ybb.253.1598626150383; Fri, 28 Aug 2020 07:49:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626150; cv=none; d=google.com; s=arc-20160816; b=bsbENz+wy0RHKBJ5PKu5pBncmJGw7m1LHjVy4bms6KxSyoIHBFPUoFwGAfaEz8oovH YxdG0A9ypxsR06WY83tyMu9DvdA/Bg0rBXC6AgK5wdx0peZCteI7FI1znevWxdiKSkJd c6X4nV1LIastvsZ81oVDWcGKPp8s60psNerH//VwnzHC4GL9hdQ3yyrgkraBnGBnk384 BV80oJSIL3H+brbLObOwmQET/qZ3o8E+8CXxV1t9iFETFkqL/aAEDEqtGMCccot331rZ UlOpDFU7RyS17cBTNdXwPOsTAFLdx2FfR/C9mgYV1cE/ophkguUCFvhsUMNzG87SjzYR nU9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WdEFi+R7EYBujKDXCMlxM8N86OEUIuERS99vJP4r/ZY=; b=w4WyK1ybYHE41xo/4jgXS8abS75vMSdxNFjDjJQmKXDUUjqVoQC1DqRUOuV/bn8VzL +aePEa5UMTimxPKszpbrwvWEodBHAMo8d6Iw7VGP+EfP6ZY5qpEML9CfvE1YYClaGVD+ SAxipU5nkMGIEnSvaUZ1jMQApNszfORirYF7NzxralDIv0o22my/gebknrPQxHucmuoU BzEzbdiKIGltHJkcma5lCxVVqk6wrIuz6DT5ro/GrmespbCnHW8arg204ZM85ePgNVbc SivxZeSfGUz7bL/UkrsThHY9V/bhfxEOLXDdUg80uJuO2jSiFH8q3pK+uyAjQmbVDP7y IOBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XuZ64azi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c186si1041652ybb.397.2020.08.28.07.49.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:49:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XuZ64azi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfgj-0006Uh-Qh for patch@linaro.org; Fri, 28 Aug 2020 10:49:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51820) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFH-0001o0-Pf for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:47 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:42425) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFF-0005Nk-Mt for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:47 -0400 Received: by mail-pl1-x641.google.com with SMTP id j11so522473plk.9 for ; Fri, 28 Aug 2020 07:20:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WdEFi+R7EYBujKDXCMlxM8N86OEUIuERS99vJP4r/ZY=; b=XuZ64aziDli3AE/LOOJNGgV5PG5yY2BybIXNRjRtjmVvvAKdu3B2WEacbPwvuN7JhR dLTEWClgwAF0thY5JWPl0KX45iaP5XcXsdceuXtndawhRWFh8sSWc4hLjDVpy+dhMeyD Rnan7PL8rwWEYZIJ1qdQKhuWptRF29KIfqGQsS4SMwePh3R1/QeUUs5La1JIAjCVjh/f A22t0HvCjNLzDB0Ed+tOFEK1ogIdzVOgwcv8gjdhvhNIdZ1gOcPvFCH83BCk4y6pjRSz 8Yhgx2EdFY3negU//XJL5BPFWPzkGGoW1ZIpDZDhYInLoY6wCGddr6p6ZtU9j5r5xXtQ kcEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WdEFi+R7EYBujKDXCMlxM8N86OEUIuERS99vJP4r/ZY=; b=ZhR6ddfu9PaK2/C228APyrBoatt0yV/lXDby4UIPrISAUEvMUFHXow7jtEIGgz8p12 /GWlUYBX0+ca2MKr7pKeCX7toaIfLstNDjh0WIOJ5iwcNgZi/2HLG8vCbN72Ch4tjWa1 +phEcRj1SdUkTYW/9sMGLXMXTiLCZ3DDV0lIwv0QjbnS3e/xjHB9OaCmBpx+HL+OGPIv zPy4Mj6gaOIVRD+0n7UcS41esX2x13OMRYiZXp4VCTTfv8vKVGtgumkddKFcclev/lj+ MUU8ygdkD9Mg0Oztc9xImrLXRz56xjkatoCf7UVpI+9THJXpeVxcY+0kMwH4kMLJemeE DwsA== X-Gm-Message-State: AOAM530pdoT7Sogs1NT1g1IpbYQZEusiS8c4EQSXcvaQdtdXiyehY3pK kSI4Q8SNYCM8RA6wiPcfF+PznkrKE1mQAw== X-Received: by 2002:a17:902:aa04:: with SMTP id be4mr1501377plb.294.1598624443915; Fri, 28 Aug 2020 07:20:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 57/76] target/microblaze: Store "current" iflags in insn_start Date: Fri, 28 Aug 2020 07:19:10 -0700 Message-Id: <20200828141929.77854-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This data is available during exception unwinding, thus we can restore it from there directly, rather than saving it during the TB. Thus we may remove the t_sync_flags() calls in the load/store operations. Note that these calls were missing from the other places where runtime exceptions may be raised, such as idiv and the floating point operations. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 ++ target/microblaze/translate.c | 24 +++++++++++++----------- 2 files changed, 15 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a5df1fa28f..83fadd36a5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -228,6 +228,8 @@ typedef struct CPUMBState CPUMBState; #define STREAM_CONTROL (1 << 3) #define STREAM_NONBLOCK (1 << 4) +#define TARGET_INSN_START_EXTRA_WORDS 1 + struct CPUMBState { uint32_t btaken; uint32_t btarget; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 97a436c8d5..d2ee163294 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; + /* TCG op of the current insn_start. */ + TCGOp *insn_start; + TCGv_i32 r0; bool r0_set; @@ -71,7 +74,7 @@ typedef struct DisasContext { unsigned int cpustate_changed; unsigned int delayed_branch; - unsigned int tb_flags, synced_flags; /* tb dependent flags. */ + unsigned int tb_flags; unsigned int clear_imm; int mem_index; @@ -96,12 +99,11 @@ static int typeb_imm(DisasContext *dc, int x) /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" -static inline void t_sync_flags(DisasContext *dc) +static void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ - if (dc->tb_flags != dc->synced_flags) { - tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); - dc->synced_flags = dc->tb_flags; + if ((dc->tb_flags ^ dc->base.tb->flags) & ~MSR_TB_MASK) { + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & ~MSR_TB_MASK); } } @@ -770,7 +772,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - t_sync_flags(dc); sync_jmpstate(dc); /* @@ -893,7 +894,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - t_sync_flags(dc); sync_jmpstate(dc); tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); @@ -929,7 +929,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - t_sync_flags(dc); sync_jmpstate(dc); tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); @@ -1046,7 +1045,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) TCGLabel *swx_fail = gen_new_label(); TCGv_i32 tval; - t_sync_flags(dc); sync_jmpstate(dc); /* swx does not throw unaligned access errors, so force alignment */ @@ -1655,7 +1653,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) int bound; dc->cpu = cpu; - dc->synced_flags = dc->tb_flags = dc->base.tb->flags; + dc->tb_flags = dc->base.tb->flags; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; @@ -1675,7 +1673,10 @@ static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs) static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) { - tcg_gen_insn_start(dcb->pc_next); + DisasContext *dc = container_of(dcb, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); + dc->insn_start = tcg_last_op(); } static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, @@ -1917,4 +1918,5 @@ void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, target_ulong *data) { env->pc = data[0]; + env->iflags = data[1]; } From patchwork Fri Aug 28 14:19:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248568 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1144034ilg; Fri, 28 Aug 2020 07:45:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMq5+aY9S5t16HMmGmiJsxa5Tw5pBjRwQGtXcvGzUxzYsG4NSNpK70kYFjvpkb3Wqu8ngc X-Received: by 2002:a25:264f:: with SMTP id m76mr2676024ybm.392.1598625945421; Fri, 28 Aug 2020 07:45:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625945; cv=none; d=google.com; s=arc-20160816; b=RQsd1s49IJiAlo5aseQlll9mNZEOv9ddD3plx3Eo0V3SPo7fkvcu+MOruIziMR91Di yMl6wrQPnLxyk3Zf46umVAgrXasaCxnexjCorQ6tSHcMZZGTh4nPeVYQ/ww6StDQZK6j BIYGTb24pn0viyAr0Z+v0zYZ9XwosWy5YG65HkUuj3oOOpvaTHTa7l6hyl5tLOaVKkk2 xQAl9HxDbSRygvw4+kbx8fgayYD++fehtuV8TOrhNcDSno3j8DNE6YWIkUNAQglvnr4v 6ZFNVJWhYMNGVAP3r4z8GNvk60SAmFMpXZZJOAO3ctNi132sZk67shEN171QhHn7yorg AUjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=p+iYZfUiWvOiZ4jhf/t12sD37PNbPvTJo79LCNu2vXI=; b=ME1QDlJv4zg+PFr00q6kj5IgLDrWahq+yYpsh5AbHk+a/iAnAV6AL5O5kbFnDfOT3a fLYR3hQOcQgT0nCYe6djPhKIIzyrTonn/EaX08sRfOAAf2YESYe3jkFGcV0X/dm2l2ag sIZpWsidBCpf6Hvx5qU9qo7FTX+v8+o45JuxjJ+J1MSLWg4q5/kQbYAxcqRP6IoEhcxT GKnSXbwH+TMrvT+B19T28EH7lPdoczcRqbAwdmmZaLxhKGbyC9KbTQXdEnpxNthqQjUf kpCszLU09koX540PL3zy0UOAx1Eb2T9VLCP7Fq6lqOtQMYpjEpMbFcZEY42d/kQdNW8v YtXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u6tTUMXl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" MicroBlaze will shortly need to update a parameter in place. Add an interface to read to match that for write. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d40c925d04..15da46131b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -777,11 +777,26 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) } #endif +static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) +{ + return op->args[arg]; +} + static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) { op->args[arg] = v; } +static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) +{ +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + return tcg_get_insn_param(op, arg); +#else + return tcg_get_insn_param(op, arg * 2) | + (tcg_get_insn_param(op, arg * 2 + 1) << 32); +#endif +} + static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) { #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS From patchwork Fri Aug 28 14:19:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248577 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1148197ilg; Fri, 28 Aug 2020 07:51:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxdQ3lyWd+VIEjklJbgomq5peQiW8z3R5L7eR+tjEvmsgKcD52uKdGshIBqd+19uMNtrqKj X-Received: by 2002:a25:80d3:: with SMTP id c19mr2932945ybm.13.1598626275623; Fri, 28 Aug 2020 07:51:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626275; cv=none; d=google.com; s=arc-20160816; b=F5KrD6F/GE2zAAXYQjmymslgKunmFdXFI1JnCyYQ70R0kMBti3Y1idBm78FW3kPK1G JjGfKeEJq50g1oMTW+2DSVsLcCZuQDUu9FDndjbM7PkxbTLH9h5nIycOfMQbk9cDG3TL pGe4MkwSfPfJ9yelTe9eZiUWaDWlHPI2oWN8p3upLCs3Ci/wykQFqtJ+/yWFReZpL1iF 3dWYx58eqAlLwzYLkvygld/LIggqlvkmJpajf7DKj5qJAcjUKAVF4oHjObKjgbiMY9o7 vUhYdliEMEWpYZi5Fhf5X0D1UZWcRMMxTSySYAOJYO5Pu/z7hw6eH966P0kFLg1q2OPl E7hA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dhPjtBgff700YZBSMkaaY04bVR10cqOe0Tp7e7EeDiY=; b=lm9wXleP8LEYKwnqVMOM9n622yyp10hyOifLyHoPLa0ZqsVeOrwJ9x7ioaTWYINDES NPK/NVQ+B4AcOGSnLOC54gMRPgSCfFqGIPudOaSVdFSPeLr/AyQhRjtRMSAnPuBMab00 Gs9Edm27SrH4IA5iPWbth+vL8r5vZNdmdiYS6/xPT+gYmMRv6O5n/P3JwkTrhfyg4uV/ ChEBfnfSmhEmsoKyjFiGeounXUlG3npWiA49Pj9zDO80HOGFkxxMXsPRu6xGK3AAFdJp WpCRnZS/dxaYJhp0Rkoo14ES5YbfJd1Xn+kBg45hVZKLvZLpFGqyLbjon7Fen8MRbBVh ehGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UjTFJePM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fixes the problem in which unaligned stores succeeded, but then we raised the exception after modifying memory. Store the ESS for the unaligned data access in the iflags for the insn, so that it can be found during unwind. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 10 ++++- target/microblaze/helper.h | 1 - target/microblaze/cpu.c | 1 + target/microblaze/helper.c | 28 ++++++++++++++ target/microblaze/op_helper.c | 21 ---------- target/microblaze/translate.c | 72 +++++++++++++---------------------- 6 files changed, 64 insertions(+), 69 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 83fadd36a5..63b8d93d41 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -79,10 +79,13 @@ typedef struct CPUMBState CPUMBState; /* Exception State Register (ESR) Fields */ #define ESR_DIZ (1<<11) /* Zone Protection */ +#define ESR_W (1<<11) /* Unaligned word access */ #define ESR_S (1<<10) /* Store instruction */ #define ESR_ESS_FSL_OFFSET 5 +#define ESR_ESS_MASK (0x7f << 5) + #define ESR_EC_FSL 0 #define ESR_EC_UNALIGNED_DATA 1 #define ESR_EC_ILLEGAL_OP 2 @@ -256,9 +259,11 @@ struct CPUMBState { /* Internal flags. */ #define IMM_FLAG (1 << 0) #define BIMM_FLAG (1 << 1) -/* MSR_EE (1 << 8) */ +#define ESR_ESS_FLAG (1 << 2) /* indicates ESR_ESS_MASK is present */ +/* MSR_EE (1 << 8) -- these 3 are not in iflags but tb_flags */ /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ +/* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) @@ -330,6 +335,9 @@ struct MicroBlazeCPU { void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index a473c1867b..3980fba797 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -25,7 +25,6 @@ DEF_HELPER_3(mmu_read, i32, env, i32, i32) DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) #endif -DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_2(get, i32, i32, i32) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 1eabf5cc3f..67017ecc33 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -317,6 +317,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = mb_cpu_class_by_name; cc->has_work = mb_cpu_has_work; cc->do_interrupt = mb_cpu_do_interrupt; + cc->do_unaligned_access = mb_cpu_do_unaligned_access; cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 06f4322e09..0e3be251a7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -296,3 +296,31 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return false; } + +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + uint32_t esr, iflags; + + /* Recover the pc and iflags from the corresponding insn_start. */ + cpu_restore_state(cs, retaddr, true); + iflags = cpu->env.iflags; + + qemu_log_mask(CPU_LOG_INT, + "Unaligned access addr=" TARGET_FMT_lx + " pc=%x iflags=%x\n", addr, cpu->env.pc, iflags); + + esr = ESR_EC_UNALIGNED_DATA; + if (likely(iflags & ESR_ESS_FLAG)) { + esr |= iflags & ESR_ESS_MASK; + } else { + qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n"); + } + + cpu->env.ear = addr; + cpu->env.esr = esr; + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit(cs); +} diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index e6dcc79243..4614e99db3 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -365,27 +365,6 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b) return 0; } -void helper_memalign(CPUMBState *env, target_ulong addr, - uint32_t dr, uint32_t wr, - uint32_t mask) -{ - if (addr & mask) { - qemu_log_mask(CPU_LOG_INT, - "unaligned access addr=" TARGET_FMT_lx - " mask=%x, wr=%d dr=r%d\n", - addr, mask, wr, dr); - env->ear = addr; - env->esr = ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) << 5; - if (mask == 3) { - env->esr |= 1 << 11; - } - if (!(env->msr & MSR_EE)) { - return; - } - helper_raise_exception(env, EXCP_HW_EXCP); - } -} - void helper_stackprot(CPUMBState *env, target_ulong addr) { if (addr < env->slr || addr > env->shr) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d2ee163294..597b96ffb3 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -751,10 +751,22 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) return ret; } +static void record_unaligned_ess(DisasContext *dc, int rd, + MemOp size, bool store) +{ + uint32_t iflags = tcg_get_insn_start_param(dc->insn_start, 1); + + iflags |= ESR_ESS_FLAG; + iflags |= rd << 5; + iflags |= store * ESR_S; + iflags |= (size == MO_32) * ESR_W; + + tcg_set_insn_start_param(dc->insn_start, 1, iflags); +} + static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) { - TCGv_i32 v; MemOp size = mop & MO_SIZE; /* @@ -774,34 +786,15 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, sync_jmpstate(dc); - /* - * Microblaze gives MMU faults priority over faults due to - * unaligned addresses. That's why we speculatively do the load - * into v. If the load succeeds, we verify alignment of the - * address and if that succeeds we write into the destination reg. - */ - v = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); - - /* TODO: Convert to CPUClass::do_unaligned_access. */ - if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { - TCGv_i32 t0 = tcg_const_i32(0); - TCGv_i32 treg = tcg_const_i32(rd); - TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_helper_memalign(cpu_env, addr, treg, t0, tsize); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); + if (size > MO_8 && + (dc->tb_flags & MSR_EE) && + dc->cpu->cfg.unaligned_exceptions) { + record_unaligned_ess(dc, rd, size, false); + mop |= MO_ALIGN; } - if (rd) { - tcg_gen_mov_i32(cpu_R[rd], v); - } + tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); - tcg_temp_free_i32(v); tcg_temp_free(addr); return true; } @@ -931,28 +924,15 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, sync_jmpstate(dc); - tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); - - /* TODO: Convert to CPUClass::do_unaligned_access. */ - if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { - TCGv_i32 t1 = tcg_const_i32(1); - TCGv_i32 treg = tcg_const_i32(rd); - TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - /* FIXME: if the alignment is wrong, we should restore the value - * in memory. One possible way to achieve this is to probe - * the MMU prior to the memaccess, thay way we could put - * the alignment checks in between the probe and the mem - * access. - */ - gen_helper_memalign(cpu_env, addr, treg, t1, tsize); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); + if (size > MO_8 && + (dc->tb_flags & MSR_EE) && + dc->cpu->cfg.unaligned_exceptions) { + record_unaligned_ess(dc, rd, size, true); + mop |= MO_ALIGN; } + tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); + tcg_temp_free(addr); return true; } From patchwork Fri Aug 28 14:19:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248549 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1137596ilg; Fri, 28 Aug 2020 07:37:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyG31b10Y2Az/Cz0uVWsyEl6diGqdcbu8OoPioUvWRfbZ9SFMVqPCOxkl/Qd3wvAiYciuGw X-Received: by 2002:a25:2e10:: with SMTP id u16mr3036074ybu.17.1598625452871; Fri, 28 Aug 2020 07:37:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625452; cv=none; d=google.com; s=arc-20160816; b=YfXF6nUL7/FsLq+9jl/WfjJIyHxXFaUqB3eM2YqQ313x043KMGVoo3FGEO+b5e9Dfi GqxnpJmKCY9EcDwVUycwvEcM10neoIIHHlYEvCSJxtvEJwq7EUDz+H7GV5fzT6WI34Ps 3uNh1lBA+BobxABltixmwbsj6i827+HRxLi+p8gLdLDnOWV4QgNqCeMdwAUrOoIS3mB1 8fsVX6HHLR6/Wj4sD6mGd2FT5MdE4FmlwwTSEOQRj2prnSOGHACmMyBhqbHPfRVE7GLX jEvm78zYdvHflUwIxk8QrS95NgJltaHyrls1GzdDTpdMcUxKLaOlwKLm2BIsY+AINCkx w2sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zwo2tLKRvQRJhDTbPnKciACBLjC4l/PhJRnGW8zacPw=; b=EE3eFAcitgNcmZ6Ef/BW1UgP/FZKVEWOEtaNN0hq7t7fWD7hdpvj4mihAZfP2OM6Xn E+JgXnVOxe5Y255o/LOSK1k78VZoiM0cxSStUdNU/n/OhedxHh/ifiMT5idkWF9iWYS1 KgxuarKFz51QjRtxSMx7IcelxYN2PbAez6jXWDJNkOJzNGMDNQKH3CtKxp0gQshEbCrE o+pzLB21Yz9mlPDAJXYmGArPUykA4UaLuwS3RjH0ZMx8s39x2e/Tv3iyJhtWyFyCxj/9 ZSntcC8yJTPl+y/k8kjtpJTDvYro/DiYYuhkVseq8rq88gLezbZGbYuK2w4zkkT18v5o qtbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PXJUCSQe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s91si939597ybi.418.2020.08.28.07.37.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:37:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PXJUCSQe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfVU-0001Iw-8k for patch@linaro.org; Fri, 28 Aug 2020 10:37:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFL-0001wq-0u for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:51 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:33318) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFJ-0005PE-8y for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:50 -0400 Received: by mail-pl1-x643.google.com with SMTP id h2so540615plr.0 for ; Fri, 28 Aug 2020 07:20:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zwo2tLKRvQRJhDTbPnKciACBLjC4l/PhJRnGW8zacPw=; b=PXJUCSQeawL24bOK+pBya9y/6qqKkx1vVpKY9dPs6244AxiKuiaXzktpKPOsQqH+E1 Iqh89YAhc2AzTQdXZWoKpfoE2seW+vGt3/h8BdIyQ5tAn1ABEeC/0PacB4qxpui6VgUN 3Gs9QNQg/SazlTJtpFa5CQlG4gw22pGv351PRUZqaMog268zsgQGXb5fp+FkO9UTRTlb teH/yY32UseutouA3xLIABj3aijsmclzb9mW4v2tKLPhuzW4ETFXTL4Cn+b5EIepHn+V 6z7uL8JVEWpBvYe0S1lid0DjIAFbomlvqpqPNEB9kCpf9mzFT45b7N0LWgtjj+wUerT5 L2+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zwo2tLKRvQRJhDTbPnKciACBLjC4l/PhJRnGW8zacPw=; b=AJT7+q8M+nlJQfSG/18w4CkdCsX5J/LWwATaJ4txEpcAzSXoOMN4w9x1WVkwvfN0hO 04DqehiMhGUoTghTqtg5dB8J2hx90ZykMbI98FXUDX668g6kaAWbNQaKS0aYyyUmIYWC mQjgaRQMDDFznpUwEcrdHbE5pEm8dLTn7MjoOB4x8Dcfwu0MjcYEihBaN3sN50LKyj+J dr/LCXsTZlV+2l1YPzvJRt+WXa/zKboLHRkeRW5+4tpoxOQnhgD4eP9/V4ysA9yV+JNT riWZXSd6Avf/YLGkL7LQfynNBnqLAsKtMPQK/Y6SSK3mLgmhQXZ3YIEGhKsP6NHKxnbY OovA== X-Gm-Message-State: AOAM532+8YWPpfrLYTmFNEgBmMvk2jqYOax0Di4/zUzlZb2XlQPUUFrA nRQmwwxzqJL4i1rXlP+8nJgF5v9gjgTlkA== X-Received: by 2002:a17:902:44c:: with SMTP id 70mr1468024ple.293.1598624447602; Fri, 28 Aug 2020 07:20:47 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 60/76] target/microblaze: Replace clear_imm with tb_flags_to_set Date: Fri, 28 Aug 2020 07:19:13 -0700 Message-Id: <20200828141929.77854-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This more general update variable will be able to handle delay slots as well. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 597b96ffb3..c0b586f467 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -75,7 +75,7 @@ typedef struct DisasContext { unsigned int cpustate_changed; unsigned int delayed_branch; unsigned int tb_flags; - unsigned int clear_imm; + unsigned int tb_flags_to_set; int mem_index; #define JMP_NOJMP 0 @@ -535,8 +535,7 @@ static bool trans_imm(DisasContext *dc, arg_imm *arg) { dc->ext_imm = arg->imm << 16; tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags |= IMM_FLAG; - dc->clear_imm = 0; + dc->tb_flags_to_set = IMM_FLAG; return true; } @@ -1688,7 +1687,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) (uint32_t)dc->base.pc_next); } - dc->clear_imm = 1; + dc->tb_flags_to_set = 0; + ir = cpu_ldl_code(env, dc->base.pc_next); if (!decode(dc, ir)) { old_decode(dc, ir); @@ -1700,10 +1700,13 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->r0_set = false; } - if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags &= ~IMM_FLAG; + /* Discard the imm global when its contents cannot be used. */ + if ((dc->tb_flags & ~dc->tb_flags_to_set) & IMM_FLAG) { tcg_gen_discard_i32(cpu_imm); } + + dc->tb_flags &= ~IMM_FLAG; + dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; if (dc->delayed_branch && --dc->delayed_branch == 0) { From patchwork Fri Aug 28 14:19:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248579 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1149319ilg; Fri, 28 Aug 2020 07:52:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyRrp7CDLLbvTJC1RWOM0s6UAFc8mqrr+Ti5KlQlPGV5DinWEV5y4lX+aCKEg6rV30JL/dy X-Received: by 2002:a5b:411:: with SMTP id m17mr2963897ybp.492.1598626369750; Fri, 28 Aug 2020 07:52:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626369; cv=none; d=google.com; s=arc-20160816; b=TA8dJ/VuMf4vmU50oXNeerWRC2Red8MtxRpZplsf4BcMUZud+2XPHt747tUiPTPMVm W8cVAPMD1uT1i2LMGiF0SZWcWs8SD7XfbMBQ6FVVzn2VeOHf34vewIOpNPGP93NPkKFs /7UMEimsT30vOtpoRJBeeFb1teL0Xmr9qi2xMyHMchHGlgxVeaIZQCXxK0zyn4sTGnnD 4MJ+giexrbMtCHSfPECv+PRM+Hvf341MXHrk0DqIFVtpD6VbclpIcFlQ6OBmGBggai7Q tL1vTCsC9Eatpnz4timhc6KBMLM5ajle1TOXw/oTytRpdAKV1i/3vuIxXRRISR7SRjPV gTpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NBFrP1+/jgZ0aFs6sSu+fBXeEHUysvclKSZS577gabk=; b=QvJzhYz3DQBR5PnUrq4G1sg43QPChl7327zO9QRV6brOFWV/GR6HHWDRg0WUgtLAwR +u4IUX8fswqQazmvhwM3Gb8u++l3wC0hdqdQJkfrxi2nUJBK9QgRjjbUrbjfq+fGPuhh j8jY6VkLzVojFyV1hfUiQfIfIk7TcxBGLT5A4WYCRf7Ma8xR54JNVO03OYcUvNmrheHg M/NCgn+C4IGb/L/JD263iwK8NvXUzDJjULoItI8GMpmJiErHqYoKIP52g/eoAOa9eHzQ HyA8xq0zxDGY6WWCl/DDkyeir9jxNJA+jhh+hDn9cb4e5gln8tl5FGVW/Yq4z4zhHJUj fqsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IzIYlYe9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The multi-stage counter can be replaced by clearing D_FLAG, the or'ing in tb_flags_to_set. The jump then happens when D_FLAG is finally cleared. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c0b586f467..811c92d23b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -73,7 +73,6 @@ typedef struct DisasContext { uint16_t imm; unsigned int cpustate_changed; - unsigned int delayed_branch; unsigned int tb_flags; unsigned int tb_flags_to_set; int mem_index; @@ -1328,10 +1327,9 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) static void dec_setup_dslot(DisasContext *dc) { - dc->delayed_branch = 2; - dc->tb_flags |= D_FLAG; + dc->tb_flags_to_set |= D_FLAG; if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags |= BIMM_FLAG; + dc->tb_flags_to_set |= BIMM_FLAG; } } @@ -1343,7 +1341,6 @@ static void dec_bcc(DisasContext *dc) cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); - dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); } @@ -1419,7 +1416,6 @@ static void dec_br(DisasContext *dc) } } - dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); } @@ -1633,8 +1629,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; - dc->delayed_branch = !!(dc->tb_flags & D_FLAG); - dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; + dc->jmp = dc->tb_flags & D_FLAG ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; @@ -1705,11 +1700,11 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) tcg_gen_discard_i32(cpu_imm); } - dc->tb_flags &= ~IMM_FLAG; + dc->tb_flags &= ~(IMM_FLAG | BIMM_FLAG | D_FLAG); dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; - if (dc->delayed_branch && --dc->delayed_branch == 0) { + if (dc->jmp != JMP_NOJMP && !(dc->tb_flags & D_FLAG)) { if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); } @@ -1719,8 +1714,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } - /* Clear the delay slot flag. */ - dc->tb_flags &= ~D_FLAG; dc->base.is_jmp = DISAS_JUMP; } From patchwork Fri Aug 28 14:19:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248567 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1143759ilg; Fri, 28 Aug 2020 07:45:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwrXN9mNYdU0vOhjytWN6F4KzatcGOM2GigID6RertlRwZy3ygiHhXGfOhknH98PKPO8IBe X-Received: by 2002:a25:d98f:: with SMTP id q137mr2843892ybg.182.1598625923634; Fri, 28 Aug 2020 07:45:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625923; cv=none; d=google.com; s=arc-20160816; b=sh/2ITgk5TrcA9hNoRhfsAyh/dNebCMkuVVPzPyQuWZkVo1p7c7P9p8T+L8ZvpaRY2 gSLRiMG5NYy7Ck5m0Pp80/ybLTNwd8cCc+Bl28QsqSwiUEUasIRi21AW9EGGwiOsGTKk 7hZT5XTYm8FdSGut2jn1xEjFTzlhXgF1ewviYD9sCeFeTKBZgavRYKWzuVHfk1hEA0ZY SWp+ajdzC4/aoN3y9Y0w9nDOFh7bge7sY7TrUwkf9JwpJrxR6mrGoRjyfNLi6R9MVyPt 4okdD5Wwlo0c75emJQA/CAPsL07ypsJHWfiVNKHR2pTFJVtAq2aWnghqxt5R74GSPo/I CpAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XgYEr9I/NlTUuTKL+AU6VwkfWOL8hdo8tZQBDIES8xQ=; b=WikUe9efHMHCdsQLFobG0ei9g2AomU7ixglgw1akIPR7Zs7zEn6jVKMNZmeh1sonEP Da7i0pV4O8ylZyIi4FvHh/bm+p0FmbaGM5+QyoWD0Q9J61/IefuZEjrwyObXkN9Uy2IC W6DJNZcvPAvfV6bNddZjKS12Igmfni00CHPdOv5iee21YuPAp7mhvHkVfXsQCZvkC7Ei 4r+R7/tC1h2n+4vM5nozV1DBoGJEWQE+ivtgQHuqgfz1BTF/0w9BSSgiLICznix2KvHS 5Dbx/afw+NMsCAhYYZqf2/HPRJMpBb0ESFPaHK0MYrWGBfpq+7/0h2bp9TjQoPWHAFQv OMgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CSSEp5lq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Using lookup_symbol is quite slow; remove that. Decode the various bits of iflags; only show imm, btaken, btarget when they are relevant to iflags. Improve formatting. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 67 +++++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 26 deletions(-) -- 2.25.1 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 811c92d23b..3b63fd79e5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1818,41 +1818,56 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; + uint32_t iflags; int i; - if (!env) { - return; - } - - qemu_fprintf(f, "IN: PC=%x %s\n", - env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "imm=%x iflags=%x fsr=%x rbtr=%x\n", - env->msr, env->esr, env->ear, - env->imm, env->iflags, env->fsr, env->btr); - qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", - env->btaken, env->btarget, + qemu_fprintf(f, "pc=0x%08x msr=0x%05x mode=%s(saved=%s) eip=%d ie=%d\n", + env->pc, env->msr, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", (bool)(env->msr & MSR_EIP), (bool)(env->msr & MSR_IE)); - for (i = 0; i < 12; i++) { - qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); - if ((i + 1) % 4 == 0) { - qemu_fprintf(f, "\n"); - } + + iflags = env->iflags; + qemu_fprintf(f, "iflags: 0x%08x", iflags); + if (iflags & IMM_FLAG) { + qemu_fprintf(f, " IMM(0x%08x)", env->imm); + } + if (iflags & BIMM_FLAG) { + qemu_fprintf(f, " BIMM"); + } + if (iflags & D_FLAG) { + qemu_fprintf(f, " D(btaken=%d btarget=0x%08x)", + env->btaken, env->btarget); + } + if (iflags & DRTI_FLAG) { + qemu_fprintf(f, " DRTI"); + } + if (iflags & DRTE_FLAG) { + qemu_fprintf(f, " DRTE"); + } + if (iflags & DRTB_FLAG) { + qemu_fprintf(f, " DRTB"); + } + if (iflags & ESR_ESS_FLAG) { + qemu_fprintf(f, " ESR_ESS(0x%04x)", iflags & ESR_ESS_MASK); + } + + qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n" + "ear=0x%016" PRIx64 " slr=0x%x shr=0x%x\n", + env->esr, env->fsr, env->btr, env->edr, + env->ear, env->slr, env->shr); + + for (i = 0; i < 12; i++) { + qemu_fprintf(f, "rpvr%-2d=%08x%c", + i, env->pvr.regs[i], i % 4 == 3 ? '\n' : ' '); } - /* Registers that aren't modeled are reported as 0 */ - qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " - "rtlblo=0 rtlbhi=0\n", env->edr); - qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { - qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); - if ((i + 1) % 4 == 0) - qemu_fprintf(f, "\n"); - } - qemu_fprintf(f, "\n\n"); + qemu_fprintf(f, "r%2.2d=%08x%c", + i, env->regs[i], i % 4 == 3 ? '\n' : ' '); + } + qemu_fprintf(f, "\n"); } void mb_tcg_init(void) From patchwork Fri Aug 28 14:19:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248552 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1138854ilg; Fri, 28 Aug 2020 07:39:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyJIy34O7Y4t4owB4XOM1MXnpZlWq74TK7voWdIPH8cj6I0uBzIHeTt86B/LJfz1YoUsJqT X-Received: by 2002:a25:fc2:: with SMTP id 185mr2823531ybp.96.1598625549056; Fri, 28 Aug 2020 07:39:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625549; cv=none; d=google.com; s=arc-20160816; b=JlCZgkPFTPJZM5QLGVnRjI8/5DgioKVB0EoTbhKoVfgTjyjOYjttcSZdiXJKxB++SF rQ0PAUlmkPwX5I13zJjQORZiZOb9dTTwoDR3QOprTexcp2CV9w+L7py2lH6lN9McjtYD F+MT8bUh6kYInvBhTPqKSbK5ydelETetBxU+vPONfxiVs880fTGBNGD8ymxW3wRnTdXg 0pSWQjTVuIgK1NVD1LjRea8qypSMB26lppSZfEIru7sSc54238Xs+R1jD/sRhoWkYqyb 7SoYCpgAckS8dvS/hR1TKewX0jL1AuO81MfjnjtSXIkDfXcKBlU/PCQQLz1IoEol6nI8 /FFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6XUqO2rYEgAKlp1UOKKGq1417JAR/UY8ohDagaMV8Xo=; b=uid0vqwvypVNcamoN7RPZdfB4PJ4n9yW/XooNTGNaA/UQltVerqYlhnbK8jJ9xybOd z1bsMPmA2WCwtgMFkGAdC1e1rSMvthRNH6uwav020Ho887q9s5XmaI/3qHXVIMpT4oM4 c9+g5eWrcxxNBOuu0FXg0LiAxrJXsIxRjqa0dKxoloHjUjTxh3TVvjz9LgNYqksBj1Uf xy0hCxlBJYKVCOAEAOo/Fx5xRcEphFvpYLshSzXbnMtItbVwDWw3ec1b9LG3ZrIYfSJ1 q5ZO1xa6c+hXdJVOyerHHC8ix63JpS7eisRijs3j5JldD3U9FlvO/1VCLCacyskKY38c P0Pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yOg+sc88; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d79si1188563ybc.11.2020.08.28.07.39.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:39:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yOg+sc88; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfX2-0004do-Ek for patch@linaro.org; Fri, 28 Aug 2020 10:39:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFP-00028y-LL for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:55 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:54370) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFN-0005Pv-GO for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:55 -0400 Received: by mail-pj1-x1044.google.com with SMTP id mt12so560522pjb.4 for ; Fri, 28 Aug 2020 07:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6XUqO2rYEgAKlp1UOKKGq1417JAR/UY8ohDagaMV8Xo=; b=yOg+sc8881FaFZ00TvoRvC1DULuB/ByNlqLh+RaX7h+Lo4zFdOLQsGU6Tbfln8aLJT PKRzzgIYQOEqU0EH3wVI65fdIxejbfWs/bELLOeRAzEH3RqRpYc0gZJOmH7Wyt+WmsZS mLxljfm+Y6eIaUQahRaFNivHo7T/oqIjJHJUFLE8U6tS91E86gzAYDQBZ+C7Du2Pi/5M 0W2nRJtbCDs6f9hKi5wFQfmlcF2dJVKsMt/LHJldxK9HOmOxsmkstlCoyeoRj6KcAd10 PDWbBP6j9EQVhzJa4ok2oGrWWVUA8ofGuzJ2Pebp+FlyMzyQ5IvgW79/u5F97asf6JrG IU1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6XUqO2rYEgAKlp1UOKKGq1417JAR/UY8ohDagaMV8Xo=; b=RRVijqvXXhk/rcL/0na6/9+CZXcirNaPCrn2LeBMZ380bwLDGuJ79I0Jy+KOi48dBL bE8LXjzjN3LJgNnkBQrCujp1omi+76PSbRqR6XM2SAr6z04F3lRawUP1ZOSG1KwGRnOw oI4dBC+dAdB/O9X8OEdqvkSEip3sCxQKudf5bd+9RlJsKa645rY1y0so9gUB87heEWDh 7/91cKOstTSJAEwOD389LzVJsYDfaVCqPlKjl0qagBxzMTDzb/W3asAuF0ZDwfgqRwGT Gx68uW98iXxhW5EXiTAtM3r9OHAb+kpuk3+3h7yuDaM+W7ZouZrzXTzTtevA8oDc4rU3 yObQ== X-Gm-Message-State: AOAM5312/pLbAaLLHsfapwZR3zivX8C7tizMtCvP+5FQ9GzoEY2M6Gt8 x7GXj1SNYtQUxc2e62ZN2bnpQALphJ/zLw== X-Received: by 2002:a17:90b:fd0:: with SMTP id gd16mr1414217pjb.122.1598624451729; Fri, 28 Aug 2020 07:20:51 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 63/76] target/microblaze: Convert brk and brki to decodetree Date: Fri, 28 Aug 2020 07:19:16 -0700 Message-Id: <20200828141929.77854-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split these out of the normal branch instructions, as they require special handling. Perform the entire operation inline, instead of raising EXCP_BREAK to do the work in mb_cpu_do_interrupt. This fixes a bug in that brki rd, imm, for imm != 0x18 is not supposed to set MSR_BIP. This fixes a bug in that imm == 0 is the reset vector and 0x18 is the debug vector, and neither should raise a tcg exception in system mode. Introduce EXCP_SYSCALL for microblaze-linux-user. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/insns.decode | 11 ++++ linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 10 +-- target/microblaze/translate.c | 107 ++++++++++++++++++------------- 5 files changed, 79 insertions(+), 53 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 63b8d93d41..1528749a0b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -31,7 +31,7 @@ typedef struct CPUMBState CPUMBState; #define EXCP_MMU 1 #define EXCP_IRQ 2 -#define EXCP_BREAK 3 +#define EXCP_SYSCALL 3 /* user-only */ #define EXCP_HW_BREAK 4 #define EXCP_HW_EXCP 5 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 47b92b9cbc..9273a51d20 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -19,7 +19,9 @@ &typea0 rd ra &typea rd ra rb +&typea_br rd rb &typeb rd ra imm +&typeb_br rd imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -30,9 +32,15 @@ # Officially typea, but with rb==0, which is not used. @typea0 ...... rd:5 ra:5 ................ &typea0 +# Officially typea, but with ra as opcode. +@typea_br ...... rd:5 ..... rb:5 ........... &typea_br + # Officially typeb, but any immediate extension is unused. @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb +# Officially typeb, but with ra as opcode. +@typeb_br ...... rd:5 ..... ................ &typeb_br imm=%extimm + # For convenience, extract the two imm_w/imm_s fields, then pack # them back together as "imm". Doing this makes it easiest to # match the required zero at bit 5. @@ -60,6 +68,9 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +brk 100110 ..... 01100 ..... 000 0000 0000 @typea_br +brki 101110 ..... 01100 ................ @typeb_br + bsrl 010001 ..... ..... ..... 000 0000 0000 @typea bsra 010001 ..... ..... ..... 010 0000 0000 @typea bsll 010001 ..... ..... ..... 100 0000 0000 @typea diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 3de99ea311..c3396a6e09 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -48,7 +48,7 @@ void cpu_loop(CPUMBState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_BREAK: + case EXCP_SYSCALL: /* Return address is 4 bytes after the call. */ env->regs[14] += 4; env->pc = env->regs[14]; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 0e3be251a7..1667822fb7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -230,7 +230,6 @@ void mb_cpu_do_interrupt(CPUState *cs) //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; - case EXCP_BREAK: case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); @@ -242,13 +241,8 @@ void mb_cpu_do_interrupt(CPUState *cs) msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); msr |= t; msr |= MSR_BIP; - if (cs->exception_index == EXCP_HW_BREAK) { - env->regs[16] = env->pc; - msr |= MSR_BIP; - env->pc = cpu->cfg.base_vectors + 0x18; - } else { - env->pc = env->btarget; - } + env->regs[16] = env->pc; + env->pc = cpu->cfg.base_vectors + 0x18; mb_cpu_write_msr(env, msr); break; default: diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3b63fd79e5..1c772b95d9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1068,6 +1068,65 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) return true; } +static bool trans_brk(DisasContext *dc, arg_typea_br *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb)); + if (arg->rd) { + tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); + } + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP); + tcg_gen_movi_tl(cpu_res_addr, -1); + + dc->base.is_jmp = DISAS_UPDATE; + return true; +} + +static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) +{ + uint32_t imm = arg->imm; + + if (trap_userspace(dc, imm != 0x8 && imm != 0x18)) { + return true; + } + tcg_gen_movi_i32(cpu_pc, imm); + if (arg->rd) { + tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); + } + tcg_gen_movi_tl(cpu_res_addr, -1); + +#ifdef CONFIG_USER_ONLY + switch (imm) { + case 0x8: /* syscall trap */ + gen_raise_exception_sync(dc, EXCP_SYSCALL); + break; + case 0x18: /* debug trap */ + gen_raise_exception_sync(dc, EXCP_DEBUG); + break; + default: /* eliminated with trap_userspace check */ + g_assert_not_reached(); + } +#else + uint32_t msr_to_set = 0; + + if (imm != 0x18) { + msr_to_set |= MSR_BIP; + } + if (imm == 0x8 || imm == 0x18) { + /* MSR_UM and MSR_VM are in tb_flags, so we know their value. */ + msr_to_set |= (dc->tb_flags & (MSR_UM | MSR_VM)) << 1; + tcg_gen_andi_i32(cpu_msr, cpu_msr, + ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM)); + } + tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set); + dc->base.is_jmp = DISAS_UPDATE; +#endif + + return true; +} + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -1359,6 +1418,7 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { unsigned int dslot, link, abs, mbar; + uint32_t add_pc; dslot = dc->ir & (1 << 20); abs = dc->ir & (1 << 19); @@ -1401,21 +1461,6 @@ static void dec_br(DisasContext *dc) return; } - if (abs && link && !dslot) { - if (dc->type_b) { - /* BRKI */ - uint32_t imm = dec_alu_typeb_imm(dc); - if (trap_userspace(dc, imm != 8 && imm != 0x18)) { - return; - } - } else { - /* BRK */ - if (trap_userspace(dc, true)) { - return; - } - } - } - if (dslot) { dec_setup_dslot(dc); } @@ -1423,38 +1468,14 @@ static void dec_br(DisasContext *dc) tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); } - if (abs) { - if (dc->type_b) { - uint32_t dest = dec_alu_typeb_imm(dc); - - dc->jmp = JMP_DIRECT; - dc->jmp_pc = dest; - tcg_gen_movi_i32(cpu_btarget, dest); - if (link && !dslot) { - switch (dest) { - case 8: - case 0x18: - gen_raise_exception_sync(dc, EXCP_BREAK); - break; - case 0: - gen_raise_exception_sync(dc, EXCP_DEBUG); - break; - } - } - } else { - dc->jmp = JMP_INDIRECT; - tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); - if (link && !dslot) { - gen_raise_exception_sync(dc, EXCP_BREAK); - } - } - } else if (dc->type_b) { + add_pc = abs ? 0 : dc->base.pc_next; + if (dc->type_b) { dc->jmp = JMP_DIRECT; - dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); + dc->jmp_pc = add_pc + dec_alu_typeb_imm(dc); tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); } tcg_gen_movi_i32(cpu_btaken, 1); } From patchwork Fri Aug 28 14:19:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248580 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1149990ilg; Fri, 28 Aug 2020 07:53:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwR0jIE0Hd1CovXsR5OWMlL518uv4cUeW8GToq0We2Heng2Ga2wnzEiNNF58ffyueaF2xX+ X-Received: by 2002:a25:502:: with SMTP id 2mr2692831ybf.2.1598626430474; Fri, 28 Aug 2020 07:53:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626430; cv=none; d=google.com; s=arc-20160816; b=P+xUMZEVrm1G2NZtD0a2sUTwVDnnP1QOcJthHaTa44w+lmJuY0k8YqQvbBrqUIxizH a4b0gKIpbg7z+P6q5tCsIqHe52vMB0V2E+5haMzJlrlYlMGOA9ZiKNVa3rw+r3vd85uN xPNiUfL61hd0huPjS4Lp5jEPt5LmgzT0mDjC8jNIavhQDTisnchBOIy3e9ixzjQt2Rl/ LsUwPF67gC7bu88WAD67WFSu7Mn4u064LYArzHrn5MoyeyGpO8cOWutE5mYFxrhG8+In rUFxPZvRUkGZTHrt3F12Jfezntt5DVb2vKloHHVrz0Wk0tllzIxMxjSHi1QpVSRgtqqS 32Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=22O6iYfJ5kkzdH0WE/DLGgphQgLtnFGPTphEDVG9AXk=; b=jdC6SiuBGnNEay9uGgwaMTreWz6v8MJ2fmaHFsdf2ddU/4HHD8D+qi41VjV9KuJmDk lTLMhUxeon7j8mKAHt3kmxhWkbRrmeDy1tfGPcC2KKEuoHZ07LUkOkxt2fNOIytBkRXB sIN56Oi2dPMbloDrX4IIB0qLptsqZ9DKXeiNuCVVXPNJh9EqSXt7gVZiroyrSqXv1zIi MNni/w2eBSLQNutaYMFHldGkfgqouZvQMv5e/iCzeWDIshzxYKP0Hj5+OoqnsUfEuFA5 Wxfzw979dTIIVwtyHOTpd6ylw/I5c5gOItZ0bldlxiuuBsnWEpkfDWEimkqX3lXYErIn gSjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gCYyfJHK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split this out of the normal branch instructions, as it requires special handling. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 2 + target/microblaze/translate.c | 85 +++++++++++++++++++--------------- 2 files changed, 49 insertions(+), 38 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 9273a51d20..8eba47d90c 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -127,6 +127,8 @@ lwea 110010 ..... ..... ..... 0001 000 0000 @typea lwx 110010 ..... ..... ..... 1000 000 0000 @typea lwi 111010 ..... ..... ................ @typeb +mbar 101110 imm:5 00010 0000 0000 0000 0100 + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 1c772b95d9..832cf85c64 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1127,6 +1127,52 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) return true; } +static bool trans_mbar(DisasContext *dc, arg_mbar *arg) +{ + int mbar_imm = arg->imm; + + /* Data access memory barrier. */ + if ((mbar_imm & 2) == 0) { + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + } + + /* Sleep. */ + if (mbar_imm & 16) { + TCGv_i32 tmp_1; + + if (trap_userspace(dc, true)) { + /* Sleep is a privileged instruction. */ + return true; + } + + t_sync_flags(dc); + + tmp_1 = tcg_const_i32(1); + tcg_gen_st_i32(tmp_1, cpu_env, + -offsetof(MicroBlazeCPU, env) + +offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp_1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); + + gen_raise_exception(dc, EXCP_HLT); + } + + /* + * If !(mbar_imm & 1), this is an instruction access memory barrier + * and we need to end the TB so that we recognize self-modified + * code immediately. + * + * However, there are some data mbars that need the TB break + * (and return to main loop) to recognize interrupts right away. + * E.g. recognizing a change to an interrupt controller register. + * + * Therefore, choose to end the TB always. + */ + dc->cpustate_changed = 1; + return true; +} + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -1417,50 +1463,13 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { - unsigned int dslot, link, abs, mbar; + unsigned int dslot, link, abs; uint32_t add_pc; dslot = dc->ir & (1 << 20); abs = dc->ir & (1 << 19); link = dc->ir & (1 << 18); - /* Memory barrier. */ - mbar = (dc->ir >> 16) & 31; - if (mbar == 2 && dc->imm == 4) { - uint16_t mbar_imm = dc->rd; - - /* Data access memory barrier. */ - if ((mbar_imm & 2) == 0) { - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); - } - - /* mbar IMM & 16 decodes to sleep. */ - if (mbar_imm & 16) { - TCGv_i32 tmp_1; - - if (trap_userspace(dc, true)) { - /* Sleep is a privileged instruction. */ - return; - } - - t_sync_flags(dc); - - tmp_1 = tcg_const_i32(1); - tcg_gen_st_i32(tmp_1, cpu_env, - -offsetof(MicroBlazeCPU, env) - +offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp_1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - - gen_raise_exception(dc, EXCP_HLT); - return; - } - /* Break the TB. */ - dc->cpustate_changed = 1; - return; - } - if (dslot) { dec_setup_dslot(dc); } From patchwork Fri Aug 28 14:19:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248569 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1144745ilg; Fri, 28 Aug 2020 07:46:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJxtkWH0JtRySRy367uC8Ubphy1t5OeCpPKyb1GOvyWzeZRf5D83VzKBRWktvMQHoNa4sU X-Received: by 2002:a25:9885:: with SMTP id l5mr3202298ybo.0.1598626002529; Fri, 28 Aug 2020 07:46:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626002; cv=none; d=google.com; s=arc-20160816; b=rN489vJ+jEweE5CdRlYUR98HBpKmUgR72D/xWXd5gDbI/BEXbtFwPpkn2QBA9GccCd yfW/NieZMYSZorG0M/8UyoH8zH/elKF5ddaB9fsxSfw0WDDBTFRuO+slY4iOL7FKHdwq VT/gWqG/TiziVgeaagL8EUWg2x3bcBL69VBu4UlGlVnXkBge0+MpF3A8GjJ15//a/9Tj 9HbsNcUmXtvh1zNwXlIgI4aO4Z++/iXnNpXlI/jJXkEgGQUM4VfZT7Gcc4gKxJBOm0jK QWn61fMibfhzAO2hs6wWPecq0m/Equ8I8KV8QWsswcsxZ3xfNKt4KAMQaFtdMxu4UdUA 6/tw== ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the btaken variable, and simplify things by always computing the full branch destination into btarget. This avoids all need for sync_jmpstate(). Retain the direct branch behaviour by remembering the jump destination in jmp_dest, discarding btarget. In the normal case, where the branch delay slot cannot trap (e.g. arithmetic not memory operation), tcg will remove the computation into btarget, leaving us with just the tcg direct branching at the end. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/translate.c | 192 ++++++++++++++-------------------- 2 files changed, 79 insertions(+), 117 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 1528749a0b..4298f242a6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -234,8 +234,8 @@ typedef struct CPUMBState CPUMBState; #define TARGET_INSN_START_EXTRA_WORDS 1 struct CPUMBState { - uint32_t btaken; - uint32_t btarget; + uint32_t bvalue; /* TCG temporary, only valid during a TB */ + uint32_t btarget; /* Full resolved branch destination */ uint32_t imm; uint32_t regs[32]; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 832cf85c64..1545974669 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -45,7 +45,7 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i32 cpu_msr_c; static TCGv_i32 cpu_imm; -static TCGv_i32 cpu_btaken; +static TCGv_i32 cpu_bvalue; static TCGv_i32 cpu_btarget; static TCGv_i32 cpu_iflags; static TCGv cpu_res_addr; @@ -77,12 +77,11 @@ typedef struct DisasContext { unsigned int tb_flags_to_set; int mem_index; -#define JMP_NOJMP 0 -#define JMP_DIRECT 1 -#define JMP_DIRECT_CC 2 -#define JMP_INDIRECT 3 - unsigned int jmp; - uint32_t jmp_pc; + /* Condition under which to jump, including NEVER and ALWAYS. */ + TCGCond jmp_cond; + + /* Immediate branch-taken destination, or -1 for indirect. */ + uint32_t jmp_dest; int abort_at_next_insn; } DisasContext; @@ -106,17 +105,6 @@ static void t_sync_flags(DisasContext *dc) } } -static inline void sync_jmpstate(DisasContext *dc) -{ - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(cpu_btaken, 1); - } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); - } -} - static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); @@ -782,8 +770,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -885,8 +871,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - sync_jmpstate(dc); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); tcg_gen_mov_tl(cpu_res_addr, addr); tcg_temp_free(addr); @@ -920,8 +904,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -1023,8 +1005,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) TCGLabel *swx_fail = gen_new_label(); TCGv_i32 tval; - sync_jmpstate(dc); - /* swx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); @@ -1392,44 +1372,6 @@ static void dec_msr(DisasContext *dc) } } -static inline void eval_cc(DisasContext *dc, unsigned int cc, - TCGv_i32 d, TCGv_i32 a) -{ - static const int mb_to_tcg_cc[] = { - [CC_EQ] = TCG_COND_EQ, - [CC_NE] = TCG_COND_NE, - [CC_LT] = TCG_COND_LT, - [CC_LE] = TCG_COND_LE, - [CC_GE] = TCG_COND_GE, - [CC_GT] = TCG_COND_GT, - }; - - switch (cc) { - case CC_EQ: - case CC_NE: - case CC_LT: - case CC_LE: - case CC_GE: - case CC_GT: - tcg_gen_setcondi_i32(mb_to_tcg_cc[cc], d, a, 0); - break; - default: - cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); - break; - } -} - -static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) -{ - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, - cpu_btaken, zero, - pc_true, pc_false); - - tcg_temp_free_i32(zero); -} - static void dec_setup_dslot(DisasContext *dc) { dc->tb_flags_to_set |= D_FLAG; @@ -1440,8 +1382,17 @@ static void dec_setup_dslot(DisasContext *dc) static void dec_bcc(DisasContext *dc) { + static const TCGCond mb_to_tcg_cc[] = { + [CC_EQ] = TCG_COND_EQ, + [CC_NE] = TCG_COND_NE, + [CC_LT] = TCG_COND_LT, + [CC_LE] = TCG_COND_LE, + [CC_GE] = TCG_COND_GE, + [CC_GT] = TCG_COND_GT, + }; unsigned int cc; unsigned int dslot; + TCGv_i32 zero, next; cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); @@ -1450,15 +1401,29 @@ static void dec_bcc(DisasContext *dc) dec_setup_dslot(dc); } + dc->jmp_cond = mb_to_tcg_cc[cc]; + + /* Cache the condition register in cpu_bvalue across any delay slot. */ + tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]); + + /* Store the branch taken destination into btarget. */ if (dc->type_b) { - dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb), + dc->base.pc_next); } - eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); + + /* Compute the final destination into btarget. */ + zero = tcg_const_i32(0); + next = tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4); + tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, + reg_for_read(dc, dc->ra), zero, + cpu_btarget, next); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(next); } static void dec_br(DisasContext *dc) @@ -1479,14 +1444,13 @@ static void dec_br(DisasContext *dc) add_pc = abs ? 0 : dc->base.pc_next; if (dc->type_b) { - dc->jmp = JMP_DIRECT; - dc->jmp_pc = add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest = add_pc + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp = JMP_INDIRECT; + dc->jmp_dest = -1; tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); } - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond = TCG_COND_ALWAYS; } static inline void do_rti(DisasContext *dc) @@ -1567,8 +1531,8 @@ static void dec_rts(DisasContext *dc) dc->tb_flags |= DRTE_FLAG; } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond = TCG_COND_ALWAYS; + dc->jmp_dest = -1; tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } @@ -1659,13 +1623,14 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; - dc->jmp = dc->tb_flags & D_FLAG ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; dc->mem_index = cpu_mmu_index(&cpu->env, false); + dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER; + dc->jmp_dest = -1; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1734,14 +1699,12 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; - if (dc->jmp != JMP_NOJMP && !(dc->tb_flags & D_FLAG)) { + if (dc->jmp_cond != TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); - } - if (dc->tb_flags & DRTB_FLAG) { + } else if (dc->tb_flags & DRTB_FLAG) { do_rtb(dc); - } - if (dc->tb_flags & DRTE_FLAG) { + } else if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } dc->base.is_jmp = DISAS_JUMP; @@ -1766,19 +1729,13 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) } t_sync_flags(dc); - if (dc->tb_flags & D_FLAG) { - sync_jmpstate(dc); - dc->jmp = JMP_NOJMP; - } switch (dc->base.is_jmp) { case DISAS_TOO_MANY: - assert(dc->jmp == JMP_NOJMP); gen_goto_tb(dc, 0, dc->base.pc_next); return; case DISAS_UPDATE: - assert(dc->jmp == JMP_NOJMP); if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { @@ -1787,35 +1744,41 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) return; case DISAS_JUMP: - switch (dc->jmp) { - case JMP_INDIRECT: - { - TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); + if (dc->jmp_dest != -1 && !cs->singlestep_enabled) { + /* Direct jump. */ + tcg_gen_discard_i32(cpu_btarget); - if (unlikely(cs->singlestep_enabled)) { - gen_raise_exception(dc, EXCP_DEBUG); - } else { - tcg_gen_exit_tb(NULL, 0); - } - } - return; + if (dc->jmp_cond != TCG_COND_ALWAYS) { + /* Conditional direct jump. */ + TCGLabel *taken = gen_new_label(); + TCGv_i32 tmp = tcg_temp_new_i32(); - case JMP_DIRECT_CC: - { - TCGLabel *l1 = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + /* + * Copy bvalue to a temp now, so we can discard bvalue. + * This can avoid writing bvalue to memory when the + * delay slot cannot raise an exception. + */ + tcg_gen_mov_i32(tmp, cpu_bvalue); + tcg_gen_discard_i32(cpu_bvalue); + + tcg_gen_brcondi_i32(dc->jmp_cond, tmp, 0, taken); gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); + gen_set_label(taken); } - /* fall through */ - - case JMP_DIRECT: - gen_goto_tb(dc, 0, dc->jmp_pc); + gen_goto_tb(dc, 0, dc->jmp_dest); return; } - /* fall through */ + + /* Indirect jump (or direct jump w/ singlestep) */ + tcg_gen_mov_i32(cpu_pc, cpu_btarget); + tcg_gen_discard_i32(cpu_btarget); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; default: g_assert_not_reached(); @@ -1867,8 +1830,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " BIMM"); } if (iflags & D_FLAG) { - qemu_fprintf(f, " D(btaken=%d btarget=0x%08x)", - env->btaken, env->btarget); + qemu_fprintf(f, " D(btarget=0x%08x)", env->btarget); } if (iflags & DRTI_FLAG) { qemu_fprintf(f, " DRTI"); @@ -1918,7 +1880,7 @@ void mb_tcg_init(void) SP(msr_c), SP(imm), SP(iflags), - SP(btaken), + SP(bvalue), SP(btarget), SP(res_val), }; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 14 ++++++ target/microblaze/translate.c | 87 +++++++++++++++++++--------------- 2 files changed, 63 insertions(+), 38 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 8eba47d90c..340dd999b6 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -68,6 +68,20 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +br 100110 ..... 00000 ..... 000 0000 0000 @typea_br +bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br +brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br +brad 100110 ..... 11000 ..... 000 0000 0000 @typea_br +brld 100110 ..... 10100 ..... 000 0000 0000 @typea_br +brald 100110 ..... 11100 ..... 000 0000 0000 @typea_br + +bri 101110 ..... 00000 ................ @typeb_br +brai 101110 ..... 01000 ................ @typeb_br +brid 101110 ..... 10000 ................ @typeb_br +braid 101110 ..... 11000 ................ @typeb_br +brlid 101110 ..... 10100 ................ @typeb_br +bralid 101110 ..... 11100 ................ @typeb_br + brk 100110 ..... 01100 ..... 000 0000 0000 @typea_br brki 101110 ..... 01100 ................ @typeb_br diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 1545974669..5c6e6e599e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1048,6 +1048,53 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) return true; } +static void setup_dslot(DisasContext *dc, bool type_b) +{ + dc->tb_flags_to_set |= D_FLAG; + if (type_b && (dc->tb_flags & IMM_FLAG)) { + dc->tb_flags_to_set |= BIMM_FLAG; + } +} + +static bool do_branch(DisasContext *dc, int dest_rb, int dest_imm, + bool delay, bool abs, int link) +{ + uint32_t add_pc; + + if (delay) { + setup_dslot(dc, dest_rb < 0); + } + + if (link) { + tcg_gen_movi_i32(cpu_R[link], dc->base.pc_next); + } + + /* Store the branch taken destination into btarget. */ + add_pc = abs ? 0 : dc->base.pc_next; + if (dest_rb > 0) { + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], add_pc); + } else { + dc->jmp_dest = add_pc + dest_imm; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); + } + dc->jmp_cond = TCG_COND_ALWAYS; + return true; +} + +#define DO_BR(NAME, NAMEI, DELAY, ABS, LINK) \ + static bool trans_##NAME(DisasContext *dc, arg_typea_br *arg) \ + { return do_branch(dc, arg->rb, 0, DELAY, ABS, LINK ? arg->rd : 0); } \ + static bool trans_##NAMEI(DisasContext *dc, arg_typeb_br *arg) \ + { return do_branch(dc, -1, arg->imm, DELAY, ABS, LINK ? arg->rd : 0); } + +DO_BR(br, bri, false, false, false) +DO_BR(bra, brai, false, true, false) +DO_BR(brd, brid, true, false, false) +DO_BR(brad, braid, true, true, false) +DO_BR(brld, brlid, true, false, true) +DO_BR(brald, bralid, true, true, true) + static bool trans_brk(DisasContext *dc, arg_typea_br *arg) { if (trap_userspace(dc, true)) { @@ -1372,14 +1419,6 @@ static void dec_msr(DisasContext *dc) } } -static void dec_setup_dslot(DisasContext *dc) -{ - dc->tb_flags_to_set |= D_FLAG; - if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags_to_set |= BIMM_FLAG; - } -} - static void dec_bcc(DisasContext *dc) { static const TCGCond mb_to_tcg_cc[] = { @@ -1398,7 +1437,7 @@ static void dec_bcc(DisasContext *dc) dslot = dc->ir & (1 << 25); if (dslot) { - dec_setup_dslot(dc); + setup_dslot(dc, dc->type_b); } dc->jmp_cond = mb_to_tcg_cc[cc]; @@ -1426,33 +1465,6 @@ static void dec_bcc(DisasContext *dc) tcg_temp_free_i32(next); } -static void dec_br(DisasContext *dc) -{ - unsigned int dslot, link, abs; - uint32_t add_pc; - - dslot = dc->ir & (1 << 20); - abs = dc->ir & (1 << 19); - link = dc->ir & (1 << 18); - - if (dslot) { - dec_setup_dslot(dc); - } - if (link && dc->rd) { - tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); - } - - add_pc = abs ? 0 : dc->base.pc_next; - if (dc->type_b) { - dc->jmp_dest = add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); - } else { - dc->jmp_dest = -1; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); - } - dc->jmp_cond = TCG_COND_ALWAYS; -} - static inline void do_rti(DisasContext *dc) { TCGv_i32 t0, t1; @@ -1521,7 +1533,7 @@ static void dec_rts(DisasContext *dc) return; } - dec_setup_dslot(dc); + setup_dslot(dc, true); if (i_bit) { dc->tb_flags |= DRTI_FLAG; @@ -1583,7 +1595,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, From patchwork Fri Aug 28 14:19:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248572 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1146522ilg; Fri, 28 Aug 2020 07:49:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw6pBXEGOlaVJIjyjX6WAS/ET6iTtwpiRr2WM+cE91L5adug72s4V7tpgiqixSpxb54eWDY X-Received: by 2002:a25:d812:: with SMTP id p18mr2700285ybg.460.1598626144546; Fri, 28 Aug 2020 07:49:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626144; cv=none; d=google.com; s=arc-20160816; b=rrM+9qEBewpdAbD7W2fKEOkz9nkYf7nzIqOY38fnG4MqgXbGc+YwRo5Hc0jGLsgjEv O9/iR8uj18E6KDZoOIBDVv78xvXqPlW68W18d8unSsVDCPtYcQIXYY+BW7lzvlz1tfy2 lCRxH81QOEh9ZCf04IFoCo0XQo7M5anWtlOtrczEepSbYYBz457Vt0PCqhSUkvhEQ64K 0oSIXGC+Xkt+h/jdorqxOxBD8OXozQ4ZosuRm7Iiu1AJ52DOOTb3+xjDAJ99NveuDQue uGBhyI7Dvq+DiJ92qD5bFs3UqcZ/6AGHV/upXnfveeyVZprN0oB/afSUqmcVHlN3IVCl O+pQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Dfp4IqU2KYAnvz32O5a9TP5rQnlGG8wPHCxVkh2Xx9w=; b=dcs8Vb3//nD9HrL64DE0HRfz8uioQ9Y0xC0mciAnP8z7TBH2JVF8+8gZB4T5ZSwa6P tpc37QjP3+TVL14Tu5ssOMKL2cXIw0i9SR3zK2IORc77bFEyMS5ogQYSqJMXarULF5gx 8HdaRV112WZ/TFd3yyxQ+/bQJL2uPve+Ra9QN8EF9R2kBtBScG5ot4kLL/OodgOQaLFT xaCGy8Tn1/9o7ZsbjbbiSWUUI8CKqkgMHFBNnIpHBcu8B15/evgO+H2Dw2ZkzNTF9bPQ erqA31xmLIftkMgGiadnb7suTcVw0XpDwBylp0fLMdbwTdcdjCXRh4NMZSlR11M1tsdV oT1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fuItrZYY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 36 +++++++++++++ target/microblaze/translate.c | 99 ++++++++++++++++++---------------- 2 files changed, 88 insertions(+), 47 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 340dd999b6..e6a61f147a 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -20,8 +20,10 @@ &typea0 rd ra &typea rd ra rb &typea_br rd rb +&typea_bc ra rb &typeb rd ra imm &typeb_br rd imm +&typeb_bc ra imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -35,12 +37,18 @@ # Officially typea, but with ra as opcode. @typea_br ...... rd:5 ..... rb:5 ........... &typea_br +# Officially typea, but with rd as opcode. +@typea_bc ...... ..... ra:5 rb:5 ........... &typea_bc + # Officially typeb, but any immediate extension is unused. @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb # Officially typeb, but with ra as opcode. @typeb_br ...... rd:5 ..... ................ &typeb_br imm=%extimm +# Officially typeb, but with rd as opcode. +@typeb_bc ...... ..... ra:5 ................ &typeb_bc imm=%extimm + # For convenience, extract the two imm_w/imm_s fields, then pack # them back together as "imm". Doing this makes it easiest to # match the required zero at bit 5. @@ -68,6 +76,34 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +beq 100111 00000 ..... ..... 000 0000 0000 @typea_bc +bge 100111 00101 ..... ..... 000 0000 0000 @typea_bc +bgt 100111 00100 ..... ..... 000 0000 0000 @typea_bc +ble 100111 00011 ..... ..... 000 0000 0000 @typea_bc +blt 100111 00010 ..... ..... 000 0000 0000 @typea_bc +bne 100111 00001 ..... ..... 000 0000 0000 @typea_bc + +beqd 100111 10000 ..... ..... 000 0000 0000 @typea_bc +bged 100111 10101 ..... ..... 000 0000 0000 @typea_bc +bgtd 100111 10100 ..... ..... 000 0000 0000 @typea_bc +bled 100111 10011 ..... ..... 000 0000 0000 @typea_bc +bltd 100111 10010 ..... ..... 000 0000 0000 @typea_bc +bned 100111 10001 ..... ..... 000 0000 0000 @typea_bc + +beqi 101111 00000 ..... ................ @typeb_bc +bgei 101111 00101 ..... ................ @typeb_bc +bgti 101111 00100 ..... ................ @typeb_bc +blei 101111 00011 ..... ................ @typeb_bc +blti 101111 00010 ..... ................ @typeb_bc +bnei 101111 00001 ..... ................ @typeb_bc + +beqid 101111 10000 ..... ................ @typeb_bc +bgeid 101111 10101 ..... ................ @typeb_bc +bgtid 101111 10100 ..... ................ @typeb_bc +bleid 101111 10011 ..... ................ @typeb_bc +bltid 101111 10010 ..... ................ @typeb_bc +bneid 101111 10001 ..... ................ @typeb_bc + br 100110 ..... 00000 ..... 000 0000 0000 @typea_br bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 5c6e6e599e..b8dcef8f1c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1095,6 +1095,58 @@ DO_BR(brad, braid, true, true, false) DO_BR(brld, brlid, true, false, true) DO_BR(brald, bralid, true, true, true) +static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm, + TCGCond cond, int ra, bool delay) +{ + TCGv_i32 zero, next; + + if (delay) { + setup_dslot(dc, dest_rb < 0); + } + + dc->jmp_cond = cond; + + /* Cache the condition register in cpu_bvalue across any delay slot. */ + tcg_gen_mov_i32(cpu_bvalue, reg_for_read(dc, ra)); + + /* Store the branch taken destination into btarget. */ + if (dest_rb > 0) { + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], dc->base.pc_next); + } else { + dc->jmp_dest = dc->base.pc_next + dest_imm; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); + } + + /* Compute the final destination into btarget. */ + zero = tcg_const_i32(0); + next = tcg_const_i32(dc->base.pc_next + (delay + 1) * 4); + tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, + reg_for_read(dc, ra), zero, + cpu_btarget, next); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(next); + + return true; +} + +#define DO_BCC(NAME, COND) \ + static bool trans_##NAME(DisasContext *dc, arg_typea_bc *arg) \ + { return do_bcc(dc, arg->rb, 0, COND, arg->ra, false); } \ + static bool trans_##NAME##d(DisasContext *dc, arg_typea_bc *arg) \ + { return do_bcc(dc, arg->rb, 0, COND, arg->ra, true); } \ + static bool trans_##NAME##i(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_bcc(dc, -1, arg->imm, COND, arg->ra, false); } \ + static bool trans_##NAME##id(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_bcc(dc, -1, arg->imm, COND, arg->ra, true); } + +DO_BCC(beq, TCG_COND_EQ) +DO_BCC(bge, TCG_COND_GE) +DO_BCC(bgt, TCG_COND_GT) +DO_BCC(ble, TCG_COND_LE) +DO_BCC(blt, TCG_COND_LT) +DO_BCC(bne, TCG_COND_NE) + static bool trans_brk(DisasContext *dc, arg_typea_br *arg) { if (trap_userspace(dc, true)) { @@ -1419,52 +1471,6 @@ static void dec_msr(DisasContext *dc) } } -static void dec_bcc(DisasContext *dc) -{ - static const TCGCond mb_to_tcg_cc[] = { - [CC_EQ] = TCG_COND_EQ, - [CC_NE] = TCG_COND_NE, - [CC_LT] = TCG_COND_LT, - [CC_LE] = TCG_COND_LE, - [CC_GE] = TCG_COND_GE, - [CC_GT] = TCG_COND_GT, - }; - unsigned int cc; - unsigned int dslot; - TCGv_i32 zero, next; - - cc = EXTRACT_FIELD(dc->ir, 21, 23); - dslot = dc->ir & (1 << 25); - - if (dslot) { - setup_dslot(dc, dc->type_b); - } - - dc->jmp_cond = mb_to_tcg_cc[cc]; - - /* Cache the condition register in cpu_bvalue across any delay slot. */ - tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]); - - /* Store the branch taken destination into btarget. */ - if (dc->type_b) { - dc->jmp_dest = dc->base.pc_next + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); - } else { - dc->jmp_dest = -1; - tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb), - dc->base.pc_next); - } - - /* Compute the final destination into btarget. */ - zero = tcg_const_i32(0); - next = tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4); - tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, - reg_for_read(dc, dc->ra), zero, - cpu_btarget, next); - tcg_temp_free_i32(zero); - tcg_temp_free_i32(next); -} - static inline void do_rti(DisasContext *dc) { TCGv_i32 t0, t1; @@ -1595,7 +1601,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, From patchwork Fri Aug 28 14:19:21 2020 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id e11si1055827ybp.435.2020.08.28.07.55.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:55:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qLeGHQN8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfmW-0001kq-43 for patch@linaro.org; Fri, 28 Aug 2020 10:55:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFV-0002QK-Rd for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:01 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:33318) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFT-0005RI-Ur for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:01 -0400 Received: by mail-pl1-x642.google.com with SMTP id h2so540833plr.0 for ; Fri, 28 Aug 2020 07:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JAaLtIFS218jhrIntO1CQBLV81E0LrWrKQYBwcRx/ss=; b=qLeGHQN8piX0iQLsD4gji7uRrL4cecjHuSY0wXonxtlxgn3Nu7DXVUHSQMwzPrJcdm O6saoHhKqfrjj355bqUWjLvQSn8CrvsopWGUEfMB7IiXP8Y/TtWKKmyc+tFyWHC4962P KlmEhhq1/rxbB/9Pow1f1GgAeTD+a8ZVcTsiNWahqTonYWkv+IDe+JfmpCvDG2IYWS0d Rq6Im67ouWoxE6t6lN2NSAXKv2pM/skQVE+XlEqlZ2ZblMQkGP8Zo+bAfXk8LzrLqwfa V27LTPx6jrnHeR6BvQ4PVv//QM3IcMUJdUvh3LfOcof1JMkazYOzqraHUdZAOhcg3/Pd t5pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JAaLtIFS218jhrIntO1CQBLV81E0LrWrKQYBwcRx/ss=; b=es6pQ3mbq4K5E5fhfNT7MmiJP3VDJo55gf+KY6Yfv32/gxZH/PpYKi7fYNXa/ZvfbW Zs5OTSsIZjKHF/Aru42dyTLeAVvRROjlrkRcCty9TWsAivqXCMnhDu4qA2HW5VHQaCqe D16HFNgqNutqUahxdZIC3MF1PHLn5sFqCHKEn+1Qx7ulITR98NMR5B3W7QrTcfU6He3K 35Is+nn/ojSKceQz19pTZPEtJL3pt1UzPcPBhV6TzQOdWE808u/nhPIJ1Fgz0BrHcZJw GjEKlsgzbJw0Bz4uRtTSHZ4BrepIXL2bEQWyFRdIyqXgtPkNNAq9aQ+cYNPiVXCILU0w jFGQ== X-Gm-Message-State: AOAM532nTtUY1NEBoBcm9v4Jo1A5xzUfo8gS8wi5H8kaQfz1lKdoEISe SrDmD8jYFu+N2bQLfUxeop7cWCu+gju0SQ== X-Received: by 2002:a17:902:988f:: with SMTP id s15mr1506833plp.26.1598624458291; Fri, 28 Aug 2020 07:20:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 68/76] target/microblaze: Convert dec_rts to decodetree Date: Fri, 28 Aug 2020 07:19:21 -0700 Message-Id: <20200828141929.77854-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 5 ++++ target/microblaze/translate.c | 51 +++++++++++++++------------------- 2 files changed, 28 insertions(+), 28 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index e6a61f147a..8906058a29 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -202,6 +202,11 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +rtbd 101101 10010 ..... ................ @typeb_bc +rtid 101101 10001 ..... ................ @typeb_bc +rted 101101 10100 ..... ................ @typeb_bc +rtsd 101101 10000 ..... ................ @typeb_bc + sb 110100 ..... ..... ..... 0000 000 0000 @typea sbr 110100 ..... ..... ..... 0100 000 0000 @typea sbea 110100 ..... ..... ..... 0001 000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b8dcef8f1c..6c1855b29a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1252,6 +1252,29 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg) return true; } +static bool do_rts(DisasContext *dc, arg_typeb_bc *arg, int to_set) +{ + if (trap_userspace(dc, to_set)) { + return true; + } + dc->tb_flags_to_set |= to_set; + setup_dslot(dc, true); + + dc->jmp_cond = TCG_COND_ALWAYS; + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, arg->ra), arg->imm); + return true; +} + +#define DO_RTS(NAME, IFLAG) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_rts(dc, arg, IFLAG); } + +DO_RTS(rtbd, DRTB_FLAG) +DO_RTS(rtid, DRTI_FLAG) +DO_RTS(rted, DRTE_FLAG) +DO_RTS(rtsd, 0) + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -1527,33 +1550,6 @@ static inline void do_rte(DisasContext *dc) dc->tb_flags &= ~DRTE_FLAG; } -static void dec_rts(DisasContext *dc) -{ - unsigned int b_bit, i_bit, e_bit; - - i_bit = dc->ir & (1 << 21); - b_bit = dc->ir & (1 << 22); - e_bit = dc->ir & (1 << 23); - - if (trap_userspace(dc, i_bit || b_bit || e_bit)) { - return; - } - - setup_dslot(dc, true); - - if (i_bit) { - dc->tb_flags |= DRTI_FLAG; - } else if (b_bit) { - dc->tb_flags |= DRTB_FLAG; - } else if (e_bit) { - dc->tb_flags |= DRTE_FLAG; - } - - dc->jmp_cond = TCG_COND_ALWAYS; - dc->jmp_dest = -1; - tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); -} - static void dec_null(DisasContext *dc) { if (trap_illegal(dc, true)) { @@ -1601,7 +1597,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} From patchwork Fri Aug 28 14:19:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248582 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1151979ilg; Fri, 28 Aug 2020 07:56:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzyy7TIvzqFFHeSdIoE58p826ddMYU6kULYGlSuMp2neL9M0ISbRYFM4dQrR+e/N5I6AsSe X-Received: by 2002:a25:4c84:: with SMTP id z126mr2643504yba.369.1598626595120; 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[209.51.188.17]) by mx.google.com with ESMTPS id e125si1102185ybh.69.2020.08.28.07.56.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:56:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eKHtIbVj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfnu-0004Se-KI for patch@linaro.org; Fri, 28 Aug 2020 10:56:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFY-0002X0-Bo for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:04 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:32795) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFV-0005RY-4H for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:04 -0400 Received: by mail-pf1-x442.google.com with SMTP id u20so750016pfn.0 for ; Fri, 28 Aug 2020 07:21:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uKt+OEZaqpTnhdobh8nWk7pSRy/ghJfhk6PLOAf1cLo=; b=eKHtIbVj8VouqCoACHN4Q82KMK8IvDfHjd9/GK5dskg0RiM40c8nwI+7d8VTgeJ1WN 5JcicoGj23WcAiWzHLpuq32iNh4AkiBvWNk457mYHzhG9qsiwbenGwKKpFVOB3bOJ3Za Y6ZI2D59P+vvzuCyPBu7W+tAGl+J1mwbY7Q1OFW/5YWXJWQiddtkGUEiUE+O9tUbUqHT D5nB5b5BRoiXZQhTKvaUGvOqCkKFQOYcy+Y2+839tnwturCiDys8eANRPmVvFI7cCJnY cU6MJ4Xp9tM2yejfjl6GPd0/YKX/RxpCeWO0KMKUPPxUPTqHl5utivDeDAi1E9OQ5MK3 Eesg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uKt+OEZaqpTnhdobh8nWk7pSRy/ghJfhk6PLOAf1cLo=; b=b8gX0mFpBM9nCLBOPLxMxiov0y8zzIKg9q73zAvYlPy41ROS30w6VHUxctACk7EWAn lb/ZD6rIlLLQsP3hZDQcGicwV5zjtWq+Cmsq1LUvNm01byU0rBOioUA6l04KylzlGVGK dIyKhOsX1qClKem7iT7VX1P3n8hagbGopPiUsgfZ/WZixGxY4i8h4IEZbHwcrFEBe2kE Wt48xpVnVINPiXnv3I6PeufzJtEePqHoN+lJQGhNdB8GAXfZ/AQhNvc3vE+shO6WRuRW qII9ItXM2qfMy3+q6TdjxLSoJeRldccEdyxHzeLlsM0MDwWdEKBWduordHYx3v51Kqyl qthA== X-Gm-Message-State: AOAM532iBed9MoBV93vIv1Rox/RLISlf1D78Px1TlpNgEGPYNdej1XNT onQG/YAWeo6dPXNcN/jkzuy2MqWWJwSdlg== X-Received: by 2002:a05:6a00:9b:: with SMTP id c27mr1430775pfj.69.1598624459478; Fri, 28 Aug 2020 07:20:59 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 69/76] target/microblaze: Tidy do_rti, do_rtb, do_rte Date: Fri, 28 Aug 2020 07:19:22 -0700 Message-Id: <20200828141929.77854-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since cpu_msr is no longer a 64-bit quantity, we can simplify the arithmetic in these functions. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 65 ++++++++++++++--------------------- 1 file changed, 25 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6c1855b29a..0872795038 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1494,59 +1494,44 @@ static void dec_msr(DisasContext *dc) } } -static inline void do_rti(DisasContext *dc) +static void do_rti(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_ori_i32(t1, t1, MSR_IE); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_IE); + tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); + + tcg_temp_free_i32(tmp); dc->tb_flags &= ~DRTI_FLAG; } -static inline void do_rtb(DisasContext *dc) +static void do_rtb(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_andi_i32(t1, t1, ~MSR_BIP); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP)); + tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); + + tcg_temp_free_i32(tmp); dc->tb_flags &= ~DRTB_FLAG; } -static inline void do_rte(DisasContext *dc) +static void do_rte(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_ori_i32(t1, t1, MSR_EE); - tcg_gen_andi_i32(t1, t1, ~MSR_EIP); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_EE); + tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_temp_free_i32(tmp); dc->tb_flags &= ~DRTE_FLAG; } From patchwork Fri Aug 28 14:19:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248573 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1146572ilg; Fri, 28 Aug 2020 07:49:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuzFpbpNeVwrkuXQ63Iv1tBwsy8QiLV1WVfuEIe/jXc6wklQhZbU+3eENJKqrlaaRgXMcQ X-Received: by 2002:a25:fc2:: with SMTP id 185mr2884772ybp.96.1598626148440; Fri, 28 Aug 2020 07:49:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626148; cv=none; d=google.com; s=arc-20160816; b=iPsDme2h4pxroU6ax/SE8vVtqjUtm77apzrbSBBB0c3GQgHg5E3IRnIwnvFNbdk2v1 h2L+l27DBaxdujHIqq7+A2FcrXjDpzMOSwM/iVzsWRJAiPG32xGjfQrK6p+CNAKSP8Dh 4g/hjeqGkxeIx0yb/jDrcM3HGWY2BeRZqJ6obiJSvS4//9eCSD+8v7vggVwENuczA4Xv xTisngrqSnLd8ytjkVCn4NA9ZNxNBoEBSU6khH/eZ6nh6N0a0mY+cg+O8Nuk/73gdDcE FSrRKxTPRYbAt8UpgckwFcImgNjnNmafrKHcPo0bd0CwkF4P3tH7g9SwqnjfknIE7pCg U2PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rirlJSos3h79Rb+snbKGxGEeQw6jeW6C2yeYS1BJjIc=; b=g1dCP/DMx/3EoTgx0w8z2B/EQm1ozaa7e9Vw4FvDGlfpkIPmhjksJTfCOT71mziUHC w9ZRH3FgPC4B5Rb+PqV133wXV1h3BzbuAfrB2KeFx3XlxZWS6qXIT3CR80cjNAG3r8aK mkdO17kmml4Mdcbxcv5OtlJ7tSWPdlWXg3djxQxbBGIsyFgk8Yoh4BYiJX4TvPv24gIL 8sCXSkaFhU8YxhqmGANQ/q94FsnWBo4UygT4L94Rih6AtTOsIQTeWtfRjZUS9r+XkQgZ Sh1lXh5m8aQXlgZyr1XcX/KHmf1MKtNyCJSZKqeHDIXQJpTbntmPK80cq+pPBRJwWwXj 7gpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kjh4Ja3g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split this out of dec_msr. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 85 +++++++++++++++++++--------------- 2 files changed, 54 insertions(+), 37 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 8906058a29..ed3312982f 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -24,6 +24,7 @@ &typeb rd ra imm &typeb_br rd imm &typeb_bc ra imm +&type_msr rd imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -55,6 +56,8 @@ %ieimm 6:5 0:5 @typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=%ieimm +@type_msr ...... rd:5 ...... imm:15 &type_msr + ### { @@ -179,6 +182,9 @@ lwi 111010 ..... ..... ................ @typeb mbar 101110 imm:5 00010 0000 0000 0000 0100 +msrclr 100101 ..... 100010 ............... @type_msr +msrset 100101 ..... 100000 ............... @type_msr + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0872795038..9479dbc103 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1311,16 +1311,61 @@ static void msr_write(DisasContext *dc, TCGv_i32 v) tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } +static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) +{ + uint32_t imm = arg->imm; + + if (trap_userspace(dc, imm != MSR_C)) { + return true; + } + + if (arg->rd) { + msr_read(dc, cpu_R[arg->rd]); + } + + /* + * Handle the carry bit separately. + * This is the only bit that userspace can modify. + */ + if (imm & MSR_C) { + tcg_gen_movi_i32(cpu_msr_c, set); + } + + /* + * MSR_C and MSR_CC set above. + * MSR_PVR is not writable, and is always clear. + */ + imm &= ~(MSR_C | MSR_CC | MSR_PVR); + + if (imm != 0) { + if (set) { + tcg_gen_ori_i32(cpu_msr, cpu_msr, imm); + } else { + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); + } + dc->cpustate_changed = 1; + } + return true; +} + +static bool trans_msrclr(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, false); +} + +static bool trans_msrset(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, true); +} + static void dec_msr(DisasContext *dc) { CPUState *cs = CPU(dc->cpu); - TCGv_i32 t0, t1; unsigned int sr, rn; - bool to, clrset, extended = false; + bool to, extended = false; sr = extract32(dc->imm, 0, 14); to = extract32(dc->imm, 14, 1); - clrset = extract32(dc->imm, 15, 1) == 0; dc->type_b = 1; if (to) { dc->cpustate_changed = 1; @@ -1334,40 +1379,6 @@ static void dec_msr(DisasContext *dc) extended = extract32(dc->imm, e_bit[to], 1); } - /* msrclr and msrset. */ - if (clrset) { - bool clr = extract32(dc->ir, 16, 1); - - if (!dc->cpu->cfg.use_msr_instr) { - /* nop??? */ - return; - } - - if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) { - return; - } - - if (dc->rd) - msr_read(dc, cpu_R[dc->rd]); - - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - msr_read(dc, t0); - tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc))); - - if (clr) { - tcg_gen_not_i32(t1, t1); - tcg_gen_and_i32(t0, t0, t1); - } else - tcg_gen_or_i32(t0, t0, t1); - msr_write(dc, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - dc->base.is_jmp = DISAS_UPDATE; - return; - } - if (trap_userspace(dc, to)) { return; } From patchwork Fri Aug 28 14:19:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248555 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1140405ilg; Fri, 28 Aug 2020 07:41:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxmndLKNdVvyHPC3CnprvY4XwsS15JYACyMsJt9djPINzCGAcEOEXVgLWsnwuQXSy2ZVIGr X-Received: by 2002:a5b:602:: with SMTP id d2mr2916745ybq.451.1598625664683; Fri, 28 Aug 2020 07:41:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625664; cv=none; d=google.com; s=arc-20160816; b=0bmlfoWl7sc/tfAo0SttfMIBrf7HA0Da5gYg+t8tEIZ/N9z278cqxyl5omuCzbmRYj fX1Ccy2EieeNJ6Rg6ENDW1pKIB1de8tf9PQWl30E8cNEcukuMIjSdshJa9fp4jVNz2gW 01+o+NabaaBpb+TnoJ3hak122dv4D75SJ01C8iOkhQD+usS776cfd2n5+JLHeOr5VL0i p0IcpolEtwIIfnC9t/OrsIAsNEip2OjJV33PGLa/r7KGdX9GPj1+kpRiUvUn6gVtcQjj zghvsPCSAAwhJ9ADuOV0aecvEAd5/WkAHfc/8b8oZsZUVLDrkFB4pxejvJ47STYiFPY+ vvfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yObi1QnU/JAJgFHydmbMkjfBv5V0TbSDxZFEaijvLV4=; b=iqD5U+H+8Qu5+Ph7lGRlLoJU5slbcHvKWMSzC3eJOkMqB5DWhKSwmp/onn9YkJyyKT XzaUmLgtHSRL6oUtsMwTvdLLrs6NZWWmRhvGnUh4n/1fY9xFxcgB9UyqQGiu40P16Br3 MIbN4CezOKAUZ0UOdPWsjWmZ8p1Z/VzFj962rqQWtaheHY6l5Wg8p6zckJbhVfe9RGoN gvFmYPmGuX1+dFI5gF5Xa3E8LhvcKkWcosckPRI3hWQZ+Btg6/dPHZhqAmX4FYsOGIDA 3H7NG5Q11fVZ9e4V7Lfs/5Wzxy8ul2p4bZto2gE34/2kyPxJq5Vz+t3NpyfMzMyTKp2S /CBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ef3MzlnD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f8si1444337ybm.367.2020.08.28.07.41.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:41:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ef3MzlnD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37642 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfYt-0008AQ-W5 for patch@linaro.org; Fri, 28 Aug 2020 10:41:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFZ-0002b3-QZ for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:05 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:38660) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFX-0005SJ-JK for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:05 -0400 Received: by mail-pg1-x543.google.com with SMTP id l191so528714pgd.5 for ; Fri, 28 Aug 2020 07:21:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yObi1QnU/JAJgFHydmbMkjfBv5V0TbSDxZFEaijvLV4=; b=Ef3MzlnDTq8dk+sCLvZQzBO2Jiy74BBmoZ6px08dznOEOHQYUP/D71r6zLhNjITVmy 9dKRdPC6Zeg9drK+/5sj2GPWtltlbGCJ3MWVkT8q3rx0m0WpafHX1mRQgmjjcIEOn7SC s6wwi77KL3VGyKW59ZyleZRb3JXuxckVpriTDlBvxlmiPHRoWRjBA2BUECj1RxwocGHw 95pdAOUBeup3HXGIV5t9vqnkI91MzwIMAGHSvVOUSDaq+Wrc/YQtPSt9wESKaqTWVPNr lD6zRiII5BBLqrP22w/ijPPAcFNfFjE+5Y+5O1g3FYZSyrufal+Qx+qusxrnbKgnGo7d pxHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yObi1QnU/JAJgFHydmbMkjfBv5V0TbSDxZFEaijvLV4=; b=XqzN3teRlb4K1CQUAObGjUXNDOrJ2eJHyhR5NNw0KLp7vVU0kyixw8yoo0zZEn9Xrw 0MBEMe/CV5jysDao2KBFiDI1lPPUPpeXK3qqDED+PC530nJCeC/cdFYdQjvhk1rWqSkd TAQY80rCveDlcvwaawQAEXwbP6FA5J3h1f5adfgOh+wvkSFT/O536KR5tklOQyZtofTa Hk3gzI+mTis/slptpjpqVjdVOLBRMhIckPGum4KF88FBCJIBsVMrCGjk5NW0xVKJQyU5 EZrX3AtFsjL7UhqS83Y231a7p2Ma0onvdzhV7inZhi4Y8wwkBwVSpXjglYFqaKTdyxEe Ui0Q== X-Gm-Message-State: AOAM5331lp4s/SuYvkOuwYxF2t7tqP0MuZH/wCpkCgeQvotJB2E7nK5a tEFQD2YGwTblbeJOCaejs5N2L5u+ruOsJw== X-Received: by 2002:a63:ec18:: with SMTP id j24mr1397720pgh.74.1598624461781; Fri, 28 Aug 2020 07:21:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:21:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 71/76] target/microblaze: Convert dec_msr to decodetree Date: Fri, 28 Aug 2020 07:19:24 -0700 Message-Id: <20200828141929.77854-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 + target/microblaze/translate.c | 270 +++++++++++++++++---------------- 2 files changed, 139 insertions(+), 134 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index ed3312982f..43c9e16819 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -182,6 +182,9 @@ lwi 111010 ..... ..... ................ @typeb mbar 101110 imm:5 00010 0000 0000 0000 0100 +mfs 100101 rd:5 0 e:1 000 10 rs:14 +mts 100101 0 e:1 000 ra:5 11 rs:14 + msrclr 100101 ..... 100010 ............... @type_msr msrset 100101 ..... 100000 ............... @type_msr diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9479dbc103..582f5a1577 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1300,6 +1300,7 @@ static void msr_read(DisasContext *dc, TCGv_i32 d) tcg_temp_free_i32(t); } +#ifndef CONFIG_USER_ONLY static void msr_write(DisasContext *dc, TCGv_i32 v) { dc->cpustate_changed = 1; @@ -1310,6 +1311,7 @@ static void msr_write(DisasContext *dc, TCGv_i32 v) /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */ tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } +#endif static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) { @@ -1358,151 +1360,152 @@ static bool trans_msrset(DisasContext *dc, arg_type_msr *arg) return do_msrclrset(dc, arg, true); } -static void dec_msr(DisasContext *dc) +static bool trans_mts(DisasContext *dc, arg_mts *arg) { - CPUState *cs = CPU(dc->cpu); - unsigned int sr, rn; - bool to, extended = false; - - sr = extract32(dc->imm, 0, 14); - to = extract32(dc->imm, 14, 1); - dc->type_b = 1; - if (to) { - dc->cpustate_changed = 1; + if (trap_userspace(dc, true)) { + return true; } - /* Extended MSRs are only available if addr_size > 32. */ - if (dc->cpu->cfg.addr_size > 32) { - /* The E-bit is encoded differently for To/From MSR. */ - static const unsigned int e_bit[] = { 19, 24 }; - - extended = extract32(dc->imm, e_bit[to], 1); +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + if (arg->e && arg->rs != 0x1003) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid extended mts reg 0x%x\n", arg->rs); + return true; } - if (trap_userspace(dc, to)) { - return; - } + TCGv_i32 src = reg_for_read(dc, arg->ra); + switch (arg->rs) { + case SR_MSR: + msr_write(dc, src); + break; + case SR_FSR: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); + break; + case 0x800: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, slr)); + break; + case 0x802: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, shr)); + break; -#if !defined(CONFIG_USER_ONLY) - /* Catch read/writes to the mmu block. */ - if ((sr & ~0xff) == 0x1000) { - TCGv_i32 tmp_ext = tcg_const_i32(extended); - TCGv_i32 tmp_sr; + case 0x1000: /* PID */ + case 0x1001: /* ZPR */ + case 0x1002: /* TLBX */ + case 0x1003: /* TLBLO */ + case 0x1004: /* TLBHI */ + case 0x1005: /* TLBSX */ + { + TCGv_i32 tmp_ext = tcg_const_i32(arg->e); + TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7); - sr &= 7; - tmp_sr = tcg_const_i32(sr); - if (to) { - gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); - } else { - gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr); + gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src); + tcg_temp_free_i32(tmp_reg); + tcg_temp_free_i32(tmp_ext); } - tcg_temp_free_i32(tmp_sr); - tcg_temp_free_i32(tmp_ext); - return; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs); + return true; } + dc->cpustate_changed = 1; + return true; +#endif +} + +static bool trans_mfs(DisasContext *dc, arg_mfs *arg) +{ + TCGv_i32 dest = reg_for_write(dc, arg->rd); + + if (arg->e) { + switch (arg->rs) { + case SR_EAR: + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_extrh_i64_i32(dest, t64); + tcg_temp_free_i64(t64); + } + return true; +#ifndef CONFIG_USER_ONLY + case 0x1003: /* TLBLO */ + /* Handled below. */ + break; +#endif + case 0x2006 ... 0x2009: + /* High bits of PVR6-9 not implemented. */ + tcg_gen_movi_i32(dest, 0); + return true; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid extended mfs reg 0x%x\n", arg->rs); + return true; + } + } + + switch (arg->rs) { + case SR_PC: + tcg_gen_movi_i32(dest, dc->base.pc_next); + break; + case SR_MSR: + msr_read(dc, dest); + break; + case SR_EAR: + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_extrl_i64_i32(dest, t64); + tcg_temp_free_i64(t64); + } + break; + case SR_ESR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, esr)); + break; + case SR_FSR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, fsr)); + break; + case SR_BTR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, btr)); + break; + case SR_EDR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, edr)); + break; + case 0x800: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, slr)); + break; + case 0x802: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, shr)); + break; + +#ifndef CONFIG_USER_ONLY + case 0x1000: /* PID */ + case 0x1001: /* ZPR */ + case 0x1002: /* TLBX */ + case 0x1003: /* TLBLO */ + case 0x1004: /* TLBHI */ + case 0x1005: /* TLBSX */ + { + TCGv_i32 tmp_ext = tcg_const_i32(arg->e); + TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7); + + gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg); + tcg_temp_free_i32(tmp_reg); + tcg_temp_free_i32(tmp_ext); + } + break; #endif - if (to) { - switch (sr) { - case SR_PC: - break; - case SR_MSR: - msr_write(dc, cpu_R[dc->ra]); - break; - case SR_EAR: - { - TCGv_i64 t64 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); - tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)); - tcg_temp_free_i64(t64); - } - break; - case SR_ESR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, esr)); - break; - case SR_FSR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, fsr)); - break; - case SR_BTR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, btr)); - break; - case SR_EDR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, edr)); - break; - case 0x800: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, slr)); - break; - case 0x802: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, shr)); - break; - default: - cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr); - break; - } - } else { - switch (sr) { - case SR_PC: - tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); - break; - case SR_MSR: - msr_read(dc, cpu_R[dc->rd]); - break; - case SR_EAR: - { - TCGv_i64 t64 = tcg_temp_new_i64(); - tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); - if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); - } else { - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); - } - tcg_temp_free_i64(t64); - } - break; - case SR_ESR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, esr)); - break; - case SR_FSR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, fsr)); - break; - case SR_BTR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, btr)); - break; - case SR_EDR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, edr)); - break; - case 0x800: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, slr)); - break; - case 0x802: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, shr)); - break; - case 0x2000 ... 0x200c: - rn = sr & 0xf; - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, pvr.regs[rn])); - break; - default: - cpu_abort(cs, "unknown mfs reg %x\n", sr); - break; - } - } - - if (dc->rd == 0) { - tcg_gen_movi_i32(cpu_R[0], 0); + case 0x2000 ... 0x200c: + tcg_gen_ld_i32(dest, cpu_env, + offsetof(CPUMBState, pvr.regs[arg->rs - 0x2000])); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid mfs reg 0x%x\n", arg->rs); + break; } + return true; } static void do_rti(DisasContext *dc) @@ -1593,7 +1596,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} }; From patchwork Fri Aug 28 14:19:25 2020 Content-Type: text/plain; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 ++++ target/microblaze/translate.c | 64 ++++++++++++++++++++++++++-------- 2 files changed, 55 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 43c9e16819..fb0f0e6838 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -159,6 +159,9 @@ flt 010110 ..... ..... ----- 0101 000 0000 @typea0 fint 010110 ..... ..... ----- 0110 000 0000 @typea0 fsqrt 010110 ..... ..... 00000 0111 000 0000 @typea0 +get 011011 rd:5 00000 0 ctrl:5 000000 imm:4 +getd 010011 rd:5 00000 rb:5 0 ctrl:5 00000 + idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea @@ -201,6 +204,9 @@ pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea +put 011011 00000 ra:5 1 ctrl:5 000000 imm:4 +putd 010011 00000 ra:5 rb:5 1 ctrl:5 00000 + rsub 000001 ..... ..... ..... 000 0000 0000 @typea rsubc 000011 ..... ..... ..... 000 0000 0000 @typea rsubk 000101 ..... ..... ..... 000 0000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 582f5a1577..2c87d671ae 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1560,33 +1560,68 @@ static void dec_null(DisasContext *dc) } /* Insns connected to FSL or AXI stream attached devices. */ -static void dec_stream(DisasContext *dc) +static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl) { TCGv_i32 t_id, t_ctrl; - int ctrl; if (trap_userspace(dc, true)) { - return; + return true; } t_id = tcg_temp_new_i32(); - if (dc->type_b) { - tcg_gen_movi_i32(t_id, dc->imm & 0xf); - ctrl = dc->imm >> 10; + if (rb) { + tcg_gen_andi_i32(t_id, cpu_R[rb], 0xf); } else { - tcg_gen_andi_i32(t_id, cpu_R[dc->rb], 0xf); - ctrl = dc->imm >> 5; + tcg_gen_movi_i32(t_id, imm); } t_ctrl = tcg_const_i32(ctrl); - - if (dc->rd == 0) { - gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); - } else { - gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); - } + gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl); tcg_temp_free_i32(t_id); tcg_temp_free_i32(t_ctrl); + return true; +} + +static bool trans_get(DisasContext *dc, arg_get *arg) +{ + return do_get(dc, arg->rd, 0, arg->imm, arg->ctrl); +} + +static bool trans_getd(DisasContext *dc, arg_getd *arg) +{ + return do_get(dc, arg->rd, arg->rb, 0, arg->ctrl); +} + +static bool do_put(DisasContext *dc, int ra, int rb, int imm, int ctrl) +{ + TCGv_i32 t_id, t_ctrl; + + if (trap_userspace(dc, true)) { + return true; + } + + t_id = tcg_temp_new_i32(); + if (rb) { + tcg_gen_andi_i32(t_id, cpu_R[rb], 0xf); + } else { + tcg_gen_movi_i32(t_id, imm); + } + + t_ctrl = tcg_const_i32(ctrl); + gen_helper_put(t_id, t_ctrl, reg_for_read(dc, ra)); + tcg_temp_free_i32(t_id); + tcg_temp_free_i32(t_ctrl); + return true; +} + +static bool trans_put(DisasContext *dc, arg_put *arg) +{ + return do_put(dc, arg->ra, 0, arg->imm, arg->ctrl); +} + +static bool trans_putd(DisasContext *dc, arg_putd *arg) +{ + return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl); } static struct decoder_info { @@ -1596,7 +1631,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} }; From patchwork Fri Aug 28 14:19:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248578 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1148451ilg; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All instructions have been convered. Issue sigill if decodetree does not match. Remove argument decode from DisasContext. Remove microblaze-decode.h. Signed-off-by: Richard Henderson --- target/microblaze/microblaze-decode.h | 59 ---------------------- target/microblaze/translate.c | 73 +-------------------------- 2 files changed, 1 insertion(+), 131 deletions(-) delete mode 100644 target/microblaze/microblaze-decode.h -- 2.25.1 diff --git a/target/microblaze/microblaze-decode.h b/target/microblaze/microblaze-decode.h deleted file mode 100644 index 17b2f29fff..0000000000 --- a/target/microblaze/microblaze-decode.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * MicroBlaze insn decoding macros. - * - * Copyright (c) 2009 Edgar E. Iglesias - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#ifndef TARGET_MICROBLAZE_MICROBLAZE_DECODE_H -#define TARGET_MICROBLAZE_MICROBLAZE_DECODE_H - -/* Convenient binary macros. */ -#define HEX__(n) 0x##n##LU -#define B8__(x) ((x&0x0000000FLU)?1:0) \ - + ((x&0x000000F0LU)?2:0) \ - + ((x&0x00000F00LU)?4:0) \ - + ((x&0x0000F000LU)?8:0) \ - + ((x&0x000F0000LU)?16:0) \ - + ((x&0x00F00000LU)?32:0) \ - + ((x&0x0F000000LU)?64:0) \ - + ((x&0xF0000000LU)?128:0) -#define B8(d) ((unsigned char)B8__(HEX__(d))) - -/* Decode logic, value and mask. */ -#define DEC_ADD {B8(00000000), B8(00110001)} -#define DEC_SUB {B8(00000001), B8(00110001)} -#define DEC_AND {B8(00100001), B8(00110101)} -#define DEC_XOR {B8(00100010), B8(00110111)} -#define DEC_OR {B8(00100000), B8(00110111)} -#define DEC_BIT {B8(00100100), B8(00111111)} -#define DEC_MSR {B8(00100101), B8(00111111)} - -#define DEC_BARREL {B8(00010001), B8(00110111)} -#define DEC_MUL {B8(00010000), B8(00110111)} -#define DEC_DIV {B8(00010010), B8(00110111)} -#define DEC_FPU {B8(00010110), B8(00111111)} - -#define DEC_LD {B8(00110000), B8(00110100)} -#define DEC_ST {B8(00110100), B8(00110100)} -#define DEC_IMM {B8(00101100), B8(00111111)} - -#define DEC_BR {B8(00100110), B8(00110111)} -#define DEC_BCC {B8(00100111), B8(00110111)} -#define DEC_RTS {B8(00101101), B8(00111111)} - -#define DEC_STREAM {B8(00010011), B8(00110111)} - -#endif diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2c87d671ae..8f69ca50b2 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -24,7 +24,6 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" -#include "microblaze-decode.h" #include "exec/cpu_ldst.h" #include "exec/helper-gen.h" #include "exec/translator.h" @@ -65,13 +64,7 @@ typedef struct DisasContext { bool r0_set; /* Decoder. */ - int type_b; - uint32_t ir; uint32_t ext_imm; - uint8_t opcode; - uint8_t rd, ra, rb; - uint16_t imm; - unsigned int cpustate_changed; unsigned int tb_flags; unsigned int tb_flags_to_set; @@ -82,8 +75,6 @@ typedef struct DisasContext { /* Immediate branch-taken destination, or -1 for indirect. */ uint32_t jmp_dest; - - int abort_at_next_insn; } DisasContext; static int typeb_imm(DisasContext *dc, int x) @@ -184,21 +175,6 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } -static int32_t dec_alu_typeb_imm(DisasContext *dc) -{ - tcg_debug_assert(dc->type_b); - return typeb_imm(dc, (int16_t)dc->imm); -} - -static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) -{ - if (dc->type_b) { - tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); - return &cpu_imm; - } - return &cpu_R[dc->rb]; -} - static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { if (likely(reg != 0)) { @@ -1549,16 +1525,6 @@ static void do_rte(DisasContext *dc) dc->tb_flags &= ~DRTE_FLAG; } -static void dec_null(DisasContext *dc) -{ - if (trap_illegal(dc, true)) { - return; - } - qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", - (uint32_t)dc->base.pc_next, dc->opcode); - dc->abort_at_next_insn = 1; -} - /* Insns connected to FSL or AXI stream attached devices. */ static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl) { @@ -1624,40 +1590,6 @@ static bool trans_putd(DisasContext *dc, arg_putd *arg) return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl); } -static struct decoder_info { - struct { - uint32_t bits; - uint32_t mask; - }; - void (*dec)(DisasContext *dc); -} decinfo[] = { - {{0, 0}, dec_null} -}; - -static void old_decode(DisasContext *dc, uint32_t ir) -{ - int i; - - dc->ir = ir; - - /* bit 2 seems to indicate insn type. */ - dc->type_b = ir & (1 << 29); - - dc->opcode = EXTRACT_FIELD(ir, 26, 31); - dc->rd = EXTRACT_FIELD(ir, 21, 25); - dc->ra = EXTRACT_FIELD(ir, 16, 20); - dc->rb = EXTRACT_FIELD(ir, 11, 15); - dc->imm = EXTRACT_FIELD(ir, 0, 15); - - /* Large switch for all insns. */ - for (i = 0; i < ARRAY_SIZE(decinfo); i++) { - if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { - decinfo[i].dec(dc); - break; - } - } -} - static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); @@ -1667,7 +1599,6 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; dc->cpustate_changed = 0; - dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; @@ -1724,7 +1655,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) ir = cpu_ldl_code(env, dc->base.pc_next); if (!decode(dc, ir)) { - old_decode(dc, ir); + trap_illegal(dc, true); } if (dc->r0) { @@ -1764,8 +1695,6 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); - assert(!dc->abort_at_next_insn); - if (dc->base.is_jmp == DISAS_NORETURN) { /* We have already exited the TB. */ return; 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[209.51.188.17]) by mx.google.com with ESMTPS id n187si1338930ybc.376.2020.08.28.07.57.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:57:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UNDrYc7l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfp5-0005yG-3K for patch@linaro.org; Fri, 28 Aug 2020 10:57:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFe-0002mJ-8i for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:10 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:43919) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFb-0005Sy-Gf for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:09 -0400 Received: by mail-pl1-x642.google.com with SMTP id y6so522253plk.10 for ; Fri, 28 Aug 2020 07:21:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=18NIsjCWGgPffd6AY/cSSTGEezPxHVhnmwAp1fnNAvY=; b=UNDrYc7liHsOV0qv2VeKLSazz71g3yWaWpoYzo9ATGzetVJZltXNJhXSJ+TncAEiEA mzGDkjvTwcILHV/DANM2+yrna/ABbstMxFA5hn1KYP5PUYm1h7+EhW9T0+631p//xq3W JkadfelGkjsnmfBt/1jnPDwmNYga3vkk9AIaG0+2+Hd0HrcQ0viVVIvspSxCgJxXpvfg my2PXYCS7ZJ+Ksr+aK3vhY4plG9ShoVlZXE/NWQfdPTRpDvMj6Vb7uIH1/5jmSAb8C5p n5pqbvyUc/+wYFbCR7DA8XF0S3HMj+Ri6NUBRqv9kF+vAX7lPWsWdIT6qvQ9c8EC7Jcj wHdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=18NIsjCWGgPffd6AY/cSSTGEezPxHVhnmwAp1fnNAvY=; b=MSjopBWFo37GgILyfMmk+eaYvO4AaZIkSf5naabyb7ivmFymSDUaLZs987Qiy1v5JM nhfL1pa9+tNoJUTHETqjVOWDO53+7h1fQ7S7RLC07bnBhUVvUAUM1Z/u5Ln/lQpLlVYE haxQCmZRDszRf+Y6rjT11PDMu9IHUCeNDULchSOU1olrGdnX5NGeZ4/KHHyjL0ejXKvx 63CLlr4VK8C++wMo3w710z7hohVPxY6KJvaAzq6mm1shOAYHvJ7kQYMQBceZfU0wCNiD QKlr0uJZ1YwE6NyolxkSMY1WEXGum0TfuN/M7fJQafLEjyVlt5U37lFqyW5Ss1DGr2Sb pjVw== X-Gm-Message-State: AOAM532J65apqbQrjYVoWVhymcZmNf3UD3QI5hZdBvKJ5RB+98ReQAJX iM6fxIuEJHwjwPfAZaGoEgKnGyOEiI5wtg== X-Received: by 2002:a17:902:748c:: with SMTP id h12mr1499502pll.316.1598624465866; Fri, 28 Aug 2020 07:21:05 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.21.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:21:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 74/76] target/microblaze: Remove cpu_R[0] Date: Fri, 28 Aug 2020 07:19:27 -0700 Message-Id: <20200828141929.77854-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not initialize cpu_R[0], as this should be totally unused. The cpu_for_read and cpu_for_write functions use a local temp. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8f69ca50b2..8c287457a9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1842,7 +1842,13 @@ void mb_tcg_init(void) static const struct { TCGv_i32 *var; int ofs; char name[8]; } i32s[] = { - R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), + /* + * Note that r0 is handled specially in reg_for_read + * and reg_for_write. Nothing should touch cpu_R[0]. + * Leave that element NULL, which will assert quickly + * inside the tcg generator functions. + */ + R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), From patchwork Fri Aug 28 14:19:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248560 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1141852ilg; Fri, 28 Aug 2020 07:43:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwvBvQDTY6naxA5ye4Tw9LvEupVdJZlAPHWNeE6tb1GIn5fMTlhaLxT0VyBKWZ54Eh3rhxl X-Received: by 2002:a25:1904:: with SMTP id 4mr2871756ybz.5.1598625780071; Fri, 28 Aug 2020 07:43:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598625780; cv=none; d=google.com; s=arc-20160816; b=yCFQyfIDW8h3yPbXhHqJ25KrNjPcIBmA5RW7oh2dhvSC8hVijYv4FnHc/uFd3q0Ag+ 48y0svXFlQC3bqF1vWAxtbo6ZqMxJsB5heS0PreiwbXovYyKcq32VJTP5m67zN/ElMeN KwhuqP5KfxnDXTRKaHpsolY0OIxu1hv99041BOA9OuYYbWgaQtGH2VxKO+R/zQ5STwnX KPtDo9sp0Gw1dvyiGejlVuJ1nWxxwCi0vfGMo1tE7x6tE1ZMiow+3uMC4ENcYFOMYPm/ PV9PczYnycxlG2D8YI7OZ9gfqsAFiS4FsD4LdHSyf/0KgA1Yai6ticWER99u0Je9p/ix TxHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/v81xo2Oa10INQECM2V7ceku/8UgY141rA25N+r+rLA=; b=w78okLlWvI/v8TgmxoyGF76xSKy7q0h1S59JDXm3G8fDOXnyFZk0P4kzYOX+/IG544 h9BaiIiOCe1qipdcDOkFV1e8dFMvWGOYBLNE0KuF6nCz1ilQcKm7Gy/5Fjyf0ifUUbi+ PMftYOEL8kj0o1EBfDHGpw5LnmFFcBz4YTBThNFAAC/Dq3Gg3zATR57/HVIFGYh8//gH a7DdtLBzCzXBVsCltTeTbWeybCkDpgdE0BLjtc7VgcgartpyRyWNrMEjdgBQ1EhR7Vmn vCql5WzuNAV489SbRl17jhwPm0SXUH4jxSsr/66JKSeuJnmm+JX9we18bcVvf2KBAZKG oYkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vh6ZzQW+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t62si1260372ybi.157.2020.08.28.07.42.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:43:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vh6ZzQW+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46224 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfal-0003A8-Hl for patch@linaro.org; Fri, 28 Aug 2020 10:42:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFf-0002pG-Bj for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:11 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:44141) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFc-0005T6-Gt for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:21:11 -0400 Received: by mail-pl1-x642.google.com with SMTP id q3so520819pls.11 for ; Fri, 28 Aug 2020 07:21:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/v81xo2Oa10INQECM2V7ceku/8UgY141rA25N+r+rLA=; b=vh6ZzQW+RwGNCOrlzmxvzget01L9cE3CdqNCroefA6J02cEjaK2A0KckaZu6M+xzYW 8G97COWlqwWc6tSN6BaXW16SRSx5leZsnAzIce10smEQI+mMyq9Lcr6cikAqpORQEzpQ mcXfpMk092zqyZsnQIWufpWl37Icze0iVjYZ1pz9in3T+29MIn5IFnwMhqZYxGgvYLMw hqIaRnf9dR/KQV91ou+H4v+0Q9ahhfJJzewub+TvgX+xnl8jvAExyvGX1aBIZzsVTgP3 DrQrou65otSfsdUZ/Fvm8TqFcS0xQxgxGiTu6UpoVdFaakx5nx/6bI6azip2HCj1WzFo Q2mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/v81xo2Oa10INQECM2V7ceku/8UgY141rA25N+r+rLA=; b=d8PvLNvPl2fUEdrtcRapfuQJ15CmNeCw6vKopjIMtNclQcu5SBeeWQaADwfesdycd4 KH+1zaCrwxDxfGWop8AAWZZIx0qA4we3zlL9rtqee+PnTuxpBt5gUxHViwwXXWiiVb7Z 9A0HBSPkPS+li8yN0nutRjS6DZrIqtZS4dgAFMfwphIDL9AqlkI31ZlE3fgySYUu48T8 RIzWeg2HvIUiFAX7ITtvwduubPDwx2MVSMt7TAK+i+kK7T0K9zxkEvuZeaQ+9fcwbJyA JJRn5JU4h4q2zW/02kgAlS+M8r4Zi39RKEPitnZXebhJM+oJKSK243a4P06FUtiGO2iv Q9pw== X-Gm-Message-State: AOAM531NfV9mJASeolIhbfxpctH+wHF2aSGoqfarCS8b+nK0u/OfB5H6 6w0WA2Poj4mA+qhOR4lpS9JTPzjMIDp+eg== X-Received: by 2002:a17:902:343:: with SMTP id 61mr1552180pld.274.1598624466936; Fri, 28 Aug 2020 07:21:06 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.21.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:21:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 75/76] target/microblaze: Add flags markup to some helpers Date: Fri, 28 Aug 2020 07:19:28 -0700 Message-Id: <20200828141929.77854-76-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The mmu_read, mmu_write, get, and put helpers do not touch the general registers, or any of the other variables managed by tcg. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 3980fba797..f740835fcb 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -21,11 +21,11 @@ DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_3(mmu_read, i32, env, i32, i32) -DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32) #endif DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_2(get, i32, i32, i32) -DEF_HELPER_3(put, void, i32, i32, i32) +DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32) +DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32) From patchwork Fri Aug 28 14:19:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248576 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1147862ilg; Fri, 28 Aug 2020 07:50:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxe+n4SnAWoz7Dapt8cB10DxmRIhVo3RhQY6sXhOp/F8D3qnXmbVCwE0oV9IvsfOyrRvNcb X-Received: by 2002:a25:d0d6:: with SMTP id h205mr2785733ybg.259.1598626247410; Fri, 28 Aug 2020 07:50:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626247; cv=none; d=google.com; s=arc-20160816; b=wZQzWpayd0OWS6o3wGHw8CC2x0FpsspFoph+dilJMdqym66RqUozaWgR8Y8TSC5YDP WF8iNpVeXhRzkd16JZrSDkK9szpNLQengs5Koq/cIzoJWV7hDaHSVuAKPpn2e2yl+w45 sgEogIEFF3+UKDr2hILeSaX70qe7nPm1kQsHo7SIin7FDOzRYR2myeYfLjcLS7/PuGmM bP44EGM+iMXad9CY1ciqWw0xHTb9+ZzSPjY+TGFZIQLy//ynGmMP3v2qLL61cEMN+WCD r4ytW0+T7E0qchO+QiryhWFCpwRpWm2a6moWU5sQRrwwni6u2de/JRsbQOdzSf48vU0I 9lMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Wk3q7sRIifjFiJkV8x6Kj24R0PtPBhZ5iMsj3wtsB2s=; b=Bzq7a2KsJcsJFMdly3XdcsiNn9Unj9Qs+Hj0Ef7xp+hm/duXZzPaiQA0oP0yBudu2c xZVGDV01zfHZ/FBsnZbeCvyiwnSLL5rMNK4oM2nzfZVHVDZR5r6JGwK5gJai6ZiVUlbz uyx7ZP6s2hS5u0DQfnuNI4jYQOZZJwhL5OTvAm0A9mvrWjObm2MJ9YHgF73Btzt6HhNu jKafR2qs5IiHEN78L4EHYQFA/WORw4Iznca3LqV6ozOz0oHm8/afQYa+4Cu39Jr+Ze0p vDPqImg8AStynPKdvMg1bCll/SFF3ln+eDZvBRFBAynsfdedpYh7PVN70sAzotWjS+d4 khbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VWEyKo1I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" User-space programs cannot use the 64-bit lwea/swea instructions. We can improve code generation and runtime by restricting the user-only address space to 32-bit. Signed-off-by: Richard Henderson --- target/microblaze/cpu-param.h | 15 +++++++++++++++ target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/translate.c | 28 +++++++++++++++++++++++++++- 4 files changed, 45 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 4abbc62d50..4d8297fa94 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -8,9 +8,24 @@ #ifndef MICROBLAZE_CPU_PARAM_H #define MICROBLAZE_CPU_PARAM_H 1 +/* + * While system mode can address up to 64 bits of address space, + * this is done via the lea/sea instructions, which are system-only + * (as they also bypass the mmu). + * + * We can improve the user-only experience by only exposing 32 bits + * of address space. + */ +#ifdef CONFIG_USER_ONLY +#define TARGET_LONG_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#else #define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 +#endif + /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 #define NB_MMU_MODES 3 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 4298f242a6..d11b6fa995 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint32_t pc; uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ - uint64_t ear; + target_ulong ear; uint32_t esr; uint32_t fsr; uint32_t btr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 1667822fb7..48547385b0 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -303,8 +303,8 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, iflags = cpu->env.iflags; qemu_log_mask(CPU_LOG_INT, - "Unaligned access addr=" TARGET_FMT_lx - " pc=%x iflags=%x\n", addr, cpu->env.pc, iflags); + "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n", + (target_ulong)addr, cpu->env.pc, iflags); esr = ESR_EC_UNALIGNED_DATA; if (likely(iflags & ESR_ESS_FLAG)) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8c287457a9..a377818b5e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -687,6 +687,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) return ret; } +#ifndef CONFIG_USER_ONLY static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) { int addr_size = dc->cpu->cfg.addr_size; @@ -712,6 +713,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) } return ret; } +#endif static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) @@ -776,8 +778,12 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +#endif } static bool trans_lbui(DisasContext *dc, arg_typeb *arg) @@ -803,8 +809,12 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +#endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) @@ -830,8 +840,12 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +#endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) @@ -910,8 +924,12 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +#endif } static bool trans_sbi(DisasContext *dc, arg_typeb *arg) @@ -937,8 +955,12 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +#endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) @@ -964,8 +986,12 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +#endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) @@ -1818,7 +1844,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n" - "ear=0x%016" PRIx64 " slr=0x%x shr=0x%x\n", + "ear=0x" TARGET_FMT_lx " slr=0x%x shr=0x%x\n", env->esr, env->fsr, env->btr, env->edr, env->ear, env->slr, env->shr);