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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/77] tests/tcg: Add microblaze to arches filter Date: Tue, 25 Aug 2020 13:58:34 -0700 Message-Id: <20200825205950.730499-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not attempting to use a single cross-compiler for both big-endian and little-endian at this time. Cc: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/configure.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Edgar E. Iglesias diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 7d714f902a..598a50cd4f 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -94,7 +94,7 @@ for target in $target_list; do xtensa|xtensaeb) arches=xtensa ;; - alpha|cris|hppa|i386|lm32|m68k|openrisc|riscv64|s390x|sh4|sparc64) + alpha|cris|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64) arches=$target ;; *) From patchwork Tue Aug 25 20:58:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248269 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3767546ils; Tue, 25 Aug 2020 14:05:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy3lt5S6omA02r2mpNRTOWwU6OWA3lfYG9dGWkX8NqEQX8e8zvLbIqLjalkRb5jrBzRRT3F X-Received: by 2002:a25:e406:: with SMTP id b6mr16203770ybh.211.1598389519774; Tue, 25 Aug 2020 14:05:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389519; cv=none; d=google.com; s=arc-20160816; b=RZQnVU5xEWri0If/IhLvkjWvHduYsEi+cW7UTc52hg6HI9B3Io1odapfRMGGECKgza oliiSPq+a4W/E5uf/j74C7j2qFXZYc8Ehhkcm/5cgbbnADVa0QVbPOiqcRF7FsQ/zZr6 AC72OUMB84XJye1ZwTimpkTt0Xx8X7LSULVRPU38WtjhnxQ/0q/c2O5bPh+6S5EE/Kwh rpnO5AlPh7CRxZn8ks2pDAfVByTAkRxWPJyEqzEIyW23FpXla6Yr5Qi04CBLLQzwhFPL w+lFo41ch7QxeH1WigDTVX+pEqxXe7JQCUmyX5E+5glmhAMpVcKgUwEKgLMbHs/g2zyZ BkQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VbBY1yItMeIkPbGFrNMfYpfJv2H3xsn/XCS3gcTz2VE=; b=V97EYflddukm+r3ZpV+yvUVnjLAmbxa/4oqqdAdd4VecUrMCVxGwdRAp+r+lrGnmkf Lt2oJenkKqYD2EvJ2RYJnAEWmP3YZshzK0PwCs5TFLfNX3JVqgUeXuLsyWsUkejjV260 bHo6tXLl+FIECpBMggvwMk5LKAIwB+Hi56l1i58NwpItAKZCs8dVCRfVQr87f+AI++4w Mc+dg9k/UV76uxARaU7qcqdsVowdv7H42VYqbfx/ieKHHcS3KAel+E16WUtROwOumnBl I6NjTAROBgRxbz6GqiC2107AOjStA9V+aP4L4hfluIsxCUlyd4HYe0fgDvU4w+3di4nE CQIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N78+NB1P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/77] tests/tcg: Do not require FE_TOWARDZERO Date: Tue, 25 Aug 2020 13:58:35 -0700 Message-Id: <20200825205950.730499-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is optional in ISO C, and not all cpus provide it. Cc: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/multiarch/float_convs.c | 2 ++ tests/tcg/multiarch/float_madds.c | 2 ++ 2 files changed, 4 insertions(+) -- 2.25.1 Reviewed-by: Edgar E. Iglesias diff --git a/tests/tcg/multiarch/float_convs.c b/tests/tcg/multiarch/float_convs.c index 47e24b8b16..e9be75c2d5 100644 --- a/tests/tcg/multiarch/float_convs.c +++ b/tests/tcg/multiarch/float_convs.c @@ -30,7 +30,9 @@ float_mapping round_flags[] = { #ifdef FE_DOWNWARD { FE_DOWNWARD, "downwards" }, #endif +#ifdef FE_TOWARDZERO { FE_TOWARDZERO, "to zero" } +#endif }; static void print_input(float input) diff --git a/tests/tcg/multiarch/float_madds.c b/tests/tcg/multiarch/float_madds.c index eceb4ae38b..e422608ccd 100644 --- a/tests/tcg/multiarch/float_madds.c +++ b/tests/tcg/multiarch/float_madds.c @@ -29,7 +29,9 @@ float_mapping round_flags[] = { #ifdef FE_DOWNWARD { FE_DOWNWARD, "downwards" }, #endif +#ifdef FE_TOWARDZERO { FE_TOWARDZERO, "to zero" } +#endif }; From patchwork Tue Aug 25 20:58:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248262 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3764401ils; Tue, 25 Aug 2020 14:01:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMm94rWHJjTFY05dLnt8OG+zKjVFyml01LVzAlTj3oK7CFqa8nd7MMq1Gdwhf+hwAEjmxq X-Received: by 2002:a05:620a:134b:: with SMTP id c11mr9167112qkl.256.1598389269963; Tue, 25 Aug 2020 14:01:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389269; cv=none; d=google.com; s=arc-20160816; b=H5wW55BHU7W8FNw6ryxSaaxhu58qKQqPOHvJrUFzsyxXVHp8H+Ejy8iaARfUxNC0Zw 8rTeMiJZAqkrlQBOsvs2lnRVLBPKb2YuivzhwtIoj2j4orXTp8/w0hZApEGStp0lWi7o HYjAAbTW+3wE8pk2tGLMKdnF9bz5vj8W/YqFQyQf7x4bfMwyOMdPvFASgESZbGcCean2 Q4VMjPw5nTS3qdZnYOuCx2E2cIz/orxzeY1nNZGQl9yUl6r8fwbX9nNysN2mSslhxfMV wV8yLEivULevAm6nOXIcFSV+S24Tio1rWsYqXgsy8XszC8Ruf+/Z4OIYe3XvbURCyeW5 XJ4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rxIBmswNh0tIGuyehJwJsuO5I+nId1kc+WGKDH86wIY=; b=rwBLYg/rG6s8VGucjLo6olnYvDUbFLjZC330BcY7/dEUk0LHczeA+gufD2CVHvmQL3 qLmpyAdvowIxdcuW+tJqdCKp4y+AE3IOQqVFzPYKodeoO/7LGotId40huWF5AStF67nX CA1Nshs1N4psn4IbIolCkmdgCejW/nWU+wY0ub3csk1l3WTTCtuKmJSMMoBa5UnqVmL0 dDQ2VrG3KRH8+CIihE+iNnk7kAM7cgvohgZss0vTa3WRlm7tUmLao4sHY1c0O12Cgg7E 6eV5s+pddX7jV1iDzWfDskfmfZS1Flyjwo2De9YFZiaSEJ/8uM3PWyrZ/x+YNRDN3cBG GmzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LOtU6s9l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/77] tests/tcg: Do not require FE_* exception bits Date: Tue, 25 Aug 2020 13:58:36 -0700 Message-Id: <20200825205950.730499-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Define anything that is missing as 0, so that flags & FE_FOO is false for any missing FOO. Cc: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/multiarch/float_helpers.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.25.1 Reviewed-by: Edgar E. Iglesias diff --git a/tests/tcg/multiarch/float_helpers.h b/tests/tcg/multiarch/float_helpers.h index 6337bc66c1..309f3f4bf1 100644 --- a/tests/tcg/multiarch/float_helpers.h +++ b/tests/tcg/multiarch/float_helpers.h @@ -8,6 +8,23 @@ #include +/* Some hosts do not have support for all of these; not required by ISO C. */ +#ifndef FE_OVERFLOW +#define FE_OVERFLOW 0 +#endif +#ifndef FE_UNDERFLOW +#define FE_UNDERFLOW 0 +#endif +#ifndef FE_DIVBYZERO +#define FE_DIVBYZERO 0 +#endif +#ifndef FE_INEXACT +#define FE_INEXACT 0 +#endif +#ifndef FE_INVALID +#define FE_INVALID 0 +#endif + /* Number of constants in each table */ int get_num_f16(void); int get_num_f32(void); From patchwork Tue Aug 25 20:58:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248266 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3766277ils; Tue, 25 Aug 2020 14:03:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtyMXAZJDnJy4Uz5PbWB0nUIkSETN+wUmT5Ue790gJhefoMwF3NLXP0qSR/WxqUeDO1jtg X-Received: by 2002:a17:902:c395:: with SMTP id g21mr9139993plg.264.1598389416216; Tue, 25 Aug 2020 14:03:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389416; cv=none; d=google.com; s=arc-20160816; b=I/0Qnir63WUosFujc3znqhDTscx4hpLGoya7Bxh00S/ol/3P9R3haQugIt2ojU5htB THQOFpVtmJpA0nfV10k1YabuKio29xCNn3sfHmY15k7ACd8HYW9gHBTltrOWCjWwSbOj hly/lQO6oZXHfXuZyXFWrYJGIx+nEXLeY5bwsd1/625GS3+REE7bwmUsb84kWG3GpK7l R1GauZuaN+fJ0OBkaq95wc2lohfoeS/d1FN1YlvwI4++SzieyvRqv6Y7xwqcZeh2fVWy FaIR0EZE6HC1nJ3RIxJP32n7GuoY/EO6ezti1Gl+LDwec50AHEQeSZhi7xPbHkXbpRNI 4DaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6qPmiblB+ZyNN9MP1YkeatmcIUSnXTMdD0ACsae5YvQ=; b=dQ+Yss/qwsp64pI3F9EHPmmiKTEzoTJwXWyy3gXe89aiSLOIaNQXoog3uF0l4ZSBiM stBIvo0Yj69HVvt341xqURbylcbGFRaUK4dDS8EvjLfYDd+jDOxE2RHBKiuk4VhjiY9I lVFT5dXYPjs3WMIsRjheMtsl0CjWuMQQqLaMozxz0JyjqhIJjS0d4nQjNVL/IF9s/kcc bpi6QfzCbWqa8sXCa1R9K67vzy1zUMII007O1okJVC3QMYVtDWUfxcKR8s18YunPBv8C e1AYR99vR2V9ODoAeH88ZnLXOnSX0L488PHdAwZuTAm3ux0OGkWGiSX15C2BzcSchrnQ DsPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J9K799MQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/77] target/microblaze: Tidy gdbstub Date: Tue, 25 Aug 2020 13:58:37 -0700 Message-Id: <20200825205950.730499-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use an enumeration for the gdb register mapping. Use one switch statement for the entire dispatch. Drop sreg_map and simply enumerate those cases explicitly. Force r0 to have value 0 and ignore writes. Signed-off-by: Richard Henderson --- target/microblaze/gdbstub.c | 193 +++++++++++++++++++----------------- 1 file changed, 101 insertions(+), 92 deletions(-) -- 2.25.1 diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 73e8973597..e65ec051a5 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -21,58 +21,80 @@ #include "cpu.h" #include "exec/gdbstub.h" +/* + * GDB expects SREGs in the following order: + * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. + * + * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't + * map them to anything and return a value of 0 instead. + */ + +enum { + GDB_PC = 32 + 0, + GDB_MSR = 32 + 1, + GDB_EAR = 32 + 2, + GDB_ESR = 32 + 3, + GDB_FSR = 32 + 4, + GDB_BTR = 32 + 5, + GDB_PVR0 = 32 + 6, + GDB_PVR11 = 32 + 17, + GDB_EDR = 32 + 18, + GDB_SLR = 32 + 25, + GDB_SHR = 32 + 26, +}; + int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUClass *cc = CPU_GET_CLASS(cs); CPUMBState *env = &cpu->env; - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything and return a value of 0 instead. - */ - static const uint8_t sreg_map[6] = { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; + uint32_t val; - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { - return gdb_get_reg32(mem_buf, env->regs[n]); - } else { - n -= 32; - switch (n) { - case 0 ... 5: - return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]); - /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -= 6; - return gdb_get_reg32(mem_buf, env->pvr.regs[n]); - case 18: - return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]); - /* Other SRegs aren't modeled, so report a value of 0 */ - case 19 ... 24: - return gdb_get_reg32(mem_buf, 0); - case 25: - return gdb_get_reg32(mem_buf, env->slr); - case 26: - return gdb_get_reg32(mem_buf, env->shr); - default: - return 0; - } + if (n > cc->gdb_num_core_regs) { + return 0; } + + switch (n) { + case 1 ... 31: + val = env->regs[n]; + break; + case GDB_PC: + val = env->sregs[SR_PC]; + break; + case GDB_MSR: + val = env->sregs[SR_MSR]; + break; + case GDB_EAR: + val = env->sregs[SR_EAR]; + break; + case GDB_ESR: + val = env->sregs[SR_ESR]; + break; + case GDB_FSR: + val = env->sregs[SR_FSR]; + break; + case GDB_BTR: + val = env->sregs[SR_BTR]; + break; + case GDB_PVR0 ... GDB_PVR11: + /* PVR12 is intentionally skipped */ + val = env->pvr.regs[n - GDB_PVR0]; + break; + case GDB_EDR: + val = env->sregs[SR_EDR]; + break; + case GDB_SLR: + val = env->slr; + break; + case GDB_SHR: + val = env->shr; + break; + default: + /* Other SRegs aren't modeled, so report a value of 0 */ + val = 0; + break; + } + return gdb_get_reg32(mem_buf, val); } int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) @@ -82,60 +104,47 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) CPUMBState *env = &cpu->env; uint32_t tmp; - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything. - */ - static const uint8_t sreg_map[6] = { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; - if (n > cc->gdb_num_core_regs) { return 0; } tmp = ldl_p(mem_buf); - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { + switch (n) { + case 1 ... 31: env->regs[n] = tmp; - } else { - n -= 32; - switch (n) { - case 0 ... 5: - env->sregs[sreg_map[n]] = tmp; - break; + break; + case GDB_PC: + env->sregs[SR_PC] = tmp; + break; + case GDB_MSR: + env->sregs[SR_MSR] = tmp; + break; + case GDB_EAR: + env->sregs[SR_EAR] = tmp; + break; + case GDB_ESR: + env->sregs[SR_ESR] = tmp; + break; + case GDB_FSR: + env->sregs[SR_FSR] = tmp; + break; + case GDB_BTR: + env->sregs[SR_BTR] = tmp; + break; + case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -= 6; - env->pvr.regs[n] = tmp; - break; - /* Only EDR is modeled in these indeces, so ignore the rest */ - case 18: - env->sregs[SR_EDR] = tmp; - break; - case 25: - env->slr = tmp; - break; - case 26: - env->shr = tmp; - break; - } + env->pvr.regs[n - GDB_PVR0] = tmp; + break; + case GDB_EDR: + env->sregs[SR_EDR] = tmp; + break; + case GDB_SLR: + env->slr = tmp; + break; + case GDB_SHR: + env->shr = tmp; + break; } return 4; } From patchwork Tue Aug 25 20:58:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248263 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3764507ils; Tue, 25 Aug 2020 14:01:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4S9PJobje1VFMhpRSRR0Vg+qllgHOjhZlDnpA51Riu7p+cGZncT26tnEMyPayZNARivn5 X-Received: by 2002:a67:7d53:: with SMTP id y80mr6974844vsc.212.1598389278633; Tue, 25 Aug 2020 14:01:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389278; cv=none; d=google.com; s=arc-20160816; b=o03TbZCcZwhwnNMQyYx0TvmGdVweZOrbnv2Uvu4UTNjusAiknkVCl9mhxNoyusZdQE QHlEOdBwqFhc8QxA+FltMhP4QjticFsaokPShcIz++4Jf8Hb3S/0LDjqgHHacMUQIjRC ncmbbmtO8jOe4rSvJ7GWdNVyPIdCnP3IjWZmwkm/tMQ0p4w51WilCyNtlbEKKLk3aEzf vpzta6QRB4BoWZs1d61LS9clX7JBx0Hf5cm+gsEmPVNHl1Pm2c17GxAn2R+/eJYQBpCK lIfrDVaBBIF6nsY7OVwz4LEHJpJhh/WqSxQqUB3A6cvfIPpbqMya2u2Ui70XGnfqmRJa Wifw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4OXLnCdYVi2j43Kppbpt72ljKyfNbleLew6fTqAwaaE=; b=CUvR4c4So7RqM2ITKHe8BGLQsly57S9Ze7zOuD+5Yj5NBpGxKHajieYDWPdxz6Ve2U DAnkqFaXFMmJjrBnpMtmLEFCzVE1Q4XQ7WA0eXlpdZJqtpqJ/0VXARazTZ9wyeLXkvRT beNhD/lyU5Wpd8lEAunbaNPJ/hM4KTPTNspFH6GzRHc8fKYx1AlNtg9hG8RZwIkqfUJG M5gAK1bdzIihcbiYkT/t6sizT5TPJ+j7RP23BF0GAbLL3uIWdfD22jVfJ+qX+lGifc6c Vbi1v76Zml3JNd01+Ljv1VcoVhB0K04+M5tJdTj/tFhHkSilVjxYDpI1QV/Afr0myx4l kBjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I8WqzWGJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/77] target/microblaze: Split out PC from env->sregs Date: Tue, 25 Aug 2020 13:58:38 -0700 Message-Id: <20200825205950.730499-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin eliminating the sregs array in favor of individual members. Does not correct the width of pc, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 ++- linux-user/microblaze/cpu_loop.c | 12 +++++------ linux-user/microblaze/signal.c | 8 ++++---- target/microblaze/cpu.c | 4 ++-- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 34 ++++++++++++++++---------------- target/microblaze/mmu.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 10 +++++++--- 9 files changed, 42 insertions(+), 37 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a31134b65c..d1f91bb318 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -236,6 +236,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; + uint64_t pc; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ @@ -351,7 +352,7 @@ typedef MicroBlazeCPU ArchCPU; static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { - *pc = env->sregs[SR_PC]; + *pc = env->pc; *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 3e0a7f730b..3c693086f4 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -51,7 +51,7 @@ void cpu_loop(CPUMBState *env) case EXCP_BREAK: /* Return address is 4 bytes after the call. */ env->regs[14] += 4; - env->sregs[SR_PC] = env->regs[14]; + env->pc = env->regs[14]; ret = do_syscall(env, env->regs[12], env->regs[5], @@ -63,7 +63,7 @@ void cpu_loop(CPUMBState *env) 0, 0); if (ret == -TARGET_ERESTARTSYS) { /* Wind back to before the syscall. */ - env->sregs[SR_PC] -= 4; + env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->regs[3] = ret; } @@ -73,13 +73,13 @@ void cpu_loop(CPUMBState *env) * not a userspace-usable register, as the kernel may clobber it * at any point.) */ - env->regs[14] = env->sregs[SR_PC]; + env->regs[14] = env->pc; break; case EXCP_HW_EXCP: - env->regs[17] = env->sregs[SR_PC] + 4; + env->regs[17] = env->pc + 4; if (env->iflags & D_FLAG) { env->sregs[SR_ESR] |= 1 << 12; - env->sregs[SR_PC] -= 4; + env->pc -= 4; /* FIXME: if branch was immed, replay the imm as well. */ } @@ -165,5 +165,5 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->regs[29] = regs->r29; env->regs[30] = regs->r30; env->regs[31] = regs->r31; - env->sregs[SR_PC] = regs->pc; + env->pc = regs->pc; } diff --git a/linux-user/microblaze/signal.c b/linux-user/microblaze/signal.c index 80950c2181..b4eeef4673 100644 --- a/linux-user/microblaze/signal.c +++ b/linux-user/microblaze/signal.c @@ -87,7 +87,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUMBState *env) __put_user(env->regs[29], &sc->regs.r29); __put_user(env->regs[30], &sc->regs.r30); __put_user(env->regs[31], &sc->regs.r31); - __put_user(env->sregs[SR_PC], &sc->regs.pc); + __put_user(env->pc, &sc->regs.pc); } static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env) @@ -124,7 +124,7 @@ static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env) __get_user(env->regs[29], &sc->regs.r29); __get_user(env->regs[30], &sc->regs.r30); __get_user(env->regs[31], &sc->regs.r31); - __get_user(env->sregs[SR_PC], &sc->regs.pc); + __get_user(env->pc, &sc->regs.pc); } static abi_ulong get_sigframe(struct target_sigaction *ka, @@ -188,7 +188,7 @@ void setup_frame(int sig, struct target_sigaction *ka, env->regs[7] = frame_addr += offsetof(typeof(*frame), uc); /* Offset of 4 to handle microblaze rtid r14, 0 */ - env->sregs[SR_PC] = (unsigned long)ka->_sa_handler; + env->pc = (unsigned long)ka->_sa_handler; unlock_user_struct(frame, frame_addr, 1); return; @@ -228,7 +228,7 @@ long do_sigreturn(CPUMBState *env) restore_sigcontext(&frame->uc.tuc_mcontext, env); /* We got here through a sigreturn syscall, our path back is via an rtb insn so setup r14 for that. */ - env->regs[14] = env->sregs[SR_PC]; + env->regs[14] = env->pc; unlock_user_struct(frame, frame_addr, 0); return -TARGET_QEMU_ESIGRETURN; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 51e5c85b10..bde9992535 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -79,7 +79,7 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - cpu->env.sregs[SR_PC] = value; + cpu->env.pc = value; } static bool mb_cpu_has_work(CPUState *cs) @@ -117,7 +117,7 @@ static void mb_cpu_reset(DeviceState *dev) /* Disable stack protector. */ env->shr = ~0; - env->sregs[SR_PC] = cpu->cfg.base_vectors; + env->pc = cpu->cfg.base_vectors; #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e65ec051a5..9ea31f8d2f 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -59,7 +59,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->regs[n]; break; case GDB_PC: - val = env->sregs[SR_PC]; + val = env->pc; break; case GDB_MSR: val = env->sregs[SR_MSR]; @@ -115,7 +115,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->regs[n] = tmp; break; case GDB_PC: - env->sregs[SR_PC] = tmp; + env->pc = tmp; break; case GDB_MSR: env->sregs[SR_MSR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ab2ceeb055..5c392deea4 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -35,7 +35,7 @@ void mb_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; env->res_addr = RES_ADDR_NONE; - env->regs[14] = env->sregs[SR_PC]; + env->regs[14] = env->pc; } bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -126,7 +126,7 @@ void mb_cpu_do_interrupt(CPUState *cs) return; } - env->regs[17] = env->sregs[SR_PC] + 4; + env->regs[17] = env->pc + 4; env->sregs[SR_ESR] &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ @@ -145,15 +145,15 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_EAR], + env->pc, env->sregs[SR_EAR], env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; + env->pc = cpu->cfg.base_vectors + 0x20; break; case EXCP_MMU: - env->regs[17] = env->sregs[SR_PC]; + env->regs[17] = env->pc; env->sregs[SR_ESR] &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ @@ -169,7 +169,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "bimm exception at pc=%" PRIx64 " " "iflags=%x\n", - env->sregs[SR_PC], env->iflags); + env->pc, env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } @@ -188,10 +188,10 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=%" PRIx64 " ear=%" PRIx64 " " "iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); + env->pc, env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; + env->pc = cpu->cfg.base_vectors + 0x20; break; case EXCP_IRQ: @@ -209,14 +209,14 @@ void mb_cpu_do_interrupt(CPUState *cs) { const char *sym; - sym = lookup_symbol(env->sregs[SR_PC]); + sym = lookup_symbol(env->pc); if (sym && (!strcmp("netif_rx", sym) || !strcmp("process_backlog", sym))) { qemu_log( "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags, + env->pc, env->sregs[SR_MSR], t, env->iflags, sym); log_cpu_state(cs, 0); @@ -226,14 +226,14 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); + env->pc, env->sregs[SR_MSR], t, env->iflags); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ | MSR_UM | MSR_IE); env->sregs[SR_MSR] |= t; - env->regs[14] = env->sregs[SR_PC]; - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10; + env->regs[14] = env->pc; + env->pc = cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; @@ -245,17 +245,17 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); + env->pc, env->sregs[SR_MSR], t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; if (cs->exception_index == EXCP_HW_BREAK) { - env->regs[16] = env->sregs[SR_PC]; + env->regs[16] = env->pc; env->sregs[SR_MSR] |= MSR_BIP; - env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18; + env->pc = cpu->cfg.base_vectors + 0x18; } else - env->sregs[SR_PC] = env->btarget; + env->pc = env->btarget; break; default: cpu_abort(cs, "unhandled exception type=%d\n", diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 6763421ba2..3f403b567b 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -251,7 +251,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%" PRIx64 "\n", - i, env->sregs[SR_PC]); + i, env->pc); env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f3b17a95b3..2deef32740 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -75,7 +75,7 @@ void helper_debug(CPUMBState *env) { int i; - qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]); + qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a96cb21d96..9f6815cc1f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1805,7 +1805,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", - env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); + env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", @@ -1868,7 +1868,11 @@ void mb_tcg_init(void) offsetof(CPUMBState, regs[i]), regnames[i]); } - for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) { + + cpu_SR[SR_PC] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + + for (i = 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); @@ -1878,5 +1882,5 @@ void mb_tcg_init(void) void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, target_ulong *data) { - env->sregs[SR_PC] = data[0]; + env->pc = data[0]; } From patchwork Tue Aug 25 20:58:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248267 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3766360ils; Tue, 25 Aug 2020 14:03:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwY9lFx3GkAxDPAuLKJoGUto6GNaq5Wt6IB1fTTGMifhJeQpXRKcSgTY+d+27rNJ3Ik0Nd5 X-Received: by 2002:a17:902:6841:: with SMTP id f1mr8603453pln.228.1598389422265; Tue, 25 Aug 2020 14:03:42 -0700 (PDT) ARC-Seal: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/77] target/microblaze: Split out MSR from env->sregs Date: Tue, 25 Aug 2020 13:58:39 -0700 Message-Id: <20200825205950.730499-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of MSR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 7 ++--- target/microblaze/cpu.c | 4 +-- target/microblaze/gdbstub.c | 4 +-- target/microblaze/helper.c | 49 +++++++++++++++++------------------ target/microblaze/op_helper.c | 22 ++++++++-------- target/microblaze/translate.c | 14 +++++----- 6 files changed, 51 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d1f91bb318..36de61d9f9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -237,6 +237,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint64_t pc; + uint64_t msr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ @@ -355,7 +356,7 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | - (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); + (env->msr & (MSR_UM | MSR_VM | MSR_EE)); } #if !defined(CONFIG_USER_ONLY) @@ -370,11 +371,11 @@ static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) MicroBlazeCPU *cpu = env_archcpu(env); /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { return MMU_NOMMU_IDX; } - if (env->sregs[SR_MSR] & MSR_UM) { + if (env->msr & MSR_UM) { return MMU_USER_IDX; } return MMU_KERNEL_IDX; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bde9992535..0eac068570 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -121,9 +121,9 @@ static void mb_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ - env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; + env->msr = MSR_EE | MSR_IE | MSR_VM | MSR_UM; #else - env->sregs[SR_MSR] = 0; + env->msr = 0; mmu_init(&env->mmu); env->mmu.c_mmu = 3; env->mmu.c_mmu_tlb_access = 3; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 9ea31f8d2f..e4c4936a7a 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -62,7 +62,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pc; break; case GDB_MSR: - val = env->sregs[SR_MSR]; + val = env->msr; break; case GDB_EAR: val = env->sregs[SR_EAR]; @@ -118,7 +118,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pc = tmp; break; case GDB_MSR: - env->sregs[SR_MSR] = tmp; + env->msr = tmp; break; case GDB_EAR: env->sregs[SR_EAR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5c392deea4..a18314540f 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -117,7 +117,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); -/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ +/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; switch (cs->exception_index) { case EXCP_HW_EXCP: @@ -136,11 +136,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |= t; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |= t; /* Exception in progress. */ - env->sregs[SR_MSR] |= MSR_EIP; + env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " @@ -179,11 +179,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |= t; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |= t; /* Exception in progress. */ - env->sregs[SR_MSR] |= MSR_EIP; + env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, "exception at pc=%" PRIx64 " ear=%" PRIx64 " " @@ -195,11 +195,11 @@ void mb_cpu_do_interrupt(CPUState *cs) break; case EXCP_IRQ: - assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))); - assert(env->sregs[SR_MSR] & MSR_IE); + assert(!(env->msr & (MSR_EIP | MSR_BIP))); + assert(env->msr & MSR_IE); assert(!(env->iflags & D_FLAG)); - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; #if 0 #include "disas/disas.h" @@ -216,7 +216,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log( "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->pc, env->sregs[SR_MSR], t, env->iflags, + env->pc, env->msr, t, env->iflags, sym); log_cpu_state(cs, 0); @@ -226,11 +226,10 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->pc, env->sregs[SR_MSR], t, env->iflags); + env->pc, env->msr, t, env->iflags); - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ - | MSR_UM | MSR_IE); - env->sregs[SR_MSR] |= t; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); + env->msr |= t; env->regs[14] = env->pc; env->pc = cpu->cfg.base_vectors + 0x10; @@ -241,18 +240,18 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); - t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; + t = (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " "iflags=%x\n", - env->pc, env->sregs[SR_MSR], t, env->iflags); + env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |= t; - env->sregs[SR_MSR] |= MSR_BIP; + env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |= t; + env->msr |= MSR_BIP; if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->pc; - env->sregs[SR_MSR] |= MSR_BIP; + env->msr |= MSR_BIP; env->pc = cpu->cfg.base_vectors + 0x18; } else env->pc = env->btarget; @@ -293,8 +292,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) CPUMBState *env = &cpu->env; if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->sregs[SR_MSR] & MSR_IE) - && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) + && (env->msr & MSR_IE) + && !(env->msr & (MSR_EIP | MSR_BIP)) && !(env->iflags & (D_FLAG | IMM_FLAG))) { cs->exception_index = EXCP_IRQ; mb_cpu_do_interrupt(cs); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 2deef32740..3668382d36 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,14 +78,14 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, - (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (bool)(env->sregs[SR_MSR] & MSR_EIP), - (bool)(env->sregs[SR_MSR] & MSR_IE)); + (env->msr & MSR_UM) ? "user" : "kernel", + (env->msr & MSR_UMS) ? "user" : "kernel", + (bool)(env->msr & MSR_EIP), + (bool)(env->msr & MSR_IE)); for (i = 0; i < 32; i++) { qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); if ((i + 1) % 4 == 0) @@ -135,15 +135,15 @@ static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) MicroBlazeCPU *cpu = env_archcpu(env); if (b == 0) { - env->sregs[SR_MSR] |= MSR_DZ; + env->msr |= MSR_DZ; - if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) { + if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { env->sregs[SR_ESR] = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; } - env->sregs[SR_MSR] &= ~MSR_DZ; + env->msr &= ~MSR_DZ; return 1; } @@ -192,7 +192,7 @@ static void update_fpu_flags(CPUMBState *env, int flags) } if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) - && (env->sregs[SR_MSR] & MSR_EE)) { + && (env->msr & MSR_EE)) { raise_fpu_exception(env); } } @@ -437,7 +437,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr, if (mask == 3) { env->sregs[SR_ESR] |= 1 << 11; } - if (!(env->sregs[SR_MSR] & MSR_EE)) { + if (!(env->msr & MSR_EE)) { return; } helper_raise_exception(env, EXCP_HW_EXCP); @@ -484,7 +484,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, env = &cpu->env; cpu_restore_state(cs, retaddr, true); - if (!(env->sregs[SR_MSR] & MSR_EE)) { + if (!(env->msr & MSR_EE)) { return; } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9f6815cc1f..9f2dcd82cd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,16 +1809,16 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", - env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", env->btaken, env->btarget, - (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (bool)(env->sregs[SR_MSR] & MSR_EIP), - (bool)(env->sregs[SR_MSR] & MSR_IE)); + (env->msr & MSR_UM) ? "user" : "kernel", + (env->msr & MSR_UMS) ? "user" : "kernel", + (bool)(env->msr & MSR_EIP), + (bool)(env->msr & MSR_IE)); for (i = 0; i < 12; i++) { qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); if ((i + 1) % 4 == 0) { @@ -1871,8 +1871,10 @@ void mb_tcg_init(void) cpu_SR[SR_PC] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + cpu_SR[SR_MSR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - for (i = 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Tue Aug 25 20:58:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248270 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3767744ils; Tue, 25 Aug 2020 14:05:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyqiR43vRn1V+pmvZhBIahEuP/JEYLng60aripwXS4nw/EpW1iQwl2mFCED08oFgPsl6PzI X-Received: by 2002:a25:e692:: with SMTP id d140mr17237268ybh.159.1598389537064; Tue, 25 Aug 2020 14:05:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389537; cv=none; d=google.com; s=arc-20160816; b=fAOyil9HlJD8aSrJaJS2K8HHQG0MQrUw7d4ObCToROjPxi18WMmPw+ujRkbB7bS4/J EEgWvt4LHLfVsj91qglrhXodSiz+le2RvM/MAkg9++eefWoxTHiE0EpGp1lrLec1bl9n CGacf6etqvdcrSkx7M3WFpacGXXPbXM4ms/o+Nlgb0qdJ/8xiKsknt63aScFCBbkgBSS BiHu41ebdOwWP9JigoVtTphBUNQU6QVf3N26cHK0R+nN0PuA0+KV92gEilKPO8lRbhcC DZJDu/Jd9cHDN3pkjS2gYqQQDMuh4pSuBiByZgBitfnFzUQCIA6d83MBdOgOFcl/xD6I vRwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3AKOFIW3VCEZ6h4ggmUpiB5wdoa5LhPs+jftJ9b2SfM=; b=MphwpD4nyfcKy+cyFacFRvx0TiEyh8fz1GzdBvxrTkQjqtK6ZcQjfXJVZ6h8+qTEcz 7LFQvOcpEOGzYkp/8kharK9Ce2ZXGEl5BlkKXi/EmgXXql5UgtW5uNcD76yumSXFjSlB jUvFkN5RjMxkafvGVGHl6ZJsIToyNF1HlmO2PgO6Mj/VnMNlR9KR/zz+yZz7agYo0jhK 62Gaxs7NZj6+xzgicZP2Z7uTL0e6yAKKrqAyy5qHRYPDB29x0GssDG4TurlHFBckp5/a 8vH6H9dm4xZwZrHIoh1wnDUsk1yTSbqGZOUkW0U8F9Zase8Rbe9HsYAiZbE/khC6cBWv leNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IaanKXrC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/77] target/microblaze: Split out EAR from env->sregs Date: Tue, 25 Aug 2020 13:58:40 -0700 Message-Id: <20200825205950.730499-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 6 +++--- target/microblaze/op_helper.c | 8 ++++---- target/microblaze/translate.c | 6 ++++-- 5 files changed, 14 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 36de61d9f9..c9035b410e 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -238,6 +238,7 @@ struct CPUMBState { uint32_t regs[32]; uint64_t pc; uint64_t msr; + uint64_t ear; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e4c4936a7a..e33a613efe 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -65,7 +65,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->msr; break; case GDB_EAR: - val = env->sregs[SR_EAR]; + val = env->ear; break; case GDB_ESR: val = env->sregs[SR_ESR]; @@ -121,7 +121,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->msr = tmp; break; case GDB_EAR: - env->sregs[SR_EAR] = tmp; + env->ear = tmp; break; case GDB_ESR: env->sregs[SR_ESR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a18314540f..afe9634781 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -85,7 +85,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", mmu_idx, address); - env->sregs[SR_EAR] = address; + env->ear = address; switch (lu.err) { case ERR_PROT: env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; @@ -145,7 +145,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", - env->pc, env->sregs[SR_EAR], + env->pc, env->ear, env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); @@ -188,7 +188,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=%" PRIx64 " ear=%" PRIx64 " " "iflags=%x\n", - env->pc, env->sregs[SR_EAR], env->iflags); + env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->pc = cpu->cfg.base_vectors + 0x20; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 3668382d36..5bacd29663 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, @@ -431,7 +431,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr, "unaligned access addr=" TARGET_FMT_lx " mask=%x, wr=%d dr=r%d\n", addr, mask, wr, dr); - env->sregs[SR_EAR] = addr; + env->ear = addr; env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ | (dr & 31) << 5; if (mask == 3) { @@ -450,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); - env->sregs[SR_EAR] = addr; + env->ear = addr; env->sregs[SR_ESR] = ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } @@ -488,7 +488,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, return; } - env->sregs[SR_EAR] = addr; + env->ear = addr; if (access_type == MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { env->sregs[SR_ESR] = ESR_EC_INSN_BUS; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9f2dcd82cd..62747b02f3 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->ear, env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " @@ -1873,8 +1873,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_SR[SR_MSR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + cpu_SR[SR_EAR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); - for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Tue Aug 25 20:58:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248260 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3763879ils; Tue, 25 Aug 2020 14:00:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhN2RJ6hxBv/AlTC8Q0s3o6yh43eGcRdahLVE7DgcVq2r/PL8qdedACB7X8wvEcyFKdY4O X-Received: by 2002:a25:c78d:: with SMTP id w135mr17381743ybe.497.1598389227569; Tue, 25 Aug 2020 14:00:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389227; cv=none; d=google.com; s=arc-20160816; b=q75AMsT2CgOqet/QxHMBOuh0+fyptEr/yN+R2n0ZMhCcGHSZYZGX9cfrLWcmNkJ507 Ffk7zJfB21GSZTsckhn9vSnSS7MmJDHmTbI0Cv4Qkv75hBYwLTo1+pKTJPPIXlHTAvSA u47evGgq2u4FmLd46o/gnyEXVCSF9xZdO5lsbU2c3ZHpVz6s+SgHpT/3LZZhcgKtHu0b CD0zcKtEIYFT/NUBxWUCe6w49D7F5O+YiL5DJhMK5fV+fD8yjDGUKmLKR4R3Dl3ze2Ac uu0Jqxok568OQEfxlYGqN8LCO4fie0IwuOSGUVdT/6KyIS/43A/69KaJQEStjaz3Xjhd vpWA== ARC-Message-Signature: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/77] target/microblaze: Split out ESR from env->sregs Date: Tue, 25 Aug 2020 13:58:41 -0700 Message-Id: <20200825205950.730499-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of ESR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 6 +++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 18 +++++++++--------- target/microblaze/op_helper.c | 17 ++++++++--------- target/microblaze/translate.c | 6 ++++-- 6 files changed, 27 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c9035b410e..7d94af43ed 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,6 +239,7 @@ struct CPUMBState { uint64_t pc; uint64_t msr; uint64_t ear; + uint64_t esr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 3c693086f4..c10e3e0261 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -78,14 +78,14 @@ void cpu_loop(CPUMBState *env) case EXCP_HW_EXCP: env->regs[17] = env->pc + 4; if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |= 1 << 12; + env->esr |= 1 << 12; env->pc -= 4; /* FIXME: if branch was immed, replay the imm as well. */ } env->iflags &= ~(IMM_FLAG | D_FLAG); - switch (env->sregs[SR_ESR] & 31) { + switch (env->esr & 31) { case ESR_EC_DIVZERO: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; @@ -107,7 +107,7 @@ void cpu_loop(CPUMBState *env) break; default: fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n", - env->sregs[SR_ESR] & ESR_EC_MASK); + env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); break; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e33a613efe..05e22f233d 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -68,7 +68,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->ear; break; case GDB_ESR: - val = env->sregs[SR_ESR]; + val = env->esr; break; case GDB_FSR: val = env->sregs[SR_FSR]; @@ -124,7 +124,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->ear = tmp; break; case GDB_ESR: - env->sregs[SR_ESR] = tmp; + env->esr = tmp; break; case GDB_FSR: env->sregs[SR_FSR] = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index afe9634781..ea290be780 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -88,12 +88,12 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, env->ear = address; switch (lu.err) { case ERR_PROT: - env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; - env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + env->esr = access_type == MMU_INST_FETCH ? 17 : 16; + env->esr |= (access_type == MMU_DATA_STORE) << 10; break; case ERR_MISS: - env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 19 : 18; - env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + env->esr = access_type == MMU_INST_FETCH ? 19 : 18; + env->esr |= (access_type == MMU_DATA_STORE) << 10; break; default: abort(); @@ -127,11 +127,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } env->regs[17] = env->pc + 4; - env->sregs[SR_ESR] &= ~(1 << 12); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |= 1 << 12 ; + env->esr |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; } @@ -146,7 +146,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", env->pc, env->ear, - env->sregs[SR_ESR], env->iflags); + env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->pc = cpu->cfg.base_vectors + 0x20; @@ -155,11 +155,11 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] = env->pc; - env->sregs[SR_ESR] &= ~(1 << 12); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); - env->sregs[SR_ESR] |= 1 << 12 ; + env->esr |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; /* Reexecute the branch. */ diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 5bacd29663..f01cf9be64 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, @@ -138,7 +138,7 @@ static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) env->msr |= MSR_DZ; if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { - env->sregs[SR_ESR] = ESR_EC_DIVZERO; + env->esr = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; @@ -166,7 +166,7 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) /* raise FPU exception. */ static void raise_fpu_exception(CPUMBState *env) { - env->sregs[SR_ESR] = ESR_EC_FPU; + env->esr = ESR_EC_FPU; helper_raise_exception(env, EXCP_HW_EXCP); } @@ -432,10 +432,9 @@ void helper_memalign(CPUMBState *env, target_ulong addr, " mask=%x, wr=%d dr=r%d\n", addr, mask, wr, dr); env->ear = addr; - env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ - | (dr & 31) << 5; + env->esr = ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) << 5; if (mask == 3) { - env->sregs[SR_ESR] |= 1 << 11; + env->esr |= 1 << 11; } if (!(env->msr & MSR_EE)) { return; @@ -451,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); env->ear = addr; - env->sregs[SR_ESR] = ESR_EC_STACKPROT; + env->esr = ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } } @@ -491,12 +490,12 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, env->ear = addr; if (access_type == MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] = ESR_EC_INSN_BUS; + env->esr = ESR_EC_INSN_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } else { if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] = ESR_EC_DATA_BUS; + env->esr = ESR_EC_DATA_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 62747b02f3..411c7b6e49 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " @@ -1875,8 +1875,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_SR[SR_EAR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); + cpu_SR[SR_ESR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); - for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Tue Aug 25 20:58:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248271 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3768035ils; Tue, 25 Aug 2020 14:06:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyQODsjInmDdVK315sVUYBkc+/z4sJVGEGoC7Eo7XxOAB7HICNnm0Oq/vwcegbNGPG8jgJI X-Received: by 2002:a25:c347:: with SMTP id t68mr18229668ybf.105.1598389564065; Tue, 25 Aug 2020 14:06:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389564; cv=none; d=google.com; s=arc-20160816; b=ArjwyanlzISK53Wuqr8DRK70p4ZFGQBhAMbDVLqtvtlv6eWPwrQYwW8VJt3zT5WVox dFVfjx1sXMCR7t2njQ3Blk6W/3j+iwjcgABc1HzQ72fmk2eJoEF35bQQ8es78IQiGvh4 /yxB5GTI/DWYkUd96t5Q2nBsJRkpwNm9kfHpU0k5yrvKLJio/8qKGiJat7l6rvz74dIh f+gUmwL8MUM/cElEXhaI25HnkNxauSgreQ6LySO4vThxbMywmzJxaZGOzNyzx47rkXJG /ESji/JVsE9ESn0gWA5pZQobNeh/zZW5Fc125FdK21dxpPFhAA/NRr6IkKm8iNEer0ht ZmCw== ARC-Message-Signature: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/77] target/microblaze: Split out FSR from env->sregs Date: Tue, 25 Aug 2020 13:58:42 -0700 Message-Id: <20200825205950.730499-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of FSR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 4 ++-- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/op_helper.c | 8 ++++---- target/microblaze/translate.c | 6 ++++-- 5 files changed, 13 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7d94af43ed..bcafef99b0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -240,6 +240,7 @@ struct CPUMBState { uint64_t msr; uint64_t ear; uint64_t esr; + uint64_t fsr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index c10e3e0261..da5e98b784 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env) case ESR_EC_FPU: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; - if (env->sregs[SR_FSR] & FSR_IO) { + if (env->fsr & FSR_IO) { info.si_code = TARGET_FPE_FLTINV; } - if (env->sregs[SR_FSR] & FSR_DZ) { + if (env->fsr & FSR_DZ) { info.si_code = TARGET_FPE_FLTDIV; } info._sifields._sigfault._addr = 0; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 05e22f233d..2634ce49fc 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -71,7 +71,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->esr; break; case GDB_FSR: - val = env->sregs[SR_FSR]; + val = env->fsr; break; case GDB_BTR: val = env->sregs[SR_BTR]; @@ -127,7 +127,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->esr = tmp; break; case GDB_FSR: - env->sregs[SR_FSR] = tmp; + env->fsr = tmp; break; case GDB_BTR: env->sregs[SR_BTR] = tmp; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f01cf9be64..ae57d45536 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -175,19 +175,19 @@ static void update_fpu_flags(CPUMBState *env, int flags) int raise = 0; if (flags & float_flag_invalid) { - env->sregs[SR_FSR] |= FSR_IO; + env->fsr |= FSR_IO; raise = 1; } if (flags & float_flag_divbyzero) { - env->sregs[SR_FSR] |= FSR_DZ; + env->fsr |= FSR_DZ; raise = 1; } if (flags & float_flag_overflow) { - env->sregs[SR_FSR] |= FSR_OF; + env->fsr |= FSR_OF; raise = 1; } if (flags & float_flag_underflow) { - env->sregs[SR_FSR] |= FSR_UF; + env->fsr |= FSR_UF; raise = 1; } if (raise diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 411c7b6e49..c58c49ea8f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1810,7 +1810,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags, env->sregs[SR_FSR], + env->debug, env->imm, env->iflags, env->fsr, env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", @@ -1877,8 +1877,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_SR[SR_ESR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); + cpu_SR[SR_FSR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); - for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Tue Aug 25 20:58:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248272 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3768753ils; Tue, 25 Aug 2020 14:07:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxnWDxkazzCXijVR7VZLw0dNDfsMX8P8DjZRKwlHUZGyqAzhFeWQ620hTdR/Bhb3Rwe8obr X-Received: by 2002:a5b:c08:: with SMTP id f8mr16182338ybq.198.1598389628226; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/77] target/microblaze: Split out BTR from env->sregs Date: Tue, 25 Aug 2020 13:58:43 -0700 Message-Id: <20200825205950.730499-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue eliminating the sregs array in favor of individual members. Does not correct the width of BTR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 4 ++-- target/microblaze/translate.c | 6 ++++-- 4 files changed, 9 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index bcafef99b0..deddb47abb 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,6 +241,7 @@ struct CPUMBState { uint64_t ear; uint64_t esr; uint64_t fsr; + uint64_t btr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 2634ce49fc..cde8c169bf 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -74,7 +74,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->fsr; break; case GDB_BTR: - val = env->sregs[SR_BTR]; + val = env->btr; break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ @@ -130,7 +130,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->fsr = tmp; break; case GDB_BTR: - env->sregs[SR_BTR] = tmp; + env->btr = tmp; break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ea290be780..b240dc76f6 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -132,7 +132,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { env->esr |= 1 << 12 ; - env->sregs[SR_BTR] = env->btarget; + env->btr = env->btarget; } /* Disable the MMU. */ @@ -160,7 +160,7 @@ void mb_cpu_do_interrupt(CPUState *cs) if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); env->esr |= 1 << 12 ; - env->sregs[SR_BTR] = env->btarget; + env->btr = env->btarget; /* Reexecute the branch. */ env->regs[17] -= 4; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c58c49ea8f..469e1f103a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1811,7 +1811,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, - env->sregs[SR_BTR]); + env->btr); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", env->btaken, env->btarget, @@ -1879,8 +1879,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); cpu_SR[SR_FSR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); + cpu_SR[SR_BTR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); From patchwork Tue Aug 25 20:58:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248278 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3770774ils; Tue, 25 Aug 2020 14:10:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwigUXCjUI36okTQNdEpTFifjR2Q8/x/GWElaYOqIBfUZRPw/uyGlufj8nMxxiseXDuHdcO X-Received: by 2002:a25:8481:: with SMTP id v1mr17291071ybk.203.1598389817315; Tue, 25 Aug 2020 14:10:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389817; cv=none; d=google.com; s=arc-20160816; b=UYVfEOpDzJeFyK5SmGbJKPSU1uVXF5h8QBe5LiWKWTqxzw9qZ61tr0b44KFFsxfwnt Scq6DCHSzqLNRoTOTuLvUp2qpZb5i3nrGxTD5jpl4NxooL84/LMgZUzIWElrAxBAuua1 pyQ3wRBIs2PZ6X6iouKX4DVcVBFy8pAMdgiyr78z1GMniepOeTDPoYOLVkkJ69w8GmQc OzDniDyn7tP3eYi5EmdFCbQrHYOseoya6BLpHJ16ubC5G9qhPKzedCLxRr6xMLkejd6Y h7W6uEVna/CkoB40qh26W00XjkF2AC4F6WfPHx7kFdF/imfdEDyOf0cTS5fIZkR1leeI HaFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kxuKPEsnkZdfVwCBdweXYlcCCLoCz5+CGJqBlv/VqWk=; b=A/G2/lvnA1yolEiXCbVpL93vfW2JmNy4z9AKG0uVSc6WUmzmRCCE9ixku4SMSXu1Yo tElVYosUiWNA+SAnYibbnvCXQGCESHPFVNULRAW3snrZOMl0pc34OsSToIRljxM3Uh8I Ylm6KHthhLATXqjwv+jrxEJIkTq8wUYAalVpy02Nk1pymP9bk8k3cQPPLcDkGFjhFcvC 0UZc2JvdmAoBe9AVKkNlsCfHobVCw5CN+DbNtxDp6ojIpTD+LmYieTScQazqXKsCPGog JpYru9Y88Men1J65zonLZ0ieV+FAI0/Dnk4MQwnwz4F9UTdXQ0auEmiKoTVXht/lc4Tv bd8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GD3E5qCk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/77] target/microblaze: Split out EDR from env->sregs Date: Tue, 25 Aug 2020 13:58:44 -0700 Message-Id: <20200825205950.730499-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Finish eliminating the sregs array in favor of individual members. Does not correct the width of EDR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/elfload.c | 9 ++++++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/translate.c | 16 +++------------- 4 files changed, 12 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index deddb47abb..610ddfb719 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint64_t esr; uint64_t fsr; uint64_t btr; - uint64_t sregs[14]; + uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index fe9dfe795d..bbfb665321 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1032,9 +1032,12 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env (*regs)[pos++] = tswapreg(env->regs[i]); } - for (i = 0; i < 6; i++) { - (*regs)[pos++] = tswapreg(env->sregs[i]); - } + (*regs)[pos++] = tswapreg(env->pc); + (*regs)[pos++] = tswapreg(env->msr); + (*regs)[pos++] = 0; + (*regs)[pos++] = tswapreg(env->ear); + (*regs)[pos++] = 0; + (*regs)[pos++] = tswapreg(env->esr); } #endif /* TARGET_MICROBLAZE */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index cde8c169bf..9cba9d2215 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -81,7 +81,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pvr.regs[n - GDB_PVR0]; break; case GDB_EDR: - val = env->sregs[SR_EDR]; + val = env->edr; break; case GDB_SLR: val = env->slr; @@ -137,7 +137,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pvr.regs[n - GDB_PVR0] = tmp; break; case GDB_EDR: - env->sregs[SR_EDR] = tmp; + env->edr = tmp; break; case GDB_SLR: env->slr = tmp; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 469e1f103a..7d307e6b48 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -103,12 +103,6 @@ static const char *regnames[] = "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", }; -static const char *special_regnames[] = -{ - "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr", - "sr8", "sr9", "sr10", "rbtr", "sr12", "redr" -}; - static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1828,7 +1822,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) /* Registers that aren't modeled are reported as 0 */ qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " - "rtlblo=0 rtlbhi=0\n", env->sregs[SR_EDR]); + "rtlblo=0 rtlbhi=0\n", env->edr); qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); @@ -1881,12 +1875,8 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_SR[SR_BTR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - - for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) { - cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUMBState, sregs[i]), - special_regnames[i]); - } + cpu_SR[SR_EDR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Tue Aug 25 20:58:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248274 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3769287ils; Tue, 25 Aug 2020 14:07:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxbiZEGlrYccCJ7+Fz85QJee19gk7ykOqna3aP7kRArJ1MCtpw0PJYiK7wFjrLkqSXzCdmz X-Received: by 2002:a25:a091:: with SMTP id y17mr16960310ybh.82.1598389672793; Tue, 25 Aug 2020 14:07:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389672; cv=none; d=google.com; s=arc-20160816; b=R+IjDfalAhwCxwQmd3k5zSQVwovHUrsVEzo0wfn/3h5zOTycFa7Due63Cdw01ApSix az96fuJvO08hg1S+dBkmPWXuIntb6vlFz7sBRRMQfVBhXwr17u3lFgjkWnNXgZisXodS xJ9c3NhqAT6f27RrB7NTBQWCj/xVUmAoyYoUO43SW5qdqCVk1tXozINale9/xgNusX+r hQ9VFwEXgadCFXE6EIUmHfkCJWooxllPx1V1xgcgfgp+9sm9+2bWGot83BrDzqYvQUzv DWTpD+RIV14pSebGwy5lDPt80Zwhgp/UeokkROkolitVVVE9YQkQLKo/fN/e60+BAqD2 wSbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mWZxIEkP4nZuOtJzfgZGg0mAj4EW15ubIN08DOn/YHw=; b=OwZBeGPdeMV6OG5xrbJ6SAUVo9SLpr8mnuNiQ3VNlp0MZSSiRblU6Cjt/5Xp9t5lkb tbudLgF6E9u8ltVY9umESBpVxo75GIVXYLi6soEhOE7tf7be651d0DV8Yw9gwiJ99R/8 uSGD6b5JE8j6QWHqhH/eU+UfxpfT56b4SYk/be3iWPj3vhkrE8q7G1BsZ2XoyQQv0uva EOp/tJk5HgteYgQdvHl1KSaplNDIBtAM8OSxrHT9x6XdWh0k292/I0v1fbgD5shHql7f wVqAAI8YIIdw1eqWEw8P03znCXxCxZb8XENnYDgK86SH+OautMiHUnhSTR9O4PpyYyzW FvfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RC6zNY84; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/77] target/microblaze: Split the cpu_SR array Date: Tue, 25 Aug 2020 13:58:45 -0700 Message-Id: <20200825205950.730499-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Similar to splitting the sregs array, this will allow further fixes and cleanups. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 106 +++++++++++++++++++++------------- 1 file changed, 65 insertions(+), 41 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7d307e6b48..19d7b8abfd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -55,7 +55,13 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; -static TCGv_i64 cpu_SR[14]; +static TCGv_i64 cpu_pc; +static TCGv_i64 cpu_msr; +static TCGv_i64 cpu_ear; +static TCGv_i64 cpu_esr; +static TCGv_i64 cpu_fsr; +static TCGv_i64 cpu_btr; +static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i64 env_btarget; @@ -117,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) TCGv_i32 tmp = tcg_const_i32(index); t_sync_flags(dc); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; @@ -136,17 +142,17 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); } else { - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(d, cpu_msr); tcg_gen_shri_i32(d, d, 31); } @@ -159,8 +165,8 @@ static void write_carry(DisasContext *dc, TCGv_i32 v) TCGv_i64 t0 = tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t0, v); /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); - tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); + tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1); + tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1); tcg_temp_free_i64(t0); } @@ -180,7 +186,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -196,7 +202,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -431,7 +437,7 @@ static void dec_xor(DisasContext *dc) static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(d, cpu_msr); } static inline void msr_write(DisasContext *dc, TCGv_i32 v) @@ -443,8 +449,8 @@ static inline void msr_write(DisasContext *dc, TCGv_i32 v) /* PVR bit is not writable. */ tcg_gen_extu_i32_i64(t, v); tcg_gen_andi_i64(t, t, ~MSR_PVR); - tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); - tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); + tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR); + tcg_gen_or_i64(cpu_msr, cpu_msr, t); tcg_temp_free_i64(t); } @@ -503,7 +509,7 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_pc, dc->pc + 4); dc->is_jmp = DISAS_UPDATE; return; } @@ -535,15 +541,25 @@ static void dec_msr(DisasContext *dc) if (to) { LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); switch (sr) { - case 0: + case SR_PC: break; - case 1: + case SR_MSR: msr_write(dc, cpu_R[dc->ra]); break; case SR_EAR: + tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); + break; case SR_ESR: + tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]); + break; case SR_FSR: - tcg_gen_extu_i32_i64(cpu_SR[sr], cpu_R[dc->ra]); + tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); + break; + case SR_BTR: + tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); + break; + case SR_EDR: + tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], @@ -561,22 +577,30 @@ static void dec_msr(DisasContext *dc) LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); switch (sr) { - case 0: + case SR_PC: tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); break; - case 1: + case SR_MSR: msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); - break; + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); + } else { + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); } + break; case SR_ESR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr); + break; case SR_FSR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); + break; case SR_BTR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); + break; case SR_EDR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -749,7 +773,7 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t0, cpu_msr); tcg_gen_andi_i32(t0, t0, MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { @@ -995,7 +1019,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); tcg_temp_free_i32(t0); @@ -1115,7 +1139,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1169,7 +1193,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false) TCGv_i64 tmp_zero = tcg_const_i64(0); tcg_gen_extu_i32_i64(tmp_btaken, env_btaken); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_SR[SR_PC], + tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tmp_btaken, tmp_zero, pc_true, pc_false); @@ -1253,7 +1277,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_pc, dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1309,7 +1333,7 @@ static inline void do_rti(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_ori_i32(t1, t1, MSR_IE); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1327,7 +1351,7 @@ static inline void do_rtb(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_andi_i32(t1, t1, ~MSR_BIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1346,7 +1370,7 @@ static inline void do_rte(DisasContext *dc) t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_ori_i32(t1, t1, MSR_EE); tcg_gen_andi_i32(t1, t1, ~MSR_EIP); tcg_gen_shri_i32(t0, t1, 1); @@ -1401,7 +1425,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU); + tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; @@ -1652,7 +1676,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_debug(); } #endif @@ -1730,7 +1754,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); sync_jmpstate(dc); } else npc = dc->jmp_pc; @@ -1740,7 +1764,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); } t_sync_flags(dc); @@ -1748,7 +1772,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1863,19 +1887,19 @@ void mb_tcg_init(void) regnames[i]); } - cpu_SR[SR_PC] = + cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); - cpu_SR[SR_MSR] = + cpu_msr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_SR[SR_EAR] = + cpu_ear = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); - cpu_SR[SR_ESR] = + cpu_esr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_SR[SR_FSR] = + cpu_fsr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); - cpu_SR[SR_BTR] = + cpu_btr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - cpu_SR[SR_EDR] = + cpu_edr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } From patchwork Tue Aug 25 20:58:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248275 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3769847ils; Tue, 25 Aug 2020 14:08:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzkdaXXjyMSWyzaTTFfrZZQyYLx/vV3IQseIOMV1JmwdJ5rF9mPWDPk+avHJsPVTgagVL1m X-Received: by 2002:a25:3b4a:: with SMTP id i71mr15930864yba.464.1598389727240; Tue, 25 Aug 2020 14:08:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389727; cv=none; d=google.com; s=arc-20160816; b=KIk/l2J50fiWaH/gpeY9k5yzmwAUFDbygI1fYBaZSioe51zY9T0b4zAFj99L37uGNp HoR0HMLkWpDtWlWOVGYyIlHI3g+R8YHwreBBXLoZJN7K4QQLalDyKwb1PjDBI+B4bPNE 70pnPpvAB666fZdo+GeFSgyRWZyg1Cc3t8Q3AXiyDf56m0r0irdvjddR5lPqHLNWqiRr 3He3vpsH9oXpLvCZHblt4r2aRteqpDyJMxKYfdfufOTo9EPO2rKhod5542X/sPNSNR7D 9UWCYHpBug5mqQQ5a62Cz9gzbIGqtnvSfAdWdydH+V843WK5or39T62iooLEOMUweD9m Cv+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rsRB0RZxqoK3N2gzIw0qX54Gonb1t6EonRXZar2I/Yw=; b=gqzHvJ0uljSk739w7Qg42vwgeW/EFCrqhdHq39H9C3w7DlJGegbp87Z3fGGEaAOT5B IqwYSESZX4wBxKG5S5rlgmGVS1tx2hyi3up9u2ThGrEY4HP/Wwgu5k0jsLUb/wa+NYeO Bbq24556AFQBNUYFSKM/dZ+IqFbaOdpWDIHpZHRFF5DSR/7UPZucLmUG1Cmjix6kAKyF CcUKmnK+kL6X9gRZczT6kz4MdTnh1/lZTFxcC/WBrt5KAzo3DhjKytr3afoUYOmFlOG0 ebvkqTpYM1a67kipviAAuLkxgcnt/cYvTAcpp/MeA7qKavTuT62UlE65J/a3T1hJMy8K KmAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sUiQyss7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/77] target/microblaze: Fix width of PC and BTARGET Date: Tue, 25 Aug 2020 13:58:46 -0700 Message-Id: <20200825205950.730499-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The program counter is only 32-bits wide. Do not use a 64-bit type to represent it. Since they are so closely related, fix btarget at the same time. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/helper.c | 16 +++---- target/microblaze/mmu.c | 4 +- target/microblaze/op_helper.c | 4 +- target/microblaze/translate.c | 78 ++++++++++++++--------------------- 5 files changed, 43 insertions(+), 63 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 610ddfb719..f4c3c09b09 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -231,12 +231,12 @@ typedef struct CPUMBState CPUMBState; struct CPUMBState { uint32_t debug; uint32_t btaken; - uint64_t btarget; + uint32_t btarget; uint32_t bimm; uint32_t imm; uint32_t regs[32]; - uint64_t pc; + uint32_t pc; uint64_t msr; uint64_t ear; uint64_t esr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b240dc76f6..b95617a81a 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -143,7 +143,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, - "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " + "hw exception at pc=%x ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", env->pc, env->ear, env->esr, env->iflags); @@ -167,8 +167,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* was the branch immprefixed?. */ if (env->bimm) { qemu_log_mask(CPU_LOG_INT, - "bimm exception at pc=%" PRIx64 " " - "iflags=%x\n", + "bimm exception at pc=%x iflags=%x\n", env->pc, env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); @@ -186,8 +185,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->msr |= MSR_EIP; qemu_log_mask(CPU_LOG_INT, - "exception at pc=%" PRIx64 " ear=%" PRIx64 " " - "iflags=%x\n", + "exception at pc=%x ear=%" PRIx64 " iflags=%x\n", env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); @@ -224,8 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x " - "iflags=%x\n", + "interrupt at pc=%x msr=%" PRIx64 " %x iflags=%x\n", env->pc, env->msr, t, env->iflags); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); @@ -242,9 +239,8 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & D_FLAG)); t = (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, - "break at pc=%" PRIx64 " msr=%" PRIx64 " %x " - "iflags=%x\n", - env->pc, env->msr, t, env->iflags); + "break at pc=%x msr=%" PRIx64 " %x iflags=%x\n", + env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->msr |= t; diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 3f403b567b..6e583d78d9 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -250,8 +250,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) if (rn == MMU_R_TLBHI) { if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) qemu_log_mask(LOG_GUEST_ERROR, - "invalidating index %x at pc=%" PRIx64 "\n", - i, env->pc); + "invalidating index %x at pc=%x\n", + i, env->pc); env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index ae57d45536..fdf706a723 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -75,12 +75,12 @@ void helper_debug(CPUMBState *env) { int i; - qemu_log("PC=%" PRIx64 "\n", env->pc); + qemu_log("PC=%08x\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); - qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", + qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 19d7b8abfd..72783c1d8a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -55,7 +55,7 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; -static TCGv_i64 cpu_pc; +static TCGv_i32 cpu_pc; static TCGv_i64 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i64 cpu_esr; @@ -64,7 +64,7 @@ static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; -static TCGv_i64 env_btarget; +static TCGv_i32 cpu_btarget; static TCGv_i32 env_iflags; static TCGv env_res_addr; static TCGv_i32 env_res_val; @@ -123,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) TCGv_i32 tmp = tcg_const_i32(index); t_sync_flags(dc); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; @@ -142,10 +142,10 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_i64(cpu_pc, dest); + tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); } else { - tcg_gen_movi_i64(cpu_pc, dest); + tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } @@ -509,7 +509,7 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i64(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); dc->is_jmp = DISAS_UPDATE; return; } @@ -850,7 +850,7 @@ static inline void sync_jmpstate(DisasContext *dc) tcg_gen_movi_i32(env_btaken, 1); } dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i64(env_btarget, dc->jmp_pc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } } @@ -1019,7 +1019,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); tcg_temp_free_i32(t0); @@ -1139,7 +1139,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1187,18 +1187,15 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, } } -static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false) +static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) { - TCGv_i64 tmp_btaken = tcg_temp_new_i64(); - TCGv_i64 tmp_zero = tcg_const_i64(0); + TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_extu_i32_i64(tmp_btaken, env_btaken); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, - tmp_btaken, tmp_zero, + tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, + env_btaken, zero, pc_true, pc_false); - tcg_temp_free_i64(tmp_btaken); - tcg_temp_free_i64(tmp_zero); + tcg_temp_free_i32(zero); } static void dec_setup_dslot(DisasContext *dc) @@ -1229,14 +1226,12 @@ static void dec_bcc(DisasContext *dc) if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - tcg_gen_movi_i64(env_btarget, dc->pc + offset); + tcg_gen_movi_i32(cpu_btarget, dc->pc + offset); dc->jmp = JMP_DIRECT_CC; dc->jmp_pc = dc->pc + offset; } else { dc->jmp = JMP_INDIRECT; - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); } @@ -1277,7 +1272,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i64(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1303,7 +1298,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_INDIRECT; if (abs) { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) t_gen_raise_exception(dc, EXCP_BREAK); @@ -1321,9 +1316,7 @@ static void dec_br(DisasContext *dc) dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); } else { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } } } @@ -1387,7 +1380,6 @@ static inline void do_rte(DisasContext *dc) static void dec_rts(DisasContext *dc) { unsigned int b_bit, i_bit, e_bit; - TCGv_i64 tmp64; i_bit = dc->ir & (1 << 21); b_bit = dc->ir & (1 << 22); @@ -1413,13 +1405,7 @@ static void dec_rts(DisasContext *dc) dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(env_btaken, 1); - - tmp64 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_extu_i32_i64(tmp64, cpu_R[dc->ra]); - tcg_gen_add_i64(env_btarget, env_btarget, tmp64); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); - tcg_temp_free_i64(tmp64); + tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } static int dec_check_fpuv2(DisasContext *dc) @@ -1676,7 +1662,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_debug(); } #endif @@ -1718,10 +1704,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) dc->tb_flags &= ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp == JMP_INDIRECT) { - TCGv_i64 tmp_pc = tcg_const_i64(dc->pc); - eval_cond_jmp(dc, env_btarget, tmp_pc); - tcg_temp_free_i64(tmp_pc); - + TCGv_i32 tmp_pc = tcg_const_i32(dc->pc); + eval_cond_jmp(dc, cpu_btarget, tmp_pc); + tcg_temp_free_i32(tmp_pc); dc->is_jmp = DISAS_JUMP; } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); @@ -1754,7 +1739,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); sync_jmpstate(dc); } else npc = dc->jmp_pc; @@ -1764,7 +1749,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { dc->is_jmp = DISAS_UPDATE; - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); } t_sync_flags(dc); @@ -1772,7 +1757,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1822,7 +1807,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) return; } - qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", + qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " @@ -1830,8 +1815,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, env->btr); - qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " - "eip=%d ie=%d\n", + qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", @@ -1869,7 +1853,7 @@ void mb_tcg_init(void) env_imm = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); - env_btarget = tcg_global_mem_new_i64(cpu_env, + cpu_btarget = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btarget), "btarget"); env_btaken = tcg_global_mem_new_i32(cpu_env, @@ -1888,7 +1872,7 @@ void mb_tcg_init(void) } cpu_pc = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_ear = From patchwork Tue Aug 25 20:58:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248276 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3770221ils; Tue, 25 Aug 2020 14:09:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy6t7nk9NCCmNLm69mLl8KRyXcwCm2W6spFrU0Cu9LpQQirdY5thzQseb67wnF2/Fj6PgNg X-Received: by 2002:a25:d917:: with SMTP id q23mr16076000ybg.450.1598389763157; Tue, 25 Aug 2020 14:09:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389763; cv=none; d=google.com; s=arc-20160816; b=AkNzDig6dZPrSiieQW6wBkexUHsA7vTYzbTAF+pxWCot6RfJ3fEWeF2UKI100/FDgM dKtKkzL65C9WzCAArSQevnpy9fSncoB9TBtUqXrRCd8RKLZ8lLz8atVfBrR+fR2r3bH5 6nVALlF60QpJiDv022tREzFuxWaRhsDQH1y5le8WSX+UH+E5fonNu/w6PZylYYWxrPiK hN2D6Obl8IDta58kGTSqWrHVNFfPx9qXAtI+B/2oIBpYnzcWTh51s/CZnlXQBZEbfQ9e fxKlUQVhaS955FywHMQp+UqqQj+UYHZzwksuyzruY0Ch5yjx5xrH9M1QWUK9d1Lv3GVq GN/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vLvNC5AlBnMMj5Xypoodm2v5NfVH1pHkbk/5dT3fkns=; b=DbhI0HpxoAilIGqZGYjgNmfuFnSKtHmq31c1FOnqCfI576aznEIbPyZlKT4X43n/zo XE4kCaYhmvVbZyu6RGG+0hMQLKAlGYLLhvCjkwVt5PnbaNPpvHNMkHvN/8Uix4eEr1Wz VSDQhm/1v8iQacJbTMZuAXAGzddVun6IqEoWnjluD4PFvWfatd2SyKdf61HJ3RvsISX2 MmQ25iTCoHvSu3ha64c5WgBuxTjKsmTKi8eYJIyImMexhapzi/Vw1+KtxjZSkySOVCBv l5fLzxwmA11lG2RJPFuBu5MYku1wpz4pmWHAaEXiScWFP3Q2WrgyQKiQh32dnazXevHL 7pTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ecipNhGo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/77] target/microblaze: Fix width of MSR Date: Tue, 25 Aug 2020 13:58:47 -0700 Message-Id: <20200825205950.730499-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The machine status register is only 32-bits wide. Do not use a 64-bit type to represent it. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 38 ++++++++++++----------------------- 4 files changed, 17 insertions(+), 29 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f4c3c09b09..019e5dfa26 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -237,7 +237,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint32_t pc; - uint64_t msr; + uint32_t msr; uint64_t ear; uint64_t esr; uint64_t fsr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b95617a81a..af79091fd2 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%x msr=%" PRIx64 " %x iflags=%x\n", + "interrupt at pc=%x msr=%x %x iflags=%x\n", env->pc, env->msr, t, env->iflags); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); @@ -239,7 +239,7 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & D_FLAG)); t = (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, - "break at pc=%x msr=%" PRIx64 " %x iflags=%x\n", + "break at pc=%x msr=%x %x iflags=%x\n", env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index fdf706a723..a7f6cb71f1 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 72783c1d8a..0e71e7ed01 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,7 +56,7 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; -static TCGv_i64 cpu_msr; +static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i64 cpu_esr; static TCGv_i64 cpu_fsr; @@ -152,8 +152,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_msr); - tcg_gen_shri_i32(d, d, 31); + tcg_gen_shri_i32(d, cpu_msr, 31); } /* @@ -162,12 +161,9 @@ static void read_carry(DisasContext *dc, TCGv_i32 d) */ static void write_carry(DisasContext *dc, TCGv_i32 v) { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(t0, v); /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1); - tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1); - tcg_temp_free_i64(t0); + tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1); + tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1); } static void write_carryi(DisasContext *dc, bool carry) @@ -437,21 +433,14 @@ static void dec_xor(DisasContext *dc) static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_msr); + tcg_gen_mov_i32(d, cpu_msr); } static inline void msr_write(DisasContext *dc, TCGv_i32 v) { - TCGv_i64 t; - - t = tcg_temp_new_i64(); dc->cpustate_changed = 1; - /* PVR bit is not writable. */ - tcg_gen_extu_i32_i64(t, v); - tcg_gen_andi_i64(t, t, ~MSR_PVR); - tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR); - tcg_gen_or_i64(cpu_msr, cpu_msr, t); - tcg_temp_free_i64(t); + /* PVR bit is not writable, and is never set. */ + tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR); } static void dec_msr(DisasContext *dc) @@ -773,8 +762,7 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_extrl_i64_i32(t0, cpu_msr); - tcg_gen_andi_i32(t0, t0, MSR_CC); + tcg_gen_andi_i32(t0, cpu_msr, MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); @@ -1326,7 +1314,7 @@ static inline void do_rti(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_ori_i32(t1, t1, MSR_IE); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1344,7 +1332,7 @@ static inline void do_rtb(DisasContext *dc) TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_andi_i32(t1, t1, ~MSR_BIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1363,7 +1351,7 @@ static inline void do_rte(DisasContext *dc) t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_ori_i32(t1, t1, MSR_EE); tcg_gen_andi_i32(t1, t1, ~MSR_EIP); tcg_gen_shri_i32(t0, t1, 1); @@ -1809,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_fprintf(f, "rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, @@ -1874,7 +1862,7 @@ void mb_tcg_init(void) cpu_pc = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_ear = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = From patchwork Tue Aug 25 20:58:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248279 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp3360ejn; Tue, 25 Aug 2020 14:11:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyL7B4sUX8u24EGozJIuYcu6oOSv/OGiOBzxLmExUtArNl0AmbilemmdBaJQO1821o6gNEo X-Received: by 2002:a25:d102:: with SMTP id i2mr17785127ybg.398.1598389888279; Tue, 25 Aug 2020 14:11:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389888; cv=none; d=google.com; s=arc-20160816; b=KxG8CqJXo+B0t8DIovzzsA9aeXGD/TsWxsri4GsSFKf9Uj0hO0EiMBc5fRnliezdOF C/diuM5p2sKQipy65/t9U4BHc9ewj18SIu4EMym8IF06LRfoZXBsm1GZQV9PMwENLaeO 0Qw0TxEkT0V/GLSTzx0GXEB3d7ZgUU1eso88leT6LbRM2ZSRAj7KBfIn38bpe3oVp3R2 Q/byioA3jQiJJJZpOJs40PPCx6uelEWXO3sK6KDnTeaLKu0diECaH9+eSQXKnmsunbjZ 9WNQz/Btp+tg6zAhZNS6XoB+2/Beo2nZz8F7d81wYdXVtFZU6DYD513q8FlavZ/Zrmdc txgA== ARC-Message-Signature: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/77] target/microblaze: Fix width of ESR Date: Tue, 25 Aug 2020 13:58:48 -0700 Message-Id: <20200825205950.730499-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 16 ++++++++-------- 5 files changed, 12 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 019e5dfa26..aaac0c9a6c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,7 +239,7 @@ struct CPUMBState { uint32_t pc; uint32_t msr; uint64_t ear; - uint64_t esr; + uint32_t esr; uint64_t fsr; uint64_t btr; uint64_t edr; diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index da5e98b784..3de99ea311 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -106,7 +106,7 @@ void cpu_loop(CPUMBState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; default: - fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n", + fprintf(stderr, "Unhandled hw-exception: 0x%x\n", env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index af79091fd2..b2373f6a23 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -144,7 +144,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%x ear=%" PRIx64 " " - "esr=%" PRIx64 " iflags=%x\n", + "esr=%x iflags=%x\n", env->pc, env->ear, env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index a7f6cb71f1..dc2bec0c99 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_log("rmsr=%x resr=%x rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0e71e7ed01..f63aae6de9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,7 +58,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; -static TCGv_i64 cpu_esr; +static TCGv_i32 cpu_esr; static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; @@ -182,7 +182,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -198,7 +198,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -539,7 +539,7 @@ static void dec_msr(DisasContext *dc) tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); break; case SR_ESR: - tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]); + tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); @@ -580,7 +580,7 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr); + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); @@ -1399,7 +1399,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU); + tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; @@ -1797,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, @@ -1866,7 +1866,7 @@ void mb_tcg_init(void) cpu_ear = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); cpu_fsr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr = From patchwork Tue Aug 25 20:58:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248282 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp3797ejn; Tue, 25 Aug 2020 14:12:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7K/++uXRt0zN3t4LJAniVD25TuWxyPuQjNMio0vb1J3NbjDXFvuC6cupKIyWMzKHT6PiA X-Received: by 2002:a25:2182:: with SMTP id h124mr17209016ybh.336.1598389945513; Tue, 25 Aug 2020 14:12:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389945; cv=none; d=google.com; s=arc-20160816; b=vugaQ699dFWwHMWjc/ZP0lbHZ5TidMU8FBEUGVH27qRAHGz1Ipc/iKu1Z8H+j8CF5z rywSpx+l9vqSjFE+1JZXFguPG23ps6Mvyry5ESZJsbvgZyZil42Oaz25i4/8w1lrUn8O lYCvbPak5spPctURwxfjGRaqwrsqQWBp6+w8kE4ypR7/naR8zMei4EqBBstSC3QDXEZz xq4m11Lo11pE1eJDAUX2et/k/Appx8GAW8Nz4Yaia1avdb0UlJsyZJjopoIgpXPwp01Y 6GynR87AHx9S0d1xYNT3fZGaeqZxm2ULjQ9TBfs3tX9e68nuFx6U8CPkGIH+5SnCKmLe 5inA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rMh4Sqcir06bVXs74gHMdeUNg4a+HHCVID7KGWDrg3A=; b=e/m3hsLiRL9teFHg6AxsDS8UenctoG5oTGK2WmNBOxgof/OSzd71vJwA+rISyzYbOu lSd+UkPmBbGYEnOj/9KmB+FFhSu7y4TZULtoGSMBM0pBhjd6tTQ6OjwVVPbCDZ4njPBp 0jRsabJ4/TTL3/YGi8reVQvJreLRA4944HSyBfLhHTBkC960Dj1LkjYtfKF3/p8fiodA gOZBImbFPdbLZbL0HxhFLpwRvITkMh/g5pIY6UmZyfPv6/RUDFyYjPMwtuZ44Fn3aPXk wBX5pWfEjRembgFG7LChjD7I1tZkx1sHChLGzGAB81TxzM+sM80+FRVQeSgVWS324XS2 BRTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pLeGcz39; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 16/77] target/microblaze: Fix width of FSR Date: Tue, 25 Aug 2020 13:58:49 -0700 Message-Id: <20200825205950.730499-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_fsr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index aaac0c9a6c..34177f9b28 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -240,7 +240,7 @@ struct CPUMBState { uint32_t msr; uint64_t ear; uint32_t esr; - uint64_t fsr; + uint32_t fsr; uint64_t btr; uint64_t edr; float_status fp_status; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f63aae6de9..3fc2feda3d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; @@ -542,7 +541,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: - tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); @@ -583,7 +583,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); @@ -1798,7 +1799,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " + "debug=%x imm=%x iflags=%x fsr=%x " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, @@ -1867,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_fsr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr = From patchwork Tue Aug 25 20:58:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248283 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp4207ejn; Tue, 25 Aug 2020 14:13:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRrx+AxIi0yY8d4aCcOtX8Rk3krBz+DLCREh45/M4742A5eC35qnNxFX2e7NL11XlAILX2 X-Received: by 2002:a25:7453:: with SMTP id p80mr16994870ybc.441.1598389997819; Tue, 25 Aug 2020 14:13:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389997; cv=none; d=google.com; s=arc-20160816; b=zwNQsyCsM5dRhUeQ3AITXi1tgGib3ss3v/uN7I7Mmr9wfC1amuNew/xzyv/zudQHfm +gXtLhQ13YzdSfWf5os1VhMV6t5qIye8pxkyNX1+YdXwi3I4UWNual3dFE5tA2Xulie1 /tHNUhv2MYvo/TYE6tH7WpPjbbnFSGrwuMuieWMXOrQrjI9J233Nhs407zxCAGKn09AM +n7x3EgARlWoF3cjKPcUfvqWKJw/6hzudzjLrmqcroaIaP21LTk7FCZV2Nct5pxNJwSp kfYacnsKXwW5ThoQysGXjnUsksvyptodcrB9CPMmAbsEoKTo4tJP+3eGkNC2qWIY4m78 tpuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AF5wUNj1rfWDk74W8hKW9/y1FLbHGsX9t+9rRKYsDAE=; b=CPXJHYLUCw2mfZELqPNq5EaMCyXhJwG2CSQKkMfXJ66eZ/yYnC0Mk157RB3bxvpNrJ WOYHzeTpMPn16WXbfKO8qiTChRTlb0Gw2g4mS0O9gRiTLx7xE2Tiq1gEZN8xrchvqTAH rOrDPG6yFnj4i6kwujs0+u4T/NAn4W1idS86EVhB54Goy2Wza2c9isGSZ97b0k/x9dht Apsvh4wnDxFxLOnLxg6UOJPyFXLdLaX31oKyi7mnksXnbSGLKM2vMloJ+gtOm7zS1XNK acYP80ucj7YWhj2EXY+22ioGZmkMAWyZxYWl5xy3wvjrA3uAbj/d6CJbEUU3+DBzueGD CqRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JoxIZUUZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/77] target/microblaze: Fix width of BTR Date: Tue, 25 Aug 2020 13:58:50 -0700 Message-Id: <20200825205950.730499-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The branch target register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_btr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 12 +++++------- 2 files changed, 6 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 34177f9b28..72f068a5fd 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,7 +241,7 @@ struct CPUMBState { uint64_t ear; uint32_t esr; uint32_t fsr; - uint64_t btr; + uint32_t btr; uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3fc2feda3d..a2bba0fe61 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -545,7 +544,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); @@ -587,7 +587,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); @@ -1799,8 +1800,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%x " - "rbtr=%" PRIx64 "\n", + "debug=%x imm=%x iflags=%x fsr=%x rbtr=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, env->btr); @@ -1868,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_btr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } From patchwork Tue Aug 25 20:58:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248285 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp4824ejn; Tue, 25 Aug 2020 14:14:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzxRKOdQu4nj9IUNZoYcwncyTHz76KmtjsN9Xr6RdhTdCGqbsDnPlVaWGfP2rLfJSZ1O1Hz X-Received: by 2002:a5b:411:: with SMTP id m17mr17073620ybp.492.1598390078569; Tue, 25 Aug 2020 14:14:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390078; cv=none; d=google.com; s=arc-20160816; b=nZfpv1ECM/iODRO5x4o/WWnv8+JemHtCnr/n681OUSY3Jwcm62Ix172Gf/v2O6UYlX 9liafZ2SVgXVOcnCXsYRH1tg0HlOq4CWBL5hs9V+4dhyEq2LTeLDxOMITUt/Kgyrudyk mslDLfJnbpPxz9zkunFqK6yfoMuO/Des7W+jY/16eHuSriyktnBlpVUdXcIAYFclTeE1 fJs/1Hu7mI5zI8udwIEIzqUbRNF0jFLqs7yZqMjkX3wzOMzkZSIIoG3a3GpthZEgprCa 2aux1lYm3LDkSEhFgkLRb5tJdbSswY28Ykpb90lljJdSAZJNwVFUh7eC/8hVA8C32Kt/ soTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZaIdcAkOSjEufmU2G8vkTG/fvmG7Z2otY+gyeoJlJtY=; b=N3H3xSk4yhXOe4aKlcXPOajRuI6xANRoB8r2k8UNWrOQ6+6Jt46RquZIe0om/3BVTu T+dcjkWpnI7TxeCbkeI2msXsHGFUkTydDMHZlRzG+Q3XR8eYCy3Lv6zvSuGneCHydeLi LvFWQttaXecBHVtxAPQuAYETSkKHXVfyCaASSWjoYC5RcxJi0///MYgS/psPZ8vHU97z /w4j7uzYhqlh9hCrl78m9i2/UIfwNf4lar5hanJLTnFJDSXC3+ACtEB2PydK4dlmkzPa z7L+emOMNvmCLuxxni8fc6pNVWnc27fKvyEyrwTOGvjZM3243+orRDURrCcVGBLYMEbc RsTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QCFFwNNo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 18/77] target/microblaze: Fix width of EDR Date: Tue, 25 Aug 2020 13:58:51 -0700 Message-Id: <20200825205950.730499-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception data register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_edr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 72f068a5fd..b88acba12b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint32_t esr; uint32_t fsr; uint32_t btr; - uint64_t edr; + uint32_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a2bba0fe61..a862ac4055 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 cpu_btarget; @@ -548,7 +547,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: - tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, edr)); break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], @@ -591,7 +591,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, edr)); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -1818,7 +1819,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } /* Registers that aren't modeled are reported as 0 */ - qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " + qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " "rtlblo=0 rtlbhi=0\n", env->edr); qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { @@ -1868,8 +1869,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_edr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Tue Aug 25 20:58:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248280 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp3481ejn; Tue, 25 Aug 2020 14:11:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwhPVlh+NNOGB5UYkvR8zBjEaB2cdjv0AkSb4B1SRLpZwkN4AkHZ0PAijFiDk/jvCxjlTzW X-Received: by 2002:a67:e28c:: with SMTP id g12mr6773488vsf.31.1598389904805; Tue, 25 Aug 2020 14:11:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389904; cv=none; d=google.com; s=arc-20160816; b=tA7kc6GTJoJHKVBYF/CDhGDUnNuuPcjheb3mBvMdmojFdN0iN5L9e3Ber7YKwfIo4e ewXUNrAKpWwep/uXUM7CA3sz6fsJTYU3zdn/62ANjFgZdlQtzyCs40FssYzaKeOluCLu Gwhf6zhIOdkRYpw/8tDaS1UDqbGDjZ86jhl/fpT1Vi+1MJMdXxTRI0mH2GBfgqPJlgrT G+NVXdktVYyG50apjfKBTBwhmD/vJ7mFXFtzBkUt+xuGZiqKIRQI7OcU/oxxIHVLAkXX Ne9s6RueEQbZEnWLGyX5hPVyyjhy1/IC2DZQ55Tm+x+s/6ju5Xuw150X0pATaACKs4xD fllA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HaAnpocjYbBqDikM80fgZOEo5h0cDqsU8in/f2nqeSk=; b=P+U1EBDI2jracVaLrSx02R+g4SBxV0cFnN83djLOKydmxysBk7IbxMCPg9UBHCqarv se6ei3O0/LgTDCBcjvhkJRLCGZUfoG9pll/de5aYBkWA2L2dL8bL7nIUw7zC2gXkAOT8 PkA8E5bLzr3+duCTVbT6XwJGUKxYUvF6HyW05kRQ4xRO3KukmgNsEePm5Yeleah0k+SV lmOX83mnQ53l8GmzJIVnQOIFuxKmxZFLdX3qrlCY2RbpQETKT95LQGOC5C06VpR5rsqU be/ucQatbh4CDMIaf32jdiIqIkCkCyt1eWksZ73DJDDHCr1BHAmOoCAfU3Z5idOfOvmv VYiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k9kjF86s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since cpu_ear is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a862ac4055..f5ca25cead 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,6 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -533,7 +532,12 @@ static void dec_msr(DisasContext *dc) msr_write(dc, cpu_R[dc->ra]); break; case SR_EAR: - tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); + tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_temp_free_i64(t64); + } break; case SR_ESR: tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); @@ -573,10 +577,15 @@ static void dec_msr(DisasContext *dc) msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: - if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); - } else { - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + if (extended) { + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); + } else { + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); + } + tcg_temp_free_i64(t64); } break; case SR_ESR: @@ -1865,8 +1874,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_ear = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); } From patchwork Tue Aug 25 20:58:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248284 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp4790ejn; Tue, 25 Aug 2020 14:14:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyXmSD22zeXb9vOnVBDBKnQMFIRwuiwgIj+2adKX2wF7sPxONFbfuoOJTVh7UoJjKLOA6Ny X-Received: by 2002:a25:e692:: with SMTP id d140mr17289908ybh.159.1598390074034; Tue, 25 Aug 2020 14:14:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390074; cv=none; d=google.com; s=arc-20160816; b=fUveXgdMXmwuuTSx0JdRDkzn8RRWYTZ9ScuYNIqZSH8G1v8rzThOsyzHwuoOuUuhPs 5Yd587RYNqlZrOF9uMS83SbAwQpu90OtJbHWcz4r1u7WNdVqhFMv9UogcywViDKrlzUa bttvRdLwLF6hdj9/7LQhuuaTPsvElmxiH7Mz/VbBgmFIjxGWU5TNRjCs9hQn6yLZCobH OsDCHuo4ltfIOJiuC065a7cefeeMZxaTy67ciFoen3pmClWvThmHSGC3G71XGfXzELSD m7TECtCyo0WzwQ2vS8+iceATRQPCeP/70M+XwGiNI25TOiWDEgKniB2WoJg7O+l+gmyW pAdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Z4AmITk5w2LQx1h3BHbpZiArbCayMAaSAdvlTGNWCzo=; b=BMVo8t3fIbv+pY84d1tqUieDXB6samfeq+QQD0+N0hkH0Sn7BFYUn0vzTS9nCfPmrR TIsCWNftqWLx5o0IWFtPCVkVe424TGL6t1GByYkK3EVR+355d/S5QCI3FssNQQFJPanm V/YN+AJ5y3mDYK80ojcZqVi58bgWdVejyEyH0j1MPHMOVzTewJZHWr1KU/F3Mjxov5LJ zYJeBKB1SYRbDsIJKM0B51acw4QNAEBr0Jpt196JyAXr/AcSU3jRHP1FaFkBEDEmABrP ZDCQc0IfvyeQUzmnv9Esf5osJsybMfiOtfRwpDMNAOtZoW4MyPDZk6gtYfiugXsEmEqT H+Ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yNqdK3Wk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 20/77] target/microblaze: Tidy raising of exceptions Date: Tue, 25 Aug 2020 13:58:53 -0700 Message-Id: <20200825205950.730499-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out gen_raise_exception which does no cpu state sync. Rename t_gen_raise_exception to gen_raise_exception_sync to emphasize that it does a sync. Create gen_raise_hw_excp to simplify code raising EXCP_HW_EXCP. Since there is now only one use of cpu_esr, perform a store instead and remove the TCG variable. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 62 +++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f5ca25cead..9a00a78b8a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,6 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i32 cpu_esr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 cpu_btarget; @@ -114,17 +113,31 @@ static inline void t_sync_flags(DisasContext *dc) } } -static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) +static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); - t_sync_flags(dc); - tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp = DISAS_UPDATE; } +static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) +{ + t_sync_flags(dc); + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_raise_exception(dc, index); +} + +static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) +{ + TCGv_i32 tmp = tcg_const_i32(esr_ec); + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr)); + tcg_temp_free_i32(tmp); + + gen_raise_exception_sync(dc, EXCP_HW_EXCP); +} + static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { #ifndef CONFIG_USER_ONLY @@ -178,8 +191,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); } return cond; } @@ -194,8 +206,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user = cond && mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); } return cond_user; } @@ -540,7 +551,8 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, esr)); break; case SR_FSR: tcg_gen_st_i32(cpu_R[dc->ra], @@ -589,7 +601,8 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, esr)); break; case SR_FSR: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -1258,8 +1271,7 @@ static void dec_br(DisasContext *dc) /* mbar IMM & 16 decodes to sleep. */ if (mbar_imm & 16) { - TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT); - TCGv_i32 tmp_1 = tcg_const_i32(1); + TCGv_i32 tmp_1; LOG_DIS("sleep\n"); @@ -1269,13 +1281,16 @@ static void dec_br(DisasContext *dc) } t_sync_flags(dc); + + tmp_1 = tcg_const_i32(1); tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); - gen_helper_raise_exception(cpu_env, tmp_hlt); - tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); + + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); + + gen_raise_exception(dc, EXCP_HLT); return; } /* Break the TB. */ @@ -1300,14 +1315,15 @@ static void dec_br(DisasContext *dc) tcg_gen_movi_i32(env_btaken, 1); tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { - if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) - t_gen_raise_exception(dc, EXCP_BREAK); + if (!(dc->tb_flags & IMM_FLAG) && + (dc->imm == 8 || dc->imm == 0x18)) { + gen_raise_exception_sync(dc, EXCP_BREAK); + } if (dc->imm == 0) { if (trap_userspace(dc, true)) { return; } - - t_gen_raise_exception(dc, EXCP_DEBUG); + gen_raise_exception_sync(dc, EXCP_DEBUG); } } } else { @@ -1411,8 +1427,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_FPU); } return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; } @@ -1668,8 +1683,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) #endif if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { - t_gen_raise_exception(dc, EXCP_DEBUG); - dc->is_jmp = DISAS_UPDATE; + gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that @@ -1874,8 +1888,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_esr = - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Tue Aug 25 20:58:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248288 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp5611ejn; Tue, 25 Aug 2020 14:16:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyIj/G9Ru0QcUsulkDIr4TK44izLYm8RJJS1sLGur+qmZTd+eWMZ4Pzeh5GWXMWN3P9b/Ab X-Received: by 2002:a25:d10d:: with SMTP id i13mr15940394ybg.158.1598390182709; Tue, 25 Aug 2020 14:16:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390182; cv=none; d=google.com; s=arc-20160816; b=htFaHjbz4wYbXmwjyJGi+mzZzQXEvkXtrFvy3VqofjBnJQWRFxBA/2SHqJaBcLxufm bHm6YYKHvxdyOmzMsG3dXpW08Ifpa0yGexpkkXrN/4ILl9FmY2GkFaJZZcNfSQrhvCzq CLG2LzQBf4uZfKewAgwpnuZNNdV9C1+zxXIG4667jrh1vxVTmJiBb7awTR/kgthuoKIE zdZkzansZ7B5cu184Pecf+Xv58+pRs5oF7OaU/+si/WiAsQXdu8KzaxVWn8uMuB9BCjy cKSOsoQQMLy/J2NYjn02D21EMOQt+YpWqbwVNt/pIrI+GG04LfEfsEnRPjlNzikHQbGW hSfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=45kd/bFobWQBgRWzCCV4KKe4PH1pZqfnSM8e41v0zaE=; b=i+BNxDH2Dpcz50v4NawNujDtjcqI9AZVmY5uJdbfrWG9Ta2qGtJmfaGbg5BC1kQOf2 BZkAtlvcGpu1ESgbN1A2wdHu9AZDl94iClIOuTgGpmn8IY9hexlpDbIFWpa5enOLqc49 1wpWHmUhph5btvd+D8QHzJQ9UeK5HG7f3rTWYVVnRjq2+ZSJXABlDiqN5aiQ5jRWmJdG M2Q9jyvTMAGXDwtA/+b261ewIufM+Cs84/WqAfG4XuTMHe4o40FeMtv6xK7D0KdJ/PjD +FHiTW6pzEIThpZlYfOUy54aKNWC8k/p6Vn9qly4KIDkxHYjr4bhGiiiE8UaHQBFIMgX aARA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fQC+I+dV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 21/77] target/microblaze: Mark raise_exception as noreturn Date: Tue, 25 Aug 2020 13:58:54 -0700 Message-Id: <20200825205950.730499-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will allow tcg to remove any dead code that might follow an exception. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 2f8bdea22b..820711366d 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,4 +1,4 @@ -DEF_HELPER_2(raise_exception, void, env, i32) +DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_1(debug, void, env) DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) From patchwork Tue Aug 25 20:58:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248287 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp5169ejn; Tue, 25 Aug 2020 14:15:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeFo40hdK+9QsFWM351Ht0vY1w4cHPQ0ZlUuI5V9K0rBtI0fZfOuVswByHJGdEyJiTmBLm X-Received: by 2002:a25:b29c:: with SMTP id k28mr17123528ybj.501.1598390126290; Tue, 25 Aug 2020 14:15:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390126; cv=none; d=google.com; s=arc-20160816; b=vjVZPkV1GhDU8KF//CkXM1hxCxjG8FxgKTuVwAek7z5ltRXsmuDoicKBG9dh0rixDP N7UbVmPvOM1n3uN9b8uIk9nixoyGnm3/Lg/jucsLvdlZCfzjyCCEtAzQalaO1vjqKs+C jPvN82j1ETYiO4UMbJ3oGZ2ntq8GAiWKWTeolW6G7cCiGSd6kKuw3JQJxEkjSjhj1M8Z AgkljbH2D0UAB1SGWAimoIhhHqViEKCF94JXbBq/cShSs7A+z8xJp+mVTiPcv8c+h7rz YOXth9B3K53CSnbCIexjmqcfuaBfYkU8VzlWO1drg1TU1IZK/0CFSvvqq+Wl8XVPAZuw DTPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lL2TV9fvxAuHwerQiahLV44CD3Djc67HSq2e2+fPjhU=; b=y3mA0NZB4lIVfJVAKkMuMTesOHMEHxhpz0UJ/iXa1lhRIpCCKj7CjCJPRqKyp2YcMK jm+lEWEXtCYbpAfEMP8sJq6AEyJfoF+FXjm+loTh1mjf+mkrhK6/14fK4CzXrPtlvg+r edPF562AjlzHiMB3Cd4fRkGyfb9AxPJmkhz9ekmYeMS587foRkwkcMzun+Brxt41g4oE cylC5FLshtEetQ2Dqm36VnBz+mPXOd9vHVgnnscfy26lJ9MJEvxv297HlN9s3/R2ml8w xIqYNGU1et6a27fsIk8XLJ4KYTrEXt+tYihrUn1S33UMNNmIqFzSXTMhV8DVYGWhWqCM DNIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vobbvPS8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 22/77] target/microblaze: Remove helper_debug and env->debug Date: Tue, 25 Aug 2020 13:58:55 -0700 Message-Id: <20200825205950.730499-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not used, and seems redundant with -d cpu. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 - target/microblaze/helper.h | 1 - target/microblaze/op_helper.c | 23 ----------------------- target/microblaze/translate.c | 16 ++-------------- 4 files changed, 2 insertions(+), 39 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b88acba12b..7708c9a3d3 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -229,7 +229,6 @@ typedef struct CPUMBState CPUMBState; #define STREAM_NONBLOCK (1 << 4) struct CPUMBState { - uint32_t debug; uint32_t btaken; uint32_t btarget; uint32_t bimm; diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 820711366d..9309142f8d 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_1(debug, void, env) DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) DEF_HELPER_2(cmpu, i32, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index dc2bec0c99..d79202c3f8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -71,29 +71,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -void helper_debug(CPUMBState *env) -{ - int i; - - qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%x resr=%x rear=%" PRIx64 " " - "debug[%x] imm=%x iflags=%x\n", - env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags); - qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", - env->btaken, env->btarget, - (env->msr & MSR_UM) ? "user" : "kernel", - (env->msr & MSR_UMS) ? "user" : "kernel", - (bool)(env->msr & MSR_EIP), - (bool)(env->msr & MSR_IE)); - for (i = 0; i < 32; i++) { - qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); - if ((i + 1) % 4 == 0) - qemu_log("\n"); - } - qemu_log("\n\n"); -} - static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) { uint32_t cout = 0; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9a00a78b8a..ecfa6b86a4 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -53,7 +53,6 @@ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ -static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; @@ -1675,13 +1674,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) tcg_gen_insn_start(dc->pc); num_insns++; -#if SIM_COMPAT - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_debug(); - } -#endif - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in @@ -1824,10 +1816,9 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%x rbtr=%x\n", + "imm=%x iflags=%x fsr=%x rbtr=%x\n", env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags, env->fsr, - env->btr); + env->imm, env->iflags, env->fsr, env->btr); qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", @@ -1857,9 +1848,6 @@ void mb_tcg_init(void) { int i; - env_debug = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, debug), - "debug0"); env_iflags = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, iflags), "iflags"); From patchwork Tue Aug 25 20:58:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248291 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp6119ejn; Tue, 25 Aug 2020 14:17:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQdZ/R4nYuXDBIMKBtM7H+quEh775NI4HMe7zrMkDmqUsVJUQs48EX3p/MHixJ7Xq/xAHx X-Received: by 2002:a25:2fcc:: with SMTP id v195mr16454359ybv.119.1598390247098; Tue, 25 Aug 2020 14:17:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390247; cv=none; d=google.com; s=arc-20160816; b=C/pP+GtrlWNTKCNMFPNJR4IrPvWTohIUj9Ivi9oT+eCw/NcUzKK+spLYHIVe8kPCMv inNVxoG2maKb2btt3vcy9yAtysYI9oF3Ji0+DkYdFrXJXGzMOc0NHdT55o+i36Y8aF+W HMs0/qDjN4v/G0FpAi7EgCNVf3f1TOweu5MUlQZF/l0qsdJCx5RmTGFdxxuQCXgzd83+ 7N+ssNbSP4XzeplqocYAC9n9LYqfssqDpq6aPmk5qfU49dLjok0XGY0AXJ+jheyme/zq LGXhCJq2iljkBA4E/kT4irJK3I036VA9i7NlDqRKCPFCObc3LqntpKyzltBKw0DH5vlS MYMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Xvkn3g2mPXtRTX9S6LWMZSG9zfZ6Smrj8vu/NEKgNeA=; b=mM2S0iwLhl7VVH1flefvORwdplmVyD1P8lPDq9mn7lPLSzSARFdhgqCaP48Y52GHym jP2g7cI9NHetm7wZSMjdLECMbd9Iyh/tav7K7p703G3SXcDTGNr7fdLFuFD7g+I0jNdR gsSlAlItTDQIlu4T6nGt2GLMhkHSb4/su/pXUJ+DXwX1YCaefCctY9IRP+DYwIODeFxp GZgGsX6kqigRr7Z2IfRXe4dJJii1DqToTs682qC1+bnz8zS049MsiBoDUbIyqTmGdJIU 3l9jAFep9L2ieUY1OeB64po82K9kT1HMZspIBsjqsRNjOqWZpZahHVwI50v5Rl7e9LZl zVmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U07UN401; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 23/77] target/microblaze: Rename env_* tcg variables to cpu_* Date: Tue, 25 Aug 2020 13:58:56 -0700 Message-Id: <20200825205950.730499-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is cpu_imm, cpu_btaken, cpu_iflags, cpu_res_addr and cpu_res_val. It is standard for these file-scope globals to begin with cpu_*. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 54 +++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ecfa6b86a4..9aa63ddcc5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,12 +56,12 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i32 env_imm; -static TCGv_i32 env_btaken; +static TCGv_i32 cpu_imm; +static TCGv_i32 cpu_btaken; static TCGv_i32 cpu_btarget; -static TCGv_i32 env_iflags; -static TCGv env_res_addr; -static TCGv_i32 env_res_val; +static TCGv_i32 cpu_iflags; +static TCGv cpu_res_addr; +static TCGv_i32 cpu_res_val; #include "exec/gen-icount.h" @@ -107,7 +107,7 @@ static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ if (dc->tb_flags != dc->synced_flags) { - tcg_gen_movi_i32(env_iflags, dc->tb_flags); + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); dc->synced_flags = dc->tb_flags; } } @@ -222,10 +222,10 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_i32(env_imm, env_imm, dc->imm); + tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm); else - tcg_gen_movi_i32(env_imm, (int32_t)((int16_t)dc->imm)); - return &env_imm; + tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm)); + return &cpu_imm; } else return &cpu_R[dc->rb]; } @@ -859,7 +859,7 @@ static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); } dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); @@ -869,7 +869,7 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { LOG_DIS("imm %x\n", dc->imm << 16); - tcg_gen_movi_i32(env_imm, (dc->imm << 16)); + tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; } @@ -1040,8 +1040,8 @@ static void dec_load(DisasContext *dc) } if (ex) { - tcg_gen_mov_tl(env_res_addr, addr); - tcg_gen_mov_i32(env_res_val, v); + tcg_gen_mov_tl(cpu_res_addr, addr); + tcg_gen_mov_i32(cpu_res_val, v); } if (dc->rd) { tcg_gen_mov_i32(cpu_R[dc->rd], v); @@ -1103,7 +1103,7 @@ static void dec_store(DisasContext *dc) write_carryi(dc, 1); swx_skip = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, addr, swx_skip); + tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); /* * Compare the value loaded at lwx with current contents of @@ -1111,11 +1111,11 @@ static void dec_store(DisasContext *dc) */ tval = tcg_temp_new_i32(); - tcg_gen_atomic_cmpxchg_i32(tval, addr, env_res_val, + tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val, cpu_R[dc->rd], mem_index, mop); - tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip); + tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); write_carryi(dc, 0); tcg_temp_free_i32(tval); } @@ -1204,7 +1204,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) TCGv_i32 zero = tcg_const_i32(0); tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, - env_btaken, zero, + cpu_btaken, zero, pc_true, pc_false); tcg_temp_free_i32(zero); @@ -1245,7 +1245,7 @@ static void dec_bcc(DisasContext *dc) dc->jmp = JMP_INDIRECT; tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } - eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); + eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } static void dec_br(DisasContext *dc) @@ -1311,7 +1311,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_INDIRECT; if (abs) { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && @@ -1330,7 +1330,7 @@ static void dec_br(DisasContext *dc) dc->jmp = JMP_DIRECT; dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); } else { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } } @@ -1419,7 +1419,7 @@ static void dec_rts(DisasContext *dc) LOG_DIS("rts ir=%x\n", dc->ir); dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } @@ -1722,7 +1722,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) TCGLabel *l1 = gen_new_label(); t_sync_flags(dc); /* Conditional jmp. */ - tcg_gen_brcondi_i32(TCG_COND_NE, env_btaken, 0, l1); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); gen_goto_tb(dc, 1, dc->pc); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); @@ -1848,22 +1848,22 @@ void mb_tcg_init(void) { int i; - env_iflags = tcg_global_mem_new_i32(cpu_env, + cpu_iflags = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, iflags), "iflags"); - env_imm = tcg_global_mem_new_i32(cpu_env, + cpu_imm = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); cpu_btarget = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btarget), "btarget"); - env_btaken = tcg_global_mem_new_i32(cpu_env, + cpu_btaken = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btaken), "btaken"); - env_res_addr = tcg_global_mem_new(cpu_env, + cpu_res_addr = tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); - env_res_val = tcg_global_mem_new_i32(cpu_env, + cpu_res_val = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, res_val), "res_val"); for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { From patchwork Tue Aug 25 20:58:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248292 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp6289ejn; Tue, 25 Aug 2020 14:17:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwK1qCC9jz1h4HgEUe5T0L6RRbxJgtsxSw5WJJGlx5sd8Iiff/LXgHgOh9Uz8be9IvFzj2C X-Received: by 2002:a25:4846:: with SMTP id v67mr17529113yba.103.1598390267795; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 24/77] target/microblaze: Tidy mb_tcg_init Date: Tue, 25 Aug 2020 13:58:57 -0700 Message-Id: <20200825205950.730499-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All of the tcg globals can be recorded in the same table. Drop the "r" prefix from "rpc" and "rmsr". Obviates the need for regnames[], which was incorrectly not const. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 62 +++++++++++++++-------------------- 1 file changed, 27 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9aa63ddcc5..e709884f2d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -95,14 +95,6 @@ typedef struct DisasContext { int singlestep_enabled; } DisasContext; -static const char *regnames[] = -{ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", -}; - static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1846,36 +1838,36 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) void mb_tcg_init(void) { - int i; +#define R(X) { &cpu_R[X], offsetof(CPUMBState, regs[X]), "r" #X } +#define SP(X) { &cpu_##X, offsetof(CPUMBState, X), #X } - cpu_iflags = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, iflags), - "iflags"); - cpu_imm = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, imm), - "imm"); - cpu_btarget = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, btarget), - "btarget"); - cpu_btaken = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, btaken), - "btaken"); - cpu_res_addr = tcg_global_mem_new(cpu_env, - offsetof(CPUMBState, res_addr), - "res_addr"); - cpu_res_val = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, res_val), - "res_val"); - for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { - cpu_R[i] = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, regs[i]), - regnames[i]); + static const struct { + TCGv_i32 *var; int ofs; char name[8]; + } i32s[] = { + R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), + R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), + R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), + R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), + + SP(pc), + SP(msr), + SP(imm), + SP(iflags), + SP(btaken), + SP(btarget), + SP(res_val), + }; + +#undef R +#undef SP + + for (int i = 0; i < ARRAY_SIZE(i32s); ++i) { + *i32s[i].var = + tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name); } - cpu_pc = - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); - cpu_msr = - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + cpu_res_addr = + tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, From patchwork Tue Aug 25 20:58:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248299 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp7843ejn; Tue, 25 Aug 2020 14:21:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxCk0SUKtIRhfoyi6j6Qwwn1K52QQYrRrgZ1TvSvKYjr2LcepVNXmbw3QIKyoriT6Wdepu9 X-Received: by 2002:a25:4288:: with SMTP id p130mr16459031yba.288.1598390479839; Tue, 25 Aug 2020 14:21:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390479; cv=none; d=google.com; s=arc-20160816; b=aF+ylk2SoCC8Z/Humz8jgF2Y3MSsVqIjqTWb4z7owcouLopbKiGuB7wXY0glGuvAY1 jGw5z7lS8h6957FDlvLZgqFxPStnh6WzuFb6XiX1Q7U2kbZowTkDawJFnx/Q0eL5e24d tke+Eszy2ZK/HH8us4Vvx1wkqwyRJrXpVGbx10oGShOpAmw2HcMejFoKoi1DNNlhmUWs rYfY6aw+girviuwiTRBVV4Fa+PL4QXZncLNPOVBLgjtsSRymbZU9jpGIOkU0uc/HFQ/A zVpg2sB+pwDkDWYyOpRO2GdpNMxAQYrh0r8glQleXp4iikXAQZh5eDbx0u1hYsKi44t8 thwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tvav2yDgl091Kla7AxGkIifdrAi1yowT9YLtoH5uMlM=; b=FcmifybpVA641DdpJ/iSDUuBKcJIm4N8My7SKrHaBDjcCcSqIm5b+Cus1j8SeFQLNk J8D5DjbvmJo6NCXOc30oGXbroVbfU8N/CY14XZ2As6jb1xP8skoC4/CFlMKFGwwrsU84 7HWu2s5E/JaBBlk4Tx92XLQBF0FZTP9je0oQwmO0OdOSmpjyWP4HUyrcwtpO2UdsqD9b J30LrZr/yMmEYraCkgj1Tpg/CpBzg4EV0L4kdgquc8uUFcAwYQaCbP2DHOm9E0TwYYa7 LAe34LZtVF2N2dNMHyO9yi5Y1skcAWRQGTJ0i5IlBZ0hITLYTB/o8nyZdENVB451CqvT I96g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cUS6GIKG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 25/77] target/microblaze: Split out MSR[C] to its own variable Date: Tue, 25 Aug 2020 13:58:58 -0700 Message-Id: <20200825205950.730499-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Having the MSR[C] bit separate will improve arithmetic that operates on the carry bit. Having mb_cpu_read_msr() populate MSR[CC] will prevent the carry copy not matching the carry bit. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 19 +++++++- linux-user/elfload.c | 2 +- target/microblaze/cpu.c | 4 +- target/microblaze/gdbstub.c | 4 +- target/microblaze/helper.c | 58 +++++++++++----------- target/microblaze/translate.c | 91 +++++++++++------------------------ 6 files changed, 82 insertions(+), 96 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7708c9a3d3..7066878ac7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -236,7 +236,8 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint32_t pc; - uint32_t msr; + uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ + uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ uint64_t ear; uint32_t esr; uint32_t fsr; @@ -327,6 +328,22 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +static inline uint32_t mb_cpu_read_msr(const CPUMBState *env) +{ + /* Replicate MSR[C] to MSR[CC]. */ + return env->msr | (env->msr_c * (MSR_C | MSR_CC)); +} + +static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) +{ + env->msr_c = (val >> 2) & 1; + /* + * Clear both MSR[C] and MSR[CC] from the saved copy. + * MSR_PVR is not writable and is always clear. + */ + env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR); +} + void mb_tcg_init(void); /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero diff --git a/linux-user/elfload.c b/linux-user/elfload.c index bbfb665321..98af4fe7e0 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1033,7 +1033,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env } (*regs)[pos++] = tswapreg(env->pc); - (*regs)[pos++] = tswapreg(env->msr); + (*regs)[pos++] = tswapreg(mb_cpu_read_msr(env)); (*regs)[pos++] = 0; (*regs)[pos++] = tswapreg(env->ear); (*regs)[pos++] = 0; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 0eac068570..1eabf5cc3f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -121,9 +121,9 @@ static void mb_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ - env->msr = MSR_EE | MSR_IE | MSR_VM | MSR_UM; + mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); #else - env->msr = 0; + mb_cpu_write_msr(env, 0); mmu_init(&env->mmu); env->mmu.c_mmu = 3; env->mmu.c_mmu_tlb_access = 3; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 9cba9d2215..08d6a0e807 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -62,7 +62,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pc; break; case GDB_MSR: - val = env->msr; + val = mb_cpu_read_msr(env); break; case GDB_EAR: val = env->ear; @@ -118,7 +118,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pc = tmp; break; case GDB_MSR: - env->msr = tmp; + mb_cpu_write_msr(env, tmp); break; case GDB_EAR: env->ear = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b2373f6a23..9a95456401 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -112,12 +112,11 @@ void mb_cpu_do_interrupt(CPUState *cs) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; - uint32_t t; + uint32_t t, msr = mb_cpu_read_msr(env); /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); -/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; switch (cs->exception_index) { case EXCP_HW_EXCP: @@ -136,11 +135,12 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->msr & (MSR_VM | MSR_UM)) << 1; - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |= t; + t = (msr & (MSR_VM | MSR_UM)) << 1; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; /* Exception in progress. */ - env->msr |= MSR_EIP; + msr |= MSR_EIP; + mb_cpu_write_msr(env, msr); qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%x ear=%" PRIx64 " " @@ -178,11 +178,12 @@ void mb_cpu_do_interrupt(CPUState *cs) } /* Disable the MMU. */ - t = (env->msr & (MSR_VM | MSR_UM)) << 1; - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |= t; + t = (msr & (MSR_VM | MSR_UM)) << 1; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; /* Exception in progress. */ - env->msr |= MSR_EIP; + msr |= MSR_EIP; + mb_cpu_write_msr(env, msr); qemu_log_mask(CPU_LOG_INT, "exception at pc=%x ear=%" PRIx64 " iflags=%x\n", @@ -193,11 +194,11 @@ void mb_cpu_do_interrupt(CPUState *cs) break; case EXCP_IRQ: - assert(!(env->msr & (MSR_EIP | MSR_BIP))); - assert(env->msr & MSR_IE); + assert(!(msr & (MSR_EIP | MSR_BIP))); + assert(msr & MSR_IE); assert(!(env->iflags & D_FLAG)); - t = (env->msr & (MSR_VM | MSR_UM)) << 1; + t = (msr & (MSR_VM | MSR_UM)) << 1; #if 0 #include "disas/disas.h" @@ -212,21 +213,20 @@ void mb_cpu_do_interrupt(CPUState *cs) && (!strcmp("netif_rx", sym) || !strcmp("process_backlog", sym))) { - qemu_log( - "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", - env->pc, env->msr, t, env->iflags, - sym); + qemu_log("interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n", + env->pc, msr, t, env->iflags, sym); log_cpu_state(cs, 0); } } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=%x msr=%x %x iflags=%x\n", - env->pc, env->msr, t, env->iflags); + "interrupt at pc=%x msr=%x %x iflags=%x\n", + env->pc, msr, t, env->iflags); - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); - env->msr |= t; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); + msr |= t; + mb_cpu_write_msr(env, msr); env->regs[14] = env->pc; env->pc = cpu->cfg.base_vectors + 0x10; @@ -237,20 +237,22 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); - t = (env->msr & (MSR_VM | MSR_UM)) << 1; + t = (msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=%x msr=%x %x iflags=%x\n", - env->pc, env->msr, t, env->iflags); + env->pc, msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |= t; - env->msr |= MSR_BIP; + msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |= t; + msr |= MSR_BIP; if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->pc; - env->msr |= MSR_BIP; + msr |= MSR_BIP; env->pc = cpu->cfg.base_vectors + 0x18; - } else + } else { env->pc = env->btarget; + } + mb_cpu_write_msr(env, msr); break; default: cpu_abort(cs, "unhandled exception type=%d\n", diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e709884f2d..0c9b4ffa5a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,6 +56,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; +static TCGv_i32 cpu_msr_c; static TCGv_i32 cpu_imm; static TCGv_i32 cpu_btaken; static TCGv_i32 cpu_btarget; @@ -150,30 +151,6 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) } } -static void read_carry(DisasContext *dc, TCGv_i32 d) -{ - tcg_gen_shri_i32(d, cpu_msr, 31); -} - -/* - * write_carry sets the carry bits in MSR based on bit 0 of v. - * v[31:1] are ignored. - */ -static void write_carry(DisasContext *dc, TCGv_i32 v) -{ - /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1); - tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1); -} - -static void write_carryi(DisasContext *dc, bool carry) -{ - TCGv_i32 t0 = tcg_temp_new_i32(); - tcg_gen_movi_i32(t0, carry); - write_carry(dc, t0); - tcg_temp_free_i32(t0); -} - /* * Returns true if the insn an illegal operation. * If exceptions are enabled, an exception is raised. @@ -243,11 +220,7 @@ static void dec_add(DisasContext *dc) if (c) { /* c - Add carry into the result. */ - cf = tcg_temp_new_i32(); - - read_carry(dc, cf); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free_i32(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); } } return; @@ -257,21 +230,15 @@ static void dec_add(DisasContext *dc) /* Extract carry. */ cf = tcg_temp_new_i32(); if (c) { - read_carry(dc, cf); + tcg_gen_mov_i32(cf, cpu_msr_c); } else { tcg_gen_movi_i32(cf, 0); } + gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); if (dc->rd) { - TCGv_i32 ncf = tcg_temp_new_i32(); - gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - write_carry(dc, ncf); - tcg_temp_free_i32(ncf); - } else { - gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - write_carry(dc, cf); } tcg_temp_free_i32(cf); } @@ -309,11 +276,7 @@ static void dec_sub(DisasContext *dc) if (c) { /* c - Add carry into the result. */ - cf = tcg_temp_new_i32(); - - read_carry(dc, cf); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free_i32(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); } } return; @@ -324,7 +287,7 @@ static void dec_sub(DisasContext *dc) cf = tcg_temp_new_i32(); na = tcg_temp_new_i32(); if (c) { - read_carry(dc, cf); + tcg_gen_mov_i32(cf, cpu_msr_c); } else { tcg_gen_movi_i32(cf, 1); } @@ -332,16 +295,10 @@ static void dec_sub(DisasContext *dc) /* d = b + ~a + c. carry defaults to 1. */ tcg_gen_not_i32(na, cpu_R[dc->ra]); + gen_helper_carry(cpu_msr_c, na, *(dec_alu_op_b(dc)), cf); if (dc->rd) { - TCGv_i32 ncf = tcg_temp_new_i32(); - gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf); tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - write_carry(dc, ncf); - tcg_temp_free_i32(ncf); - } else { - gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf); - write_carry(dc, cf); } tcg_temp_free_i32(cf); tcg_temp_free_i32(na); @@ -429,16 +386,26 @@ static void dec_xor(DisasContext *dc) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } -static inline void msr_read(DisasContext *dc, TCGv_i32 d) +static void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_mov_i32(d, cpu_msr); + TCGv_i32 t; + + /* Replicate the cpu_msr_c boolean into the proper bit and the copy. */ + t = tcg_temp_new_i32(); + tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC); + tcg_gen_or_i32(d, cpu_msr, t); + tcg_temp_free_i32(t); } -static inline void msr_write(DisasContext *dc, TCGv_i32 v) +static void msr_write(DisasContext *dc, TCGv_i32 v) { dc->cpustate_changed = 1; - /* PVR bit is not writable, and is never set. */ - tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR); + + /* Install MSR_C. */ + tcg_gen_extract_i32(cpu_msr_c, v, 2, 1); + + /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */ + tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } static void dec_msr(DisasContext *dc) @@ -778,8 +745,8 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new_i32(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_i32(t0, cpu_msr, MSR_CC); - write_carry(dc, cpu_R[dc->ra]); + tcg_gen_shli_i32(t0, cpu_msr_c, 31); + tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); @@ -792,8 +759,7 @@ static void dec_bit(DisasContext *dc) /* srl. */ LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); - /* Update carry. Note that write carry only looks at the LSB. */ - write_carry(dc, cpu_R[dc->ra]); + tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { if (op == 0x41) tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); @@ -1042,7 +1008,7 @@ static void dec_load(DisasContext *dc) if (ex) { /* lwx */ /* no support for AXI exclusive so always clear C */ - write_carryi(dc, 0); + tcg_gen_movi_i32(cpu_msr_c, 0); } tcg_temp_free(addr); @@ -1093,7 +1059,7 @@ static void dec_store(DisasContext *dc) /* swx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - write_carryi(dc, 1); + tcg_gen_movi_i32(cpu_msr_c, 1); swx_skip = gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); @@ -1108,7 +1074,7 @@ static void dec_store(DisasContext *dc) mop); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); - write_carryi(dc, 0); + tcg_gen_movi_i32(cpu_msr_c, 0); tcg_temp_free_i32(tval); } @@ -1851,6 +1817,7 @@ void mb_tcg_init(void) SP(pc), SP(msr), + SP(msr_c), SP(imm), SP(iflags), SP(btaken), From patchwork Tue Aug 25 20:58:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248264 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3766059ils; Tue, 25 Aug 2020 14:03:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwc1JwyBzt6sqPc/gFbGnG6AoQwQJYaoLdMTkbgAVxDANaZqqP51s3kHvlry5zjv+Ese8JM X-Received: by 2002:a1f:9651:: with SMTP id y78mr7403612vkd.5.1598389397861; Tue, 25 Aug 2020 14:03:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389397; cv=none; d=google.com; s=arc-20160816; b=D27CcsUBCeAzY6sRxGZiIdImUNblT9GvmdO9yB5+gG4ruZofjCo895cUF1LKj4qG73 Kox1Z3yTKHcdfPT+rnppXGHvWBz/GhJ2E+4uo4okQMY2jgm9x0r3WCvYWeVasejxkUVT IFO8xMawNfVhAQvhPg5p5Qn+5PX4XeNhsLUVr1W9lPXv3dyd4JPGFXjIMRWhUZijnFgN KgCA3Rziz9tgW7EejHGWFWs1p+rotPH71hu3BvcXjKbJkI8QHprCq3+xyOArYpkTagu6 HLWaDsXv+iFWYkbVCD3rwOfyZ/eYRTE9vXFmttQfAl+9KhJRD4QCidfkuta+8ONNcyPF ntMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qXpLGSkTUh0l6cihbLBx2yxjRuaY4I2Cb0zQBnRmSlQ=; b=Nebub911oBGmpyKMhV5GUwbTdozydGmdmol+8Q7NhbkMTQF4gxmAspyS4eS0cucPRL /51qlPG7dUGSXcpCW4fekggGiW8ytwP6Tq4lFC4MeQi+6HYRf55eVDpBEudizk/6XlfD F3jsY1/2fMn6m++lXvAXKCtv4lCZTeDJwSDDND3WQEGbxgfGd3ZVfavTGa93X6FVHAJG ImBVmXpn0deyYl0eED9Ff+AsRH8njtXDHX4ReDf0DezTXtFNlFNtFG1LC+3vpL174ZTf 9yRNfpO0l+h2e+tYdO2QBgnhD6JYOrWF3CMTsLJtwzcUTAKawq5MSirU+d2dIox77D3W lJuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xt5JE9G8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 26/77] target/microblaze: Use DISAS_NORETURN Date: Tue, 25 Aug 2020 13:58:59 -0700 Message-Id: <20200825205950.730499-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both exceptions and gen_goto_tb do not return. Use the official DISAS_NORETURN enumerator for this case. This eliminates all use of DISAS_TB_JUMP. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0c9b4ffa5a..53ca0bfb38 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -51,7 +51,6 @@ /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ -#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; @@ -111,7 +110,7 @@ static void gen_raise_exception(DisasContext *dc, uint32_t index) gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; } static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) @@ -149,6 +148,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } + dc->is_jmp = DISAS_NORETURN; } /* @@ -1675,7 +1675,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); gen_goto_tb(dc, 0, dc->jmp_pc); - dc->is_jmp = DISAS_TB_JUMP; } else if (dc->jmp == JMP_DIRECT_CC) { TCGLabel *l1 = gen_new_label(); t_sync_flags(dc); @@ -1684,8 +1683,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) gen_goto_tb(dc, 1, dc->pc); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); - - dc->is_jmp = DISAS_TB_JUMP; } break; } @@ -1717,7 +1714,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } t_sync_flags(dc); - if (unlikely(cs->singlestep_enabled)) { + if (dc->is_jmp == DISAS_NORETURN) { + /* nothing more to generate */ + } else if (unlikely(cs->singlestep_enabled)) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { @@ -1730,16 +1729,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) case DISAS_NEXT: gen_goto_tb(dc, 1, npc); break; - default: case DISAS_JUMP: case DISAS_UPDATE: /* indicate that the hash table must be used to find the next TB */ tcg_gen_exit_tb(NULL, 0); break; - case DISAS_TB_JUMP: - /* nothing more to generate */ - break; + default: + g_assert_not_reached(); } } gen_tb_end(tb, num_insns); From patchwork Tue Aug 25 20:59:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248294 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp6706ejn; Tue, 25 Aug 2020 14:18:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzaK/SgjXLxHipbwd1yegqmDetn3LIKTRrFmJVU5gvWqLwJdvwv6OS+AMnZLD7hkj0Zzo7r X-Received: by 2002:a25:824a:: with SMTP id d10mr17538174ybn.260.1598390320130; Tue, 25 Aug 2020 14:18:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390320; cv=none; d=google.com; s=arc-20160816; b=uDsoVWmsOuxzrAhehNpF0+WzJGVfSk2NzixESrtLyml3AuoIp6O3qvqt3o19MgKovd hC94kl6MN/HYvqPBb0q+ae6HywMVXo4hdVTkO+nwrUXl5Z4WVcEwq24lfKNy3vjx39lF cvnahe6k6cLB/YEfFx7qWQvj39sjev160/JRYwUc0GrG6o2N5XDzH+wYkPHwEKJMiOob pwJRRsifQVp/nwX8ZvWwb/w2Q+YzXLy8uB740RBf43MN6JMm3/4yOCOaewWlDCZ/7UEb RIhlYUO92VNVYJ64vDvo7BAFbT6rBpW1HEfk8gwslVVmsuQlcwgNy80HnGquYAZ5rt03 mtjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vRHfeWYe4t2JOdjOnGDnZu1tFFPEQawCvJ5AdLU8/XA=; b=QJwGClmBoJiIskFcCV3oAsEyischpqDgfV6ZDXWGQmsEC6/yXUJFl8OytakrTisD8G v6/+zbkP3PXvMQHwc0a0FiEthvsDgeWUBuGU4mPhQOCSDdCIzNW9uFQnb3XtQVyRmI76 IWv98aN8+OOf1pGCwSdSRXmD0Lw32yoPJDz8UN7a+YfyxoOme/xMuKZAA2+s72t20bQX FGQlD5Sjv5r/H8Qsv2/eY7D/uOu+Uyk7podWNn/lcJL2Vr4bcgnsckb+EWN44uhxZ7su xAyLKp6oCXCbVw/SpaO1LgA5IRfFjz4vUUdjKL81+9apR7WefiB2lGeCVpBVMeIJeE8A 7ulw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B8Uu8iDo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 27/77] target/microblaze: Check singlestep_enabled in gen_goto_tb Date: Tue, 25 Aug 2020 13:59:00 -0700 Message-Id: <20200825205950.730499-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not use goto_tb if we're single-stepping. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 53ca0bfb38..7d5b96c38b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -140,7 +140,12 @@ static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { - if (use_goto_tb(dc, dest)) { + if (dc->singlestep_enabled) { + TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); + tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + gen_helper_raise_exception(cpu_env, tmp); + tcg_temp_free_i32(tmp); + } else if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); From patchwork Tue Aug 25 20:59:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248296 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp7543ejn; Tue, 25 Aug 2020 14:20:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyG54m4vp0UcBT4BL4rPvqIGQo40NAB6vmqBR7ms2J7F9FsHnAu0MqVQiZNZJdELzqgzfmo X-Received: by 2002:a25:502:: with SMTP id 2mr16495993ybf.6.1598390431991; Tue, 25 Aug 2020 14:20:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390431; cv=none; d=google.com; s=arc-20160816; b=l/UXAL6qmoazjYHdDZ4M9LsYGPwQk7pewx5i3PQ5Iap+XCzI+33cAdZqZPumqJhmDM PX+MJGWxVAIObqbAQXXH4C+pZQLbH0LaaLc+OyHHCqhrXJX5aWwM5/pOiAR0WER87yGM ZvIXQxgX0EKrfRCzrnCxgLlfk4Zu0+xMNB02/hZeVF/0eObMqYhIE6D6/8kzYVpmJq0N j9lFCwAny7ukSMFwmeRe8lYJyHwlXFDBbQTbyw8RRpzvm6MwCNkf6c4SkO8/InmEVmhP OJVmT9wPkTMQs61Mub5jViA+pqvcOwYhD7hnUGB5zB+tOmxbFPnnzKOV4v+OKi8fHJN0 kPpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kv9Q2CNP0xNdIj9IWSGlA1oMnFfXI9CS46hFWNSGG9w=; b=0Dl/WyUbfBT/eACxg8quwKOtB4PeqbrI62zhdQOhCB6I7AcEZ5qPAX8fLOqFcSU3Cz hmz+umoIzhTFqWvnfPq++uuI/BQmjGHBFhKDfsc/HRkxn7EBMsS9TH9KHg87M+6D6MUi rt79LQpELR6zjfhu2Zu4sLqX71HzDRsXtLcdZDyYF7KElyiQWTCuq7XDsehY7Gu5Vl0g dbNQZQJpJB0YAtYUPrlwu/PFIQBgch6t5OgaBIDgTwbli+czVWtVu4IjHcoS7rC4TSWK kWBQOw9bEBrGGq/kl3b8/jIWjDhDkZ8J/qVTyuvtaTKaGo454NygUQ+pcfEyezrZYmNA OKPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NERN6mRc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 28/77] target/microblaze: Convert to DisasContextBase Date: Tue, 25 Aug 2020 13:59:01 -0700 Message-Id: <20200825205950.730499-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Part one of conversion to the generic translator_loop is to use the DisasContextBase and the members therein. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 104 +++++++++++++++++----------------- 1 file changed, 52 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7d5b96c38b..45b1555f85 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -67,8 +67,8 @@ static TCGv_i32 cpu_res_val; /* This is the state at translation time. */ typedef struct DisasContext { + DisasContextBase base; MicroBlazeCPU *cpu; - uint32_t pc; /* Decoder. */ int type_b; @@ -81,7 +81,6 @@ typedef struct DisasContext { unsigned int delayed_branch; unsigned int tb_flags, synced_flags; /* tb dependent flags. */ unsigned int clear_imm; - int is_jmp; #define JMP_NOJMP 0 #define JMP_DIRECT 1 @@ -91,8 +90,6 @@ typedef struct DisasContext { uint32_t jmp_pc; int abort_at_next_insn; - struct TranslationBlock *tb; - int singlestep_enabled; } DisasContext; static inline void t_sync_flags(DisasContext *dc) @@ -110,13 +107,13 @@ static void gen_raise_exception(DisasContext *dc, uint32_t index) gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; } static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) { t_sync_flags(dc); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_raise_exception(dc, index); } @@ -132,7 +129,7 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); + return (dc->base.pc_first & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); #else return true; #endif @@ -140,20 +137,20 @@ static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { - if (dc->singlestep_enabled) { + if (dc->base.singlestep_enabled) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i32(cpu_pc, dest); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); } else if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb(dc->tb, n); + tcg_gen_exit_tb(dc->base.tb, n); } else { tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; } /* @@ -468,8 +465,8 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); - dc->is_jmp = DISAS_UPDATE; + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); + dc->base.is_jmp = DISAS_UPDATE; return; } @@ -546,7 +543,7 @@ static void dec_msr(DisasContext *dc) switch (sr) { case SR_PC: - tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); break; case SR_MSR: msr_read(dc, cpu_R[dc->rd]); @@ -813,7 +810,7 @@ static void dec_bit(DisasContext *dc) break; default: cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", - dc->pc, op, dc->rd, dc->ra, dc->rb); + (uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->rb); break; } } @@ -994,7 +991,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); tcg_temp_free_i32(t0); @@ -1114,7 +1111,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1201,12 +1198,12 @@ static void dec_bcc(DisasContext *dc) if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - tcg_gen_movi_i32(cpu_btarget, dc->pc + offset); + tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset); dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->pc + offset; + dc->jmp_pc = dc->base.pc_next + offset; } else { dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); } eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } @@ -1250,7 +1247,7 @@ static void dec_br(DisasContext *dc) +offsetof(CPUState, halted)); tcg_temp_free_i32(tmp_1); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); gen_raise_exception(dc, EXCP_HLT); return; @@ -1270,7 +1267,7 @@ static void dec_br(DisasContext *dc) dec_setup_dslot(dc); } if (link && dc->rd) - tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); dc->jmp = JMP_INDIRECT; if (abs) { @@ -1291,10 +1288,10 @@ static void dec_br(DisasContext *dc) } else { if (dec_alu_op_b_is_small_imm(dc)) { dc->jmp = JMP_DIRECT; - dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); + dc->jmp_pc = dc->base.pc_next + (int32_t)((int16_t)dc->imm); } else { tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); } } } @@ -1459,7 +1456,8 @@ static void dec_fpu(DisasContext *dc) qemu_log_mask(LOG_UNIMP, "unimplemented fcmp fpu_insn=%x pc=%x" " opc=%x\n", - fpu_insn, dc->pc, dc->opcode); + fpu_insn, (uint32_t)dc->base.pc_next, + dc->opcode); dc->abort_at_next_insn = 1; break; } @@ -1489,7 +1487,7 @@ static void dec_fpu(DisasContext *dc) default: qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" " opc=%x\n", - fpu_insn, dc->pc, dc->opcode); + fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode); dc->abort_at_next_insn = 1; break; } @@ -1500,7 +1498,8 @@ static void dec_null(DisasContext *dc) if (trap_illegal(dc, true)) { return; } - qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode); + qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", + (uint32_t)dc->base.pc_next, dc->opcode); dc->abort_at_next_insn = 1; } @@ -1610,19 +1609,20 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) pc_start = tb->pc; dc->cpu = cpu; - dc->tb = tb; org_flags = dc->synced_flags = dc->tb_flags = tb->flags; - dc->is_jmp = DISAS_NEXT; dc->jmp = 0; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); if (dc->delayed_branch) { dc->jmp = JMP_INDIRECT; } - dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->base.pc_first = pc_start; + dc->base.pc_next = pc_start; + dc->base.singlestep_enabled = cs->singlestep_enabled; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; + dc->base.is_jmp = DISAS_NEXT; + dc->base.tb = tb; if (pc_start & 3) { cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); @@ -1634,31 +1634,31 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) gen_tb_start(tb); do { - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->base.pc_next); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - dc->pc += 4; + dc->base.pc_next += 4; break; } /* Pretty disas. */ - LOG_DIS("%8.8x:\t", dc->pc); + LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next); if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } dc->clear_imm = 1; - decode(dc, cpu_ldl_code(env, dc->pc)); + decode(dc, cpu_ldl_code(env, dc->base.pc_next)); if (dc->clear_imm) dc->tb_flags &= ~IMM_FLAG; - dc->pc += 4; + dc->base.pc_next += 4; if (dc->delayed_branch) { dc->delayed_branch--; @@ -1673,10 +1673,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) dc->tb_flags &= ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp == JMP_INDIRECT) { - TCGv_i32 tmp_pc = tcg_const_i32(dc->pc); + TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); eval_cond_jmp(dc, cpu_btarget, tmp_pc); tcg_temp_free_i32(tmp_pc); - dc->is_jmp = DISAS_JUMP; + dc->base.is_jmp = DISAS_JUMP; } else if (dc->jmp == JMP_DIRECT) { t_sync_flags(dc); gen_goto_tb(dc, 0, dc->jmp_pc); @@ -1685,26 +1685,26 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) t_sync_flags(dc); /* Conditional jmp. */ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); - gen_goto_tb(dc, 1, dc->pc); + gen_goto_tb(dc, 1, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); } break; } } - if (cs->singlestep_enabled) { + if (dc->base.singlestep_enabled) { break; } - } while (!dc->is_jmp && !dc->cpustate_changed + } while (!dc->base.is_jmp && !dc->cpustate_changed && !tcg_op_buf_full() && !singlestep - && (dc->pc - page_start < TARGET_PAGE_SIZE) + && (dc->base.pc_next - page_start < TARGET_PAGE_SIZE) && num_insns < max_insns); - npc = dc->pc; + npc = dc->base.pc_next; if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { - dc->is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_UPDATE; tcg_gen_movi_i32(cpu_pc, npc); sync_jmpstate(dc); } else @@ -1712,25 +1712,25 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } /* Force an update if the per-tb cpu state has changed. */ - if (dc->is_jmp == DISAS_NEXT + if (dc->base.is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { - dc->is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_UPDATE; tcg_gen_movi_i32(cpu_pc, npc); } t_sync_flags(dc); - if (dc->is_jmp == DISAS_NORETURN) { + if (dc->base.is_jmp == DISAS_NORETURN) { /* nothing more to generate */ } else if (unlikely(cs->singlestep_enabled)) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); - if (dc->is_jmp != DISAS_JUMP) { + if (dc->base.is_jmp != DISAS_JUMP) { tcg_gen_movi_i32(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); } else { - switch(dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, npc); break; @@ -1746,7 +1746,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) } gen_tb_end(tb, num_insns); - tb->size = dc->pc - pc_start; + tb->size = dc->base.pc_next - pc_start; tb->icount = num_insns; #ifdef DEBUG_DISAS @@ -1755,7 +1755,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) && qemu_log_in_addr_range(pc_start)) { FILE *logfile = qemu_log_lock(); qemu_log("--------------\n"); - log_target_disas(cs, pc_start, dc->pc - pc_start); + log_target_disas(cs, pc_start, dc->base.pc_next - pc_start); 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 29/77] target/microblaze: Convert to translator_loop Date: Tue, 25 Aug 2020 13:59:02 -0700 Message-Id: <20200825205950.730499-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Part two of conversion to the generic translator_loop. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 289 ++++++++++++++++++---------------- 1 file changed, 149 insertions(+), 140 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 45b1555f85..6a9710d76d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1595,172 +1595,181 @@ static inline void decode(DisasContext *dc, uint32_t ir) } } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) +static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { - CPUMBState *env = cs->env_ptr; - MicroBlazeCPU *cpu = env_archcpu(env); - uint32_t pc_start; - struct DisasContext ctx; - struct DisasContext *dc = &ctx; - uint32_t page_start, org_flags; - uint32_t npc; - int num_insns; + DisasContext *dc = container_of(dcb, DisasContext, base); + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + int bound; - pc_start = tb->pc; dc->cpu = cpu; - org_flags = dc->synced_flags = dc->tb_flags = tb->flags; - - dc->jmp = 0; + dc->synced_flags = dc->tb_flags = dc->base.tb->flags; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); - if (dc->delayed_branch) { - dc->jmp = JMP_INDIRECT; - } - dc->base.pc_first = pc_start; - dc->base.pc_next = pc_start; - dc->base.singlestep_enabled = cs->singlestep_enabled; + dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; - dc->base.is_jmp = DISAS_NEXT; - dc->base.tb = tb; - if (pc_start & 3) { - cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); + bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + dc->base.max_insns = MIN(dc->base.max_insns, bound); +} + +static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs) +{ +} + +static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) +{ + tcg_gen_insn_start(dcb->pc_next); +} + +static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcb, DisasContext, base); + + gen_raise_exception_sync(dc, EXCP_DEBUG); + + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + dc->base.pc_next += 4; + return true; +} + +static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc = container_of(dcb, DisasContext, base); + CPUMBState *env = cs->env_ptr; + + /* TODO: This should raise an exception, not terminate qemu. */ + if (dc->base.pc_next & 3) { + cpu_abort(cs, "Microblaze: unaligned PC=%x\n", + (uint32_t)dc->base.pc_next); } - page_start = pc_start & TARGET_PAGE_MASK; - num_insns = 0; + dc->clear_imm = 1; + decode(dc, cpu_ldl_code(env, dc->base.pc_next)); + if (dc->clear_imm) { + dc->tb_flags &= ~IMM_FLAG; + } + dc->base.pc_next += 4; - gen_tb_start(tb); - do - { - tcg_gen_insn_start(dc->base.pc_next); - num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { - gen_raise_exception_sync(dc, EXCP_DEBUG); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next += 4; - break; + if (dc->delayed_branch && --dc->delayed_branch == 0) { + if (dc->tb_flags & DRTI_FLAG) { + do_rti(dc); } - - /* Pretty disas. */ - LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next); - - if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); + if (dc->tb_flags & DRTB_FLAG) { + do_rtb(dc); } - - dc->clear_imm = 1; - decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) - dc->tb_flags &= ~IMM_FLAG; - dc->base.pc_next += 4; - - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - if (dc->tb_flags & DRTI_FLAG) - do_rti(dc); - if (dc->tb_flags & DRTB_FLAG) - do_rtb(dc); - if (dc->tb_flags & DRTE_FLAG) - do_rte(dc); - /* Clear the delay slot flag. */ - dc->tb_flags &= ~D_FLAG; - /* If it is a direct jump, try direct chaining. */ - if (dc->jmp == JMP_INDIRECT) { - TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); - dc->base.is_jmp = DISAS_JUMP; - } else if (dc->jmp == JMP_DIRECT) { - t_sync_flags(dc); - gen_goto_tb(dc, 0, dc->jmp_pc); - } else if (dc->jmp == JMP_DIRECT_CC) { - TCGLabel *l1 = gen_new_label(); - t_sync_flags(dc); - /* Conditional jmp. */ - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); - gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); - gen_goto_tb(dc, 0, dc->jmp_pc); - } - break; - } + if (dc->tb_flags & DRTE_FLAG) { + do_rte(dc); } - if (dc->base.singlestep_enabled) { - break; - } - } while (!dc->base.is_jmp && !dc->cpustate_changed - && !tcg_op_buf_full() - && !singlestep - && (dc->base.pc_next - page_start < TARGET_PAGE_SIZE) - && num_insns < max_insns); - - npc = dc->base.pc_next; - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->tb_flags & D_FLAG) { - dc->base.is_jmp = DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); - sync_jmpstate(dc); - } else - npc = dc->jmp_pc; + /* Clear the delay slot flag. */ + dc->tb_flags &= ~D_FLAG; + dc->base.is_jmp = DISAS_JUMP; } - /* Force an update if the per-tb cpu state has changed. */ - if (dc->base.is_jmp == DISAS_NEXT - && (dc->cpustate_changed || org_flags != dc->tb_flags)) { + /* Force an exit if the per-tb cpu state has changed. */ + if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) { dc->base.is_jmp = DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); } - t_sync_flags(dc); +} + +static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc = container_of(dcb, DisasContext, base); + + assert(!dc->abort_at_next_insn); if (dc->base.is_jmp == DISAS_NORETURN) { - /* nothing more to generate */ - } else if (unlikely(cs->singlestep_enabled)) { - TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); - - if (dc->base.is_jmp != DISAS_JUMP) { - tcg_gen_movi_i32(cpu_pc, npc); - } - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - gen_goto_tb(dc, 1, npc); - break; - case DISAS_JUMP: - case DISAS_UPDATE: - /* indicate that the hash table must be used - to find the next TB */ - tcg_gen_exit_tb(NULL, 0); - break; - default: - g_assert_not_reached(); - } + /* We have already exited the TB. */ + return; } - gen_tb_end(tb, num_insns); - tb->size = dc->base.pc_next - pc_start; - tb->icount = num_insns; + t_sync_flags(dc); + if (dc->tb_flags & D_FLAG) { + sync_jmpstate(dc); + dc->jmp = JMP_NOJMP; + } + switch (dc->base.is_jmp) { + case DISAS_TOO_MANY: + assert(dc->jmp == JMP_NOJMP); + gen_goto_tb(dc, 0, dc->base.pc_next); + return; + + case DISAS_UPDATE: + assert(dc->jmp == JMP_NOJMP); + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; + + case DISAS_JUMP: + switch (dc->jmp) { + case JMP_INDIRECT: + { + TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); + eval_cond_jmp(dc, cpu_btarget, tmp_pc); + tcg_temp_free_i32(tmp_pc); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + } + return; + + case JMP_DIRECT_CC: + { + TCGLabel *l1 = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + gen_goto_tb(dc, 1, dc->base.pc_next); + gen_set_label(l1); + } + /* fall through */ + + case JMP_DIRECT: + gen_goto_tb(dc, 0, dc->jmp_pc); + return; + } + /* fall through */ + + default: + g_assert_not_reached(); + } +} + +static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) +{ #ifdef DEBUG_DISAS #if !SIM_COMPAT - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - FILE *logfile = qemu_log_lock(); - qemu_log("--------------\n"); - log_target_disas(cs, pc_start, dc->base.pc_next - pc_start); - qemu_log_unlock(logfile); - } + qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); + log_target_disas(cs, dcb->pc_first, dcb->tb->size); #endif #endif - assert(!dc->abort_at_next_insn); +} + +static const TranslatorOps mb_tr_ops = { + .init_disas_context = mb_tr_init_disas_context, + .tb_start = mb_tr_tb_start, + .insn_start = mb_tr_insn_start, + .breakpoint_check = mb_tr_breakpoint_check, + .translate_insn = mb_tr_translate_insn, + .tb_stop = mb_tr_tb_stop, + .disas_log = mb_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns) +{ + DisasContext dc; + translator_loop(&mb_tr_ops, &dc.base, cpu, tb, max_insns); } void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) From patchwork Tue Aug 25 20:59:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248268 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3767327ils; Tue, 25 Aug 2020 14:05:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7ueWjK6xaqHwkVzyhQyvuYLEYDixUtC08jOdzAvyi9Xyo3/LJ2TC/uPVrXM9h7c5mlV2T X-Received: by 2002:a25:3f83:: with SMTP id m125mr16607396yba.324.1598389501210; Tue, 25 Aug 2020 14:05:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389501; cv=none; d=google.com; s=arc-20160816; b=mVflbJdd8C2WwWg/bmdka7R8GnRbw2pjIgeYF2oaverEQ5qsgPjgBgQfvCcvClRxIt jsCHn/Y4UcFh2GD2GUtSxFQ6EsM2z/O5QEUgkEMn+oMLLTOwCtq6SBOyTQURnQ+NZmgb EbTv22JFFOqzO50BoZcUJjF//qbTCiQtL3fT93V7yFvE0PksFBw3pobQvChqkKsoIbVd BtScCy4IpkZITMXBHeZzJdeKnm9kAG1xHcX/VFhq8uia9MW9NxVLcSeen3SExv0XGsUP F5RlQonYyO6n1d2Ye+VWGXrlH9WyLNbljf1XcoXw90qm684bT5cD6AEVh0S8aNra+LRA 7j4A== ARC-Message-Signature: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 30/77] target/microblaze: Remove SIM_COMPAT Date: Tue, 25 Aug 2020 13:59:03 -0700 Message-Id: <20200825205950.730499-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6a9710d76d..a90e56a17f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -34,10 +34,9 @@ #include "exec/log.h" -#define SIM_COMPAT 0 #define DISAS_GNU 1 #define DISAS_MB 1 -#if DISAS_MB && !SIM_COMPAT +#if DISAS_MB # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) #else # define LOG_DIS(...) do { } while (0) @@ -1749,11 +1748,9 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) { #ifdef DEBUG_DISAS -#if !SIM_COMPAT qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); log_target_disas(cs, dcb->pc_first, dcb->tb->size); #endif -#endif } static const TranslatorOps mb_tr_ops = { From patchwork Tue Aug 25 20:59:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248273 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3769037ils; Tue, 25 Aug 2020 14:07:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxb/q+jqXceAvaqzu2I/46QAvcDMqp29OuT9hJSkQXRD8bQgHeIgCvq5TFZf+qyvs1FAHtF X-Received: by 2002:a25:d0c2:: with SMTP id h185mr17070463ybg.73.1598389652492; Tue, 25 Aug 2020 14:07:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389652; cv=none; d=google.com; s=arc-20160816; b=zzhNBUxYj7C50wuyJ7dVZ2H7vxDZ26BDN3WsxHRs71N0slTQOqGISZVwppVcAmYCLI vW9KAJeXweIeopC09Ggb6blWMi/lqgbpqTX4N0DSU1S3Ure2m66jOaQ/PB1N48jiFyrO vG6q0d1djjQ8kb4u0IYenIeq1i6WreojzrB2dyI52tIgCQUUt+Clu3qR+FyAkRR547JA 0WVDw19mipweFRPWyaq39S10kZctohV8LiAEvBqvtEMMy8Z/D0M2HDC5/wUy/bLSG+x4 YAVpVTUX9eSQbfBZ4VM1Zq6cCB4VhaypJsdt7wNG+M/eR/fFdOHtO31N5VcRuYEIpo9T Bdvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Vc1/n0PAMq2ruFSCbPStrg/chGbNzuC4FGRX/oeXBs0=; b=hfVs0/0KSqgcBX2vAP6r1scsfeurSpNf28Wm2lxRKs2gYbBbbSxKEiB2u72UvAKLcU QTo5DXAIcJEmeful654jGBaB8yYenT8mLe5k1bghag7tcpi5nBWZeeCJbwDkjFexWuMb B474K29EYvOchVDc1v+YNm9t5Dt+jhHtsK+AobdM/bHr1+QieLO8zCZjyBMss5y79tWS 7MbwRQMJi/1yNBIzKBI4reBh0VkAE7nXrGiBWextAX6NCJ0jOC8IQ+juGggSmN1ldGhh 1KIgS3Td5nZCCFVw7MCYmu0Ip8RytX1T1nHyL3QNdfz0vlP2t62zgd6s6wrDmW3R/7bh hMbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R5oQvlbF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 1 - 1 file changed, 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a90e56a17f..6757720776 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -34,7 +34,6 @@ #include "exec/log.h" -#define DISAS_GNU 1 #define DISAS_MB 1 #if DISAS_MB # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) From patchwork Tue Aug 25 20:59:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248302 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp8232ejn; Tue, 25 Aug 2020 14:22:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyMqSr8Sxwa85ZJhAWgrBFZI4wZ0tRJsjSiWconkBGlT1Up2CeIIqxdknYMrCYVE4i72lVr X-Received: by 2002:a25:2e41:: with SMTP id b1mr15466080ybn.300.1598390537297; Tue, 25 Aug 2020 14:22:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390537; cv=none; d=google.com; s=arc-20160816; b=zwoELyxHVPCMgvxgnCso83Li3vq48blDPQ6w1X5fVNlSUbNZ1mbM+bU45e5TcZSOew IhTVVbhRP6zvzXvRnJaGz15nu5AIuyCgIFd18xEmobv2EH+/9zL8kC10w5Di6Snq5l0e UB/g29rhDDAJfoGiyv5obJ1QqvXn2MxJcyxi62qGyjfQOvDFdsp0urdRG+u4KzorbzMK UQPnQUaLLa+mP0Fb67zusmgIJ3hEIrCPQ4E5fOvEtlrTKeqrpvNWpmxATcbVQ5/4D497 e0VbXCN39ItKGstVjbQX9Wlz7R8k4ssflGA4tbpC4fjepjw2otROAvj5IEPGBc7UesvS ZIwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b/4g1T+WE9RDnuv3IAKyPSAVgdbvulTxnio8bcXmxqI=; b=hOpHrLVrh4t13s53nQYDTbN35448ay67O0kkW/p0BiL5IxTc8kXzOumaytqTju+C7C 7c56VfIuX+As2Vxtmqa7LPinA28ZmQNAKhNSP5PDAui70QMfQ7dQ506V5b7gNdOHKpvN 1hcMjL8gNbGWGbWfBcT+UrUiq7dMXqbgIfm4eSkZigOAlvQCX1GdhqrG4xnGrjzOdUOz +X7vsN3iw408GJy5VXmqegwPC6SxWmNdVv2YVitLUbyYqnVS9Dmj40TJ57lGryWLCpK/ OIuYdSJcXg4hbX/ylXkTQentYWBr26xJJsRQcLkMLnYScTDA5v3D8Uio8xOML3U122vT 62kg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B0twTuks; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 32/77] target/microblaze: Remove empty D macros Date: Tue, 25 Aug 2020 13:59:05 -0700 Message-Id: <20200825205950.730499-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is never used in op_helper.c and translate.c. There are two trivial uses in helper.c which can be improved by always logging MMU_EXCP to CPU_LOG_INT. Signed-off-by: Richard Henderson --- target/microblaze/helper.c | 11 ++++------- target/microblaze/op_helper.c | 2 -- target/microblaze/translate.c | 2 -- 3 files changed, 4 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 9a95456401..f8e2ca12a9 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,8 +24,6 @@ #include "qemu/host-utils.h" #include "exec/log.h" -#define D(x) - #if defined(CONFIG_USER_ONLY) void mb_cpu_do_interrupt(CPUState *cs) @@ -155,10 +153,13 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] = env->pc; + qemu_log_mask(CPU_LOG_INT, + "MMU exception at pc=%x iflags=%x ear=%" PRIx64 "\n", + env->pc, env->iflags, env->ear); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); env->esr |= 1 << 12 ; env->btr = env->btarget; @@ -166,14 +167,10 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[17] -= 4; /* was the branch immprefixed?. */ if (env->bimm) { - qemu_log_mask(CPU_LOG_INT, - "bimm exception at pc=%x iflags=%x\n", - env->pc, env->iflags); env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } } else if (env->iflags & IMM_FLAG) { - D(qemu_log("IMM_FLAG set at exception\n")); env->regs[17] -= 4; } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index d79202c3f8..decdca0fd8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -26,8 +26,6 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" -#define D(x) - void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { int test = ctrl & STREAM_TEST; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6757720776..860859324a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -41,8 +41,6 @@ # define LOG_DIS(...) do { } while (0) #endif -#define D(x) - #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) From patchwork Tue Aug 25 20:59:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248309 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp9873ejn; Tue, 25 Aug 2020 14:25:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxW7+T8sHjmCxwwKacxUPqSz2c92VCmjhl9Q7VkVmk0JWaKPFNqMxsgRcLqaFRAkhtHy2bE X-Received: by 2002:a25:86cf:: with SMTP id y15mr15746798ybm.25.1598390754580; Tue, 25 Aug 2020 14:25:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390754; cv=none; d=google.com; s=arc-20160816; b=QJRqh/9h/Pq/KQ5s4j3j7yYwEq6dypWC5+iz8ZGqqNat3gwFDphoc/1kkaEK8CeIJ7 Q2cAcl1ZcxXl+6XPA9iJb3H2SmGM9FZE1NXAHLZLFHUN2IS33YogEOPLOpW1MccQoRpi nv1xsSK1NWUpBWgCIfUVTOo61dhls15rOpZXiLnHVFfhyRoW333BZnK1tQkFzEsfU/jX hGmMBua7tufURHF05DHBi8xRkpeKRjPEu3gtwVeQbdN2jxwYlrRiZs44x4IDx4l6elHb Mcm9OMVs4lDPDv+1Ct6pRppdmjDx/vBCGdpTdSUFqi6geQ+8AOVzB5wP28GhrlDt9ZN9 Oebg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KOp/91/a2BIVMe1u/E83L0OjODEkWinQdZcmcUxF1f8=; b=OBO86VZ2m4JNF38tPC/qnKmbb8UnrTOB7mHB9rU4p8FixtTU7zWInAYhPQS5Yc/vFf QW36GrT1gtE/p0cO09pB2ewXLkhNAjr3PB9k9Zub84CkOxNXNU9tkc6xEWaHmivHZCR7 ICY3cdhYS+54xNooGIW+tMbJHQBEzhYPySlfHQspuudKKU+jg7N5Rv+d30qAictjJ6Ma myt/bv/LW/S3R9aBgXAuKucN/pCG35kg5UA22h1TMDkRFTWGHXbxm8ZkuNPnbu3eA2Bm lWQkmEbxPsShXPqSRMf9/fOqaDPPxiSFyb1LeNVJrvtiOScZYsmkS9pbYdOm+r12NWAi cBIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BftyHZ81; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 33/77] target/microblaze: Remove LOG_DIS Date: Tue, 25 Aug 2020 13:59:06 -0700 Message-Id: <20200825205950.730499-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also remove the related defines, DISAS_MB and DEBUG_DISAS. Rely on print_insn_microblaze. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 78 +---------------------------------- 1 file changed, 1 insertion(+), 77 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 860859324a..133ec24870 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -33,14 +33,6 @@ #include "trace-tcg.h" #include "exec/log.h" - -#define DISAS_MB 1 -#if DISAS_MB -# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) -#else -# define LOG_DIS(...) do { } while (0) -#endif - #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) @@ -205,10 +197,6 @@ static void dec_add(DisasContext *dc) k = dc->opcode & 4; c = dc->opcode & 2; - LOG_DIS("add%s%s%s r%d r%d r%d\n", - dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "", - dc->rd, dc->ra, dc->rb); - /* Take care of the easy cases first. */ if (k) { /* k - keep carry, no need to update MSR. */ @@ -252,7 +240,6 @@ static void dec_sub(DisasContext *dc) cmp = (dc->imm & 1) && (!dc->type_b) && k; if (cmp) { - LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir); if (dc->rd) { if (u) gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); @@ -262,9 +249,6 @@ static void dec_sub(DisasContext *dc) return; } - LOG_DIS("sub%s%s r%d, r%d r%d\n", - k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb); - /* Take care of the easy cases first. */ if (k) { /* k - keep carry, no need to update MSR. */ @@ -314,19 +298,16 @@ static void dec_pattern(DisasContext *dc) switch (mode) { case 0: /* pcmpbf. */ - LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 2: - LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); } break; case 3: - LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); @@ -349,7 +330,6 @@ static void dec_and(DisasContext *dc) } not = dc->opcode & (1 << 1); - LOG_DIS("and%s\n", not ? "n" : ""); if (!dc->rd) return; @@ -367,7 +347,6 @@ static void dec_or(DisasContext *dc) return; } - LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm); if (dc->rd) tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } @@ -379,7 +358,6 @@ static void dec_xor(DisasContext *dc) return; } - LOG_DIS("xor r%d\n", dc->rd); if (dc->rd) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } @@ -433,9 +411,6 @@ static void dec_msr(DisasContext *dc) if (clrset) { bool clr = extract32(dc->ir, 16, 1); - LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", - dc->rd, dc->imm); - if (!dc->cpu->cfg.use_msr_instr) { /* nop??? */ return; @@ -478,7 +453,6 @@ static void dec_msr(DisasContext *dc) sr &= 7; tmp_sr = tcg_const_i32(sr); - LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); if (to) { gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); } else { @@ -491,7 +465,6 @@ static void dec_msr(DisasContext *dc) #endif if (to) { - LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); switch (sr) { case SR_PC: break; @@ -535,8 +508,6 @@ static void dec_msr(DisasContext *dc) break; } } else { - LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); - switch (sr) { case SR_PC: tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); @@ -609,7 +580,6 @@ static void dec_mul(DisasContext *dc) subcode = dc->imm & 3; if (dc->type_b) { - LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); return; } @@ -622,21 +592,17 @@ static void dec_mul(DisasContext *dc) tmp = tcg_temp_new_i32(); switch (subcode) { case 0: - LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 1: - LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 2: - LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 3: - LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; default: @@ -652,7 +618,6 @@ static void dec_div(DisasContext *dc) unsigned int u; u = dc->imm & 2; - LOG_DIS("div\n"); if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { return; @@ -688,10 +653,6 @@ static void dec_barrel(DisasContext *dc) imm_w = extract32(dc->imm, 6, 5); imm_s = extract32(dc->imm, 0, 5); - LOG_DIS("bs%s%s%s r%d r%d r%d\n", - e ? "e" : "", - s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); - if (e) { if (imm_w + imm_s > 32 || imm_w == 0) { /* These inputs have an undefined behavior. */ @@ -742,7 +703,6 @@ static void dec_bit(DisasContext *dc) /* src. */ t0 = tcg_temp_new_i32(); - LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); tcg_gen_shli_i32(t0, cpu_msr_c, 31); tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { @@ -755,8 +715,6 @@ static void dec_bit(DisasContext *dc) case 0x1: case 0x41: /* srl. */ - LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { if (op == 0x41) @@ -766,11 +724,9 @@ static void dec_bit(DisasContext *dc) } break; case 0x60: - LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra); tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x61: - LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra); tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x64: @@ -778,12 +734,10 @@ static void dec_bit(DisasContext *dc) case 0x74: case 0x76: /* wdc. */ - LOG_DIS("wdc r%d\n", dc->ra); trap_userspace(dc, true); break; case 0x68: /* wic. */ - LOG_DIS("wic r%d\n", dc->ra); trap_userspace(dc, true); break; case 0xe0: @@ -796,12 +750,10 @@ static void dec_bit(DisasContext *dc) break; case 0x1e0: /* swapb */ - LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra); tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x1e2: /*swaph */ - LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra); tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); break; default: @@ -824,7 +776,6 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { - LOG_DIS("imm %x\n", dc->imm << 16); tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; @@ -928,10 +879,6 @@ static void dec_load(DisasContext *dc) return; } - LOG_DIS("l%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", - ex ? "x" : "", - ea ? "ea" : ""); - t_sync_flags(dc); addr = tcg_temp_new(); compute_ldst_addr(dc, ea, addr); @@ -1039,9 +986,6 @@ static void dec_store(DisasContext *dc) trap_userspace(dc, ea); - LOG_DIS("s%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", - ex ? "x" : "", - ea ? "ea" : ""); t_sync_flags(dc); /* If we get a fault on a dslot, the jmpstate better be in sync. */ sync_jmpstate(dc); @@ -1184,7 +1128,6 @@ static void dec_bcc(DisasContext *dc) cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); - LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm); dc->delayed_branch = 1; if (dslot) { @@ -1217,8 +1160,6 @@ static void dec_br(DisasContext *dc) if (mbar == 2 && dc->imm == 4) { uint16_t mbar_imm = dc->rd; - LOG_DIS("mbar %d\n", mbar_imm); - /* Data access memory barrier. */ if ((mbar_imm & 2) == 0) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); @@ -1228,8 +1169,6 @@ static void dec_br(DisasContext *dc) if (mbar_imm & 16) { TCGv_i32 tmp_1; - LOG_DIS("sleep\n"); - if (trap_userspace(dc, true)) { /* Sleep is a privileged instruction. */ return; @@ -1253,11 +1192,6 @@ static void dec_br(DisasContext *dc) return; } - LOG_DIS("br%s%s%s%s imm=%x\n", - abs ? "a" : "", link ? "l" : "", - dc->type_b ? "i" : "", dslot ? "d" : "", - dc->imm); - dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); @@ -1363,16 +1297,12 @@ static void dec_rts(DisasContext *dc) dec_setup_dslot(dc); if (i_bit) { - LOG_DIS("rtid ir=%x\n", dc->ir); dc->tb_flags |= DRTI_FLAG; } else if (b_bit) { - LOG_DIS("rtbd ir=%x\n", dc->ir); dc->tb_flags |= DRTB_FLAG; } else if (e_bit) { - LOG_DIS("rted ir=%x\n", dc->ir); dc->tb_flags |= DRTE_FLAG; - } else - LOG_DIS("rts ir=%x\n", dc->ir); + } dc->jmp = JMP_INDIRECT; tcg_gen_movi_i32(cpu_btaken, 1); @@ -1505,9 +1435,6 @@ static void dec_stream(DisasContext *dc) TCGv_i32 t_id, t_ctrl; int ctrl; - LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put", - dc->type_b ? "" : "d", dc->imm); - if (trap_userspace(dc, true)) { return; } @@ -1565,7 +1492,6 @@ static inline void decode(DisasContext *dc, uint32_t ir) int i; dc->ir = ir; - LOG_DIS("%8.8x\t", dc->ir); if (ir == 0) { trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); @@ -1744,10 +1670,8 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) { -#ifdef DEBUG_DISAS qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); log_target_disas(cs, dcb->pc_first, dcb->tb->size); -#endif } static const TranslatorOps mb_tr_ops = { From patchwork Tue Aug 25 20:59:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248304 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp8555ejn; Tue, 25 Aug 2020 14:23:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzrFrnC4LzGB8u66LVfWa6oO7JdkB0bHXXBC6ZVsZPM7WKdVFoIbcChsimVJ4/ADxAnQPOm X-Received: by 2002:a25:e83:: with SMTP id 125mr18441161ybo.376.1598390583646; Tue, 25 Aug 2020 14:23:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390583; cv=none; d=google.com; s=arc-20160816; b=tnFARJAqLFqrHGXhNdifRH2HazyoqMO64/Pg2X+dWK1EyuS6wFhFfv3XQWb9yTRWyf qno57II3tXpzAtUrzcJt9ea3Ax1ffCWNhESkW7oHDPo3pitqZj5c7FV5H91HbYcjpMEX e/Iub7Gq4GX4TVR0b1wocGotsW6pd85AUH3zSvQPahqHofmxi6O3hRzCPOYpgXuVy8KJ oew/PgUD+VDD8Ea8m+m47yTfSlB0lqZzXCEW2l/eFs2pL8Dupdfs0EUw5gapDqMeyYeq yRkYrYWuwcAyfGSeMXSWZJe7wYe0qEj/xemz5PG83MZXe2Ej5MIfDwq2qfXApB0yiilp 0oHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wse7zD0pJo6WjEez5LvLZIudG6q/fbgb3bbbGW9ilgU=; b=C6bi4V5BPXWf52kD+9/glM8bPlxcWXw78x2A6tn6DGaLIQs7CdKYwLdQjmTeRdVa2V hogeoyVmdo5l+pK9XHCx6D8VR6V6bxz0cyq357+qQjL8lDC+ASzgID+LW4iOoixnOs3T SPguEQRlFbT7tUpeVddX0alypqQ01zM/vgE11eulQwLIDCvllz4mEGaIochxtpZXC1Na bPeVnM9QcgYBQe+6yp2WNvI+sYaUivsw1RhnvkShULoSqTK2XXoa+bX8GGY7fqGKaeXI O481UI2xpBdNxLDlZ3LKTvfKCAQde/3dTVxO5UDRB0TvYC+keaftn6R5ryukhvxiXeI6 WVzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qvup682K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 34/77] target/microblaze: Ensure imm constant is always available Date: Tue, 25 Aug 2020 13:59:07 -0700 Message-Id: <20200825205950.730499-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 111 ++++++++++++++++++++-------------- 2 files changed, 67 insertions(+), 46 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7066878ac7..013858b8e0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -374,9 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { *pc = env->pc; - *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & (MSR_UM | MSR_VM | MSR_EE)); + *cs_base = (*flags & IMM_FLAG ? env->imm : 0); } #if !defined(CONFIG_USER_ONLY) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 133ec24870..65ce8f3cd6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -61,6 +61,7 @@ typedef struct DisasContext { /* Decoder. */ int type_b; uint32_t ir; + uint32_t ext_imm; uint8_t opcode; uint8_t rd, ra, rb; uint16_t imm; @@ -169,24 +170,23 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } -/* True if ALU operand b is a small immediate that may deserve - faster treatment. */ -static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) +static int32_t dec_alu_typeb_imm(DisasContext *dc) { - /* Immediate insn without the imm prefix ? */ - return dc->type_b && !(dc->tb_flags & IMM_FLAG); + tcg_debug_assert(dc->type_b); + if (dc->tb_flags & IMM_FLAG) { + return dc->ext_imm | dc->imm; + } else { + return (int16_t)dc->imm; + } } static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { - if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm); - else - tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm)); + tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); return &cpu_imm; - } else - return &cpu_R[dc->rb]; + } + return &cpu_R[dc->rb]; } static void dec_add(DisasContext *dc) @@ -776,14 +776,14 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { - tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); + dc->ext_imm = dc->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); dc->tb_flags |= IMM_FLAG; dc->clear_imm = 0; } static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) { - bool extimm = dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ bool stackprot = false; TCGv_i32 t32; @@ -836,11 +836,7 @@ static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) } /* Immediate. */ t32 = tcg_temp_new_i32(); - if (!extimm) { - tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm); - } else { - tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); - } + tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); tcg_gen_extu_i32_tl(t, t32); tcg_temp_free_i32(t32); @@ -1134,15 +1130,13 @@ static void dec_bcc(DisasContext *dc) dec_setup_dslot(dc); } - if (dec_alu_op_b_is_small_imm(dc)) { - int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ - - tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset); + if (dc->type_b) { dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->base.pc_next + offset; + dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } @@ -1192,38 +1186,63 @@ static void dec_br(DisasContext *dc) return; } + if (abs && link && !dslot) { + if (dc->type_b) { + /* BRKI */ + uint32_t imm = dec_alu_typeb_imm(dc); + if (trap_userspace(dc, imm != 8 && imm != 0x18)) { + return; + } + } else { + /* BRK */ + if (trap_userspace(dc, true)) { + return; + } + } + } + dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); } - if (link && dc->rd) + if (link && dc->rd) { tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); + } - dc->jmp = JMP_INDIRECT; if (abs) { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); - if (link && !dslot) { - if (!(dc->tb_flags & IMM_FLAG) && - (dc->imm == 8 || dc->imm == 0x18)) { + if (dc->type_b) { + uint32_t dest = dec_alu_typeb_imm(dc); + + dc->jmp = JMP_DIRECT; + dc->jmp_pc = dest; + tcg_gen_movi_i32(cpu_btarget, dest); + if (link && !dslot) { + switch (dest) { + case 8: + case 0x18: + gen_raise_exception_sync(dc, EXCP_BREAK); + break; + case 0: + gen_raise_exception_sync(dc, EXCP_DEBUG); + break; + } + } + } else { + dc->jmp = JMP_INDIRECT; + tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); + if (link && !dslot) { gen_raise_exception_sync(dc, EXCP_BREAK); } - if (dc->imm == 0) { - if (trap_userspace(dc, true)) { - return; - } - gen_raise_exception_sync(dc, EXCP_DEBUG); - } } + } else if (dc->type_b) { + dc->jmp = JMP_DIRECT; + dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { - if (dec_alu_op_b_is_small_imm(dc)) { - dc->jmp = JMP_DIRECT; - dc->jmp_pc = dc->base.pc_next + (int32_t)((int16_t)dc->imm); - } else { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); - } + dc->jmp = JMP_INDIRECT; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } + tcg_gen_movi_i32(cpu_btaken, 1); } static inline void do_rti(DisasContext *dc) @@ -1529,6 +1548,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; + dc->ext_imm = dc->base.tb->cs_base; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1573,8 +1593,9 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->clear_imm = 1; decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) { + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; + tcg_gen_discard_i32(cpu_imm); } dc->base.pc_next += 4; From patchwork Tue Aug 25 20:59:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248305 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp9125ejn; Tue, 25 Aug 2020 14:24:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzU9uXI7btj75F5/vKLt+cpFHWNdrEhw0nuFb+cHuYXKEiLukrLOvZv1JkVQ+d06HQ24XP7 X-Received: by 2002:a25:d8d4:: with SMTP id p203mr15999966ybg.289.1598390656615; Tue, 25 Aug 2020 14:24:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390656; cv=none; d=google.com; s=arc-20160816; b=eL0VSoSgkjR2TlA1LAfFMj7P+uGa21YbuNpDS6/40Yezn4oiatZg9ueo3D1ER+GOxI kbh6qRPu7XwIwsL1x5+CNwzYy+OX/XPsQBCetXnXhVr8abX+4VNVfclH/uJDG1lqn8aB HsmrYDJkQ3cgSKslt3dGGN89EbGAFHY/RfecPBcB0G3dKQ/rR8dCfz5c6uO74rWxqoRr 7aG51/euyHPklulrr6XBegAv/uBYKj6nsN/ZRA6VdWbHHJ44dXbybbpqGuLf/TlAYF/G 0IAp102ZLD1GT9/ZJaee1pzesTGlLfvSBUZ+uo3V4RZJYdzleWxueIb02LLs9L13K5iw Y0wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+kEx0UptQCrtmnph6sgV6tFoh7UCNGXW3aCpI+f1tQA=; b=O8yvQNQh+E4VREDII5yuwrFFY/cAT9G1qHRoX8+3lYBPBXQ9LcKZZYdMmowYMP2WCs /Ha+oL0QRw8w+DoP3+6qnPr9FZ+rMdrj9++w+gF7mDpVkNg20OWHnngaS+37pt0ZBxWC h99EfeQ93vVWLNrEkwx2S3aMuNRl/TAtGIuY04qMwhPU+q7Ed/xoYUduOGdZmjQnM0oY yGUqplvQZxbnCOZwFwes6FX4aq7KV3+fmBR53v1QgCwASUmC2zP8OnL/2Eqzggmyq0Yd ETCkr/oFMBDh0FVbnPNkSZu9y3VJxCwnT2/HxBvbD3NMB6esFgxmBFD4eviUOkqw0TsR 3jag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JirQcFos; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 35/77] target/microblaze: Add decodetree infrastructure Date: Tue, 25 Aug 2020 13:59:08 -0700 Message-Id: <20200825205950.730499-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The new interface is a stub that recognizes no instructions. It falls back to the old decoder for all instructions. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 18 ++++++++++++++++++ target/microblaze/translate.c | 11 +++++++++-- target/microblaze/meson.build | 3 +++ 3 files changed, 30 insertions(+), 2 deletions(-) create mode 100644 target/microblaze/insns.decode -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode new file mode 100644 index 0000000000..1ed9ca0731 --- /dev/null +++ b/target/microblaze/insns.decode @@ -0,0 +1,18 @@ +# +# MicroBlaze instruction decode definitions. +# +# Copyright (c) 2020 Richard Henderson +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 65ce8f3cd6..e624093745 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -81,6 +81,9 @@ typedef struct DisasContext { int abort_at_next_insn; } DisasContext; +/* Include the auto-generated decoder. */ +#include "decode-insns.c.inc" + static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1506,7 +1509,7 @@ static struct decoder_info { {{0, 0}, dec_null} }; -static inline void decode(DisasContext *dc, uint32_t ir) +static void old_decode(DisasContext *dc, uint32_t ir) { int i; @@ -1584,6 +1587,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); CPUMBState *env = cs->env_ptr; + uint32_t ir; /* TODO: This should raise an exception, not terminate qemu. */ if (dc->base.pc_next & 3) { @@ -1592,7 +1596,10 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) } dc->clear_imm = 1; - decode(dc, cpu_ldl_code(env, dc->base.pc_next)); + ir = cpu_ldl_code(env, dc->base.pc_next); + if (!decode(dc, ir)) { + old_decode(dc, ir); + } if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; tcg_gen_discard_i32(cpu_imm); diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index b8fe4afe61..639c3f73a8 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -1,4 +1,7 @@ +gen = decodetree.process('insns.decode') + microblaze_ss = ss.source_set() +microblaze_ss.add(gen) microblaze_ss.add(files( 'cpu.c', 'gdbstub.c', From patchwork Tue Aug 25 20:59:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248277 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3770332ils; Tue, 25 Aug 2020 14:09:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz88iQqHIeOOcnd4m0fq3Vw1xgocNRdxZ4738yEpZsQIeMrYyhpfKaXHGYA0HVg6QT1aJmz X-Received: by 2002:a25:e00e:: with SMTP id x14mr16914099ybg.263.1598389774580; Tue, 25 Aug 2020 14:09:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389774; cv=none; d=google.com; s=arc-20160816; b=PY0tFjnawAY2aKlVJiLO0MaTmwT46uKsUIL3Ilxn31MgTohW6nbfYlWyTfJfL9T1hm kblOM0oJbHPpp5GGA8zCvJfasGLAqOgOiCIT6wBDZF9zpxSpCstfGHogKC/aq/pJo+1Y I7ryTIIQX5Fz6QQbPOKaLsWuB0hQ3psi7RHsm+V4/5mlT0+CWd3cX43WhfFwHXGU61+X quQExybq7MP6f9JDVupqT55Pg4cvHn6nUkFBvsZsSK4TopH2NNnlMUixo0XzwxPKEDAN aEWO73KFdpqUpkWuymUMciZz/cuOjgmijicrbgVmszmfy+L0Ubd3MQr18FQKf6xRgIoH hW0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3tIkPYiOnQsOVuosyAmz/ThXo6OaMIkZVJ4NrFAYJ24=; b=XhuFqGaKhHjFHg9WbOGgPQts34xubT9YfloJV3VNmn9HbqSBwtTSOsmGMFMF6M7vf1 AF7//JcVx4ABRKLTmlqxVh6UCIDwAv7MBHMNxrGe8vahgJajkRe0ARwisch0PmVbcTfT 2sBhoVKGz0zZPQ0MbK5qghIty3e9PB2eKlzRNWZDO4Hjvlsr/ElaOyLK+U9Kjl4tLV5l YR6jZIsT+3IDEDoynIYQ8dtUeshYuTs8ZOAE3rwaOR+Iu7/fX0++/IUtAIBY9GdLyPVs Sj+YGCXeL/PdQrytkJBVRQdA+IuQ+og2eHud5ElIJbW6SRzaijF4srJclJvNeZ7mun8T CrKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d1Qixezz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 36/77] target/microblaze: Convert dec_add to decodetree Date: Tue, 25 Aug 2020 13:59:09 -0700 Message-Id: <20200825205950.730499-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Adds infrastrucure for translation of instructions, which could not be added before their first use. Cache a temporary which represents r0 as the immediate 0 value, or a sink. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 21 ++++ target/microblaze/translate.c | 185 +++++++++++++++++++++++++-------- 2 files changed, 165 insertions(+), 41 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 1ed9ca0731..c62f826bcc 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -16,3 +16,24 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +&typea rd ra rb +&typeb rd ra imm + +# Include any IMM prefix in the value reported. +%extimm 0:s16 !function=typeb_imm + +@typea ...... rd:5 ra:5 rb:5 ... .... .... &typea +@typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm + +### + +add 000000 ..... ..... ..... 000 0000 0000 @typea +addc 000010 ..... ..... ..... 000 0000 0000 @typea +addk 000100 ..... ..... ..... 000 0000 0000 @typea +addkc 000110 ..... ..... ..... 000 0000 0000 @typea + +addi 001000 ..... ..... ................ @typeb +addic 001010 ..... ..... ................ @typeb +addik 001100 ..... ..... ................ @typeb +addikc 001110 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e624093745..c3cc4db629 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; + TCGv_i32 r0; + bool r0_set; + /* Decoder. */ int type_b; uint32_t ir; @@ -81,6 +84,14 @@ typedef struct DisasContext { int abort_at_next_insn; } DisasContext; +static int typeb_imm(DisasContext *dc, int x) +{ + if (dc->tb_flags & IMM_FLAG) { + return deposit32(dc->ext_imm, 0, 16, x); + } + return x; +} + /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -176,11 +187,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) static int32_t dec_alu_typeb_imm(DisasContext *dc) { tcg_debug_assert(dc->type_b); - if (dc->tb_flags & IMM_FLAG) { - return dc->ext_imm | dc->imm; - } else { - return (int16_t)dc->imm; - } + return typeb_imm(dc, (int16_t)dc->imm); } static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) @@ -192,46 +199,134 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) return &cpu_R[dc->rb]; } -static void dec_add(DisasContext *dc) +static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { - unsigned int k, c; - TCGv_i32 cf; - - k = dc->opcode & 4; - c = dc->opcode & 2; - - /* Take care of the easy cases first. */ - if (k) { - /* k - keep carry, no need to update MSR. */ - /* If rd == r0, it's a nop. */ - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - - if (c) { - /* c - Add carry into the result. */ - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); - } + if (likely(reg != 0)) { + return cpu_R[reg]; + } + if (!dc->r0_set) { + if (dc->r0 == NULL) { + dc->r0 = tcg_temp_new_i32(); } - return; + tcg_gen_movi_i32(dc->r0, 0); + dc->r0_set = true; } - - /* From now on, we can assume k is zero. So we need to update MSR. */ - /* Extract carry. */ - cf = tcg_temp_new_i32(); - if (c) { - tcg_gen_mov_i32(cf, cpu_msr_c); - } else { - tcg_gen_movi_i32(cf, 0); - } - - gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - } - tcg_temp_free_i32(cf); + return dc->r0; } +static TCGv_i32 reg_for_write(DisasContext *dc, int reg) +{ + if (likely(reg != 0)) { + return cpu_R[reg]; + } + if (dc->r0 == NULL) { + dc->r0 = tcg_temp_new_i32(); + } + return dc->r0; +} + +static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, rb; + + if (arg->rd == 0 && !side_effects) { + return true; + } + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + rb = reg_for_read(dc, arg->rb); + fn(rd, ra, rb); + return true; +} + +static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects, + void (*fni)(TCGv_i32, TCGv_i32, int32_t)) +{ + TCGv_i32 rd, ra; + + if (arg->rd == 0 && !side_effects) { + return true; + } + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + fni(rd, ra, arg->imm); + return true; +} + +static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, imm; + + if (arg->rd == 0 && !side_effects) { + return true; + } + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + imm = tcg_const_i32(arg->imm); + + fn(rd, ra, imm); + + tcg_temp_free_i32(imm); + return true; +} + +#define DO_TYPEA(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ + { return do_typea(dc, a, SE, FN); } + +#define DO_TYPEBI(NAME, SE, FNI) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_imm(dc, a, SE, FNI); } + +#define DO_TYPEBV(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_val(dc, a, SE, FN); } + +/* No input carry, but output carry. */ +static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + + tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero); + + tcg_temp_free_i32(zero); +} + +/* Input and output carry. */ +static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero); + tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(zero); +} + +/* Input carry, but no output carry. */ +static void gen_addkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_add_i32(out, ina, inb); + tcg_gen_add_i32(out, out, cpu_msr_c); +} + +DO_TYPEA(add, true, gen_add) +DO_TYPEA(addc, true, gen_addc) +DO_TYPEA(addk, false, tcg_gen_add_i32) +DO_TYPEA(addkc, true, gen_addkc) + +DO_TYPEBV(addi, true, gen_add) +DO_TYPEBV(addic, true, gen_addc) +DO_TYPEBI(addik, false, tcg_gen_addi_i32) +DO_TYPEBV(addikc, true, gen_addkc) + static void dec_sub(DisasContext *dc) { unsigned int u, cmp, k, c; @@ -1488,7 +1583,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_ADD, dec_add}, {DEC_SUB, dec_sub}, {DEC_AND, dec_and}, {DEC_XOR, dec_xor}, @@ -1552,6 +1646,8 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; + dc->r0 = NULL; + dc->r0_set = false; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1600,6 +1696,13 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) if (!decode(dc, ir)) { old_decode(dc, ir); } + + if (dc->r0) { + tcg_temp_free_i32(dc->r0); + dc->r0 = NULL; + dc->r0_set = false; + } + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; tcg_gen_discard_i32(cpu_imm); From patchwork Tue Aug 25 20:59:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248290 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp5845ejn; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 37/77] target/microblaze: Convert dec_sub to decodetree Date: Tue, 25 Aug 2020 13:59:10 -0700 Message-Id: <20200825205950.730499-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use tcg_gen_add2_i32 for computing carry. This removes the last use of helper_carry, so remove that. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 1 - target/microblaze/insns.decode | 13 +++++ target/microblaze/op_helper.c | 16 ----- target/microblaze/translate.c | 104 ++++++++++++++++----------------- 4 files changed, 62 insertions(+), 72 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 9309142f8d..988abf7661 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) DEF_HELPER_2(cmpu, i32, i32, i32) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index c62f826bcc..3f5f7b1852 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -37,3 +37,16 @@ addi 001000 ..... ..... ................ @typeb addic 001010 ..... ..... ................ @typeb addik 001100 ..... ..... ................ @typeb addikc 001110 ..... ..... ................ @typeb + +cmp 000101 ..... ..... ..... 000 0000 0001 @typea +cmpu 000101 ..... ..... ..... 000 0000 0011 @typea + +rsub 000001 ..... ..... ..... 000 0000 0000 @typea +rsubc 000011 ..... ..... ..... 000 0000 0000 @typea +rsubk 000101 ..... ..... ..... 000 0000 0000 @typea +rsubkc 000111 ..... ..... ..... 000 0000 0000 @typea + +rsubi 001001 ..... ..... ................ @typeb +rsubic 001011 ..... ..... ................ @typeb +rsubik 001101 ..... ..... ................ @typeb +rsubikc 001111 ..... ..... ................ @typeb diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index decdca0fd8..9bb6a2ad76 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,17 +69,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) -{ - uint32_t cout = 0; - - if ((b == ~0) && cin) - cout = 1; - else if ((~0 - a) < (b + cin)) - cout = 1; - return cout; -} - uint32_t helper_cmp(uint32_t a, uint32_t b) { uint32_t t; @@ -100,11 +89,6 @@ uint32_t helper_cmpu(uint32_t a, uint32_t b) return t; } -uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) -{ - return compute_carry(a, b, cf); -} - static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { MicroBlazeCPU *cpu = env_archcpu(env); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c3cc4db629..98050f64b7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -327,63 +327,58 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) -static void dec_sub(DisasContext *dc) +DO_TYPEA(cmp, false, gen_helper_cmp) +DO_TYPEA(cmpu, false, gen_helper_cmpu) + +/* No input carry, but output carry. */ +static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { - unsigned int u, cmp, k, c; - TCGv_i32 cf, na; - - u = dc->imm & 2; - k = dc->opcode & 4; - c = dc->opcode & 2; - cmp = (dc->imm & 1) && (!dc->type_b) && k; - - if (cmp) { - if (dc->rd) { - if (u) - gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - else - gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - } - return; - } - - /* Take care of the easy cases first. */ - if (k) { - /* k - keep carry, no need to update MSR. */ - /* If rd == r0, it's a nop. */ - if (dc->rd) { - tcg_gen_sub_i32(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); - - if (c) { - /* c - Add carry into the result. */ - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); - } - } - return; - } - - /* From now on, we can assume k is zero. So we need to update MSR. */ - /* Extract carry. And complement a into na. */ - cf = tcg_temp_new_i32(); - na = tcg_temp_new_i32(); - if (c) { - tcg_gen_mov_i32(cf, cpu_msr_c); - } else { - tcg_gen_movi_i32(cf, 1); - } - - /* d = b + ~a + c. carry defaults to 1. */ - tcg_gen_not_i32(na, cpu_R[dc->ra]); - - gen_helper_carry(cpu_msr_c, na, *(dec_alu_op_b(dc)), cf); - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - } - tcg_temp_free_i32(cf); - tcg_temp_free_i32(na); + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_msr_c, inb, ina); + tcg_gen_sub_i32(out, inb, ina); } +/* Input and output carry. */ +static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_not_i32(tmp, ina); + tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero); + tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); + + tcg_temp_free_i32(zero); + tcg_temp_free_i32(tmp); +} + +/* No input or output carry. */ +static void gen_rsubk(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_sub_i32(out, inb, ina); +} + +/* Input carry, no output carry. */ +static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 nota = tcg_temp_new_i32(); + + tcg_gen_not_i32(nota, ina); + tcg_gen_add_i32(out, inb, nota); + tcg_gen_add_i32(out, out, cpu_msr_c); + + tcg_temp_free_i32(nota); +} + +DO_TYPEA(rsub, true, gen_rsub) +DO_TYPEA(rsubc, true, gen_rsubc) +DO_TYPEA(rsubk, false, gen_rsubk) +DO_TYPEA(rsubkc, true, gen_rsubkc) + +DO_TYPEBV(rsubi, true, gen_rsub) +DO_TYPEBV(rsubic, true, gen_rsubc) +DO_TYPEBV(rsubik, false, gen_rsubk) +DO_TYPEBV(rsubikc, true, gen_rsubkc) + static void dec_pattern(DisasContext *dc) { unsigned int mode; @@ -1583,7 +1578,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_SUB, dec_sub}, {DEC_AND, dec_and}, {DEC_XOR, dec_xor}, {DEC_OR, dec_or}, From patchwork Tue Aug 25 20:59:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248307 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp9563ejn; Tue, 25 Aug 2020 14:25:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwBYfVpLV2q98GGciWKRWgFncydnj51s0jKt7LQSfPGO6FXou0g2uP8SdiymYkKBEKS508e X-Received: by 2002:a25:7341:: with SMTP id o62mr18957712ybc.305.1598390713384; Tue, 25 Aug 2020 14:25:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390713; cv=none; d=google.com; s=arc-20160816; b=o0YQ13vMHVsq0s/QYvrkm/gLNXvo79i3sn14WJj1tzltKcGXxRsgpC8SbJ/eUIcWv9 pDZutinaveU3PKMHPE4v5pu8CJl+GKWKlWcynimpRGemkrPzCOnGu+22VXlgKodY50GB Upp0ghGKMnnVRS6mFzIvcNyOwZpcAVGnxJVcbYaf73boUQld9qD375ryj2drwS4RBstT TiB2KKAITIT8A0gzjIUF56g4UWPviXRJF0zyEpMO3FDqFJMkzDA+RPmoNJ6k5Rsyz5Qh 75MQzGIIo7JBIq7Rcp6bTTd8aLrM/h/Tg36s2qlKAGbQgHoTHlZMVmloodRmq/vYdxiv dpfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=028+vI/58nZnbjOmGLeS9QgMrm8aOm1Pu2VJuR4D8gY=; b=opMuzHAR3ZckMdNPXMwDOH/IUMSu/yFkXIKUtFqW3APybV0hcEbGPUyeten3IKW6I3 dvXtVdrEDdxZwTpuIuSnW83IaZyCo8zCuu/iIj618rxHm94mZfGQKGMQhmnQNcEMPXGY ccb5WFfsL8thRRNoxv44FtL+IpeezmZvdAS7OLcfh75MsjmqMLUoKQ/islXh/gkZ1686 S3TbtVUih7r+uSRJFMVtJZPDuTmF+RGKcHzFNLnza/xTV5uukfvV9V+3gXXxPnS3e4Fx svB4C4pkZYi09IbwloxqjjrWgswjR2DEPvaCspKNOuATJ95pB2mUcV5t5PqGfQ/sNXXE dkng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A857IRIF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 38/77] target/microblaze: Implement cmp and cmpu inline Date: Tue, 25 Aug 2020 13:59:11 -0700 Message-Id: <20200825205950.730499-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are simple enough operations; we do not need to call an out-of-line helper. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 -- target/microblaze/op_helper.c | 20 -------------------- target/microblaze/translate.c | 24 ++++++++++++++++++++++-- 3 files changed, 22 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 988abf7661..6f7f96421f 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,6 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_2(cmp, i32, i32, i32) -DEF_HELPER_2(cmpu, i32, i32, i32) DEF_HELPER_3(divs, i32, env, i32, i32) DEF_HELPER_3(divu, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 9bb6a2ad76..f976d112eb 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,26 +69,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -uint32_t helper_cmp(uint32_t a, uint32_t b) -{ - uint32_t t; - - t = b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t = (t & 0x7fffffff) | (b & 0x80000000); - return t; -} - -uint32_t helper_cmpu(uint32_t a, uint32_t b) -{ - uint32_t t; - - t = b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t = (t & 0x7fffffff) | (a & 0x80000000); - return t; -} - static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { MicroBlazeCPU *cpu = env_archcpu(env); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 98050f64b7..ce91645f05 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -327,8 +327,28 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) -DO_TYPEA(cmp, false, gen_helper_cmp) -DO_TYPEA(cmpu, false, gen_helper_cmpu) +static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt = tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt = tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +DO_TYPEA(cmp, false, gen_cmp) +DO_TYPEA(cmpu, false, gen_cmpu) /* No input carry, but output carry. */ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) From patchwork Tue Aug 25 20:59:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248313 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp10511ejn; Tue, 25 Aug 2020 14:27:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxpzwZ0YaSI9kq0/6blL281XNNqvUn5bXc8IjkQyBCsRQyglaYE0ymCWjj9PTKWLEfSTpnC X-Received: by 2002:a5b:744:: with SMTP id s4mr17916306ybq.26.1598390842740; Tue, 25 Aug 2020 14:27:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390842; cv=none; d=google.com; s=arc-20160816; b=GMrcWnQAkbGYzusaZdraE0O//xLoXPTCcfre+uzE/LdO1j/ZQbN2NZ9J+yOmDw280Z xOY3fZvFCRBFKIqFcEWieSCDjjDXnzoj5xEVbrhXMif9OKKUcO+6W4OT8fuVzvhYYvdX t8kV96PN53O8u7qqocR3OFRKfQpk0yFUWlYkCzG7HA0WUBBCi+rTCbLpv0oFmrNbnDor DVQPJZZuZLciIgN5+vh8FHbUYE2hEJ3hYoEStIs/P2QzRD0xL3LV1SUZXX4MWsamQ6kn N4n7nQEhPi4d6di2ZEp1h3sxtSJpQOFI4Jc6YkeTZ5FmB7/8PYvkx0ruCIeJsIFiB/cO LyPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SnN2rcoH8SEue8/YmUSsyA4G1cGVPVXaIp+iYJ1qNQA=; b=grGiK0/LdbjqgltuXOXZ5HCkp5vq7hRoEhNVHemanOcpU+SaS6NuDFDRCHu2nFcHUZ K52LywPPBPi6xnZJIelaDyLyMBKFTGJvS/knr5adOzOiZN5e6QAPQcHVxTSxwGMnSp54 Jeocgqb5252GCWHJ3L+UDIOVDVqim9atF+l/OSaAsMikQrlfkpG+8y1uqHiP7deQKv0z SZ2gnvKDPafVmpnnd5dG85RIxVMRwEPMQ7qk/+RD3/CMtXA0eM5nCe+ctVOAqPIBbdWm mf4NYniF35wM5QRumUSgJPiSqvN+Mv/yL2+3rSK/SYguBg8B+q6E8D4Xhe/rEkESQmfz q0gA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tqaRjjts; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 39/77] target/microblaze: Convert dec_pattern to decodetree Date: Tue, 25 Aug 2020 13:59:12 -0700 Message-Id: <20200825205950.730499-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 4 ++ target/microblaze/translate.c | 67 +++++++++------------------------- 2 files changed, 22 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 3f5f7b1852..8d3de039fb 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -41,6 +41,10 @@ addikc 001110 ..... ..... ................ @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea +pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea +pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea + rsub 000001 ..... ..... ..... 000 0000 0000 @typea rsubc 000011 ..... ..... ..... 000 0000 0000 @typea rsubk 000101 ..... ..... ..... 000 0000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ce91645f05..de2cf5b153 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -279,6 +279,10 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ { return do_typea(dc, a, SE, FN); } +#define DO_TYPEA_CFG(NAME, CFG, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ + { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } + #define DO_TYPEBI(NAME, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } @@ -350,6 +354,20 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); +} + +static void gen_pcmpne(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_NE, out, ina, inb); +} + +DO_TYPEA_CFG(pcmpbf, use_pcmp_instr, false, gen_helper_pcmpbf) +DO_TYPEA_CFG(pcmpeq, use_pcmp_instr, false, gen_pcmpeq) +DO_TYPEA_CFG(pcmpne, use_pcmp_instr, false, gen_pcmpne) + /* No input carry, but output carry. */ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { @@ -399,49 +417,10 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) -static void dec_pattern(DisasContext *dc) -{ - unsigned int mode; - - if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { - return; - } - - mode = dc->opcode & 3; - switch (mode) { - case 0: - /* pcmpbf. */ - if (dc->rd) - gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - if (dc->rd) { - tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - } - break; - case 3: - if (dc->rd) { - tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - } - break; - default: - cpu_abort(CPU(dc->cpu), - "unsupported pattern insn opcode=%x\n", dc->opcode); - break; - } -} - static void dec_and(DisasContext *dc) { unsigned int not; - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - not = dc->opcode & (1 << 1); if (!dc->rd) @@ -455,22 +434,12 @@ static void dec_and(DisasContext *dc) static void dec_or(DisasContext *dc) { - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - if (dc->rd) tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } static void dec_xor(DisasContext *dc) { - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - if (dc->rd) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } From patchwork Tue Aug 25 20:59:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248311 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp10425ejn; Tue, 25 Aug 2020 14:27:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwwbnJ0KlEeCmeddrEWV3g7CG1CzwvssRLJldy6Wdl7KxVKHEG4dXPJjjB7TwhPKsxLV0Ug X-Received: by 2002:a25:bf86:: with SMTP id l6mr15956286ybk.323.1598390832839; Tue, 25 Aug 2020 14:27:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390832; cv=none; d=google.com; s=arc-20160816; b=EcZukO0Mt0+XroPJgpuRKAd2S656ja6rbjrmXNM0NT00dAVbvI0L5bnYJh63X1U2qv O+yZrDYR66uxSqhyLzjjdKWA7UE6z9n7Umkqtfe8ReHdL6Vtj80ooYv+/muocrSTwEKP nPVK1j/k9kD/21vGBjrdPg5y9qkm+wOh6kcZskEtR+Z5J1pmj6eTyc5nr5ynEMdKV6DC DB49z540udvFJ11HUc03NqVEvijmsyd3uq/BQXJERfTxsNrIOYoeqjGLBz25rOyDh7qU oRE5LLIivOl3wWWMgAijyCfyDj7KvqaiR1vSHaSTRvjbATHnlhN5tmeAe9ikxIZbV4zl 7DxQ== ARC-Message-Signature: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 40/77] target/microblaze: Convert dec_and, dec_or, dec_xor to decodetree Date: Tue, 25 Aug 2020 13:59:13 -0700 Message-Id: <20200825205950.730499-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 12 ++++++++++ target/microblaze/translate.c | 44 ++++++++++++---------------------- 2 files changed, 27 insertions(+), 29 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 8d3de039fb..6b3cc9a182 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -38,9 +38,18 @@ addic 001010 ..... ..... ................ @typeb addik 001100 ..... ..... ................ @typeb addikc 001110 ..... ..... ................ @typeb +and 100001 ..... ..... ..... 000 0000 0000 @typea +andi 101001 ..... ..... ................ @typeb + +andn 100011 ..... ..... ..... 000 0000 0000 @typea +andni 101011 ..... ..... ................ @typeb + cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +or 100000 ..... ..... ..... 000 0000 0000 @typea +ori 101000 ..... ..... ................ @typeb + pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea @@ -54,3 +63,6 @@ rsubi 001001 ..... ..... ................ @typeb rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb + +xor 100010 ..... ..... ..... 000 0000 0000 @typea +xori 101010 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index de2cf5b153..5252790b09 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -331,6 +331,16 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) +static void gen_andni(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + tcg_gen_andi_i32(out, ina, ~imm); +} + +DO_TYPEA(and, false, tcg_gen_and_i32) +DO_TYPEBI(andi, false, tcg_gen_andi_i32) +DO_TYPEA(andn, false, tcg_gen_andc_i32) +DO_TYPEBI(andni, false, gen_andni) + static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 lt = tcg_temp_new_i32(); @@ -354,6 +364,9 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +DO_TYPEA(or, false, tcg_gen_or_i32) +DO_TYPEBI(ori, false, tcg_gen_ori_i32) + static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); @@ -417,32 +430,8 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) -static void dec_and(DisasContext *dc) -{ - unsigned int not; - - not = dc->opcode & (1 << 1); - - if (!dc->rd) - return; - - if (not) { - tcg_gen_andc_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - } else - tcg_gen_and_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - -static void dec_or(DisasContext *dc) -{ - if (dc->rd) - tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - -static void dec_xor(DisasContext *dc) -{ - if (dc->rd) - tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} +DO_TYPEA(xor, false, tcg_gen_xor_i32) +DO_TYPEBI(xori, false, tcg_gen_xori_i32) static void msr_read(DisasContext *dc, TCGv_i32 d) { @@ -1567,9 +1556,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_AND, dec_and}, - {DEC_XOR, dec_xor}, - {DEC_OR, dec_or}, {DEC_BIT, dec_bit}, {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, From patchwork Tue Aug 25 20:59:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248281 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp3632ejn; Tue, 25 Aug 2020 14:12:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxTaYmkja/J3y8byiFyI7GoCD/2n4wFSAieA8TU+w6XVtkkyF9n51LXpCVwSL68Bk4DCunS X-Received: by 2002:a25:84cd:: with SMTP id x13mr16709064ybm.425.1598389925781; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 41/77] target/microblaze: Convert dec_mul to decodetree Date: Tue, 25 Aug 2020 13:59:14 -0700 Message-Id: <20200825205950.730499-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 77 ++++++++++++++-------------------- 2 files changed, 37 insertions(+), 46 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 6b3cc9a182..65a8a53b54 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -47,6 +47,12 @@ andni 101011 ..... ..... ................ @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +mul 010000 ..... ..... ..... 000 0000 0000 @typea +mulh 010000 ..... ..... ..... 000 0000 0001 @typea +mulhu 010000 ..... ..... ..... 000 0000 0011 @typea +mulhsu 010000 ..... ..... ..... 000 0000 0010 @typea +muli 011000 ..... ..... ................ @typeb + or 100000 ..... ..... ..... 000 0000 0000 @typea ori 101000 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 5252790b09..dc6ea523b5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -287,6 +287,10 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } +#define DO_TYPEBI_CFG(NAME, CFG, SE, FNI) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return dc->cpu->cfg.CFG && do_typeb_imm(dc, a, SE, FNI); } + #define DO_TYPEBV(NAME, SE, FN) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_val(dc, a, SE, FN); } @@ -364,6 +368,33 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_muls2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +static void gen_mulhu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mulu2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +static void gen_mulhsu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mulsu2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +DO_TYPEA_CFG(mul, use_hw_mul, false, tcg_gen_mul_i32) +DO_TYPEA_CFG(mulh, use_hw_mul >= 2, false, gen_mulh) +DO_TYPEA_CFG(mulhu, use_hw_mul >= 2, false, gen_mulhu) +DO_TYPEA_CFG(mulhsu, use_hw_mul >= 2, false, gen_mulhsu) +DO_TYPEBI_CFG(muli, use_hw_mul, false, tcg_gen_muli_i32) + DO_TYPEA(or, false, tcg_gen_or_i32) DO_TYPEBI(ori, false, tcg_gen_ori_i32) @@ -638,51 +669,6 @@ static void dec_msr(DisasContext *dc) } } -/* Multiplier unit. */ -static void dec_mul(DisasContext *dc) -{ - TCGv_i32 tmp; - unsigned int subcode; - - if (trap_illegal(dc, !dc->cpu->cfg.use_hw_mul)) { - return; - } - - subcode = dc->imm & 3; - - if (dc->type_b) { - tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - return; - } - - /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ - if (subcode >= 1 && subcode <= 3 && dc->cpu->cfg.use_hw_mul < 2) { - /* nop??? */ - } - - tmp = tcg_temp_new_i32(); - switch (subcode) { - case 0: - tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 1: - tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 3: - tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - default: - cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); - break; - } - tcg_temp_free_i32(tmp); -} - /* Div unit. */ static void dec_div(DisasContext *dc) { @@ -1565,7 +1551,6 @@ static struct decoder_info { {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_FPU, dec_fpu}, - {DEC_MUL, dec_mul}, {DEC_DIV, dec_div}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, From patchwork Tue Aug 25 20:59:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248316 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp11556ejn; Tue, 25 Aug 2020 14:29:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx66XR3UhrfBuY1Vi7zQPj4+zA1vHA27EdosfPEXKiLbB7nBcacIe1zH0wrDvue3T3oCu9B X-Received: by 2002:a5b:b03:: with SMTP id z3mr15917501ybp.341.1598390994730; Tue, 25 Aug 2020 14:29:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390994; cv=none; d=google.com; s=arc-20160816; b=SwfhMsmpEFc3mv/1GQ83k+EAfWtyTT3Wkmtz/Q2xNctgQkKUnB0Tpe1n0YettFGJSQ Bw4q9Y1l9KclcakC8/BmU1oWm7zJHzioqUZP30t+5Go1zFcI8xmlZvmOvv4O688nuNnI iyyPFLAoDk5CndJbR2WqvrG2/sImqr5ssL7bTYfIiuMX92IKEHQHyJ1wGkIweoxL5y1w Yy3eDxiH4EFiHJjh1AddaSgJA4+GF5VQx+x7Tc+Q4+UJIpBb8TXfGoi5IvyzzGVVzSUH QraI3Q6xN+plyTYfYct3bPq2pNLyuEz4yJXnsZvshCm7TtqCduDuZ4hz9mmCLqOzEzMM QaQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=k4SMKMjkRRkG1Mjn2l2ewz/RkrM2zbTl1em1p59D3mo=; b=ycB9Np5895OPael7lrzqUEQ9tD53oDoGM5J3JgyLydEvR0jBZtHMvMuLduKa4vdvVV 7O7wvA6B73EvNnAOIwjPBwYDRk7sK4xG1sIGwjuLPyBaYdica2gqh4pFsucyEXOZhKeL y/IsxE6bv7Z+Oi8TkHERcb+5GM2ALC3q93+N5emGL0Mqp/cRD8/IxLnwJ96Vb5J2hiWf Rz8vmD7SyxvhX/BMaa+GAzz5KNdCl3OwIXJHqghcGC43TA7dID8PiE7rCarUE72BjaZx pj9nywruf/aw4Tw6WN+DmdsOCTLmUkyE1eOpUuDk6DVm8CbkJvOCOGR6f/1mGx6Ni2y4 z2Pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XOMZ4l05; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 42/77] target/microblaze: Convert dec_div to decodetree Date: Tue, 25 Aug 2020 13:59:15 -0700 Message-Id: <20200825205950.730499-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 +++ target/microblaze/translate.c | 35 +++++++++++++--------------------- 2 files changed, 16 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 65a8a53b54..18619e923e 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -47,6 +47,9 @@ andni 101011 ..... ..... ................ @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +idiv 010010 ..... ..... ..... 000 0000 0000 @typea +idivu 010010 ..... ..... ..... 000 0000 0010 @typea + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index dc6ea523b5..1d54ea02f0 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -368,6 +368,19 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + gen_helper_divs(out, cpu_env, inb, ina); +} + +static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + gen_helper_divu(out, cpu_env, inb, ina); +} + +DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) +DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) + static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp = tcg_temp_new_i32(); @@ -669,27 +682,6 @@ static void dec_msr(DisasContext *dc) } } -/* Div unit. */ -static void dec_div(DisasContext *dc) -{ - unsigned int u; - - u = dc->imm & 2; - - if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { - return; - } - - if (u) - gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), - cpu_R[dc->ra]); - else - gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), - cpu_R[dc->ra]); - if (!dc->rd) - tcg_gen_movi_i32(cpu_R[dc->rd], 0); -} - static void dec_barrel(DisasContext *dc) { TCGv_i32 t0; @@ -1551,7 +1543,6 @@ static struct decoder_info { {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_FPU, dec_fpu}, - {DEC_DIV, dec_div}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} From patchwork Tue Aug 25 20:59:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248286 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp4873ejn; Tue, 25 Aug 2020 14:14:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJymcAHaSHbQoHQG1+bU5ZdSsiK+uQR6VjaY4101zRTpLi6+r/mlrrAbZIFuU/a8sTE+YdF5 X-Received: by 2002:a05:6902:511:: with SMTP id x17mr16203825ybs.66.1598390083885; Tue, 25 Aug 2020 14:14:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390083; cv=none; d=google.com; s=arc-20160816; b=LSYJu1+RRLo8spnrjbIdeOH0RKIV804+24J5//VdcHcM5Ghb8aesR65ant53tgwIj3 J5IiefSaC+Pwl44xuLRaiwcJw6+NXp0rjWAKlPnmYukOTpqvAlg4PKKzKWH1a9J2pJ4b GiAdEkkuvxnMaOrtSTRMt4DY9y4ZRfxN/XD2GC0immBb9gomNxXXoipt4Ulf1eAKyReg nJ1E3tmOUWp3igm0F6mShtumHgONai8KB/xanLKNd3BFWwgr9XBrSUSW8a0eoqhQBWNP pHXyLNbRJ9E8huj2TzmuomzQ1R4WRJdkdPeryGIt5mvRyW9verhxeBCDfwhSB4IZrq4L ygig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bQC2NsHcUulzW6D5RhH+hzBIgYR+xbZNPdmPEiO9k08=; b=aepq7ZVAtpsVrEdin/Ja35CsQLAQwRVVSLlXXXRw2Z2vgILQzmZ0BZ+J+E3rHWnAkk 35wnfqmHzJISZUxlLEnVkvHgiQXfKN2+aNQj5sS0Cqxj6yXRQbNCAYZFbcqi7Or4P+Pe CDrr2TvcLus+4vA0DAeLu+UksOJYAqEun1QEUyxJYdflHqaIrWKOEOGkzopQXMBacihi R+vZaCY5iDMtnZFIltQwFQOwfa89wQujtzyL905OtPDFzrpvSuY+WtPCeb9IhJesSqFq /HTdbcM7Tuk1JpKTurm8E6mWMVKxaM9BE/E6u0z34ngX1Gr03ENbTA7EFG+TSJYeG/QS g2Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QlQW0mth; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 43/77] target/microblaze: Unwind properly when raising divide-by-zero Date: Tue, 25 Aug 2020 13:59:16 -0700 Message-Id: <20200825205950.730499-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Restore the correct pc when raising divide-by-zero. Also, the MSR[DZO] bit is sticky -- it is not cleared with a successful divide. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 4 ++-- target/microblaze/op_helper.c | 23 ++++++++++++----------- 2 files changed, 14 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 6f7f96421f..79e1e8ecc7 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,7 +1,7 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_3(divs, i32, env, i32, i32) -DEF_HELPER_3(divu, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_3(fadd, i32, env, i32, i32) DEF_HELPER_3(frsub, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f976d112eb..d99d98051a 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,26 +69,27 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) +static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t ra) { - MicroBlazeCPU *cpu = env_archcpu(env); - - if (b == 0) { + if (unlikely(b == 0)) { env->msr |= MSR_DZ; - if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { + if ((env->msr & MSR_EE) && + env_archcpu(env)->cfg.div_zero_exception) { + CPUState *cs = env_cpu(env); + env->esr = ESR_EC_DIVZERO; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); } - return 0; + return false; } - env->msr &= ~MSR_DZ; - return 1; + return true; } uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(env, a, b)) { + if (!check_divz(env, a, b, GETPC())) { return 0; } return (int32_t)a / (int32_t)b; @@ -96,7 +97,7 @@ uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(env, a, b)) { + if (!check_divz(env, a, b, GETPC())) { return 0; } return a / b; From patchwork Tue Aug 25 20:59:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248289 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp5829ejn; Tue, 25 Aug 2020 14:16:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAWlxdUQSgl0eClt0WnHQZnsuXakdfJCc15xar6ZR9urFwKMNcdoVvy9aytFC2YNRfnuYj X-Received: by 2002:a25:2415:: with SMTP id k21mr17509527ybk.156.1598390208628; Tue, 25 Aug 2020 14:16:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390208; cv=none; d=google.com; s=arc-20160816; b=Uj/ahSoiJ0bWu1H8EMALsxj45iS+pXXYcEkpi1V7p0Kp0LmCwMcrYKS6/P+yqGzcmv 9ja3b2dMmwRCH16K1F2ssFpXJZOelRq0oO/dnrh4oV9uopPEz0qtGCYS84Iavse/AxBD jjn9NwxPyL+nqPthhd9PXCnwX7XmPUyrXGgjFd3pWZpQ0uvCZw6gx4pjlSKJcWsHx0me Vdmy/uwWa2Zv/D5IAl+XERgRIbPECShCxGg/A6EXQJYUxEMzrlamwLECNwD55auQUCiB q/pTAiv/K7onDBP1shKvoiEj/+JEuFBvUjeg3q+D8zsAbeHsXtVnHO3eqB+Vy/lyxpsi nPlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EBVpcdmGEzyJpy5TxBqmLFo/yQsChKNTx1tPZX/BrS4=; b=Fny1bwjLPb0PX5e/V/aNZcibYRi/cglW0gcwt66wVSC29F2kHtDVWVXANEWqnLnnmT Z392PAFby4gFP8vlvewyK7ZKCrxwRATQXfpnM7TCXT6Pa1gMHt0szu03FJ8pAKRU1Ei6 jK3rdVIQYrVkBlzfZrAErXn5RLdW2S5buZ39kUGzG7ASTJ2W4PInEWxzKSjIkyxfkH4r HWoJxeTHPmcVqY2Qp/u2uiF/ZNODwIffa2FkM8WwJ2xbmMB7ipSJZp0sII5SxQulmQB1 rUdoMnSXcPhVfC3NCynwh05ILqx4Y3838dxrf3V83qDFI94udqnYPXEnAcNt9fd0q1FU RfvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G9oMrc3T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 44/77] target/microblaze: Convert dec_bit to decodetree Date: Tue, 25 Aug 2020 13:59:17 -0700 Message-Id: <20200825205950.730499-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 +++++ target/microblaze/translate.c | 148 +++++++++++++++++---------------- 2 files changed, 95 insertions(+), 73 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 18619e923e..5666b381b9 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -17,6 +17,7 @@ # License along with this library; if not, see . # +&typea0 rd ra &typea rd ra rb &typeb rd ra imm @@ -26,6 +27,9 @@ @typea ...... rd:5 ra:5 rb:5 ... .... .... &typea @typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm +# Officially typea, but with rb==0, which is not used. +@typea0 ...... rd:5 ra:5 ................ &typea0 + ### add 000000 ..... ..... ..... 000 0000 0000 @typea @@ -44,6 +48,8 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +clz 100100 ..... ..... 00000 000 1110 0000 @typea0 + cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea @@ -73,5 +79,19 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +sext8 100100 ..... ..... 00000 000 0110 0000 @typea0 +sext16 100100 ..... ..... 00000 000 0110 0001 @typea0 + +sra 100100 ..... ..... 00000 000 0000 0001 @typea0 +src 100100 ..... ..... 00000 000 0010 0001 @typea0 +srl 100100 ..... ..... 00000 000 0100 0001 @typea0 + +swapb 100100 ..... ..... 00000 001 1110 0000 @typea0 +swaph 100100 ..... ..... 00000 001 1110 0010 @typea0 + +# Cache operations have no effect in qemu: discard the arguments. +wdic 100100 00000 ----- ----- -00 -11- 01-0 # wdc +wdic 100100 00000 ----- ----- 000 0110 1000 # wic + xor 100010 ..... ..... ..... 000 0000 0000 @typea xori 101010 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 1d54ea02f0..10ae369cb0 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -241,6 +241,21 @@ static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, return true; } +static bool do_typea0(DisasContext *dc, arg_typea0 *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra; + + if (arg->rd == 0 && !side_effects) { + return true; + } + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + fn(rd, ra); + return true; +} + static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects, void (*fni)(TCGv_i32, TCGv_i32, int32_t)) { @@ -283,6 +298,14 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } +#define DO_TYPEA0(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ + { return do_typea0(dc, a, SE, FN); } + +#define DO_TYPEA0_CFG(NAME, CFG, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ + { return dc->cpu->cfg.CFG && do_typea0(dc, a, SE, FN); } + #define DO_TYPEBI(NAME, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } @@ -345,6 +368,13 @@ DO_TYPEBI(andi, false, tcg_gen_andi_i32) DO_TYPEA(andn, false, tcg_gen_andc_i32) DO_TYPEBI(andni, false, gen_andni) +static void gen_clz(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_clzi_i32(out, ina, 32); +} + +DO_TYPEA0_CFG(clz, use_pcmp_instr, false, gen_clz) + static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 lt = tcg_temp_new_i32(); @@ -474,6 +504,51 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) +DO_TYPEA0(sext8, false, tcg_gen_ext8s_i32) +DO_TYPEA0(sext16, false, tcg_gen_ext16s_i32) + +static void gen_sra(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_sari_i32(out, ina, 1); +} + +static void gen_src(TCGv_i32 out, TCGv_i32 ina) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_mov_i32(tmp, cpu_msr_c); + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_extract2_i32(out, ina, tmp, 1); + + tcg_temp_free_i32(tmp); +} + +static void gen_srl(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_shri_i32(out, ina, 1); +} + +DO_TYPEA0(sra, false, gen_sra) +DO_TYPEA0(src, false, gen_src) +DO_TYPEA0(srl, false, gen_srl) + +static void gen_swaph(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_rotri_i32(out, ina, 16); +} + +DO_TYPEA0(swapb, false, tcg_gen_bswap32_i32) +DO_TYPEA0(swaph, false, gen_swaph) + +static bool trans_wdic(DisasContext *dc, arg_wdic *a) +{ + /* Cache operations are nops: only check for supervisor mode. */ + trap_userspace(dc, true); + return true; +} + DO_TYPEA(xor, false, tcg_gen_xor_i32) DO_TYPEBI(xori, false, tcg_gen_xori_i32) @@ -740,78 +815,6 @@ static void dec_barrel(DisasContext *dc) } } -static void dec_bit(DisasContext *dc) -{ - CPUState *cs = CPU(dc->cpu); - TCGv_i32 t0; - unsigned int op; - - op = dc->ir & ((1 << 9) - 1); - switch (op) { - case 0x21: - /* src. */ - t0 = tcg_temp_new_i32(); - - tcg_gen_shli_i32(t0, cpu_msr_c, 31); - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); - if (dc->rd) { - tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); - } - tcg_temp_free_i32(t0); - break; - - case 0x1: - case 0x41: - /* srl. */ - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); - if (dc->rd) { - if (op == 0x41) - tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - else - tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - } - break; - case 0x60: - tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x61: - tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x64: - case 0x66: - case 0x74: - case 0x76: - /* wdc. */ - trap_userspace(dc, true); - break; - case 0x68: - /* wic. */ - trap_userspace(dc, true); - break; - case 0xe0: - if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { - return; - } - if (dc->cpu->cfg.use_pcmp_instr) { - tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); - } - break; - case 0x1e0: - /* swapb */ - tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x1e2: - /*swaph */ - tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); - break; - default: - cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", - (uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->rb); - break; - } -} - static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { @@ -1534,7 +1537,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BIT, dec_bit}, {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, {DEC_ST, dec_store}, From patchwork Tue Aug 25 20:59:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248314 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp11245ejn; Tue, 25 Aug 2020 14:29:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3psBHYN2XSRTRBDO4K0gtsylmbJja5NmaDYzsjP1f7xURUvWbekhqfuRBK7AOpjsabDW0 X-Received: by 2002:a25:1fd5:: with SMTP id f204mr18228464ybf.236.1598390946896; Tue, 25 Aug 2020 14:29:06 -0700 (PDT) ARC-Seal: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 45/77] target/microblaze: Convert dec_barrel to decodetree Date: Tue, 25 Aug 2020 13:59:18 -0700 Message-Id: <20200825205950.730499-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 ++++++ target/microblaze/translate.c | 125 +++++++++++++++++---------------- 2 files changed, 86 insertions(+), 59 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 5666b381b9..31e50549ea 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -30,6 +30,15 @@ # Officially typea, but with rb==0, which is not used. @typea0 ...... rd:5 ra:5 ................ &typea0 +# Officially typeb, but any immediate extension is unused. +@typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb + +# For convenience, extract the two imm_w/imm_s fields, then pack +# them back together as "imm". Doing this makes it easiest to +# match the required zero at bit 5. +%ieimm 6:5 0:5 +@typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=%ieimm + ### add 000000 ..... ..... ..... 000 0000 0000 @typea @@ -48,6 +57,17 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +bsrl 010001 ..... ..... ..... 000 0000 0000 @typea +bsra 010001 ..... ..... ..... 010 0000 0000 @typea +bsll 010001 ..... ..... ..... 100 0000 0000 @typea + +bsrli 011001 ..... ..... 00000 000000 ..... @typeb_bs +bsrai 011001 ..... ..... 00000 010000 ..... @typeb_bs +bslli 011001 ..... ..... 00000 100000 ..... @typeb_bs + +bsefi 011001 ..... ..... 01000 .....0 ..... @typeb_ie +bsifi 011001 ..... ..... 10000 .....0 ..... @typeb_ie + clz 100100 ..... ..... 00000 000 1110 0000 @typea0 cmp 000101 ..... ..... ..... 000 0000 0001 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 10ae369cb0..8fdd03fb5a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -368,6 +368,72 @@ DO_TYPEBI(andi, false, tcg_gen_andi_i32) DO_TYPEA(andn, false, tcg_gen_andc_i32) DO_TYPEBI(andni, false, gen_andni) +static void gen_bsra(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_sar_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_shr_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_shl_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsefi(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + /* Note that decodetree has extracted and reassembled imm_w/imm_s. */ + int imm_w = extract32(imm, 5, 5); + int imm_s = extract32(imm, 0, 5); + + if (imm_w + imm_s > 32 || imm_w == 0) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", + imm_w, imm_s); + } else { + tcg_gen_extract_i32(out, ina, imm_s, imm_w); + } +} + +static void gen_bsifi(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + /* Note that decodetree has extracted and reassembled imm_w/imm_s. */ + int imm_w = extract32(imm, 5, 5); + int imm_s = extract32(imm, 0, 5); + int width = imm_w - imm_s + 1; + + if (imm_w < imm_s) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", + imm_w, imm_s); + } else { + tcg_gen_deposit_i32(out, out, ina, imm_s, width); + } +} + +DO_TYPEA_CFG(bsra, use_barrel, false, gen_bsra) +DO_TYPEA_CFG(bsrl, use_barrel, false, gen_bsrl) +DO_TYPEA_CFG(bsll, use_barrel, false, gen_bsll) + +DO_TYPEBI_CFG(bsrai, use_barrel, false, tcg_gen_sari_i32) +DO_TYPEBI_CFG(bsrli, use_barrel, false, tcg_gen_shri_i32) +DO_TYPEBI_CFG(bslli, use_barrel, false, tcg_gen_shli_i32) + +DO_TYPEBI_CFG(bsefi, use_barrel, false, gen_bsefi) +DO_TYPEBI_CFG(bsifi, use_barrel, false, gen_bsifi) + static void gen_clz(TCGv_i32 out, TCGv_i32 ina) { tcg_gen_clzi_i32(out, ina, 32); @@ -757,64 +823,6 @@ static void dec_msr(DisasContext *dc) } } -static void dec_barrel(DisasContext *dc) -{ - TCGv_i32 t0; - unsigned int imm_w, imm_s; - bool s, t, e = false, i = false; - - if (trap_illegal(dc, !dc->cpu->cfg.use_barrel)) { - return; - } - - if (dc->type_b) { - /* Insert and extract are only available in immediate mode. */ - i = extract32(dc->imm, 15, 1); - e = extract32(dc->imm, 14, 1); - } - s = extract32(dc->imm, 10, 1); - t = extract32(dc->imm, 9, 1); - imm_w = extract32(dc->imm, 6, 5); - imm_s = extract32(dc->imm, 0, 5); - - if (e) { - if (imm_w + imm_s > 32 || imm_w == 0) { - /* These inputs have an undefined behavior. */ - qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", - imm_w, imm_s); - } else { - tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w); - } - } else if (i) { - int width = imm_w - imm_s + 1; - - if (imm_w < imm_s) { - /* These inputs have an undefined behavior. */ - qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", - imm_w, imm_s); - } else { - tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra], - imm_s, width); - } - } else { - t0 = tcg_temp_new_i32(); - - tcg_gen_mov_i32(t0, *(dec_alu_op_b(dc))); - tcg_gen_andi_i32(t0, t0, 31); - - if (s) { - tcg_gen_shl_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } else { - if (t) { - tcg_gen_sar_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } else { - tcg_gen_shr_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } - } - tcg_temp_free_i32(t0); - } -} - static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { @@ -1537,7 +1545,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, {DEC_ST, dec_store}, {DEC_IMM, dec_imm}, From patchwork Tue Aug 25 20:59:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248319 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp12380ejn; Tue, 25 Aug 2020 14:31:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzdCNlliSn4rdBnTGkTtr90Z+QstD3ddoqfX/tC0DDXrArnynhSEtKnHAzROtao2T6ffU7e X-Received: by 2002:a25:bf86:: with SMTP id l6mr15977888ybk.323.1598391089350; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 46/77] target/microblaze: Convert dec_imm to decodetree Date: Tue, 25 Aug 2020 13:59:19 -0700 Message-Id: <20200825205950.730499-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 2 ++ target/microblaze/translate.c | 18 +++++++++--------- 2 files changed, 11 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 31e50549ea..a7eb7d4e6f 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -76,6 +76,8 @@ cmpu 000101 ..... ..... ..... 000 0000 0011 @typea idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea +imm 101100 00000 00000 imm:16 + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8fdd03fb5a..c1d19f4678 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -477,6 +477,15 @@ static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) +static bool trans_imm(DisasContext *dc, arg_imm *arg) +{ + dc->ext_imm = arg->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); + dc->tb_flags |= IMM_FLAG; + dc->clear_imm = 0; + return true; +} + static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp = tcg_temp_new_i32(); @@ -834,14 +843,6 @@ static inline void sync_jmpstate(DisasContext *dc) } } -static void dec_imm(DisasContext *dc) -{ - dc->ext_imm = dc->imm << 16; - tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags |= IMM_FLAG; - dc->clear_imm = 0; -} - static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) { /* Should be set to true if r1 is used by loadstores. */ @@ -1547,7 +1548,6 @@ static struct decoder_info { } decinfo[] = { {DEC_LD, dec_load}, {DEC_ST, dec_store}, - {DEC_IMM, dec_imm}, {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, From patchwork Tue Aug 25 20:59:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248295 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp7080ejn; Tue, 25 Aug 2020 14:19:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5JHx1m21qKLf0DHCY/wrfOcJuZxu8YpAa6BD7bLFCvuspvRngtGmFEmEr12nM8DuRv+M5 X-Received: by 2002:a25:7341:: with SMTP id o62mr18925271ybc.305.1598390369432; Tue, 25 Aug 2020 14:19:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390369; cv=none; d=google.com; s=arc-20160816; b=pxc1gDo5iCNNUnKwJtyoPsdmknVIH7nrpVbFqERG2fT8zAV2c9faa8F1mT8o8qMMP2 iqWJUg10WafTtzxik8N7zYeCRvn87M0+F9sCeiMl5gMF/fpkkXnRrz4wb291bem5n0Vr VNRqQUqRgRYJK7gyv/qM+q57sRS8bLnuHlFiJExxQ7tH6x+CF+8/Gm9gXUtj7TSxptbL 2lZg28bQl/tqQ1vqho4cThEoTiOmyzzvZXwGSyYLmWhNbkmEa2wV+3oCIXpgIuK6ZSKH m//17LTBdakYHTWPte9Ms4HJiaeeH58xC1YnFvB51q/GL7k/pv1sFV138QfmBPlnNMy4 9qnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=j79ljoP5zzbkRewQNHGjmrrLK+0Gv9JhkSWBpicBIVs=; b=CDkVVSHZWm8UjdM4EfphCqoR5QyzOu7tYz9C63DUdYZBg1EeRiaV6QbLOaOdy6NSMn gw3x1nBPUWuKla7EUTz1Okwn2FRDojFFtP7o3Au6/98jes/hN2JtPZfbWaI94T5FxlHj 6ew7r8f8wJEoD7SZITTPGdbqLEgXlvHfzZWLR2q/4HM/Mk1ID53Bfi4yDxH4TpyoTava JiOfOBtUq/p1q185I5YxjWKbs7GCAT3iSQtrHAcKtH3wEuK3pdkUgzsFWysCn5acY7Hs BA0GF1iw+WvDOaB9PxrSs9prjU+WccWkZo/ErCp8lyDVFDsngJF+upWeepwOnGYJ0J75 itNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ULTV3v1R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 47/77] target/microblaze: Convert dec_fpu to decodetree Date: Tue, 25 Aug 2020 13:59:20 -0700 Message-Id: <20200825205950.730499-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The current dec_check_fpuv2 test, raising an FPU exception for an unimplemented instruction, appears to be contradictory to the manual. Drop that and merely check use_fpu == 2. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 19 +++++ target/microblaze/translate.c | 152 +++++++++------------------------ 2 files changed, 60 insertions(+), 111 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index a7eb7d4e6f..ea6743c7e5 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -73,6 +73,25 @@ clz 100100 ..... ..... 00000 000 1110 0000 @typea0 cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea +fadd 010110 ..... ..... ..... 0000 000 0000 @typea +frsub 010110 ..... ..... ..... 0001 000 0000 @typea +fmul 010110 ..... ..... ..... 0010 000 0000 @typea +fdiv 010110 ..... ..... ..... 0011 000 0000 @typea +fcmp_un 010110 ..... ..... ..... 0100 000 0000 @typea +fcmp_lt 010110 ..... ..... ..... 0100 001 0000 @typea +fcmp_eq 010110 ..... ..... ..... 0100 010 0000 @typea +fcmp_le 010110 ..... ..... ..... 0100 011 0000 @typea +fcmp_gt 010110 ..... ..... ..... 0100 100 0000 @typea +fcmp_ne 010110 ..... ..... ..... 0100 101 0000 @typea +fcmp_ge 010110 ..... ..... ..... 0100 110 0000 @typea + +# Note that flt and fint, unlike fsqrt, are documented as having the RB +# operand which is unused. So allow the field to be non-zero but discard +# the value and treat as 2-operand insns. +flt 010110 ..... ..... ----- 0101 000 0000 @typea0 +fint 010110 ..... ..... ----- 0110 000 0000 @typea0 +fsqrt 010110 ..... ..... 00000 0111 000 0000 @typea0 + idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c1d19f4678..7d1ada7aad 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -318,6 +318,14 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_val(dc, a, SE, FN); } +#define ENV_WRAPPER2(NAME, HELPER) \ + static void NAME(TCGv_i32 out, TCGv_i32 ina) \ + { HELPER(out, cpu_env, ina); } + +#define ENV_WRAPPER3(NAME, HELPER) \ + static void NAME(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) \ + { HELPER(out, cpu_env, ina, inb); } + /* No input carry, but output carry. */ static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { @@ -464,6 +472,39 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) +ENV_WRAPPER3(gen_fadd, gen_helper_fadd) +ENV_WRAPPER3(gen_frsub, gen_helper_frsub) +ENV_WRAPPER3(gen_fmul, gen_helper_fmul) +ENV_WRAPPER3(gen_fdiv, gen_helper_fdiv) +ENV_WRAPPER3(gen_fcmp_un, gen_helper_fcmp_un) +ENV_WRAPPER3(gen_fcmp_lt, gen_helper_fcmp_lt) +ENV_WRAPPER3(gen_fcmp_eq, gen_helper_fcmp_eq) +ENV_WRAPPER3(gen_fcmp_le, gen_helper_fcmp_le) +ENV_WRAPPER3(gen_fcmp_gt, gen_helper_fcmp_gt) +ENV_WRAPPER3(gen_fcmp_ne, gen_helper_fcmp_ne) +ENV_WRAPPER3(gen_fcmp_ge, gen_helper_fcmp_ge) + +DO_TYPEA_CFG(fadd, use_fpu, true, gen_fadd) +DO_TYPEA_CFG(frsub, use_fpu, true, gen_frsub) +DO_TYPEA_CFG(fmul, use_fpu, true, gen_fmul) +DO_TYPEA_CFG(fdiv, use_fpu, true, gen_fdiv) +DO_TYPEA_CFG(fcmp_un, use_fpu, true, gen_fcmp_un) +DO_TYPEA_CFG(fcmp_lt, use_fpu, true, gen_fcmp_lt) +DO_TYPEA_CFG(fcmp_eq, use_fpu, true, gen_fcmp_eq) +DO_TYPEA_CFG(fcmp_le, use_fpu, true, gen_fcmp_le) +DO_TYPEA_CFG(fcmp_gt, use_fpu, true, gen_fcmp_gt) +DO_TYPEA_CFG(fcmp_ne, use_fpu, true, gen_fcmp_ne) +DO_TYPEA_CFG(fcmp_ge, use_fpu, true, gen_fcmp_ge) + +ENV_WRAPPER2(gen_flt, gen_helper_flt) +ENV_WRAPPER2(gen_fint, gen_helper_fint) +ENV_WRAPPER2(gen_fsqrt, gen_helper_fsqrt) + +DO_TYPEA0_CFG(flt, use_fpu >= 2, true, gen_flt) +DO_TYPEA0_CFG(fint, use_fpu >= 2, true, gen_fint) +DO_TYPEA0_CFG(fsqrt, use_fpu >= 2, true, gen_fsqrt) + +/* Does not use ENV_WRAPPER3, because arguments are swapped as well. */ static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { gen_helper_divs(out, cpu_env, inb, ina); @@ -1389,116 +1430,6 @@ static void dec_rts(DisasContext *dc) tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } -static int dec_check_fpuv2(DisasContext *dc) -{ - if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { - gen_raise_hw_excp(dc, ESR_EC_FPU); - } - return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; -} - -static void dec_fpu(DisasContext *dc) -{ - unsigned int fpu_insn; - - if (trap_illegal(dc, !dc->cpu->cfg.use_fpu)) { - return; - } - - fpu_insn = (dc->ir >> 7) & 7; - - switch (fpu_insn) { - case 0: - gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 1: - gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 2: - gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 3: - gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 4: - switch ((dc->ir >> 4) & 7) { - case 0: - gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 1: - gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 3: - gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 4: - gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 5: - gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 6: - gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - default: - qemu_log_mask(LOG_UNIMP, - "unimplemented fcmp fpu_insn=%x pc=%x" - " opc=%x\n", - fpu_insn, (uint32_t)dc->base.pc_next, - dc->opcode); - dc->abort_at_next_insn = 1; - break; - } - break; - - case 5: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - case 6: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - case 7: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - default: - qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" - " opc=%x\n", - fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode); - dc->abort_at_next_insn = 1; - break; - } -} - static void dec_null(DisasContext *dc) { if (trap_illegal(dc, true)) { @@ -1551,7 +1482,6 @@ static struct decoder_info { {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, - {DEC_FPU, dec_fpu}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} From patchwork Tue Aug 25 20:59:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248321 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp13707ejn; Tue, 25 Aug 2020 14:34:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwN9TecdN+otib8svSEoxfIE3W2y1NE3jjCaS+P62m8tVnrqvu1WYuUqth7T5FYFNsIVjgl X-Received: by 2002:a25:c60b:: with SMTP id k11mr16346860ybf.482.1598391272906; Tue, 25 Aug 2020 14:34:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391272; cv=none; d=google.com; s=arc-20160816; b=mDmxKtIloL0RmMV+WFY7vTuqMd2USMBROm0H2RHNXYGBHQZ44Co5ehwgquPxtXGyyW aReu0O4QnRvp+jsB8hrUzfzqlDzrzgVYAYQsmhs9j2Aor6YUgB3DCw+R2GjJIlOibD6k 3noBxTssKfm4x17BbQ+KC3v2gzmQpylQ12A6w9Eka6uGfIpwckwh6uLC/TcBJ6xogk7D dX6dcMBUzWAj5SKeR7ET/3LFRQjVDT8pBxs0NznUpvpc3paS5id/8LB4kZkUv4cz5iE3 lOWz2IOQxJ6+nKOB/gvXNRvPBhMzeZOZ+ROqu66cBFsGlSKNoksLyREtYetsQTUPkkKq njCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5Gx/7ND2enUqh97byGs4EhjEjQPx9quOoqiJMUHgOSo=; b=e5f1LlhvInMZr/dUZHVzDKiO53zoYMz0WGAQz4yUd6zmjwnBZt6rz7C8tIkzn/8SNA xIDjnzXyAuOV6ZH82AGUvkUBrdSFFr9UTp5UQD2WK4eq8yYHddf3ZuaqBE/N+QblczNq +qm6ovdK+K74iRF7OYZXkj0A6Js7/7FerDWZfA/EZz3AXq5fFhj2KGGDbdr39Qgec20A Wgw4EtxRQRX6JAjfX65VjZUGrrj5OHuEhsh4u14ElZEwU/cKroNg1FtPlLzGP13XFnU5 5ZNFd7qCoSPCSl2sMzpiGlfP4sHcntrrrw81mCRa60RZCUpoElUNYjvBWMeiWsRcAfY4 Navg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O45yb+jx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 48/77] target/microblaze: Fix cpu unwind for fpu exceptions Date: Tue, 25 Aug 2020 13:59:21 -0700 Message-Id: <20200825205950.730499-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Restore the correct PC when an exception must be raised. Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 37 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index d99d98051a..2c59d4492d 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -104,13 +104,16 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) } /* raise FPU exception. */ -static void raise_fpu_exception(CPUMBState *env) +static void raise_fpu_exception(CPUMBState *env, uintptr_t ra) { + CPUState *cs = env_cpu(env); + env->esr = ESR_EC_FPU; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); } -static void update_fpu_flags(CPUMBState *env, int flags) +static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) { int raise = 0; @@ -133,7 +136,7 @@ static void update_fpu_flags(CPUMBState *env, int flags) if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) && (env->msr & MSR_EE)) { - raise_fpu_exception(env); + raise_fpu_exception(env, ra); } } @@ -148,7 +151,7 @@ uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) fd.f = float32_add(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -162,7 +165,7 @@ uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; fd.f = float32_sub(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -176,7 +179,7 @@ uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; fd.f = float32_mul(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -191,7 +194,7 @@ uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; fd.f = float32_div(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } @@ -206,7 +209,7 @@ uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) if (float32_is_signaling_nan(fa.f, &env->fp_status) || float32_is_signaling_nan(fb.f, &env->fp_status)) { - update_fpu_flags(env, float_flag_invalid); + update_fpu_flags(env, float_flag_invalid, GETPC()); r = 1; } @@ -229,7 +232,7 @@ uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; r = float32_lt(fb.f, fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -245,7 +248,7 @@ uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) fb.l = b; r = float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -261,7 +264,7 @@ uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = float32_le(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; @@ -277,7 +280,7 @@ uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = float32_lt(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -291,7 +294,7 @@ uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -306,7 +309,7 @@ uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) set_float_exception_flags(0, &env->fp_status); r = !float32_lt(fa.f, fb.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } @@ -330,7 +333,7 @@ uint32_t helper_fint(CPUMBState *env, uint32_t a) fa.l = a; r = float32_to_int32(fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return r; } @@ -344,7 +347,7 @@ uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) fa.l = a; fd.l = float32_sqrt(fa.f, &env->fp_status); flags = get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 49/77] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG Date: Tue, 25 Aug 2020 13:59:22 -0700 Message-Id: <20200825205950.730499-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that FSR is no longer a tcg global temp, we can say that the fpu helpers do not write to tcg temps. All temps are read implicitly by the fpu exception path. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 79e1e8ecc7..64816c89e1 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -3,21 +3,21 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) -DEF_HELPER_3(fadd, i32, env, i32, i32) -DEF_HELPER_3(frsub, i32, env, i32, i32) -DEF_HELPER_3(fmul, i32, env, i32, i32) -DEF_HELPER_3(fdiv, i32, env, i32, i32) -DEF_HELPER_2(flt, i32, env, i32) -DEF_HELPER_2(fint, i32, env, i32) -DEF_HELPER_2(fsqrt, i32, env, i32) +DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(frsub, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_2(flt, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_2(fint, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_2(fsqrt, TCG_CALL_NO_WG, i32, env, i32) -DEF_HELPER_3(fcmp_un, i32, env, i32, i32) -DEF_HELPER_3(fcmp_lt, i32, env, i32, i32) -DEF_HELPER_3(fcmp_eq, i32, env, i32, i32) -DEF_HELPER_3(fcmp_le, i32, env, i32, i32) -DEF_HELPER_3(fcmp_gt, i32, env, i32, i32) -DEF_HELPER_3(fcmp_ne, i32, env, i32, i32) -DEF_HELPER_3(fcmp_ge, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_un, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_lt, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_eq, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_le, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_gt, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) #if !defined(CONFIG_USER_ONLY) From patchwork Tue Aug 25 20:59:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248298 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp7640ejn; Tue, 25 Aug 2020 14:20:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyOHV2PZ/jqTlnj6VGnFyWvPyN5KZ0GXHVnr+6q6y/cjjd4M4uAw8ljPsxZby5JQjNz+4uj X-Received: by 2002:a25:cbc3:: with SMTP id b186mr18832215ybg.36.1598390449910; Tue, 25 Aug 2020 14:20:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390449; cv=none; d=google.com; s=arc-20160816; b=IRLiTkBXbtsj80Vrfvz/M6EgDrqGNrs2KYebuTJijd0V8Mf0V+mWgmymnAhANgcWeS 742fuCyVi7Ru62JnW9ILu80FqJL6c0JC7qZKMzm1Vb43AL5ETfR5dTJU+yeSfwitwqrQ tL5VnoaxC55Ji/b6wiMYzfu4c/xuv7vbRnUraI38T9Ty4ocfp1tfjAw95NpvlR62sBbs /SMrn92COHf/dS78IWreXLo5UKy84NzpzJ58fGuOrzXvubPQtj0GVtB/yDPFx7fK2k5z +jneTLxcCECweeaeYlPHfpup+VOEWDQLghcta1j5yQKod8ItJdiIkwSV7Xp4UE7SmcC5 xBow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lr71+uB2rqlQWi1mZS+Omspl/b6K02nPk8zKl55dRRU=; b=K/A4S980URIAkqbsPtpg3MErq/+d4RU3eZa+VcE8xTmXHpz9ORjdnzpTteuPcscAVj NSzA+KldS0XQvBLd+5aCz/O/NtRV8ph4oipNOj1B7WicGu16wYLfyicDU61fK0ICNHEb GL7Rj6i1D/TuZgL17IdR9OoHsEv2n0xADuzPr/2ghpHoM7/9ltGXbyHi6GMYuqlBJZq3 3mU5K7GxQMNVDBjz3Pv0koNXAhdmpzr6yYacFx891HHUwt3hiaLgbl8agnt27MSmXjhP QaA9/aaC/sCZkWOilq9f1BM0e5YF+pXb3Yg/2P/FQXXQ9UvMD81ykHAyXRNjnr3mwKtn PXQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xJwhO4Gk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 50/77] target/microblaze: Replace MSR_EE_FLAG with MSR_EE Date: Tue, 25 Aug 2020 13:59:23 -0700 Message-Id: <20200825205950.730499-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There's no reason to define MSR_EE_FLAG; we can just use the original MSR_EE define. Document the other flags copied into tb_flags with iflag to reserve those bits. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +++- target/microblaze/translate.c | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 013858b8e0..594501e4e7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -254,7 +254,9 @@ struct CPUMBState { /* Internal flags. */ #define IMM_FLAG 4 -#define MSR_EE_FLAG (1 << 8) +/* MSR_EE (1 << 8) */ +/* MSR_UM (1 << 11) */ +/* MSR_VM (1 << 13) */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7d1ada7aad..cb490488a6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -162,7 +162,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) */ static bool trap_illegal(DisasContext *dc, bool cond) { - if (cond && (dc->tb_flags & MSR_EE_FLAG) + if (cond && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.illegal_opcode_exception) { gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); } @@ -178,7 +178,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) int mem_index = cpu_mmu_index(&dc->cpu->env, false); bool cond_user = cond && mem_index == MMU_USER_IDX; - if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { + if (cond_user && (dc->tb_flags & MSR_EE)) { gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); } return cond_user; From patchwork Tue Aug 25 20:59:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248325 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp15561ejn; Tue, 25 Aug 2020 14:38:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqSrnzDJcejFqlLPJun2nrUUlFSkVthOj2AxgBw+6oJDghXlRKYQ5eNpACirCXshSdMvCW X-Received: by 2002:a25:2057:: with SMTP id g84mr16290506ybg.169.1598391519264; Tue, 25 Aug 2020 14:38:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391519; cv=none; d=google.com; s=arc-20160816; b=wTlw5YOACHHnjZ+ZTjHJR62K4o7AkHazXMkyj1ROQHIMxaZ7FFb2Fsg0yCQOLqmGsM IJcBfNI6Po0hM24Pdp16R4f23N3UQmQQJF5dVoioJgOJjp+8LdnHhaGmgWotm8vfc65I cBHvcxg/TxlQVdI1u/TAbjS6CxrAmAQkUur7dvr9OZ0K2VRBG4HJRFN+GkC9WAy/JxK0 NowJnpurAtzQdJF72/Pp3vl6H6/V0b72gkmacdbNyoDpHIZcULW8Wnpdo9TDgaWlaAmS DGQXcBrjqCs9QfyTWXgDecaSTN1U9hvpbwa7xhAMqazvmjDcQ0ZPGTQVHgV7dyvgjjz4 4FoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=urcrD5NFXjwPKRscyzfCPuOFRd/yp7ofBRVH50uRonY=; b=sVlFXPTAe3YIa1Xbupc2J0QGrSDBMkW45T1WGKlwSQmh9O46KDgkD+yE24Rtzm0aGF t4AztmlHQMU9/V21z8V6c7SFkRh8hF8hMKZPMNftsOOOXSntrXHJkBUDWQXcC67X03Z/ d2WJpSp7s5QFPLKGdSEfLVaAIOt1KLsHuOE+KFHXOQHtTqQt+LrD1vRn1EbLt/ddjrZr ZIm67WSwNzMW1KiRXJ5Aje+HyYcAlcLmn7dCu4r2E3h9DDA1rjCV5myJnSB5AHRLQMFA Nhjz/d76SRuO+4tC+aEM8UxkrIUuQw13INGh6FLBXOJZdP49dKENXGrkBE60QZQ5jhuc uQ+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C8Z2qsY7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 51/77] target/microblaze: Cache mem_index in DisasContext Date: Tue, 25 Aug 2020 13:59:24 -0700 Message-Id: <20200825205950.730499-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Ideally, nothing outside the top-level of translation even has access to env. Cache the value in init_disas_context. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index cb490488a6..8a251b35d9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -73,6 +73,7 @@ typedef struct DisasContext { unsigned int delayed_branch; unsigned int tb_flags, synced_flags; /* tb dependent flags. */ unsigned int clear_imm; + int mem_index; #define JMP_NOJMP 0 #define JMP_DIRECT 1 @@ -175,8 +176,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) */ static bool trap_userspace(DisasContext *dc, bool cond) { - int mem_index = cpu_mmu_index(&dc->cpu->env, false); - bool cond_user = cond && mem_index == MMU_USER_IDX; + bool cond_user = cond && dc->mem_index == MMU_USER_IDX; if (cond_user && (dc->tb_flags & MSR_EE)) { gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); @@ -954,7 +954,7 @@ static void dec_load(DisasContext *dc) TCGv addr; unsigned int size; bool rev = false, ex = false, ea = false; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); + int mem_index = dc->mem_index; MemOp mop; mop = dc->opcode & 3; @@ -1063,7 +1063,7 @@ static void dec_store(DisasContext *dc) TCGLabel *swx_skip = NULL; unsigned int size; bool rev = false, ex = false, ea = false; - int mem_index = cpu_mmu_index(&dc->cpu->env, false); + int mem_index = dc->mem_index; MemOp mop; mop = dc->opcode & 3; @@ -1532,6 +1532,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; + dc->mem_index = cpu_mmu_index(&cpu->env, false); bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); From patchwork Tue Aug 25 20:59:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248293 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp6395ejn; Tue, 25 Aug 2020 14:18:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxm3XW/XAcHgNDfWOURc1MzOhO7uvD54hYipEQI//Y/MQj/EfsAp6FDc/JkE/vJl34Kdsiz X-Received: by 2002:a25:bf86:: with SMTP id l6mr15910940ybk.323.1598390280135; Tue, 25 Aug 2020 14:18:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390280; cv=none; d=google.com; s=arc-20160816; b=fmbAQHzeSTB3p8UYlSNlsykXOoM689QpJeLcd/BQK84T59JXawrP4GMkuO5zet9ZMp CSflC25QRev2xPg863COgkTbriMAWAiAEcnqGsYBePnm9RXo44Rby3x8AWz9JzhWqODh EL7IfSfkYI5HXk2q0hQOgH9oxq7EtFUBuwjqC5MomKoTwRokMZlXRVNZNhOXDFPLwr0+ /W+tm3JY2vY393CA7fLWhowLB5ULUwk7O4RqP0Swvaj72ihXV2nHVJI803r6HN7F7JNS Wflf5LfvxduInXr9AUFTX6c/y7zoZHP9JXi1HQZ1gD+0FW+MuCwkQyC9kK9KJUaAaFwG TaaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=R2cuEf3Qt/jcGcIZclz+3Hjy1ReL2CdcRjCqzKw0P3k=; b=SC8/kFN19KD10q9p+XR6vzzP0TRrCZvssvieZNU11GWMb7mjkM/c66Kk02pVvriane f4ZXWWFVZsrl0TJb/pR5lui3LygTafYGNVDidRnlj+MP4DNwy/HutkueW5nPOl2lHOkH yMxXTXr/KF1sxjlKlsQh5HeOH6sa6N7NIhl3PdF/Yeqv3tMumTbCPPzdIwnhKvjom3kD 99TrtM/Ax81cjYL0NFBEoE60oyeXfkZUFztAYpT17wvKkY0gj0QJ305Z0jrMQvb/1Ggv bgICJ2DGGRehNfXeLDT4aMjxXuRzIlM/sX0fbcv/Sb9KeXfj3U2//z61QYz/ObbIiFwR j2EA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y7j3LQ8y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 52/77] target/microblaze: Fix cpu unwind for stackprot Date: Tue, 25 Aug 2020 13:59:25 -0700 Message-Id: <20200825205950.730499-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Restore the correct PC when an exception must be raised. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 +- target/microblaze/op_helper.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 64816c89e1..a473c1867b 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -26,7 +26,7 @@ DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) #endif DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) -DEF_HELPER_2(stackprot, void, env, tl) +DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_2(get, i32, i32, i32) DEF_HELPER_3(put, void, i32, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 2c59d4492d..a99c467364 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -389,12 +389,16 @@ void helper_memalign(CPUMBState *env, target_ulong addr, void helper_stackprot(CPUMBState *env, target_ulong addr) { if (addr < env->slr || addr > env->shr) { + CPUState *cs = env_cpu(env); + qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); + env->ear = addr; env->esr = ESR_EC_STACKPROT; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, GETPC()); } } From patchwork Tue Aug 25 20:59:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248326 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp16018ejn; Tue, 25 Aug 2020 14:39:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzr9Ut7uS8I4tIckR/hriZS6KW/G9VO4h8yY+WeQ10HIm2ty7znK/n5VZTO/qNIjclG/5K7 X-Received: by 2002:a25:ba4f:: with SMTP id z15mr17987127ybj.171.1598391576822; Tue, 25 Aug 2020 14:39:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391576; cv=none; d=google.com; s=arc-20160816; b=nha2mwJUR5xhpcs/IR8EPiXs4XQtcvnODB8Gp0DUZOBpyTmz4lIXxtQLky9GdrKr+W sJNnFgV5h0eBdVrnvkE9Kztn97PTiOOgEcJlyZQwbwoBVC+MHNt75SEnhsiLOfk4tqlr ook+xfOOu4C5EOocRRakEqndaoIfDq+G5HLcBnNrshaKs3PESdcnWTEg7Zuo0vQM/KdM AAPk0c6E0ev9Hep5Twgja3g2FTtDilGqRPuFwEkCfC09/bsqEgWSAeqRxVTdbdpSEuVP D6NxRXOWiIvf9GZPM1sUKDFfoG33T3Vb8/gkeLLtCjj1F0WFzLUo9XBU2eOvNUXu+qWJ Gngw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WyzqXCeR3DuXy4jQfHiKsdQqH3q0PeYbF+siivFcZWI=; b=RuMOfFhDu4r/XDxSk0Gch1XENE5V9bylLUscihViSnrlpICQlccFQKLbMDyMS0n3Nl neLAebbiptU5Z2f0qRV/08wqhOCYnlkyTytlCBESUPYZxFT+9ghDesw/O7X0j6FGVg2t zBUwvxuZ4Bd4E+mJcpAPY2jTzLse0LFcneRZTGtvuU4RtKraKCffFXj1bSngq/COXCog CYYImZ2lIlIq88hQbZGJYlC5jrgZ5BEeihmPNr1lik/Vn+/qefwQQjchRtOIpygKGy/0 UOau6u58F5lSL3RW51GKS36R5IP5DCtCdK7O8wUXn/VOdvneJ2/r/vg9K7c2+9/7/PTv 3Iww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WTHBusgN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 53/77] target/microblaze: Convert dec_load and dec_store to decodetree Date: Tue, 25 Aug 2020 13:59:26 -0700 Message-Id: <20200825205950.730499-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 32 ++ target/microblaze/translate.c | 723 +++++++++++++++++++-------------- 2 files changed, 456 insertions(+), 299 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index ea6743c7e5..998f997adc 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -97,6 +97,22 @@ idivu 010010 ..... ..... ..... 000 0000 0010 @typea imm 101100 00000 00000 imm:16 +lbu 110000 ..... ..... ..... 0000 000 0000 @typea +lbur 110000 ..... ..... ..... 0100 000 0000 @typea +lbuea 110000 ..... ..... ..... 0001 000 0000 @typea +lbui 111000 ..... ..... ................ @typeb + +lhu 110001 ..... ..... ..... 0000 000 0000 @typea +lhur 110001 ..... ..... ..... 0100 000 0000 @typea +lhuea 110001 ..... ..... ..... 0001 000 0000 @typea +lhui 111001 ..... ..... ................ @typeb + +lw 110010 ..... ..... ..... 0000 000 0000 @typea +lwr 110010 ..... ..... ..... 0100 000 0000 @typea +lwea 110010 ..... ..... ..... 0001 000 0000 @typea +lwx 110010 ..... ..... ..... 1000 000 0000 @typea +lwi 111010 ..... ..... ................ @typeb + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea @@ -120,6 +136,22 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +sb 110100 ..... ..... ..... 0000 000 0000 @typea +sbr 110100 ..... ..... ..... 0100 000 0000 @typea +sbea 110100 ..... ..... ..... 0001 000 0000 @typea +sbi 111100 ..... ..... ................ @typeb + +sh 110101 ..... ..... ..... 0000 000 0000 @typea +shr 110101 ..... ..... ..... 0100 000 0000 @typea +shea 110101 ..... ..... ..... 0001 000 0000 @typea +shi 111101 ..... ..... ................ @typeb + +sw 110110 ..... ..... ..... 0000 000 0000 @typea +swr 110110 ..... ..... ..... 0100 000 0000 @typea +swea 110110 ..... ..... ..... 0001 000 0000 @typea +swx 110110 ..... ..... ..... 1000 000 0000 @typea +swi 111110 ..... ..... ................ @typeb + sext8 100100 ..... ..... 00000 000 0110 0000 @typea0 sext16 100100 ..... ..... 00000 000 0110 0001 @typea0 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8a251b35d9..42d6d2a593 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -105,6 +105,17 @@ static inline void t_sync_flags(DisasContext *dc) } } +static inline void sync_jmpstate(DisasContext *dc) +{ + if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { + if (dc->jmp == JMP_DIRECT) { + tcg_gen_movi_i32(cpu_btaken, 1); + } + dc->jmp = JMP_INDIRECT; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + } +} + static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); @@ -668,6 +679,419 @@ static bool trans_wdic(DisasContext *dc, arg_wdic *a) DO_TYPEA(xor, false, tcg_gen_xor_i32) DO_TYPEBI(xori, false, tcg_gen_xori_i32) +static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) +{ + TCGv ret = tcg_temp_new(); + + /* If any of the regs is r0, set t to the value of the other reg. */ + if (ra && rb) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]); + tcg_gen_extu_i32_tl(ret, tmp); + tcg_temp_free_i32(tmp); + } else if (ra) { + tcg_gen_extu_i32_tl(ret, cpu_R[ra]); + } else if (rb) { + tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + } else { + tcg_gen_movi_tl(ret, 0); + } + + if ((ra == 1 || rb == 1) && dc->cpu->cfg.stackprot) { + gen_helper_stackprot(cpu_env, ret); + } + return ret; +} + +static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) +{ + TCGv ret = tcg_temp_new(); + + /* If any of the regs is r0, set t to the value of the other reg. */ + if (ra) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[ra], imm); + tcg_gen_extu_i32_tl(ret, tmp); + tcg_temp_free_i32(tmp); + } else { + tcg_gen_movi_tl(ret, (uint32_t)imm); + } + + if (ra == 1 && dc->cpu->cfg.stackprot) { + gen_helper_stackprot(cpu_env, ret); + } + return ret; +} + +static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) +{ + int addr_size = dc->cpu->cfg.addr_size; + TCGv ret = tcg_temp_new(); + + if (addr_size == 32 || ra == 0) { + if (rb) { + tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + } else { + tcg_gen_movi_tl(ret, 0); + } + } else { + if (rb) { + tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]); + } else { + tcg_gen_extu_i32_tl(ret, cpu_R[ra]); + tcg_gen_shli_tl(ret, ret, 32); + } + if (addr_size < 64) { + /* Mask off out of range bits. */ + tcg_gen_andi_i64(ret, ret, MAKE_64BIT_MASK(0, addr_size)); + } + } + return ret; +} + +static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, + int mem_index, bool rev) +{ + TCGv_i32 v; + MemOp size = mop & MO_SIZE; + + /* + * When doing reverse accesses we need to do two things. + * + * 1. Reverse the address wrt endianness. + * 2. Byteswap the data lanes on the way back into the CPU core. + */ + if (rev) { + if (size > MO_8) { + mop ^= MO_BSWAP; + } + if (size < MO_32) { + tcg_gen_xori_tl(addr, addr, 3 - size); + } + } + + t_sync_flags(dc); + sync_jmpstate(dc); + + /* + * Microblaze gives MMU faults priority over faults due to + * unaligned addresses. That's why we speculatively do the load + * into v. If the load succeeds, we verify alignment of the + * address and if that succeeds we write into the destination reg. + */ + v = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); + + /* TODO: Convert to CPUClass::do_unaligned_access. */ + if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { + TCGv_i32 t0 = tcg_const_i32(0); + TCGv_i32 treg = tcg_const_i32(rd); + TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + gen_helper_memalign(cpu_env, addr, treg, t0, tsize); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); + } + + if (rd) { + tcg_gen_mov_i32(cpu_R[rd], v); + } + + tcg_temp_free_i32(v); + tcg_temp_free(addr); + return true; +} + +static bool trans_lbu(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_lbur(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, true); +} + +static bool trans_lbuea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +} + +static bool trans_lbui(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_lhu(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_lhur(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); +} + +static bool trans_lhuea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +} + +static bool trans_lhui(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_lw(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_lwr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); +} + +static bool trans_lwea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +} + +static bool trans_lwi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_lwx(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + + /* lwx does not throw unaligned access errors, so force alignment */ + tcg_gen_andi_tl(addr, addr, ~3); + + t_sync_flags(dc); + sync_jmpstate(dc); + + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_mov_tl(cpu_res_addr, addr); + tcg_temp_free(addr); + + if (arg->rd) { + tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val); + } + + /* No support for AXI exclusive so always clear C */ + tcg_gen_movi_i32(cpu_msr_c, 0); + return true; +} + +static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, + int mem_index, bool rev) +{ + MemOp size = mop & MO_SIZE; + + /* + * When doing reverse accesses we need to do two things. + * + * 1. Reverse the address wrt endianness. + * 2. Byteswap the data lanes on the way back into the CPU core. + */ + if (rev) { + if (size > MO_8) { + mop ^= MO_BSWAP; + } + if (size < MO_32) { + tcg_gen_xori_tl(addr, addr, 3 - size); + } + } + + t_sync_flags(dc); + sync_jmpstate(dc); + + tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); + + /* TODO: Convert to CPUClass::do_unaligned_access. */ + if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { + TCGv_i32 t1 = tcg_const_i32(1); + TCGv_i32 treg = tcg_const_i32(rd); + TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + /* FIXME: if the alignment is wrong, we should restore the value + * in memory. One possible way to achieve this is to probe + * the MMU prior to the memaccess, thay way we could put + * the alignment checks in between the probe and the mem + * access. + */ + gen_helper_memalign(cpu_env, addr, treg, t1, tsize); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); + } + + tcg_temp_free(addr); + return true; +} + +static bool trans_sb(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_sbr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, true); +} + +static bool trans_sbea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +} + +static bool trans_sbi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_sh(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_shr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); +} + +static bool trans_shea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +} + +static bool trans_shi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_sw(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_swr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); +} + +static bool trans_swea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +} + +static bool trans_swi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_swx(DisasContext *dc, arg_typea *arg) +{ + TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCGLabel *swx_done = gen_new_label(); + TCGLabel *swx_fail = gen_new_label(); + TCGv_i32 tval; + + t_sync_flags(dc); + sync_jmpstate(dc); + + /* swx does not throw unaligned access errors, so force alignment */ + tcg_gen_andi_tl(addr, addr, ~3); + + /* + * Compare the address vs the one we used during lwx. + * On mismatch, the operation fails. On match, addr dies at the + * branch, but we know we can use the equal version in the global. + * In either case, addr is no longer needed. + */ + tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail); + tcg_temp_free(addr); + + /* + * Compare the value loaded during lwx with current contents of + * the reserved location. + */ + tval = tcg_temp_new_i32(); + + tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, + reg_for_write(dc, arg->rd), + dc->mem_index, MO_TEUL); + + tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); + tcg_temp_free_i32(tval); + + /* Success */ + tcg_gen_movi_i32(cpu_msr_c, 0); + tcg_gen_br(swx_done); + + /* Failure */ + gen_set_label(swx_fail); + tcg_gen_movi_i32(cpu_msr_c, 1); + + gen_set_label(swx_done); + + /* + * Prevent the saved address from working again without another ldx. + * Akin to the pseudocode setting reservation = 0. + */ + tcg_gen_movi_tl(cpu_res_addr, -1); + return true; +} + static void msr_read(DisasContext *dc, TCGv_i32 d) { TCGv_i32 t; @@ -873,303 +1297,6 @@ static void dec_msr(DisasContext *dc) } } -static inline void sync_jmpstate(DisasContext *dc) -{ - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(cpu_btaken, 1); - } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); - } -} - -static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) -{ - /* Should be set to true if r1 is used by loadstores. */ - bool stackprot = false; - TCGv_i32 t32; - - /* All load/stores use ra. */ - if (dc->ra == 1 && dc->cpu->cfg.stackprot) { - stackprot = true; - } - - /* Treat the common cases first. */ - if (!dc->type_b) { - if (ea) { - int addr_size = dc->cpu->cfg.addr_size; - - if (addr_size == 32) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); - return; - } - - tcg_gen_concat_i32_i64(t, cpu_R[dc->rb], cpu_R[dc->ra]); - if (addr_size < 64) { - /* Mask off out of range bits. */ - tcg_gen_andi_i64(t, t, MAKE_64BIT_MASK(0, addr_size)); - } - return; - } - - /* If any of the regs is r0, set t to the value of the other reg. */ - if (dc->ra == 0) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); - return; - } else if (dc->rb == 0) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->ra]); - return; - } - - if (dc->rb == 1 && dc->cpu->cfg.stackprot) { - stackprot = true; - } - - t32 = tcg_temp_new_i32(); - tcg_gen_add_i32(t32, cpu_R[dc->ra], cpu_R[dc->rb]); - tcg_gen_extu_i32_tl(t, t32); - tcg_temp_free_i32(t32); - - if (stackprot) { - gen_helper_stackprot(cpu_env, t); - } - return; - } - /* Immediate. */ - t32 = tcg_temp_new_i32(); - tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); - tcg_gen_extu_i32_tl(t, t32); - tcg_temp_free_i32(t32); - - if (stackprot) { - gen_helper_stackprot(cpu_env, t); - } - return; -} - -static void dec_load(DisasContext *dc) -{ - TCGv_i32 v; - TCGv addr; - unsigned int size; - bool rev = false, ex = false, ea = false; - int mem_index = dc->mem_index; - MemOp mop; - - mop = dc->opcode & 3; - size = 1 << mop; - if (!dc->type_b) { - ea = extract32(dc->ir, 7, 1); - rev = extract32(dc->ir, 9, 1); - ex = extract32(dc->ir, 10, 1); - } - mop |= MO_TE; - if (rev) { - mop ^= MO_BSWAP; - } - - if (trap_illegal(dc, size > 4)) { - return; - } - - if (trap_userspace(dc, ea)) { - return; - } - - t_sync_flags(dc); - addr = tcg_temp_new(); - compute_ldst_addr(dc, ea, addr); - /* Extended addressing bypasses the MMU. */ - mem_index = ea ? MMU_NOMMU_IDX : mem_index; - - /* - * When doing reverse accesses we need to do two things. - * - * 1. Reverse the address wrt endianness. - * 2. Byteswap the data lanes on the way back into the CPU core. - */ - if (rev && size != 4) { - /* Endian reverse the address. t is addr. */ - switch (size) { - case 1: - { - tcg_gen_xori_tl(addr, addr, 3); - break; - } - - case 2: - /* 00 -> 10 - 10 -> 00. */ - tcg_gen_xori_tl(addr, addr, 2); - break; - default: - cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); - break; - } - } - - /* lwx does not throw unaligned access errors, so force alignment */ - if (ex) { - tcg_gen_andi_tl(addr, addr, ~3); - } - - /* If we get a fault on a dslot, the jmpstate better be in sync. */ - sync_jmpstate(dc); - - /* Verify alignment if needed. */ - /* - * Microblaze gives MMU faults priority over faults due to - * unaligned addresses. That's why we speculatively do the load - * into v. If the load succeeds, we verify alignment of the - * address and if that succeeds we write into the destination reg. - */ - v = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); - - if (dc->cpu->cfg.unaligned_exceptions && size > 1) { - TCGv_i32 t0 = tcg_const_i32(0); - TCGv_i32 treg = tcg_const_i32(dc->rd); - TCGv_i32 tsize = tcg_const_i32(size - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_helper_memalign(cpu_env, addr, treg, t0, tsize); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); - } - - if (ex) { - tcg_gen_mov_tl(cpu_res_addr, addr); - tcg_gen_mov_i32(cpu_res_val, v); - } - if (dc->rd) { - tcg_gen_mov_i32(cpu_R[dc->rd], v); - } - tcg_temp_free_i32(v); - - if (ex) { /* lwx */ - /* no support for AXI exclusive so always clear C */ - tcg_gen_movi_i32(cpu_msr_c, 0); - } - - tcg_temp_free(addr); -} - -static void dec_store(DisasContext *dc) -{ - TCGv addr; - TCGLabel *swx_skip = NULL; - unsigned int size; - bool rev = false, ex = false, ea = false; - int mem_index = dc->mem_index; - MemOp mop; - - mop = dc->opcode & 3; - size = 1 << mop; - if (!dc->type_b) { - ea = extract32(dc->ir, 7, 1); - rev = extract32(dc->ir, 9, 1); - ex = extract32(dc->ir, 10, 1); - } - mop |= MO_TE; - if (rev) { - mop ^= MO_BSWAP; - } - - if (trap_illegal(dc, size > 4)) { - return; - } - - trap_userspace(dc, ea); - - t_sync_flags(dc); - /* If we get a fault on a dslot, the jmpstate better be in sync. */ - sync_jmpstate(dc); - /* SWX needs a temp_local. */ - addr = ex ? tcg_temp_local_new() : tcg_temp_new(); - compute_ldst_addr(dc, ea, addr); - /* Extended addressing bypasses the MMU. */ - mem_index = ea ? MMU_NOMMU_IDX : mem_index; - - if (ex) { /* swx */ - TCGv_i32 tval; - - /* swx does not throw unaligned access errors, so force alignment */ - tcg_gen_andi_tl(addr, addr, ~3); - - tcg_gen_movi_i32(cpu_msr_c, 1); - swx_skip = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); - - /* - * Compare the value loaded at lwx with current contents of - * the reserved location. - */ - tval = tcg_temp_new_i32(); - - tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val, - cpu_R[dc->rd], mem_index, - mop); - - tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); - tcg_gen_movi_i32(cpu_msr_c, 0); - tcg_temp_free_i32(tval); - } - - if (rev && size != 4) { - /* Endian reverse the address. t is addr. */ - switch (size) { - case 1: - { - tcg_gen_xori_tl(addr, addr, 3); - break; - } - - case 2: - /* 00 -> 10 - 10 -> 00. */ - /* Force addr into the temp. */ - tcg_gen_xori_tl(addr, addr, 2); - break; - default: - cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); - break; - } - } - - if (!ex) { - tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop); - } - - /* Verify alignment if needed. */ - if (dc->cpu->cfg.unaligned_exceptions && size > 1) { - TCGv_i32 t1 = tcg_const_i32(1); - TCGv_i32 treg = tcg_const_i32(dc->rd); - TCGv_i32 tsize = tcg_const_i32(size - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - /* FIXME: if the alignment is wrong, we should restore the value - * in memory. One possible way to achieve this is to probe - * the MMU prior to the memaccess, thay way we could put - * the alignment checks in between the probe and the mem - * access. - */ - gen_helper_memalign(cpu_env, addr, treg, t1, tsize); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); - } - - if (ex) { - gen_set_label(swx_skip); - } - - tcg_temp_free(addr); -} - static inline void eval_cc(DisasContext *dc, unsigned int cc, TCGv_i32 d, TCGv_i32 a) { @@ -1477,8 +1604,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_LD, dec_load}, - {DEC_ST, dec_store}, {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, From patchwork Tue Aug 25 20:59:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248297 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp7626ejn; Tue, 25 Aug 2020 14:20:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4rEr+XSHrZqkPQrAEmmhtDzSbsSY9LNm2cPWD2EccYy6nny4ubm5i0zlNC628sFpRr3V3 X-Received: by 2002:a25:38c5:: with SMTP id f188mr17091105yba.132.1598390447525; Tue, 25 Aug 2020 14:20:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390447; cv=none; d=google.com; s=arc-20160816; b=mTWRrUkJEJYR3GnyzlVUn/Apu8wQJZkQ5kLNJ4VZusFqekV6bSFb/j1iqjCDqQXMUc 4Y7rPZxfye1WpsXtHDlb+afDo1YLkcePJOwvKmmYMBfXf+J8s9EP5zRGuSZD1/2V591l K7AnTCUo0uGsB8/z39Ye9dTV/18ZWYMHt4KEqTqlnoIY+Z/HuacagFDoXP4Ca3iDeoiU 5IUW98ZsgHCLtXeI829IioFT4mi/ZOj5mRzRjDw1CIuaRfNBHWmkWuTHPk3Zjzub+UFK 0RVLnU52Vi3AU9xTYoLJBKqzFGPT7IfU0hWy0K+lxkrI05JKus7SnWyxpydGZ2VM0d/v 3kHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=50E0hW76gnTgLCYM21b2+hcWFagS0hoFg/XoJTnl9H8=; b=l4znk707CH/M8bXSVFRW7M0nv2hFrcZ+f/x0+XwIHeq0mf84HTfqXqvvTW96yWh3M7 /QrkpbX87ATWd8nmNf+bRZGg2bGPkimjBrJTX9iG93WZg+N7Rw/JY9joCX7A+6+J9CMq Jfq4e3lGM2wWDTeVLiOnvyT6h9MsUN+3Z7TFsMQY3kqJxzRknCokb+M5JljwVgk3LbOC xk1NRsPGug8rPV7++IOf4jsMaWQbctj/l0sK/sujnWh61WraCJDu7uD6zE4MBq+/BcKJ LEfu7HUImT5/G2f5VQQ0xM+70jSSUCzyzcWIY0dx48FkNvbNoIw+g+qfUhnR+0FzMv1D X+7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qQpzcyXP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 54/77] target/microblaze: Assert no overlap in flags making up tb_flags Date: Tue, 25 Aug 2020 13:59:27 -0700 Message-Id: <20200825205950.730499-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create MSR_TB_MASK. Use it in cpu_get_tb_cpu_state, and check that IFLAGS_TB_MASK does not overlap. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 594501e4e7..2fc7cf26f1 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -261,8 +261,11 @@ struct CPUMBState { #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) #define D_FLAG (1 << 19) /* Bit in ESR. */ + /* TB dependent CPUMBState. */ #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) +#define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE) + uint32_t iflags; #if !defined(CONFIG_USER_ONLY) @@ -372,12 +375,14 @@ typedef MicroBlazeCPU ArchCPU; #include "exec/cpu-all.h" +/* Ensure there is no overlap between the two masks. */ +QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); + static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { *pc = env->pc; - *flags = (env->iflags & IFLAGS_TB_MASK) | - (env->msr & (MSR_UM | MSR_VM | MSR_EE)); + *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); *cs_base = (*flags & IMM_FLAG ? env->imm : 0); } From patchwork Tue Aug 25 20:59:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248301 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp8185ejn; Tue, 25 Aug 2020 14:22:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyPavPOTmDxdNLqajPrpDsQ4eQoNlkoykis7/sZHN5u2ZUqWQs0DXXOlwO7E+U7oSK5R3/e X-Received: by 2002:a25:4288:: with SMTP id p130mr16463274yba.288.1598390528817; Tue, 25 Aug 2020 14:22:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390528; cv=none; d=google.com; s=arc-20160816; b=gi2jskC967wPXxIcHjnzP9Z/TGTLsUmDDg/DjB3znZWH/AJj7RFzvLMbyNzK/iJCUj q3LwDlz2dCVFdlvBBsH/6s2HFhudHe0mimUSX81zpQyCUpxJoeyP/njAD+Ietewt1/ms kwbKNj90paOguu56AezT3uvZuRkcAtdMoRPNNbUWM8Te3wgVHR2dgzpGfYW9xLpSNvfG QjZRAloRdyylObIBLZeuOUZUTtJqXdkFzA9XjFC9BbWxkk4ppBrPYR1Vs3FYaoZE/h3C 9Fu88PVv88rr6LPVBMnGrrSujwHdww7peyqHYf7YOPM8tTFDUCdmGpHvvNa8+Ohs/6lV ruVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8b0bp9mk+1WbNfIATZBmVlR2NfvcC4JEryF82Ik81YY=; b=ZEeDGk1v+X/js9nJ6w1zOtpgGSayW6HCfFW+nSfxCHPfOUUyqQCaEBHVzfNJ630kBQ v1OE/UlUdqjTdX9C2KKiuTII8n+ehklm3N4MuSqE7mgluCESUsDnPlx3OQQ0DdHK45vj YGRUN1cFYy2o/Y/HtIQyvAgsu+JxTyc+WUjE9VHr7S9rQ3VXK04XX687z+m4oaT0U7t6 rSstsGvp2iY8gUyAHftEMkSNTibBd+V/P1aOl8jmjnc41Zr0zwRoVyVJ3//firTHulua G1UwQib800BBRJ/GNfnUQDKCH8FmkQuLbiS2xwsABB4vqizap88yUyU//0TFgIBsHcvR k9fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r2HUuPvh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 55/77] target/microblaze: Move bimm to BIMM_FLAG Date: Tue, 25 Aug 2020 13:59:28 -0700 Message-Id: <20200825205950.730499-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It makes sense to keep BIMM with D_FLAG, as they can be written back to iflags at the same time. BIMM_FLAG does not need to be added to IFLAGS_TB_MASK because it does not affect the next TB, only the exception path out of the current TB. Renumber IMM_FLAG, as the value 4 holds no particular significance; pack these two flags at the bottom of the bitfield. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 ++-- target/microblaze/helper.c | 2 +- target/microblaze/translate.c | 12 +++++------- 3 files changed, 8 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 2fc7cf26f1..a5df1fa28f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -231,7 +231,6 @@ typedef struct CPUMBState CPUMBState; struct CPUMBState { uint32_t btaken; uint32_t btarget; - uint32_t bimm; uint32_t imm; uint32_t regs[32]; @@ -253,7 +252,8 @@ struct CPUMBState { uint32_t res_val; /* Internal flags. */ -#define IMM_FLAG 4 +#define IMM_FLAG (1 << 0) +#define BIMM_FLAG (1 << 1) /* MSR_EE (1 << 8) */ /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index f8e2ca12a9..06f4322e09 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -166,7 +166,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* Reexecute the branch. */ env->regs[17] -= 4; /* was the branch immprefixed?. */ - if (env->bimm) { + if (env->iflags & BIMM_FLAG) { env->regs[17] -= 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 42d6d2a593..7fd1efd3fb 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1337,13 +1337,11 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) static void dec_setup_dslot(DisasContext *dc) { - TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)); - - dc->delayed_branch = 2; - dc->tb_flags |= D_FLAG; - - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm)); - tcg_temp_free_i32(tmp); + dc->delayed_branch = 2; + dc->tb_flags |= D_FLAG; + if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + dc->tb_flags |= BIMM_FLAG; + } } static void dec_bcc(DisasContext *dc) From patchwork Tue Aug 25 20:59:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248328 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp16821ejn; Tue, 25 Aug 2020 14:41:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxr7l51SzA2i6K4sID80axoayWgzyrrzLaTXV5INbCTrFqyenFF7MQe+Ks8QQsvI+MZ0GMh X-Received: by 2002:a25:6b4e:: with SMTP id o14mr16616295ybm.506.1598391683540; Tue, 25 Aug 2020 14:41:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391683; cv=none; d=google.com; s=arc-20160816; b=slidzjsS3jtXn3RnNXP1tuQkWQzqQgJQQuOpFPq8kMCXtn3mUlZZtqFsyYLoDtCR3O aLBOfRIGSGcY4Z+dYG8NfVCLvv3zGi/ewVsi6Ij6VtJkB6hnBZCQZuJgom+TC4l/kzbP 5Xm78AJvS7YhHTs2ntbvHJK7/38CrNZET594krZHV/i6j4/3nCkNoK5JkglO4cTsprCu IZ8M0czNTtu3ecJr2uUnHns6qO0aLku5hbMnlbRcJUakpq69zBrv0sV3itDCXfbpRTas okBIMq8aNl92MNUogWGdWOsCpUskNxL2mlbgjE44Mm0tynjHcqapSC5fW6OVEYMC8dxj 82CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RvFJSD7Zh4rSxdM1y2eF+nLQTn/KQL07U6ICYBiMb68=; b=KZtUauNnj5YFKWkESM7RMLfqJlTrpGRScXTGtzoDS4eRJ4bqkPezNQl8uo+zFrWBMC 4qRCkX7cTspXwH/QjtJ3D/SFwk22NEs7XTCo90hv90z8vpZREK7CNgGHuFk8zv+iSYGM 1Z5kP2unFidzN+4lBGwobiaBzT6bgHzk7Vd/OR1vxlXHwIqfxDOHWQNqCRakslT2bux3 2mXLxjryXsO17+GfhjhOMk1A+EtUROB5yWMfO5SeZhvh18tAQao98zvv5MJCQVKAdwO+ NK96CFcas62orwfzIWxha2B5Ai2VCrrxszOsHpn732zJmhBVCJpiT5skMHJD7ex+xOc0 uZ+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kFRER9Dx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 56/77] target/microblaze: Store "current" iflags in insn_start Date: Tue, 25 Aug 2020 13:59:29 -0700 Message-Id: <20200825205950.730499-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This data is available during exception unwinding, thus we can restore it from there directly, rather than saving it during the TB. Thus we may remove the t_sync_flags() calls in the load/store operations. Note that these calls were missing from the other places where runtime exceptions may be raised, such as idiv and the floating point operations. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 ++ target/microblaze/translate.c | 24 +++++++++++++----------- 2 files changed, 15 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a5df1fa28f..83fadd36a5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -228,6 +228,8 @@ typedef struct CPUMBState CPUMBState; #define STREAM_CONTROL (1 << 3) #define STREAM_NONBLOCK (1 << 4) +#define TARGET_INSN_START_EXTRA_WORDS 1 + struct CPUMBState { uint32_t btaken; uint32_t btarget; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7fd1efd3fb..930b8a9600 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; + /* TCG op of the current insn_start. */ + TCGOp *insn_start; + TCGv_i32 r0; bool r0_set; @@ -71,7 +74,7 @@ typedef struct DisasContext { unsigned int cpustate_changed; unsigned int delayed_branch; - unsigned int tb_flags, synced_flags; /* tb dependent flags. */ + unsigned int tb_flags; unsigned int clear_imm; int mem_index; @@ -96,12 +99,11 @@ static int typeb_imm(DisasContext *dc, int x) /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" -static inline void t_sync_flags(DisasContext *dc) +static void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ - if (dc->tb_flags != dc->synced_flags) { - tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); - dc->synced_flags = dc->tb_flags; + if ((dc->tb_flags ^ dc->base.tb->flags) & ~MSR_TB_MASK) { + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & ~MSR_TB_MASK); } } @@ -770,7 +772,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - t_sync_flags(dc); sync_jmpstate(dc); /* @@ -893,7 +894,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - t_sync_flags(dc); sync_jmpstate(dc); tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); @@ -929,7 +929,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - t_sync_flags(dc); sync_jmpstate(dc); tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); @@ -1046,7 +1045,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) TCGLabel *swx_fail = gen_new_label(); TCGv_i32 tval; - t_sync_flags(dc); sync_jmpstate(dc); /* swx does not throw unaligned access errors, so force alignment */ @@ -1647,7 +1645,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) int bound; dc->cpu = cpu; - dc->synced_flags = dc->tb_flags = dc->base.tb->flags; + dc->tb_flags = dc->base.tb->flags; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; @@ -1667,7 +1665,10 @@ static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs) static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) { - tcg_gen_insn_start(dcb->pc_next); + DisasContext *dc = container_of(dcb, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); + dc->insn_start = tcg_last_op(); } static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, @@ -1909,4 +1910,5 @@ void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, target_ulong *data) { env->pc = data[0]; + env->iflags = data[1]; } From patchwork Tue Aug 25 20:59:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248318 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp12303ejn; Tue, 25 Aug 2020 14:31:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzrakAtSQ+3E3AEW/9B4FUwmzc23ii4NhULyqpvIe7IN8KYVQnrzQJEXyX0aN+cAfQoboE5 X-Received: by 2002:a25:bd13:: with SMTP id f19mr16548115ybk.124.1598391081009; Tue, 25 Aug 2020 14:31:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391081; cv=none; d=google.com; s=arc-20160816; b=aje1I8kaLpfM9861JBirJHNLNIPl8wrE7NKawukS6kXG3UPNv4akwNCg0D2X2WAQih u2/JCvojtoss4JKj6PS3knO7pEbB9m22xUp5pL5E74GRp5ryYMl2di0ghX3UWzJgMCpH S8xfj5lhBtnIuCB3cvnVmaYpb4nrZEcgnbhq6sE81ZZNgrnxBXZvwLGKccnCWJsw9W6X CkjGhCWb7h+trH6EON5H7vLunufk/Qyf+luglLKOy1WOI63Dr81v0aYyNOqOlIi6DVE+ 5NASWF6PhWcqoe1D7VUyakQP3pS75zFD8dcTB/aJ4UaADNkzS1XNUAOwwk1Fo2IODNxs f9WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=p+iYZfUiWvOiZ4jhf/t12sD37PNbPvTJo79LCNu2vXI=; b=01LpgREaXlO2sB4jsEAobQsCwS+Xm/T8T1r/S7Cdw92Rh3l7oyoRAAQpZM7ri42vpz BBiRQJvZdHFdQNB9LYmx9uc68ZN3+r+57h37nMdDGdfXLheLPN16Cd1G4Xwh7+0Af4YT mD+VifcRwxEWrvyokLvQTusOt5fLsfXxpHvsz1o7iwsZVbWXmXfAsXC+GUyzBuSneYMv hyCjnYVhCJrjV5oITUXjZPdNXqID8V7UTATiViZztcnHF/c+lWAiVRU3zzkId8fnqlQj RB6nlTRUFx2WGtlS56PFi2H1qe/mhV9n6i5KIC5RSuxXQAh6asNnQFT18N4XgrBAJ/LY P2gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="io4EfYM/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 57/77] tcg: Add tcg_get_insn_start_param Date: Tue, 25 Aug 2020 13:59:30 -0700 Message-Id: <20200825205950.730499-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" MicroBlaze will shortly need to update a parameter in place. Add an interface to read to match that for write. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d40c925d04..15da46131b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -777,11 +777,26 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) } #endif +static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) +{ + return op->args[arg]; +} + static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) { op->args[arg] = v; } +static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) +{ +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + return tcg_get_insn_param(op, arg); +#else + return tcg_get_insn_param(op, arg * 2) | + (tcg_get_insn_param(op, arg * 2 + 1) << 32); +#endif +} + static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) { #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS From patchwork Tue Aug 25 20:59:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248320 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp13345ejn; Tue, 25 Aug 2020 14:33:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyr7p6/AG6lUvFgHspM/1HBagFKWVJe48jN8ea0WU/7vAuhKWiAkjecDjXspKL4LoMRAc6M X-Received: by 2002:a25:bbc2:: with SMTP id c2mr16595690ybk.174.1598391220959; Tue, 25 Aug 2020 14:33:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391220; cv=none; d=google.com; s=arc-20160816; b=U85lUOJYmDVSgaQGcDpAVkC8QDxU4Ff1ZB02jeprr/Bo5ohwNHcdgDRwe7GJlhRvX7 PpytXWqbK9PxQwHziHNjYSNEZHTuC2bZ6FTJ9bmx2Js4+Ek9Lu/OiwrgiicMB0blxa7H v+8pVvRLwzSTeXF1RZw8bkEQbXEeGfMNcodE/7VsbCsNMrA66pguAKvqmhGTM918wCv3 mKPkItD9+u6eAgA6EH+0YNCKQPV2U8hr+74+Uwe8Fa3Tx+Zvq9wzhEv0MGX0bGnbI1jg uNxiVA/hFwblAPKQh0Z6STxVDKpdTdDGrrjns7E3QpKJFN7+x0NF12TjcWg43PysOJP+ Kizw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DL6mixLq6S/ykZHeP+netlYcRnE/vfVwl7yqTg4dZh0=; b=QKCO1zh03XtbPeby1B6l3nXaw/BGwo5fUivqvsF/KW2il8Ga3J4kq07omV9yqk6Cz2 bi21QsQj5QMcPtZACR1djO4JejVJjduC5JCG1kCt/biDoL5RTnI2ZxwF9MiGM2gw7RGP F8jF9ge/TulyJUkdDszYXjIbM89fIpsVq6pjF1gRN4dafWynoDWwYRhLrRrPDs+qGtXA H44UJ5MKMDrHx6lZr01fp6lG15Q7Esci3LZ64ruBKwTL7sxZHd9X8Z7yw2a7GQuUcjyw uFJZKbfyzBuGvubEpotTnJ9wBbMOhrX0sXLQySlX/75xrm0wxbrWqe6p4cDT9s+2qzVh xgaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YBgK5IbW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 58/77] target/microblaze: Use cc->do_unaligned_access Date: Tue, 25 Aug 2020 13:59:31 -0700 Message-Id: <20200825205950.730499-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fixes the problem in which unaligned stores succeeded, but then we raised the exception after modifying memory. Store the ESS for the unaligned data access in the iflags for the insn, so that it can be found during unwind. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 10 ++++- target/microblaze/helper.h | 1 - target/microblaze/cpu.c | 1 + target/microblaze/helper.c | 28 ++++++++++++++ target/microblaze/op_helper.c | 21 ---------- target/microblaze/translate.c | 72 +++++++++++++---------------------- 6 files changed, 64 insertions(+), 69 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 83fadd36a5..63b8d93d41 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -79,10 +79,13 @@ typedef struct CPUMBState CPUMBState; /* Exception State Register (ESR) Fields */ #define ESR_DIZ (1<<11) /* Zone Protection */ +#define ESR_W (1<<11) /* Unaligned word access */ #define ESR_S (1<<10) /* Store instruction */ #define ESR_ESS_FSL_OFFSET 5 +#define ESR_ESS_MASK (0x7f << 5) + #define ESR_EC_FSL 0 #define ESR_EC_UNALIGNED_DATA 1 #define ESR_EC_ILLEGAL_OP 2 @@ -256,9 +259,11 @@ struct CPUMBState { /* Internal flags. */ #define IMM_FLAG (1 << 0) #define BIMM_FLAG (1 << 1) -/* MSR_EE (1 << 8) */ +#define ESR_ESS_FLAG (1 << 2) /* indicates ESR_ESS_MASK is present */ +/* MSR_EE (1 << 8) -- these 3 are not in iflags but tb_flags */ /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ +/* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) @@ -330,6 +335,9 @@ struct MicroBlazeCPU { void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index a473c1867b..3980fba797 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -25,7 +25,6 @@ DEF_HELPER_3(mmu_read, i32, env, i32, i32) DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) #endif -DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_2(get, i32, i32, i32) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 1eabf5cc3f..67017ecc33 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -317,6 +317,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = mb_cpu_class_by_name; cc->has_work = mb_cpu_has_work; cc->do_interrupt = mb_cpu_do_interrupt; + cc->do_unaligned_access = mb_cpu_do_unaligned_access; cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 06f4322e09..0e3be251a7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -296,3 +296,31 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return false; } + +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + uint32_t esr, iflags; + + /* Recover the pc and iflags from the corresponding insn_start. */ + cpu_restore_state(cs, retaddr, true); + iflags = cpu->env.iflags; + + qemu_log_mask(CPU_LOG_INT, + "Unaligned access addr=" TARGET_FMT_lx + " pc=%x iflags=%x\n", addr, cpu->env.pc, iflags); + + esr = ESR_EC_UNALIGNED_DATA; + if (likely(iflags & ESR_ESS_FLAG)) { + esr |= iflags & ESR_ESS_MASK; + } else { + qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n"); + } + + cpu->env.ear = addr; + cpu->env.esr = esr; + cs->exception_index = EXCP_HW_EXCP; + cpu_loop_exit(cs); +} diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index a99c467364..4a07d0ce3c 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -365,27 +365,6 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b) return 0; } -void helper_memalign(CPUMBState *env, target_ulong addr, - uint32_t dr, uint32_t wr, - uint32_t mask) -{ - if (addr & mask) { - qemu_log_mask(CPU_LOG_INT, - "unaligned access addr=" TARGET_FMT_lx - " mask=%x, wr=%d dr=r%d\n", - addr, mask, wr, dr); - env->ear = addr; - env->esr = ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) << 5; - if (mask == 3) { - env->esr |= 1 << 11; - } - if (!(env->msr & MSR_EE)) { - return; - } - helper_raise_exception(env, EXCP_HW_EXCP); - } -} - void helper_stackprot(CPUMBState *env, target_ulong addr) { if (addr < env->slr || addr > env->shr) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 930b8a9600..6e70873333 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -751,10 +751,22 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) return ret; } +static void record_unaligned_ess(DisasContext *dc, int rd, + MemOp size, bool store) +{ + uint32_t iflags = tcg_get_insn_start_param(dc->insn_start, 1); + + iflags |= ESR_ESS_FLAG; + iflags |= rd << 5; + iflags |= store * ESR_S; + iflags |= (size == MO_32) * ESR_W; + + tcg_set_insn_start_param(dc->insn_start, 1, iflags); +} + static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) { - TCGv_i32 v; MemOp size = mop & MO_SIZE; /* @@ -774,34 +786,15 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, sync_jmpstate(dc); - /* - * Microblaze gives MMU faults priority over faults due to - * unaligned addresses. That's why we speculatively do the load - * into v. If the load succeeds, we verify alignment of the - * address and if that succeeds we write into the destination reg. - */ - v = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); - - /* TODO: Convert to CPUClass::do_unaligned_access. */ - if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { - TCGv_i32 t0 = tcg_const_i32(0); - TCGv_i32 treg = tcg_const_i32(rd); - TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_helper_memalign(cpu_env, addr, treg, t0, tsize); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); + if (size > MO_8 && + (dc->tb_flags & MSR_EE) && + dc->cpu->cfg.unaligned_exceptions) { + record_unaligned_ess(dc, rd, size, false); + mop |= MO_ALIGN; } - if (rd) { - tcg_gen_mov_i32(cpu_R[rd], v); - } + tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); - tcg_temp_free_i32(v); tcg_temp_free(addr); return true; } @@ -931,28 +924,15 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, sync_jmpstate(dc); - tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); - - /* TODO: Convert to CPUClass::do_unaligned_access. */ - if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { - TCGv_i32 t1 = tcg_const_i32(1); - TCGv_i32 treg = tcg_const_i32(rd); - TCGv_i32 tsize = tcg_const_i32((1 << size) - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - /* FIXME: if the alignment is wrong, we should restore the value - * in memory. One possible way to achieve this is to probe - * the MMU prior to the memaccess, thay way we could put - * the alignment checks in between the probe and the mem - * access. - */ - gen_helper_memalign(cpu_env, addr, treg, t1, tsize); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); + if (size > MO_8 && + (dc->tb_flags & MSR_EE) && + dc->cpu->cfg.unaligned_exceptions) { + record_unaligned_ess(dc, rd, size, true); + mop |= MO_ALIGN; } + tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); + tcg_temp_free(addr); return true; } From patchwork Tue Aug 25 20:59:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248322 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp14501ejn; Tue, 25 Aug 2020 14:36:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7Oxav+XazHESsQZNgvVvqm+CXbWhpOVJMybvVeyIgDblTDKA0VPaTgYtYJuMdG98K6iQ8 X-Received: by 2002:a5b:b03:: with SMTP id z3mr15947657ybp.341.1598391359945; Tue, 25 Aug 2020 14:35:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391359; cv=none; d=google.com; s=arc-20160816; b=02sSD9HOahZPQmIx7iX0L8kV1zGwSgztYxEMdXgxpZMXEIGBjttYr18WmOsEBtou+P 8fxLCl2xBYLKonRlKDXwoLAw/H63bfmXHyHyJCCIw1Cp0xjltiyPb263fRPKmGyXxw3I If9SpFv3gGqGFjyKpwvdTBpN/xOw4r4gauXKky8bfZug+zjotsou2ls/HIW/d/YDHaMh NHAett/Ypoy8A6xlqsqnOeFPgErC5F1B2qDzYNS4+BW44xE7vUEiFaXMTR/Tivp6tuXU 75tl5iImI5pgG1hTnUfRHEk8joDwMCvxsAb8XjSb2rDCACYgJaQESjHmkmIh7eGCxq5F pC+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0IyoDEFe3ZWYDga+MAV6Bg/xEkFwuDqD20ZUdnvyl1Q=; b=fw/lIVXSmejU8IG1/cJjeEqlpu+h+PtWpmRK57ZvcV5vGpiQ+mSEI1jTi4R1XKWW0Q UVoPftRwur0PS6yaiMUsQJ8XrXP1dwxuVwZI9FxjtRmGvb0U2LuJomi5Twt4VvlRI9uz U1FCvzNGoqY3cHOoJft+zFk7oJO35XS6pSqPmHbvit7fgu9F/R6fce/7y9YNM/Tdt9a2 3a6//avQLbSKH/AytD5ffm0Kdy2mi3Sr1IKe1m40R4zUUKnCiAnbSnBwELqimdXgQRB8 kHPTvfFfiRXIuzUelNufcavXVzFr5AbgQ5hF5WOJwQJL9/6f8OFJ8HnEgGUw+VntI51V LXzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i1mG4tBB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 59/77] target/microblaze: Replace clear_imm with tb_flags_to_set Date: Tue, 25 Aug 2020 13:59:32 -0700 Message-Id: <20200825205950.730499-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This more general update variable will be able to handle delay slots as well. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6e70873333..18009103c7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -75,7 +75,7 @@ typedef struct DisasContext { unsigned int cpustate_changed; unsigned int delayed_branch; unsigned int tb_flags; - unsigned int clear_imm; + unsigned int tb_flags_to_set; int mem_index; #define JMP_NOJMP 0 @@ -535,8 +535,7 @@ static bool trans_imm(DisasContext *dc, arg_imm *arg) { dc->ext_imm = arg->imm << 16; tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags |= IMM_FLAG; - dc->clear_imm = 0; + dc->tb_flags_to_set = IMM_FLAG; return true; } @@ -1680,7 +1679,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) (uint32_t)dc->base.pc_next); } - dc->clear_imm = 1; + dc->tb_flags_to_set = 0; + ir = cpu_ldl_code(env, dc->base.pc_next); if (!decode(dc, ir)) { old_decode(dc, ir); @@ -1692,10 +1692,13 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->r0_set = false; } - if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags &= ~IMM_FLAG; + /* Discard the imm global when its contents cannot be used. */ + if ((dc->tb_flags & ~dc->tb_flags_to_set) & IMM_FLAG) { tcg_gen_discard_i32(cpu_imm); } + + dc->tb_flags &= ~IMM_FLAG; + dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; if (dc->delayed_branch && --dc->delayed_branch == 0) { From patchwork Tue Aug 25 20:59:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248324 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp14985ejn; Tue, 25 Aug 2020 14:37:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwxuGCBJfLupu3gzMYO/YP6e+sGK0OjCUP4farO5OAiAnCO967Cv0AKKfJsUCb3y1Yzku4V X-Received: by 2002:a25:cc44:: with SMTP id l65mr17865862ybf.177.1598391435040; Tue, 25 Aug 2020 14:37:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391435; cv=none; d=google.com; s=arc-20160816; b=od3NEaqNydHQHDm2CD2eIDlegIw/UhF6oZaL9LUTyXqB1/rPCVedF8grj61T+Jx1Bl UCh3bV+vnhQH68iltsyAR0GtbvC2rF5n7EmsuHiGatzry5/5+x//gn8NpHVlGP8qagjJ ZhQjx8PpUuOdRCzNee3goHjOZT+H/40c9rlwFaUWe2kFMiynLNlJbOzd9xSxT6XZxV2S 0TT3ICFIM/evHsfsgVIHxQyKhjViMwnu0rpwsZLRTOkp3VkUgZ5A3+NUDT6+YZNjQKXw bcCJ+SnFDbNRRl0K0AGs7hULZ2UKJ5rYf/H6xeUvBPBBbknR3omM5oE5YZ33KMQ0dD+e R7LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ifoPB2xrefiphamrfMAWhJL0YX7DJDQgoCM7PfPYN9w=; b=mcXC69q5i9tBpocd5pMKTygX7pMhd1QHsHTw09EqrUdK1Pr+PsTNTpZhrA7Qfm+4k7 jQSki3uEVAPXdZuChBpd6v+Av5l8o3q5QmX3+iaflkg51esQwcY+5oNu43IOj42Juad3 xlqYR7HrGUZ0iZj6+WW4WeOI6JLM9GZMcSp5jHzjfzJig3yz9MhVBqfr2DRUtV8jORZj ntxNdQ6XEgf0ISgIIa9NmR0eDdszWN480N1ALVVuJybQXu9X732K49w7YKTCmG1F+lJs CzZFYhcwe7ULfZRLUFt14UjC9q2u6GXOFiC6Eh7vT2RHk7HVpgVvpjL8WwjhharkNgbW 08Rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="L8+p6R/N"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 60/77] target/microblaze: Replace delayed_branch with tb_flags_to_set Date: Tue, 25 Aug 2020 13:59:33 -0700 Message-Id: <20200825205950.730499-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The multi-stage counter can be replaced by clearing D_FLAG, the or'ing in tb_flags_to_set. The jump then happens when D_FLAG is finally cleared. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 18009103c7..3ba2dc1800 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -73,7 +73,6 @@ typedef struct DisasContext { uint16_t imm; unsigned int cpustate_changed; - unsigned int delayed_branch; unsigned int tb_flags; unsigned int tb_flags_to_set; int mem_index; @@ -1314,10 +1313,9 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) static void dec_setup_dslot(DisasContext *dc) { - dc->delayed_branch = 2; - dc->tb_flags |= D_FLAG; + dc->tb_flags_to_set |= D_FLAG; if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags |= BIMM_FLAG; + dc->tb_flags_to_set |= BIMM_FLAG; } } @@ -1329,7 +1327,6 @@ static void dec_bcc(DisasContext *dc) cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); - dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); } @@ -1405,7 +1402,6 @@ static void dec_br(DisasContext *dc) } } - dc->delayed_branch = 1; if (dslot) { dec_setup_dslot(dc); } @@ -1625,8 +1621,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; - dc->delayed_branch = !!(dc->tb_flags & D_FLAG); - dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; + dc->jmp = dc->tb_flags & D_FLAG ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; @@ -1697,11 +1692,11 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) tcg_gen_discard_i32(cpu_imm); } - dc->tb_flags &= ~IMM_FLAG; + dc->tb_flags &= ~(IMM_FLAG | BIMM_FLAG | D_FLAG); dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; - if (dc->delayed_branch && --dc->delayed_branch == 0) { + if (dc->jmp != JMP_NOJMP && !(dc->tb_flags & D_FLAG)) { if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); } @@ -1711,8 +1706,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } - /* Clear the delay slot flag. */ - dc->tb_flags &= ~D_FLAG; dc->base.is_jmp = DISAS_JUMP; } From patchwork Tue Aug 25 20:59:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248330 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp17422ejn; Tue, 25 Aug 2020 14:42:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVQ7ldlvWpRJQ8/m+bssGo6SB/xe3dSa/IalIqADF6Un3qlVzxfOsei1uqjPOFnibwl9OB X-Received: by 2002:a25:8892:: with SMTP id d18mr18283680ybl.70.1598391771839; Tue, 25 Aug 2020 14:42:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391771; cv=none; d=google.com; s=arc-20160816; b=CVvGSRGlhQwdh0p2tIrPjeegASbEW+QR3d15lzQ15uQHN8S+DC/YWNF4XA1L362Yfl b7Xwi1kbxPYj+xgrzudky8WnYabjJI1qbkwLWoqp5ik9lcd2X2GvVziiBcONYkYQLHw9 iKv5NOQAax85SwIsTbXU2Av8kOmFiTvNA3vZxYNm6ZbyUTGB/PCKAf81cXWEPa6nMWGw GwoJ/eYZGfSyK4zwAS3ru9WzBZQ6GDKZxGfdJUMxCv5j0eVm7foSpodb7Ebcg1g5Aax9 NMheHHpGKyZ1+TFyqWZ8E/tOZGY6sbXC6HVGMwiwmyzAsGyywYhwPoX9VbxtYVkSYYd2 tvJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0+lbMujB7ENQF6DPdS7wnVUjhoKJE7Rkmv+oxgd9wrg=; b=NzIBBDy2HjTEipWpOOyfZSDOwXjpGjuRu6NS8PnKX5xq/NYVD4/SG3UL/a8kPZmbh2 mUkUBrGKLColmPf+iCw/ZgN8vRPuHRaiJe84+Pb1J8K8ng3Ag0EzP8nWBvY10l30Mg2r OU9m+0lgswHzCtaqMMe+6sZmYg0SzoC1TtWft8OHABIUoFQHwBErIfVwqzvUW62JjDyw aUAQbRdhkg85kJAubdckc9dony/r+H65eMglRZD8tJTY52PEiYKOPZsXp0h/iv1ZdtMT 8if5buRjP0Rbm5KJwM2oiwcYEvpMoZBoTYcwVI58YUFb0ExzkTZeGivFLJ92pbhcfect yJzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WCymE3jW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 61/77] target/microblaze: Tidy mb_cpu_dump_state Date: Tue, 25 Aug 2020 13:59:34 -0700 Message-Id: <20200825205950.730499-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Using lookup_symbol is quite slow; remove that. Decode the various bits of iflags; only show imm, btaken, btarget when they are relevant to iflags. Improve formatting. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 67 +++++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3ba2dc1800..4675326083 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1810,41 +1810,56 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; + uint32_t iflags; int i; - if (!env) { - return; - } - - qemu_fprintf(f, "IN: PC=%x %s\n", - env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "imm=%x iflags=%x fsr=%x rbtr=%x\n", - env->msr, env->esr, env->ear, - env->imm, env->iflags, env->fsr, env->btr); - qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", - env->btaken, env->btarget, + qemu_fprintf(f, "pc=0x%08x msr=0x%05x mode=%s(saved=%s) eip=%d ie=%d\n", + env->pc, env->msr, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", (bool)(env->msr & MSR_EIP), (bool)(env->msr & MSR_IE)); - for (i = 0; i < 12; i++) { - qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); - if ((i + 1) % 4 == 0) { - qemu_fprintf(f, "\n"); - } + + iflags = env->iflags; + qemu_fprintf(f, "iflags: 0x%08x", iflags); + if (iflags & IMM_FLAG) { + qemu_fprintf(f, " IMM(0x%08x)", env->imm); + } + if (iflags & BIMM_FLAG) { + qemu_fprintf(f, " BIMM"); + } + if (iflags & D_FLAG) { + qemu_fprintf(f, " D(btaken=%d btarget=0x%08x)", + env->btaken, env->btarget); + } + if (iflags & DRTI_FLAG) { + qemu_fprintf(f, " DRTI"); + } + if (iflags & DRTE_FLAG) { + qemu_fprintf(f, " DRTE"); + } + if (iflags & DRTB_FLAG) { + qemu_fprintf(f, " DRTB"); + } + if (iflags & ESR_ESS_FLAG) { + qemu_fprintf(f, " ESR_ESS(0x%04x)", iflags & ESR_ESS_MASK); + } + + qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n" + "ear=0x%016" PRIx64 " slr=0x%x shr=0x%x\n", + env->esr, env->fsr, env->btr, env->edr, + env->ear, env->slr, env->shr); + + for (i = 0; i < 12; i++) { + qemu_fprintf(f, "rpvr%-2d=%08x%c", + i, env->pvr.regs[i], i % 4 == 3 ? '\n' : ' '); } - /* Registers that aren't modeled are reported as 0 */ - qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " - "rtlblo=0 rtlbhi=0\n", env->edr); - qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { - qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); - if ((i + 1) % 4 == 0) - qemu_fprintf(f, "\n"); - } - qemu_fprintf(f, "\n\n"); + qemu_fprintf(f, "r%2.2d=%08x%c", + i, env->regs[i], i % 4 == 3 ? '\n' : ' '); + } + qemu_fprintf(f, "\n"); } void mb_tcg_init(void) From patchwork Tue Aug 25 20:59:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248308 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp9582ejn; Tue, 25 Aug 2020 14:25:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyn/370WyxeOIH6DYWQj9oHCObPdfqHgSCkNFEhi6ngGo/SWwm/ni7Qw/T9nJWOZ/oQvhLy X-Received: by 2002:a25:2e46:: with SMTP id b6mr17115070ybn.196.1598390716725; Tue, 25 Aug 2020 14:25:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390716; cv=none; d=google.com; s=arc-20160816; b=YLMOevQBO/Wnu1dLn7Lhvf6HUOV5I5BxlLG7zJWzkxLrC1Ukm3M4cu2Vs3Hh4cqs15 I9lrxCCSN+FZ3FcnBdXAnZY9Xl2b6F/EomT0b0y3cFDE79msbZU5NlMl1Ni9DzOFeqt4 X8ng1Q9IVIbEoikn9Y840Y2wGmZIiWJy/kHSVsOSfRsnBYZ40q/unRpB2qDAUqq/QMw3 5XBgxrnrbIP2wN9ayz8A0ltzkiETKh1wMM9VvMz+Jkz2sVJ5ZucMG/hP8mlksAdlQpU/ p6h6ZRDzVRqbqffKzs94iXPYjzuy8F2e2s+18GyQEbuuKcCb3+cJksDdcOaHOgQ+iM9g k+bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ulBZsejW2MG0+XvkBxJ405c+w3o2ybsU7Ko1+l3VylQ=; b=bxJBPgdptdAh1O+lj5WJE7qym9Nh18J2pscJcSo8uXPDFfPF+cUz1LsghYuXb1Rr3j MzqVLqqWZf2vjt0e3QAvD4IsS8JInSy2hefKh80jajpVyhFO4GZKHoRip2VqKJCkDdEH 1qQmt+QIa6o3cY+o6lJxVxlfk/Ril01TJz2RDJPrHzdsuj0BWsshOS0SCmrhHk6AV85U 03zQLrcQzhNczaMMv7ZBimZ7hxH/Yo7ToFmq6Y4BDZUSjjXMgrLPYZCIg/GIY4bGeKUW wlkpAkI+kU8u9KHJ0CXW335sEwMUrGVumLkRsY5wkFN/TMx6O/7duXhdEK5LlH9D5G4Z k4vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ouP3GNpw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 62/77] target/microblaze: Try to keep imm and delay slot together Date: Tue, 25 Aug 2020 13:59:35 -0700 Message-Id: <20200825205950.730499-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If the last insn on a page is imm, or a branch with delay slot, then end a tb early if this has not begun the tb. If it has begun the tb, then we can allow the tb to span two pages as if the imm plus its consumer, or branch plus delay, or imm plus branch plus delay, are a single insn. If the insn in the delay slot faults, then the exception handler will have reset the PC to the beginning of this sequence anyway, via the stored D_FLAG and BIMM_FLAG bits. Disable all of this when single-stepping. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 65 ++++++++++++++++++++++++++++++----- 1 file changed, 56 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4675326083..fcfc1ac184 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -530,11 +530,50 @@ static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) +/* + * Try to keep the current instruction with the one following. + * So if this insn is the last in the TB, and is not the first + * in the TB, and we are not singlestepping, then back up and + * exit the current TB. + */ +static bool wait_for_next_tb(DisasContext *dc) +{ + if (dc->base.num_insns >= dc->base.max_insns + && !dc->base.singlestep_enabled) { + /* Also consider if this insn (e.g. brid) itself uses an imm. */ + int ninsns = (dc->tb_flags & IMM_FLAG ? 2 : 1); + + /* + * If this is not the first insn in the TB, back up and + * start again with a new TB. + */ + if (dc->base.num_insns > ninsns) { + dc->base.pc_next -= ninsns * 4; + dc->base.num_insns -= ninsns; + dc->base.is_jmp = DISAS_TOO_MANY; + return true; + } + + /* + * Correspondingly, if this is the first insn of the TB, + * then extend the TB as necessary to keep it with the + * next insn. Do this by *reducing* the number of insns + * processed by this TB so that icount does fail an assertion. + */ + if (dc->base.num_insns == ninsns) { + dc->base.num_insns = 0; + } + } + return false; +} + static bool trans_imm(DisasContext *dc, arg_imm *arg) { - dc->ext_imm = arg->imm << 16; - tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags_to_set = IMM_FLAG; + if (!wait_for_next_tb(dc)) { + dc->ext_imm = arg->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); + dc->tb_flags_to_set = IMM_FLAG; + } return true; } @@ -1311,12 +1350,17 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) tcg_temp_free_i32(zero); } -static void dec_setup_dslot(DisasContext *dc) +static bool dec_setup_dslot(DisasContext *dc) { + if (wait_for_next_tb(dc)) { + return true; + } + dc->tb_flags_to_set |= D_FLAG; if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags_to_set |= BIMM_FLAG; } + return false; } static void dec_bcc(DisasContext *dc) @@ -1327,8 +1371,8 @@ static void dec_bcc(DisasContext *dc) cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); - if (dslot) { - dec_setup_dslot(dc); + if (dslot && dec_setup_dslot(dc)) { + return; } if (dc->type_b) { @@ -1402,9 +1446,10 @@ static void dec_br(DisasContext *dc) } } - if (dslot) { - dec_setup_dslot(dc); + if (dslot && dec_setup_dslot(dc)) { + return; } + if (link && dc->rd) { tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); } @@ -1513,7 +1558,9 @@ static void dec_rts(DisasContext *dc) return; } - dec_setup_dslot(dc); + if (dec_setup_dslot(dc)) { + return; + } if (i_bit) { dc->tb_flags |= DRTI_FLAG; From patchwork Tue Aug 25 20:59:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248312 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp10459ejn; Tue, 25 Aug 2020 14:27:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxEKIAklkQ2BrLe8hLo30UXZ1e+oAk8UROabHfXjHfe9Uhhzp/W/C8/B6vujPPpZ/Ry0sAg X-Received: by 2002:a5b:1c4:: with SMTP id f4mr16719468ybp.48.1598390836030; Tue, 25 Aug 2020 14:27:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390836; cv=none; d=google.com; s=arc-20160816; b=VX/y1QIPe/ap0Wu4YClxlRBM3aRLea5IeA+ndvmJiFF6RGsZ7rJ0lD7tkViM1yx7fz SlgFmztl2LdSs85SXkC8VZ6+qkGoawy0D+A7PpBft3uYv8xxTWtcCNVUO1BfDTK3DHBm NxBO31eUfpq9S7SuIyo4dCWmbgnpghG2YYz6qdNX9688HowINNuFJ5bjKUAc9BajaJX2 OeKepyBh/PuOLqI5v1+kfZP+mCsgI+QNUa8rjT1LswutuauaytJLvKAQu2JOcGzstPNg /jZX+UlxCf3NV6mDVD6xxork6soCnSF5+riyqwAS1OaxzPAgsBFN5lEi6W0NzH+uhdZr ynVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=i2qfh0mDAgjTBP8C+mFuEsdvxN4n1xrDbeVevJtZNBs=; b=X4hYj1ZROW4fGhQDmT2mmV2OBTZmBee3Jcn/+OX370jHMVcQBCrnPi7VrS/r8iPpfw iL4kqEE2QIkWHW9Cp5hMWee8uexJ7ZJin3lpsAvM+orJkH1ts/RGxhaH4yOZseztjGRJ /AV//Y0NeElKFA2ULZIYjufIWJgGIbR5PjI7dHUJG4ZoUlcZzvnZeMwk3fGwSTpL8HcQ /uS4MW1CkNOwpz7wJpCVtQj0p0gbwYfu/zM4DnpynXc84/Hz6KS8JKdrQ+PzqBaadD5h zl6CD8XrC5E83qeLGLNkrQRxJU1CtQYp4alnrvby1jbNP41Hn8hyHdk9641MGZ7Ki3tD 0mwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lbppmRKo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 63/77] target/microblaze: Convert brk and brki to decodetree Date: Tue, 25 Aug 2020 13:59:36 -0700 Message-Id: <20200825205950.730499-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split these out of the normal branch instructions, as they require special handling. Perform the entire operation inline, instead of raising EXCP_BREAK to do the work in mb_cpu_do_interrupt. This fixes a bug in that brki rd, imm, for imm != 0x18 is not supposed to set MSR_BIP. This fixes a bug in that imm == 0 is the reset vector and 0x18 is the debug vector, and neither should raise a tcg exception in system mode. Introduce EXCP_SYSCALL for microblaze-linux-user. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/insns.decode | 11 ++++ linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 10 +-- target/microblaze/translate.c | 107 ++++++++++++++++++------------- 5 files changed, 79 insertions(+), 53 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 63b8d93d41..1528749a0b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -31,7 +31,7 @@ typedef struct CPUMBState CPUMBState; #define EXCP_MMU 1 #define EXCP_IRQ 2 -#define EXCP_BREAK 3 +#define EXCP_SYSCALL 3 /* user-only */ #define EXCP_HW_BREAK 4 #define EXCP_HW_EXCP 5 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 998f997adc..53da2b75aa 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -19,7 +19,9 @@ &typea0 rd ra &typea rd ra rb +&typea_br rd rb &typeb rd ra imm +&typeb_br rd imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -30,9 +32,15 @@ # Officially typea, but with rb==0, which is not used. @typea0 ...... rd:5 ra:5 ................ &typea0 +# Officially typea, but with ra as opcode. +@typea_br ...... rd:5 ..... rb:5 ........... &typea_br + # Officially typeb, but any immediate extension is unused. @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb +# Officially typeb, but with ra as opcode. +@typeb_br ...... rd:5 ..... ................ &typeb_br imm=%extimm + # For convenience, extract the two imm_w/imm_s fields, then pack # them back together as "imm". Doing this makes it easiest to # match the required zero at bit 5. @@ -57,6 +65,9 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +brk 100110 ..... 01100 ..... 000 0000 0000 @typea_br +brki 101110 ..... 01100 ................ @typeb_br + bsrl 010001 ..... ..... ..... 000 0000 0000 @typea bsra 010001 ..... ..... ..... 010 0000 0000 @typea bsll 010001 ..... ..... ..... 100 0000 0000 @typea diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 3de99ea311..c3396a6e09 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -48,7 +48,7 @@ void cpu_loop(CPUMBState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_BREAK: + case EXCP_SYSCALL: /* Return address is 4 bytes after the call. */ env->regs[14] += 4; env->pc = env->regs[14]; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 0e3be251a7..1667822fb7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -230,7 +230,6 @@ void mb_cpu_do_interrupt(CPUState *cs) //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; - case EXCP_BREAK: case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); @@ -242,13 +241,8 @@ void mb_cpu_do_interrupt(CPUState *cs) msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); msr |= t; msr |= MSR_BIP; - if (cs->exception_index == EXCP_HW_BREAK) { - env->regs[16] = env->pc; - msr |= MSR_BIP; - env->pc = cpu->cfg.base_vectors + 0x18; - } else { - env->pc = env->btarget; - } + env->regs[16] = env->pc; + env->pc = cpu->cfg.base_vectors + 0x18; mb_cpu_write_msr(env, msr); break; default: diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index fcfc1ac184..fc1c661368 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1107,6 +1107,65 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) return true; } +static bool trans_brk(DisasContext *dc, arg_typea_br *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb)); + if (arg->rd) { + tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); + } + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP); + tcg_gen_movi_tl(cpu_res_addr, -1); + + dc->base.is_jmp = DISAS_UPDATE; + return true; +} + +static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) +{ + uint32_t imm = arg->imm; + + if (trap_userspace(dc, imm != 0x8 && imm != 0x18)) { + return true; + } + tcg_gen_movi_i32(cpu_pc, imm); + if (arg->rd) { + tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); + } + tcg_gen_movi_tl(cpu_res_addr, -1); + +#ifdef CONFIG_USER_ONLY + switch (imm) { + case 0x8: /* syscall trap */ + gen_raise_exception_sync(dc, EXCP_SYSCALL); + break; + case 0x18: /* debug trap */ + gen_raise_exception_sync(dc, EXCP_DEBUG); + break; + default: /* eliminated with trap_userspace check */ + g_assert_not_reached(); + } +#else + uint32_t msr_to_set = 0; + + if (imm != 0x18) { + msr_to_set |= MSR_BIP; + } + if (imm == 0x8 || imm == 0x18) { + /* MSR_UM and MSR_VM are in tb_flags, so we know their value. */ + msr_to_set |= (dc->tb_flags & (MSR_UM | MSR_VM)) << 1; + tcg_gen_andi_i32(cpu_msr, cpu_msr, + ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM)); + } + tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set); + dc->base.is_jmp = DISAS_UPDATE; +#endif + + return true; +} + static void msr_read(DisasContext *dc, TCGv_i32 d) { TCGv_i32 t; @@ -1389,6 +1448,7 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { unsigned int dslot, link, abs, mbar; + uint32_t add_pc; dslot = dc->ir & (1 << 20); abs = dc->ir & (1 << 19); @@ -1431,21 +1491,6 @@ static void dec_br(DisasContext *dc) return; } - if (abs && link && !dslot) { - if (dc->type_b) { - /* BRKI */ - uint32_t imm = dec_alu_typeb_imm(dc); - if (trap_userspace(dc, imm != 8 && imm != 0x18)) { - return; - } - } else { - /* BRK */ - if (trap_userspace(dc, true)) { - return; - } - } - } - if (dslot && dec_setup_dslot(dc)) { return; } @@ -1454,38 +1499,14 @@ static void dec_br(DisasContext *dc) tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); } - if (abs) { - if (dc->type_b) { - uint32_t dest = dec_alu_typeb_imm(dc); - - dc->jmp = JMP_DIRECT; - dc->jmp_pc = dest; - tcg_gen_movi_i32(cpu_btarget, dest); - if (link && !dslot) { - switch (dest) { - case 8: - case 0x18: - gen_raise_exception_sync(dc, EXCP_BREAK); - break; - case 0: - gen_raise_exception_sync(dc, EXCP_DEBUG); - break; - } - } - } else { - dc->jmp = JMP_INDIRECT; - tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); - if (link && !dslot) { - gen_raise_exception_sync(dc, EXCP_BREAK); - } - } - } else if (dc->type_b) { + add_pc = abs ? 0 : dc->base.pc_next; + if (dc->type_b) { dc->jmp = JMP_DIRECT; - dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); + dc->jmp_pc = add_pc + dec_alu_typeb_imm(dc); tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); } tcg_gen_movi_i32(cpu_btaken, 1); } From patchwork Tue Aug 25 20:59:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248332 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp17853ejn; Tue, 25 Aug 2020 14:44:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZWkyeg0LRt+Cwf0qoEJ4u6A15u7Z+B6dbgSxBkOGLtujlKEy29jGVGtwOJj4Ed2YYRsfA X-Received: by 2002:a25:f304:: with SMTP id c4mr15261350ybs.209.1598391848075; Tue, 25 Aug 2020 14:44:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391848; cv=none; d=google.com; s=arc-20160816; b=CJ0BMRwNpHM7MzzYhvkiDYUSbpIXbQ6cuz34MR9vcbnC6dU50TINFDB7JAzl3iN2M2 GWoaUBWjFb5g31c/Zf6986B/tkBK1D6CvmssHdv91WKtVpxGSsf7H8VJV2K8JW4cNxVM wXwH4WWYC0X6umZC+QAH+LnPGYw5MipNDROmVOq5aJ+LfxDIJxUnaJG6QHYNkUWtYyDw WWcioakJS3Ie8r7OsbKVNFsdBFFrILP58iRral+r1cTJfrmSTB3AnclDcORli8T7u9tR zLofWMosqBXSqCLaNHukOOi3jdfvrigrBtQq8u6VRIAL1A8I2CPnqN05Q2r9sJo1ZNgC b8XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4PiB9ZbjBaKjglLtNBxW9KhOjXdbTfOtuRsASAhW4TM=; b=NaMY61bYpjUwdx1+a6AKyzYd75MwPyZioB9wTMs6nJ+QtoUoDeB+fTPH0iOxqHZndi NzPaCGN9Oks7+/qAOBqICuRTcwyW4xGC2YiYcsjae0Qj1nrmzFK8JOY+4/5AFgseUL0Q AFp22YVfRkZDKIQm89ddgrVvg3Leq8Krk+Hjec76U5QKHx0kbO1IAKobumajZ0XxEzgc Rway3yKLgjok3PSJ8sJuic394WyMkPdvZLPwiEpRrJaRQTL730A5l63QFEpkfHTdQLEI fhPwYT0k2OwnYbNZR3yt6aqz1tOgG7xABlaqNH6F7ivJg2V3y73x3qFZfvDJf+RwNGzn aWfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f+bq5+bU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 64/77] target/microblaze: Convert mbar to decodetree Date: Tue, 25 Aug 2020 13:59:37 -0700 Message-Id: <20200825205950.730499-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split this out of the normal branch instructions, as it requires special handling. End the TB only for an instruction barrier. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 2 + target/microblaze/translate.c | 81 ++++++++++++++++++---------------- 2 files changed, 45 insertions(+), 38 deletions(-) -- 2.25.1 Reviewed-by: Edgar E. Iglesias diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 53da2b75aa..77b073be9e 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -124,6 +124,8 @@ lwea 110010 ..... ..... ..... 0001 000 0000 @typea lwx 110010 ..... ..... ..... 1000 000 0000 @typea lwi 111010 ..... ..... ................ @typeb +mbar 101110 imm:5 00010 0000 0000 0000 0100 + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index fc1c661368..a391e80fb9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1166,6 +1166,48 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) return true; } +static bool trans_mbar(DisasContext *dc, arg_mbar *arg) +{ + int mbar_imm = arg->imm; + + /* + * Instruction access memory barrier. + * End the TB so that we recognize self-modified code immediately. + */ + if (mbar_imm & 1) { + dc->cpustate_changed = 1; + } + + /* Data access memory barrier. */ + if (mbar_imm & 2) { + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + } + + /* Sleep. */ + if (mbar_imm & 16) { + TCGv_i32 tmp_1; + + if (trap_userspace(dc, true)) { + /* Sleep is a privileged instruction. */ + return true; + } + + t_sync_flags(dc); + + tmp_1 = tcg_const_i32(1); + tcg_gen_st_i32(tmp_1, cpu_env, + -offsetof(MicroBlazeCPU, env) + +offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp_1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); + + gen_raise_exception(dc, EXCP_HLT); + } + return true; +} + + static void msr_read(DisasContext *dc, TCGv_i32 d) { TCGv_i32 t; @@ -1447,50 +1489,13 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { - unsigned int dslot, link, abs, mbar; + unsigned int dslot, link, abs; uint32_t add_pc; dslot = dc->ir & (1 << 20); abs = dc->ir & (1 << 19); link = dc->ir & (1 << 18); - /* Memory barrier. */ - mbar = (dc->ir >> 16) & 31; - if (mbar == 2 && dc->imm == 4) { - uint16_t mbar_imm = dc->rd; - - /* Data access memory barrier. */ - if ((mbar_imm & 2) == 0) { - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); - } - - /* mbar IMM & 16 decodes to sleep. */ - if (mbar_imm & 16) { - TCGv_i32 tmp_1; - - if (trap_userspace(dc, true)) { - /* Sleep is a privileged instruction. */ - return; - } - - t_sync_flags(dc); - - tmp_1 = tcg_const_i32(1); - tcg_gen_st_i32(tmp_1, cpu_env, - -offsetof(MicroBlazeCPU, env) - +offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp_1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - - gen_raise_exception(dc, EXCP_HLT); - return; - } - /* Break the TB. */ - dc->cpustate_changed = 1; - return; - } - if (dslot && dec_setup_dslot(dc)) { return; } From patchwork Tue Aug 25 20:59:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248333 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp18334ejn; Tue, 25 Aug 2020 14:45:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxpPxGB313Wd8SddrM11CZUTtOCFXMqGcSM4V/cnbHuM514wQgmW6D9PtAr11xJRFtZikMW X-Received: by 2002:a25:8105:: with SMTP id o5mr16103559ybk.495.1598391921595; Tue, 25 Aug 2020 14:45:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391921; cv=none; d=google.com; s=arc-20160816; b=wt524Mte3LKMTm8zDVnV9tg6La0F0mQv2cfjuDnfOZ+IltUYkz3aGvka/Kq2zUsuEJ wEFGqZLABfw3brrMNr00sDSPeeMZPVRXMTfqtd4FrIgKky9aJ605zCaNyfx1F8lbDNfV DzIBwRwI3b3+lY85b10UcQ4//JwLY+XokpmP9Rhu5uwUFVYcSV6St4VM0ACljiWJvzVW Z3FEA1MVg9XTr22JCRORzpmtcyISNdxNQfhVCySgChTwOmr+G22HNUyPMxsMjwF1QXVa CyCmq/pC1itGy93punPGsVtb6bEkMMPz3eYAUseaOIhlOaSxKl5gYw1O46X4/ttRyKQN U1oA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zHtJR2PgLnYmwJnfF35UuanJnJx2PjTcBTvuZ0jGjNE=; b=G37ev97Lzp7dsei9/5i6DYq/sd52USwfpTp6qXFwSPANjgioNBF+ZLVslq3G+4dDzY Cxfu/2k3zR5lfdBqgNnMp7wDuw+6vTh9VM+vXgBznB7ZyNfba/Ssvmyb+TjM5zaZVngF MBF8hCsMxn0XfF2/sOTUbaFS4lrD3CLc+VE0+nSSU7wJ8Fqob0xl1J2Bj5cwsD1SRimO 1yvz4+Q6gX8Dusqdo8GWI0Kkm+rdjCw6a561ODXFnf0iv4YLwGD3YKJNrlz4sTEAHFeb wUq0FKfm3IO4mfRGFTZqt3GYSPX1GVczFjRdtvKliwRcYB6saYkzn/JZWwcyM20fe2yv zA0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KiQEVfCo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 65/77] target/microblaze: Reorganize branching Date: Tue, 25 Aug 2020 13:59:38 -0700 Message-Id: <20200825205950.730499-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the btaken variable, and simplify things by always computing the full branch destination into btarget. This avoids all need for sync_jmpstate(). Retain the direct branch behaviour by remembering the jump destination in jmp_dest, discarding btarget. In the normal case, where the branch delay slot cannot trap (e.g. arithmetic not memory operation), tcg will remove the computation into btarget, leaving us with just the tcg direct branching at the end. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/translate.c | 192 ++++++++++++++-------------------- 2 files changed, 79 insertions(+), 117 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 1528749a0b..4298f242a6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -234,8 +234,8 @@ typedef struct CPUMBState CPUMBState; #define TARGET_INSN_START_EXTRA_WORDS 1 struct CPUMBState { - uint32_t btaken; - uint32_t btarget; + uint32_t bvalue; /* TCG temporary, only valid during a TB */ + uint32_t btarget; /* Full resolved branch destination */ uint32_t imm; uint32_t regs[32]; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a391e80fb9..6f9b20d391 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -45,7 +45,7 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i32 cpu_msr_c; static TCGv_i32 cpu_imm; -static TCGv_i32 cpu_btaken; +static TCGv_i32 cpu_bvalue; static TCGv_i32 cpu_btarget; static TCGv_i32 cpu_iflags; static TCGv cpu_res_addr; @@ -77,12 +77,11 @@ typedef struct DisasContext { unsigned int tb_flags_to_set; int mem_index; -#define JMP_NOJMP 0 -#define JMP_DIRECT 1 -#define JMP_DIRECT_CC 2 -#define JMP_INDIRECT 3 - unsigned int jmp; - uint32_t jmp_pc; + /* Condition under which to jump, including NEVER and ALWAYS. */ + TCGCond jmp_cond; + + /* Immediate branch-taken destination, or -1 for indirect. */ + uint32_t jmp_dest; int abort_at_next_insn; } DisasContext; @@ -106,17 +105,6 @@ static void t_sync_flags(DisasContext *dc) } } -static inline void sync_jmpstate(DisasContext *dc) -{ - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(cpu_btaken, 1); - } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); - } -} - static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); @@ -821,8 +809,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -924,8 +910,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - sync_jmpstate(dc); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); tcg_gen_mov_tl(cpu_res_addr, addr); tcg_temp_free(addr); @@ -959,8 +943,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -1062,8 +1044,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) TCGLabel *swx_fail = gen_new_label(); TCGv_i32 tval; - sync_jmpstate(dc); - /* swx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); @@ -1413,44 +1393,6 @@ static void dec_msr(DisasContext *dc) } } -static inline void eval_cc(DisasContext *dc, unsigned int cc, - TCGv_i32 d, TCGv_i32 a) -{ - static const int mb_to_tcg_cc[] = { - [CC_EQ] = TCG_COND_EQ, - [CC_NE] = TCG_COND_NE, - [CC_LT] = TCG_COND_LT, - [CC_LE] = TCG_COND_LE, - [CC_GE] = TCG_COND_GE, - [CC_GT] = TCG_COND_GT, - }; - - switch (cc) { - case CC_EQ: - case CC_NE: - case CC_LT: - case CC_LE: - case CC_GE: - case CC_GT: - tcg_gen_setcondi_i32(mb_to_tcg_cc[cc], d, a, 0); - break; - default: - cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); - break; - } -} - -static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) -{ - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, - cpu_btaken, zero, - pc_true, pc_false); - - tcg_temp_free_i32(zero); -} - static bool dec_setup_dslot(DisasContext *dc) { if (wait_for_next_tb(dc)) { @@ -1466,8 +1408,17 @@ static bool dec_setup_dslot(DisasContext *dc) static void dec_bcc(DisasContext *dc) { + static const TCGCond mb_to_tcg_cc[] = { + [CC_EQ] = TCG_COND_EQ, + [CC_NE] = TCG_COND_NE, + [CC_LT] = TCG_COND_LT, + [CC_LE] = TCG_COND_LE, + [CC_GE] = TCG_COND_GE, + [CC_GT] = TCG_COND_GT, + }; unsigned int cc; unsigned int dslot; + TCGv_i32 zero, next; cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); @@ -1476,15 +1427,29 @@ static void dec_bcc(DisasContext *dc) return; } + dc->jmp_cond = mb_to_tcg_cc[cc]; + + /* Cache the condition register in cpu_bvalue across any delay slot. */ + tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]); + + /* Store the branch taken destination into btarget. */ if (dc->type_b) { - dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb), + dc->base.pc_next); } - eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); + + /* Compute the final destination into btarget. */ + zero = tcg_const_i32(0); + next = tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4); + tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, + reg_for_read(dc, dc->ra), zero, + cpu_btarget, next); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(next); } static void dec_br(DisasContext *dc) @@ -1506,14 +1471,13 @@ static void dec_br(DisasContext *dc) add_pc = abs ? 0 : dc->base.pc_next; if (dc->type_b) { - dc->jmp = JMP_DIRECT; - dc->jmp_pc = add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest = add_pc + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp = JMP_INDIRECT; + dc->jmp_dest = -1; tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); } - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond = TCG_COND_ALWAYS; } static inline void do_rti(DisasContext *dc) @@ -1596,8 +1560,8 @@ static void dec_rts(DisasContext *dc) dc->tb_flags |= DRTE_FLAG; } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond = TCG_COND_ALWAYS; + dc->jmp_dest = -1; tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } @@ -1694,13 +1658,14 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; - dc->jmp = dc->tb_flags & D_FLAG ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; dc->mem_index = cpu_mmu_index(&cpu->env, false); + dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER; + dc->jmp_dest = -1; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1769,14 +1734,12 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; - if (dc->jmp != JMP_NOJMP && !(dc->tb_flags & D_FLAG)) { + if (dc->jmp_cond != TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); - } - if (dc->tb_flags & DRTB_FLAG) { + } else if (dc->tb_flags & DRTB_FLAG) { do_rtb(dc); - } - if (dc->tb_flags & DRTE_FLAG) { + } else if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } dc->base.is_jmp = DISAS_JUMP; @@ -1801,19 +1764,13 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) } t_sync_flags(dc); - if (dc->tb_flags & D_FLAG) { - sync_jmpstate(dc); - dc->jmp = JMP_NOJMP; - } switch (dc->base.is_jmp) { case DISAS_TOO_MANY: - assert(dc->jmp == JMP_NOJMP); gen_goto_tb(dc, 0, dc->base.pc_next); return; case DISAS_UPDATE: - assert(dc->jmp == JMP_NOJMP); if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { @@ -1822,35 +1779,41 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) return; case DISAS_JUMP: - switch (dc->jmp) { - case JMP_INDIRECT: - { - TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); + if (dc->jmp_dest != -1 && !cs->singlestep_enabled) { + /* Direct jump. */ + tcg_gen_discard_i32(cpu_btarget); - if (unlikely(cs->singlestep_enabled)) { - gen_raise_exception(dc, EXCP_DEBUG); - } else { - tcg_gen_exit_tb(NULL, 0); - } - } - return; + if (dc->jmp_cond != TCG_COND_ALWAYS) { + /* Conditional direct jump. */ + TCGLabel *taken = gen_new_label(); + TCGv_i32 tmp = tcg_temp_new_i32(); - case JMP_DIRECT_CC: - { - TCGLabel *l1 = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + /* + * Copy bvalue to a temp now, so we can discard bvalue. + * This can avoid writing bvalue to memory when the + * delay slot cannot raise an exception. + */ + tcg_gen_mov_i32(tmp, cpu_bvalue); + tcg_gen_discard_i32(cpu_bvalue); + + tcg_gen_brcondi_i32(dc->jmp_cond, tmp, 0, taken); gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); + gen_set_label(taken); } - /* fall through */ - - case JMP_DIRECT: - gen_goto_tb(dc, 0, dc->jmp_pc); + gen_goto_tb(dc, 0, dc->jmp_dest); return; } - /* fall through */ + + /* Indirect jump (or direct jump w/ singlestep) */ + tcg_gen_mov_i32(cpu_pc, cpu_btarget); + tcg_gen_discard_i32(cpu_btarget); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; default: g_assert_not_reached(); @@ -1902,8 +1865,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " BIMM"); } if (iflags & D_FLAG) { - qemu_fprintf(f, " D(btaken=%d btarget=0x%08x)", - env->btaken, env->btarget); + qemu_fprintf(f, " D(btarget=0x%08x)", env->btarget); } if (iflags & DRTI_FLAG) { qemu_fprintf(f, " DRTI"); @@ -1953,7 +1915,7 @@ void mb_tcg_init(void) SP(msr_c), SP(imm), SP(iflags), - SP(btaken), + SP(bvalue), SP(btarget), SP(res_val), }; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 66/77] target/microblaze: Use tcg_gen_lookup_and_goto_ptr Date: Tue, 25 Aug 2020 13:59:39 -0700 Message-Id: <20200825205950.730499-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When goto_tb cannot be used due to branch page crossing, or due to indirect jumping, tcg_gen_lookup_and_goto_ptr can be used instead. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6f9b20d391..5bd771671b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -152,7 +152,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) tcg_gen_exit_tb(dc->base.tb, n); } else { tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } dc->base.is_jmp = DISAS_NORETURN; } @@ -1811,7 +1811,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } return; From patchwork Tue Aug 25 20:59:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248334 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp18868ejn; Tue, 25 Aug 2020 14:46:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzUxFIKatF9McQLebV2mxlJuVfWsMEiq3QgyyACO4qnsRHSzSwaRr/AtzBmReXIgUYY5pC4 X-Received: by 2002:a25:6d86:: with SMTP id i128mr3826654ybc.61.1598391993790; Tue, 25 Aug 2020 14:46:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391993; cv=none; d=google.com; s=arc-20160816; b=ihtDU35cDCEYtVDR9qQfAxtuK20bVkRDy27MwjDXh68T+R74LzqMxt3i84CwSefWz6 IT8V57H8ZRce2pgDlM7Y1ukGMKgy3PqZq8L+icvUfXVuYTHrPhHz6drbtypNHw9MdSUB GMGZGsPUHOf9rvd3tcMC64MukK5WEN0mA83lPEXYcV7nFLuCvcFvpyIQC/NcsY2z0aFa ogQnfpJ2hrXUZqMe2goXEvVG9znLT+vZnz/PtO/ge3ohwrKEtJ7cuHh8nj9OfRjJvbp1 sJMFZRptn79W3lKPNfsm6q2HzOTQq7L6UstlQenx1pffzRS4YTu3iAF7BOpLQsVqA4+n LAjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=U/xg7pKRu/7l+32EdVsp/pmb28o9isw6bULWSNvN3q8=; b=HW93c8nLc7bU+PWHFGQH/AYhbV437dvY2DFpGkCc5zIeVIGD/DX87JZMxSjTBQ6PcW 4qm/HuUcykTMkE11dM7hXFmQhKn07NxBE4nNakejfMOHYGZ4hPq8n6vvMuRYYeZT9e+r EQqvD0E1Zkf+BQIhvlupbjcEl4d6+uHMHYLX7N6oQlY+n80DDI16zsfnePbJx0XXjy0z 0mBKhATmMTzEg27e6C2GLcJCZdMVK5risgEndrfTzNlS51kKYAU4SD3N3hEKbxSd/AlX ohmXakYGvU1+GZC4Nc+95YfBtZHCZczYxD7eVMb+l13Ui6PpgFa1roZL8aXLlDg9zB5N XJdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zu1rPsZa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 67/77] target/microblaze: Convert dec_br to decodetree Date: Tue, 25 Aug 2020 13:59:40 -0700 Message-Id: <20200825205950.730499-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 14 +++++ target/microblaze/translate.c | 98 +++++++++++++++++++--------------- 2 files changed, 68 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 77b073be9e..94520e92dd 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -65,6 +65,20 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +br 100110 ..... 00000 ..... 000 0000 0000 @typea_br +bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br +brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br +brad 100110 ..... 11000 ..... 000 0000 0000 @typea_br +brld 100110 ..... 10100 ..... 000 0000 0000 @typea_br +brald 100110 ..... 11100 ..... 000 0000 0000 @typea_br + +bri 101110 ..... 00000 ................ @typeb_br +brai 101110 ..... 01000 ................ @typeb_br +brid 101110 ..... 10000 ................ @typeb_br +braid 101110 ..... 11000 ................ @typeb_br +brlid 101110 ..... 10100 ................ @typeb_br +bralid 101110 ..... 11100 ................ @typeb_br + brk 100110 ..... 01100 ..... 000 0000 0000 @typea_br brki 101110 ..... 01100 ................ @typeb_br diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 5bd771671b..73c956cd76 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1087,6 +1087,58 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) return true; } +static bool setup_dslot(DisasContext *dc) +{ + if (wait_for_next_tb(dc)) { + return true; + } + + dc->tb_flags_to_set |= D_FLAG; + if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + dc->tb_flags_to_set |= BIMM_FLAG; + } + return false; +} + +static bool do_branch(DisasContext *dc, int dest_rb, int dest_imm, + bool delay, bool abs, int link) +{ + uint32_t add_pc; + + if (delay && setup_dslot(dc)) { + return true; + } + + if (link) { + tcg_gen_movi_i32(cpu_R[link], dc->base.pc_next); + } + + /* Store the branch taken destination into btarget. */ + add_pc = abs ? 0 : dc->base.pc_next; + if (dest_rb) { + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], add_pc); + } else { + dc->jmp_dest = add_pc + dest_imm; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); + } + dc->jmp_cond = TCG_COND_ALWAYS; + return true; +} + +#define DO_BR(NAME, NAMEI, DELAY, ABS, LINK) \ + static bool trans_##NAME(DisasContext *dc, arg_typea_br *arg) \ + { return do_branch(dc, arg->rb, 0, DELAY, ABS, LINK ? arg->rd : 0); } \ + static bool trans_##NAMEI(DisasContext *dc, arg_typeb_br *arg) \ + { return do_branch(dc, 0, arg->imm, DELAY, ABS, LINK ? arg->rd : 0); } + +DO_BR(br, bri, false, false, false) +DO_BR(bra, brai, false, true, false) +DO_BR(brd, brid, true, false, false) +DO_BR(brad, braid, true, true, false) +DO_BR(brld, brlid, true, false, true) +DO_BR(brald, bralid, true, true, true) + static bool trans_brk(DisasContext *dc, arg_typea_br *arg) { if (trap_userspace(dc, true)) { @@ -1393,19 +1445,6 @@ static void dec_msr(DisasContext *dc) } } -static bool dec_setup_dslot(DisasContext *dc) -{ - if (wait_for_next_tb(dc)) { - return true; - } - - dc->tb_flags_to_set |= D_FLAG; - if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags_to_set |= BIMM_FLAG; - } - return false; -} - static void dec_bcc(DisasContext *dc) { static const TCGCond mb_to_tcg_cc[] = { @@ -1423,7 +1462,7 @@ static void dec_bcc(DisasContext *dc) cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); - if (dslot && dec_setup_dslot(dc)) { + if (dslot && setup_dslot(dc)) { return; } @@ -1452,34 +1491,6 @@ static void dec_bcc(DisasContext *dc) tcg_temp_free_i32(next); } -static void dec_br(DisasContext *dc) -{ - unsigned int dslot, link, abs; - uint32_t add_pc; - - dslot = dc->ir & (1 << 20); - abs = dc->ir & (1 << 19); - link = dc->ir & (1 << 18); - - if (dslot && dec_setup_dslot(dc)) { - return; - } - - if (link && dc->rd) { - tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); - } - - add_pc = abs ? 0 : dc->base.pc_next; - if (dc->type_b) { - dc->jmp_dest = add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); - } else { - dc->jmp_dest = -1; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); - } - dc->jmp_cond = TCG_COND_ALWAYS; -} - static inline void do_rti(DisasContext *dc) { TCGv_i32 t0, t1; @@ -1548,7 +1559,7 @@ static void dec_rts(DisasContext *dc) return; } - if (dec_setup_dslot(dc)) { + if (setup_dslot(dc)) { return; } @@ -1612,7 +1623,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, From patchwork Tue Aug 25 20:59:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248315 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp11281ejn; Tue, 25 Aug 2020 14:29:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwaHF8zL0lcESv4jJ7FduZW7mW2s+ligDt5Rd9m/2mnmaHWDTgOqRTpXPlNjComge8vCsRP X-Received: by 2002:a25:e644:: with SMTP id d65mr17632766ybh.452.1598390951682; Tue, 25 Aug 2020 14:29:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390951; cv=none; d=google.com; s=arc-20160816; b=SDSoa1TvtfLWwby0PQcQ6P1kQi/yqZXLkVrX9C+M/zBQroTqnK4Et+X7EhesFUpGkW UHYoNGo4ThE2zGtFNVNIF/StCFjwvVbTKVRXyRUovrfTCQg2YsplMd6Oc2I0L4lduh51 GTdCqbTsUGXyb6mCduJoCVyThP4uSUkKGToj998ZUsgRR/NfKSCFpQCnW5w9aecDWD4Z R9wX1O7KiqYF0LBWgQQe9jSKQ+TWjWTf5MO3JFRuAkpkmrt/VrXylVMmIkr+58zcsQMx VSULegdvrNqjoEgJ26kxyh1VAhnpktHV1YAsopU44URX3hsA2wNkAB0bJ6eoh3WEpGcs oIvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bfpqz7V+nismyYMkhAn5GwE9vkpITs4IMKYzm6EnI7g=; b=vE2+Pc5n6grzyasUkLhmA7jam53noVR0lyB8epeP6LFaSGqGve8mqu++Z4PSwvoOkH bfs4V/iYTgdP+IM7ecbRS48uM7kCQglkPHftgofgK6qh1w9XOKCm6aQVSuUhLS9VcoWL O/TtfioOVcdPbJd3iMgwUwS72PTZRuYbjkCzC95Rtkfk7GohKcwP4D3Ce7CWpL6LZWYc FHqPM5CaUs1CpYPA8NdmnhtYCOEJB6tIsSty1Tt6npDjCB6RV1qFWiXx/nv/la/b+RhP m/4OBq2KbIOa0Fj9uh85lxVB6haAxjNePjVh38gxkS0bg5mhbouBcHa6FofH9/uHryrF l7Ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KKeywVn9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 68/77] target/microblaze: Convert dec_bcc to decodetree Date: Tue, 25 Aug 2020 13:59:41 -0700 Message-Id: <20200825205950.730499-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 36 +++++++++++++ target/microblaze/translate.c | 99 ++++++++++++++++++---------------- 2 files changed, 88 insertions(+), 47 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 94520e92dd..21d08289f7 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -20,8 +20,10 @@ &typea0 rd ra &typea rd ra rb &typea_br rd rb +&typea_bc ra rb &typeb rd ra imm &typeb_br rd imm +&typeb_bc ra imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -35,12 +37,18 @@ # Officially typea, but with ra as opcode. @typea_br ...... rd:5 ..... rb:5 ........... &typea_br +# Officially typea, but with rd as opcode. +@typea_bc ...... ..... ra:5 rb:5 ........... &typea_bc + # Officially typeb, but any immediate extension is unused. @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb # Officially typeb, but with ra as opcode. @typeb_br ...... rd:5 ..... ................ &typeb_br imm=%extimm +# Officially typeb, but with rd as opcode. +@typeb_bc ...... ..... ra:5 ................ &typeb_bc imm=%extimm + # For convenience, extract the two imm_w/imm_s fields, then pack # them back together as "imm". Doing this makes it easiest to # match the required zero at bit 5. @@ -65,6 +73,34 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +beq 100111 00000 ..... ..... 000 0000 0000 @typea_bc +bge 100111 00101 ..... ..... 000 0000 0000 @typea_bc +bgt 100111 00100 ..... ..... 000 0000 0000 @typea_bc +ble 100111 00011 ..... ..... 000 0000 0000 @typea_bc +blt 100111 00010 ..... ..... 000 0000 0000 @typea_bc +bne 100111 00001 ..... ..... 000 0000 0000 @typea_bc + +beqd 100111 10000 ..... ..... 000 0000 0000 @typea_bc +bged 100111 10101 ..... ..... 000 0000 0000 @typea_bc +bgtd 100111 10100 ..... ..... 000 0000 0000 @typea_bc +bled 100111 10011 ..... ..... 000 0000 0000 @typea_bc +bltd 100111 10010 ..... ..... 000 0000 0000 @typea_bc +bned 100111 10001 ..... ..... 000 0000 0000 @typea_bc + +beqi 101111 00000 ..... ................ @typeb_bc +bgei 101111 00101 ..... ................ @typeb_bc +bgti 101111 00100 ..... ................ @typeb_bc +blei 101111 00011 ..... ................ @typeb_bc +blti 101111 00010 ..... ................ @typeb_bc +bnei 101111 00001 ..... ................ @typeb_bc + +beqid 101111 10000 ..... ................ @typeb_bc +bgeid 101111 10101 ..... ................ @typeb_bc +bgtid 101111 10100 ..... ................ @typeb_bc +bleid 101111 10011 ..... ................ @typeb_bc +bltid 101111 10010 ..... ................ @typeb_bc +bneid 101111 10001 ..... ................ @typeb_bc + br 100110 ..... 00000 ..... 000 0000 0000 @typea_br bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 73c956cd76..f79b02e987 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1139,6 +1139,58 @@ DO_BR(brad, braid, true, true, false) DO_BR(brld, brlid, true, false, true) DO_BR(brald, bralid, true, true, true) +static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm, + TCGCond cond, int ra, bool delay) +{ + TCGv_i32 zero, next; + + if (delay && setup_dslot(dc)) { + return true; + } + + dc->jmp_cond = cond; + + /* Cache the condition register in cpu_bvalue across any delay slot. */ + tcg_gen_mov_i32(cpu_bvalue, reg_for_read(dc, ra)); + + /* Store the branch taken destination into btarget. */ + if (dest_rb) { + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], dc->base.pc_next); + } else { + dc->jmp_dest = dc->base.pc_next + dest_imm; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); + } + + /* Compute the final destination into btarget. */ + zero = tcg_const_i32(0); + next = tcg_const_i32(dc->base.pc_next + (delay + 1) * 4); + tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, + reg_for_read(dc, ra), zero, + cpu_btarget, next); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(next); + + return true; +} + +#define DO_BCC(NAME, COND) \ + static bool trans_##NAME(DisasContext *dc, arg_typea_bc *arg) \ + { return do_bcc(dc, arg->rb, 0, COND, arg->ra, false); } \ + static bool trans_##NAME##d(DisasContext *dc, arg_typea_bc *arg) \ + { return do_bcc(dc, arg->rb, 0, COND, arg->ra, true); } \ + static bool trans_##NAME##i(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_bcc(dc, 0, arg->imm, COND, arg->ra, false); } \ + static bool trans_##NAME##id(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_bcc(dc, 0, arg->imm, COND, arg->ra, true); } + +DO_BCC(beq, TCG_COND_EQ) +DO_BCC(bge, TCG_COND_GE) +DO_BCC(bgt, TCG_COND_GT) +DO_BCC(ble, TCG_COND_LE) +DO_BCC(blt, TCG_COND_LT) +DO_BCC(bne, TCG_COND_NE) + static bool trans_brk(DisasContext *dc, arg_typea_br *arg) { if (trap_userspace(dc, true)) { @@ -1445,52 +1497,6 @@ static void dec_msr(DisasContext *dc) } } -static void dec_bcc(DisasContext *dc) -{ - static const TCGCond mb_to_tcg_cc[] = { - [CC_EQ] = TCG_COND_EQ, - [CC_NE] = TCG_COND_NE, - [CC_LT] = TCG_COND_LT, - [CC_LE] = TCG_COND_LE, - [CC_GE] = TCG_COND_GE, - [CC_GT] = TCG_COND_GT, - }; - unsigned int cc; - unsigned int dslot; - TCGv_i32 zero, next; - - cc = EXTRACT_FIELD(dc->ir, 21, 23); - dslot = dc->ir & (1 << 25); - - if (dslot && setup_dslot(dc)) { - return; - } - - dc->jmp_cond = mb_to_tcg_cc[cc]; - - /* Cache the condition register in cpu_bvalue across any delay slot. */ - tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]); - - /* Store the branch taken destination into btarget. */ - if (dc->type_b) { - dc->jmp_dest = dc->base.pc_next + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); - } else { - dc->jmp_dest = -1; - tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb), - dc->base.pc_next); - } - - /* Compute the final destination into btarget. */ - zero = tcg_const_i32(0); - next = tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4); - tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, - reg_for_read(dc, dc->ra), zero, - cpu_btarget, next); - tcg_temp_free_i32(zero); - tcg_temp_free_i32(next); -} - static inline void do_rti(DisasContext *dc) { TCGv_i32 t0, t1; @@ -1623,7 +1629,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, From patchwork Tue Aug 25 20:59:42 2020 Content-Type: text/plain; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 69/77] target/microblaze: Convert dec_rts to decodetree Date: Tue, 25 Aug 2020 13:59:42 -0700 Message-Id: <20200825205950.730499-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 5 ++++ target/microblaze/translate.c | 54 +++++++++++++++------------------- 2 files changed, 29 insertions(+), 30 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 21d08289f7..f12e85b492 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -199,6 +199,11 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +rtbd 101101 10010 ..... ................ @typeb_bc +rtid 101101 10001 ..... ................ @typeb_bc +rted 101101 10100 ..... ................ @typeb_bc +rtsd 101101 10000 ..... ................ @typeb_bc + sb 110100 ..... ..... ..... 0000 000 0000 @typea sbr 110100 ..... ..... ..... 0100 000 0000 @typea sbea 110100 ..... ..... ..... 0001 000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f79b02e987..22569693f7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1291,6 +1291,30 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg) return true; } +static bool do_rts(DisasContext *dc, arg_typeb_bc *arg, int to_set) +{ + if (trap_userspace(dc, to_set)) { + return true; + } + if (setup_dslot(dc)) { + return true; + } + dc->tb_flags_to_set |= to_set; + + dc->jmp_cond = TCG_COND_ALWAYS; + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, arg->ra), arg->imm); + return true; +} + +#define DO_RTS(NAME, IFLAG) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_rts(dc, arg, IFLAG); } + +DO_RTS(rtbd, DRTB_FLAG) +DO_RTS(rtid, DRTI_FLAG) +DO_RTS(rted, DRTE_FLAG) +DO_RTS(rtsd, 0) static void msr_read(DisasContext *dc, TCGv_i32 d) { @@ -1553,35 +1577,6 @@ static inline void do_rte(DisasContext *dc) dc->tb_flags &= ~DRTE_FLAG; } -static void dec_rts(DisasContext *dc) -{ - unsigned int b_bit, i_bit, e_bit; - - i_bit = dc->ir & (1 << 21); - b_bit = dc->ir & (1 << 22); - e_bit = dc->ir & (1 << 23); - - if (trap_userspace(dc, i_bit || b_bit || e_bit)) { - return; - } - - if (setup_dslot(dc)) { - return; - } - - if (i_bit) { - dc->tb_flags |= DRTI_FLAG; - } else if (b_bit) { - dc->tb_flags |= DRTB_FLAG; - } else if (e_bit) { - dc->tb_flags |= DRTE_FLAG; - } - - dc->jmp_cond = TCG_COND_ALWAYS; - dc->jmp_dest = -1; - tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); -} - static void dec_null(DisasContext *dc) { if (trap_illegal(dc, true)) { @@ -1629,7 +1624,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} From patchwork Tue Aug 25 20:59:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248306 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp9131ejn; Tue, 25 Aug 2020 14:24:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyv8sBvKmuztICjCw1WlsJbdq77vJ7W2bF4hENhWDQVtLx7ku8zau8vFqBL47cNBEcSoCF4 X-Received: by 2002:a25:8b09:: with SMTP id i9mr17090536ybl.149.1598390657327; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 70/77] target/microblaze: Tidy do_rti, do_rtb, do_rte Date: Tue, 25 Aug 2020 13:59:43 -0700 Message-Id: <20200825205950.730499-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since cpu_msr is no longer a 64-bit quantity, we can simplify the arithmetic in these functions. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 65 ++++++++++++++--------------------- 1 file changed, 25 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 22569693f7..71ceabfffd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1521,59 +1521,44 @@ static void dec_msr(DisasContext *dc) } } -static inline void do_rti(DisasContext *dc) +static void do_rti(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_ori_i32(t1, t1, MSR_IE); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_IE); + tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); + + tcg_temp_free_i32(tmp); dc->tb_flags &= ~DRTI_FLAG; } -static inline void do_rtb(DisasContext *dc) +static void do_rtb(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_andi_i32(t1, t1, ~MSR_BIP); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP)); + tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); + + tcg_temp_free_i32(tmp); dc->tb_flags &= ~DRTB_FLAG; } -static inline void do_rte(DisasContext *dc) +static void do_rte(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_ori_i32(t1, t1, MSR_EE); - tcg_gen_andi_i32(t1, t1, ~MSR_EIP); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_EE); + tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_temp_free_i32(tmp); dc->tb_flags &= ~DRTE_FLAG; } From patchwork Tue Aug 25 20:59:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248329 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp16857ejn; Tue, 25 Aug 2020 14:41:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyf2jKwfKFmaJnn1dlNIhPnTRWcZJKgcdVtP6P7J2WtEL3UIPZiewtOJGZR313AaKjLKRjn X-Received: by 2002:a25:d497:: with SMTP id m145mr17106606ybf.484.1598391687758; Tue, 25 Aug 2020 14:41:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391687; cv=none; d=google.com; s=arc-20160816; b=ZuXT/qetlmXo1fmBDmL8uhq1lGYE02wiSQ3xC7KrYI00QP94nLG6FgxVnHHucocVvW sP85yiIfJ/uNmGi+6XreVARmOQaIeKtk5T6ydKaYRqTv4eQ0Kycu9c+Pj+AU2bimv0vM AepJXc+TKZOXKRrf8cwpmev7H5fEL3fcaLhS4cJbP0wsOfsiN+wusobr8d77TIOdd8Oz LXv5DTPmC9qUgiq/RY9TwBIpOILnuWsVVqdsljsKsmSy3YR76Pj86YeCBxCbdBUb9v5G D9vkI4hoHcw/gtB1kVYQZZ0J1zvREYu2Z9zOBcFRR5UngynjTWs+4xqWp3sP3wfLmOqe d4EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4nKzEtDvQ/HGhwSfCseZ1hDjTvu3zAu+DRp/TAzlmzg=; b=GyF+K1m42xLnRgqUR1h9eUEI8tV9qowpCwlvaxIhXqvj8768/jWmAJkjjU+dcmvOum aIlALEYbKw6Vpa3bP68hM74KZbqtXyttHt9VUrhoNIOLx/mh6Ng8HqZZ7cqTOo4ew0Fm eKd/eVqHs3WXkon1vQQoGQdgKfLM6HZxpsAnD/xzxykSsVOTrzpSNdRMwC6isdDwP+f8 rWrstBFp1GM5826mBmnokVui3S/hS7CFp13moE/nDomIWH9q/RVuuP2dU0I+zLE6RWPf r2RM5RVaTiUsw31pFJNQcKDsUeHwyEnAQdsRMJdUv0IzkkVP1kHZG8irY519jBwMUM1e ntmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DcvCRwsl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 71/77] target/microblaze: Convert msrclr, msrset to decodetree Date: Tue, 25 Aug 2020 13:59:44 -0700 Message-Id: <20200825205950.730499-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split this out of dec_msr. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 85 +++++++++++++++++++--------------- 2 files changed, 54 insertions(+), 37 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index f12e85b492..e80283cce6 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -24,6 +24,7 @@ &typeb rd ra imm &typeb_br rd imm &typeb_bc ra imm +&type_msr rd imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -55,6 +56,8 @@ %ieimm 6:5 0:5 @typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=%ieimm +@type_msr ...... rd:5 ...... imm:15 &type_msr + ### add 000000 ..... ..... ..... 000 0000 0000 @typea @@ -176,6 +179,9 @@ lwi 111010 ..... ..... ................ @typeb mbar 101110 imm:5 00010 0000 0000 0000 0100 +msrclr 100101 ..... 100010 ............... @type_msr +msrset 100101 ..... 100000 ............... @type_msr + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 71ceabfffd..e05523bd5b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1338,16 +1338,61 @@ static void msr_write(DisasContext *dc, TCGv_i32 v) tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } +static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) +{ + uint32_t imm = arg->imm; + + if (trap_userspace(dc, imm != MSR_C)) { + return true; + } + + if (arg->rd) { + msr_read(dc, cpu_R[arg->rd]); + } + + /* + * Handle the carry bit separately. + * This is the only bit that userspace can modify. + */ + if (imm & MSR_C) { + tcg_gen_movi_i32(cpu_msr_c, set); + } + + /* + * MSR_C and MSR_CC set above. + * MSR_PVR is not writable, and is always clear. + */ + imm &= ~(MSR_C | MSR_CC | MSR_PVR); + + if (imm != 0) { + if (set) { + tcg_gen_ori_i32(cpu_msr, cpu_msr, imm); + } else { + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); + } + dc->cpustate_changed = 1; + } + return true; +} + +static bool trans_msrclr(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, false); +} + +static bool trans_msrset(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, true); +} + static void dec_msr(DisasContext *dc) { CPUState *cs = CPU(dc->cpu); - TCGv_i32 t0, t1; unsigned int sr, rn; - bool to, clrset, extended = false; + bool to, extended = false; sr = extract32(dc->imm, 0, 14); to = extract32(dc->imm, 14, 1); - clrset = extract32(dc->imm, 15, 1) == 0; dc->type_b = 1; if (to) { dc->cpustate_changed = 1; @@ -1361,40 +1406,6 @@ static void dec_msr(DisasContext *dc) extended = extract32(dc->imm, e_bit[to], 1); } - /* msrclr and msrset. */ - if (clrset) { - bool clr = extract32(dc->ir, 16, 1); - - if (!dc->cpu->cfg.use_msr_instr) { - /* nop??? */ - return; - } - - if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) { - return; - } - - if (dc->rd) - msr_read(dc, cpu_R[dc->rd]); - - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - msr_read(dc, t0); - tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc))); - - if (clr) { - tcg_gen_not_i32(t1, t1); - tcg_gen_and_i32(t0, t0, t1); - } else - tcg_gen_or_i32(t0, t0, t1); - msr_write(dc, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - dc->base.is_jmp = DISAS_UPDATE; - return; - } - if (trap_userspace(dc, to)) { return; } From patchwork Tue Aug 25 20:59:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248310 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp9875ejn; Tue, 25 Aug 2020 14:25:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwpRaJd7OOaR6PXNVE0wcCnEfhYPtCjPbv/QvpjQcy5FhkQyrBbbkn2etk9cVpicNzjFd5D X-Received: by 2002:a25:4b47:: with SMTP id y68mr15253088yba.89.1598390754996; Tue, 25 Aug 2020 14:25:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598390754; cv=none; d=google.com; s=arc-20160816; b=WL5sQUWvYknme5b+zAOncR/O/PF4ezWkqqwRsD7pOIL3fQJiE5Dz1CswyPotMykyGz VZYgQRDnSeStmvSiuCjpZb466/m/OUSjmgfEk3/BjrPFGv3PDt42B//8ilJNXn+8lIyN sO2ds96ErLfLuHt4EyKpXmmswR6OSgqYoaFPGTSXupjlnLy1F2NzktCwTPLhejUhEBtb Morb4oERR0hnpGb6RhZBHQeHdtCMI9Xh0xTg5ECBPCR9uQiGrvVicsezEa43tJnWiUl8 0HlBqBfl9/SVPnEnesSlGnq6ghahtLJfeCwlacajDvFiL7jDNROTV6FtFU8RHjulDiwJ kXng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=m6fh136WeDEV1UTM3Bn7M1wdgMRKLLNiRWtU8qzbrz8=; b=UwhbhTtjRWFTOLahu6XHp/ijbF75stKJJnujqKa0gbNuRfRGBekrlWSBJhUSNmrRst f00AsP7rESc1ndtOSODOdSRzWs5p+UGEYDrdEGWNjvQ1zaBCH14y0IbPZnTWzC7K8N2Q Pkgezjcz3dIEJK2KhPfXyhA/u+N4RK81c9wr4wf45BK9WnRJymerEvhmJc6ycUdfcSQD dXEgrwZEggABmPcYvXgisHm+FyZuXc9l/UTdIOzJQ3UvNFhmcEWKlT74wr8fyCh00KG9 562o1TsF2M/oEzjMp71jiToyRO8+W9dFqozLXXIF0y0D9qMvXHBZpeJc8pGpDfdnwBmd yBcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oDega+RG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 72/77] target/microblaze: Convert dec_msr to decodetree Date: Tue, 25 Aug 2020 13:59:45 -0700 Message-Id: <20200825205950.730499-73-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 + target/microblaze/translate.c | 270 +++++++++++++++++---------------- 2 files changed, 139 insertions(+), 134 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index e80283cce6..48c60082e0 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -179,6 +179,9 @@ lwi 111010 ..... ..... ................ @typeb mbar 101110 imm:5 00010 0000 0000 0000 0100 +mfs 100101 rd:5 0 e:1 000 10 rs:14 +mts 100101 0 e:1 000 ra:5 11 rs:14 + msrclr 100101 ..... 100010 ............... @type_msr msrset 100101 ..... 100000 ............... @type_msr diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e05523bd5b..e9e4a0e1db 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1327,6 +1327,7 @@ static void msr_read(DisasContext *dc, TCGv_i32 d) tcg_temp_free_i32(t); } +#ifndef CONFIG_USER_ONLY static void msr_write(DisasContext *dc, TCGv_i32 v) { dc->cpustate_changed = 1; @@ -1337,6 +1338,7 @@ static void msr_write(DisasContext *dc, TCGv_i32 v) /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */ tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } +#endif static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) { @@ -1385,151 +1387,152 @@ static bool trans_msrset(DisasContext *dc, arg_type_msr *arg) return do_msrclrset(dc, arg, true); } -static void dec_msr(DisasContext *dc) +static bool trans_mts(DisasContext *dc, arg_mts *arg) { - CPUState *cs = CPU(dc->cpu); - unsigned int sr, rn; - bool to, extended = false; - - sr = extract32(dc->imm, 0, 14); - to = extract32(dc->imm, 14, 1); - dc->type_b = 1; - if (to) { - dc->cpustate_changed = 1; + if (trap_userspace(dc, true)) { + return true; } - /* Extended MSRs are only available if addr_size > 32. */ - if (dc->cpu->cfg.addr_size > 32) { - /* The E-bit is encoded differently for To/From MSR. */ - static const unsigned int e_bit[] = { 19, 24 }; - - extended = extract32(dc->imm, e_bit[to], 1); +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + if (arg->e && arg->rs != 0x1003) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid extended mts reg 0x%x\n", arg->rs); + return true; } - if (trap_userspace(dc, to)) { - return; - } + TCGv_i32 src = reg_for_read(dc, arg->ra); + switch (arg->rs) { + case SR_MSR: + msr_write(dc, src); + break; + case SR_FSR: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); + break; + case 0x800: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, slr)); + break; + case 0x802: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, shr)); + break; -#if !defined(CONFIG_USER_ONLY) - /* Catch read/writes to the mmu block. */ - if ((sr & ~0xff) == 0x1000) { - TCGv_i32 tmp_ext = tcg_const_i32(extended); - TCGv_i32 tmp_sr; + case 0x1000: /* PID */ + case 0x1001: /* ZPR */ + case 0x1002: /* TLBX */ + case 0x1003: /* TLBLO */ + case 0x1004: /* TLBHI */ + case 0x1005: /* TLBSX */ + { + TCGv_i32 tmp_ext = tcg_const_i32(arg->e); + TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7); - sr &= 7; - tmp_sr = tcg_const_i32(sr); - if (to) { - gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); - } else { - gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr); + gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src); + tcg_temp_free_i32(tmp_reg); + tcg_temp_free_i32(tmp_ext); } - tcg_temp_free_i32(tmp_sr); - tcg_temp_free_i32(tmp_ext); - return; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs); + return true; } + dc->cpustate_changed = 1; + return true; +#endif +} + +static bool trans_mfs(DisasContext *dc, arg_mfs *arg) +{ + TCGv_i32 dest = reg_for_write(dc, arg->rd); + + if (arg->e) { + switch (arg->rs) { + case SR_EAR: + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_extrh_i64_i32(dest, t64); + tcg_temp_free_i64(t64); + } + return true; +#ifndef CONFIG_USER_ONLY + case 0x1003: /* TLBLO */ + /* Handled below. */ + break; +#endif + case 0x2006 ... 0x2009: + /* High bits of PVR6-9 not implemented. */ + tcg_gen_movi_i32(dest, 0); + return true; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid extended mfs reg 0x%x\n", arg->rs); + return true; + } + } + + switch (arg->rs) { + case SR_PC: + tcg_gen_movi_i32(dest, dc->base.pc_next); + break; + case SR_MSR: + msr_read(dc, dest); + break; + case SR_EAR: + { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_extrl_i64_i32(dest, t64); + tcg_temp_free_i64(t64); + } + break; + case SR_ESR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, esr)); + break; + case SR_FSR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, fsr)); + break; + case SR_BTR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, btr)); + break; + case SR_EDR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, edr)); + break; + case 0x800: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, slr)); + break; + case 0x802: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, shr)); + break; + +#ifndef CONFIG_USER_ONLY + case 0x1000: /* PID */ + case 0x1001: /* ZPR */ + case 0x1002: /* TLBX */ + case 0x1003: /* TLBLO */ + case 0x1004: /* TLBHI */ + case 0x1005: /* TLBSX */ + { + TCGv_i32 tmp_ext = tcg_const_i32(arg->e); + TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7); + + gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg); + tcg_temp_free_i32(tmp_reg); + tcg_temp_free_i32(tmp_ext); + } + break; #endif - if (to) { - switch (sr) { - case SR_PC: - break; - case SR_MSR: - msr_write(dc, cpu_R[dc->ra]); - break; - case SR_EAR: - { - TCGv_i64 t64 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); - tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)); - tcg_temp_free_i64(t64); - } - break; - case SR_ESR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, esr)); - break; - case SR_FSR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, fsr)); - break; - case SR_BTR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, btr)); - break; - case SR_EDR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, edr)); - break; - case 0x800: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, slr)); - break; - case 0x802: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, shr)); - break; - default: - cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr); - break; - } - } else { - switch (sr) { - case SR_PC: - tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); - break; - case SR_MSR: - msr_read(dc, cpu_R[dc->rd]); - break; - case SR_EAR: - { - TCGv_i64 t64 = tcg_temp_new_i64(); - tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); - if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); - } else { - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); - } - tcg_temp_free_i64(t64); - } - break; - case SR_ESR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, esr)); - break; - case SR_FSR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, fsr)); - break; - case SR_BTR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, btr)); - break; - case SR_EDR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, edr)); - break; - case 0x800: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, slr)); - break; - case 0x802: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, shr)); - break; - case 0x2000 ... 0x200c: - rn = sr & 0xf; - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, pvr.regs[rn])); - break; - default: - cpu_abort(cs, "unknown mfs reg %x\n", sr); - break; - } - } - - if (dc->rd == 0) { - tcg_gen_movi_i32(cpu_R[0], 0); + case 0x2000 ... 0x200c: + tcg_gen_ld_i32(dest, cpu_env, + offsetof(CPUMBState, pvr.regs[arg->rs - 0x2000])); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid mfs reg 0x%x\n", arg->rs); + break; } + return true; } static void do_rti(DisasContext *dc) @@ -1620,7 +1623,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} }; From patchwork Tue Aug 25 20:59:46 2020 Content-Type: text/plain; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 73/77] target/microblaze: Convert dec_stream to decodetree Date: Tue, 25 Aug 2020 13:59:46 -0700 Message-Id: <20200825205950.730499-74-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 ++++ target/microblaze/translate.c | 64 ++++++++++++++++++++++++++-------- 2 files changed, 55 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 48c60082e0..79d32c826c 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -156,6 +156,9 @@ flt 010110 ..... ..... ----- 0101 000 0000 @typea0 fint 010110 ..... ..... ----- 0110 000 0000 @typea0 fsqrt 010110 ..... ..... 00000 0111 000 0000 @typea0 +get 011011 rd:5 00000 0 ctrl:5 000000 imm:4 +getd 010011 rd:5 00000 rb:5 0 ctrl:5 00000 + idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea @@ -198,6 +201,9 @@ pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea +put 011011 00000 ra:5 1 ctrl:5 000000 imm:4 +putd 010011 00000 ra:5 rb:5 1 ctrl:5 00000 + rsub 000001 ..... ..... ..... 000 0000 0000 @typea rsubc 000011 ..... ..... ..... 000 0000 0000 @typea rsubk 000101 ..... ..... ..... 000 0000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e9e4a0e1db..0a05b49f8e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1587,33 +1587,68 @@ static void dec_null(DisasContext *dc) } /* Insns connected to FSL or AXI stream attached devices. */ -static void dec_stream(DisasContext *dc) +static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl) { TCGv_i32 t_id, t_ctrl; - int ctrl; if (trap_userspace(dc, true)) { - return; + return true; } t_id = tcg_temp_new_i32(); - if (dc->type_b) { - tcg_gen_movi_i32(t_id, dc->imm & 0xf); - ctrl = dc->imm >> 10; + if (rb) { + tcg_gen_andi_i32(t_id, cpu_R[rb], 0xf); } else { - tcg_gen_andi_i32(t_id, cpu_R[dc->rb], 0xf); - ctrl = dc->imm >> 5; + tcg_gen_movi_i32(t_id, imm); } t_ctrl = tcg_const_i32(ctrl); - - if (dc->rd == 0) { - gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); - } else { - gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); - } + gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl); tcg_temp_free_i32(t_id); tcg_temp_free_i32(t_ctrl); + return true; +} + +static bool trans_get(DisasContext *dc, arg_get *arg) +{ + return do_get(dc, arg->rd, 0, arg->imm, arg->ctrl); +} + +static bool trans_getd(DisasContext *dc, arg_getd *arg) +{ + return do_get(dc, arg->rd, arg->rb, 0, arg->ctrl); +} + +static bool do_put(DisasContext *dc, int ra, int rb, int imm, int ctrl) +{ + TCGv_i32 t_id, t_ctrl; + + if (trap_userspace(dc, true)) { + return true; + } + + t_id = tcg_temp_new_i32(); + if (rb) { + tcg_gen_andi_i32(t_id, cpu_R[rb], 0xf); + } else { + tcg_gen_movi_i32(t_id, imm); + } + + t_ctrl = tcg_const_i32(ctrl); + gen_helper_get(t_id, t_ctrl, reg_for_read(dc, ra)); + tcg_temp_free_i32(t_id); + tcg_temp_free_i32(t_ctrl); + return true; +} + +static bool trans_put(DisasContext *dc, arg_put *arg) +{ + return do_put(dc, arg->ra, 0, arg->imm, arg->ctrl); +} + +static bool trans_putd(DisasContext *dc, arg_putd *arg) +{ + return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl); } static struct decoder_info { @@ -1623,7 +1658,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} }; From patchwork Tue Aug 25 20:59:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248317 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp11821ejn; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 74/77] target/microblaze: Remove last of old decoder Date: Tue, 25 Aug 2020 13:59:47 -0700 Message-Id: <20200825205950.730499-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All instructions have been convered. Issue sigill if decodetree does not match. Remove argument decode from DisasContext. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 75 +---------------------------------- 1 file changed, 2 insertions(+), 73 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0a05b49f8e..2df22e8c2a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -65,13 +65,7 @@ typedef struct DisasContext { bool r0_set; /* Decoder. */ - int type_b; - uint32_t ir; uint32_t ext_imm; - uint8_t opcode; - uint8_t rd, ra, rb; - uint16_t imm; - unsigned int cpustate_changed; unsigned int tb_flags; unsigned int tb_flags_to_set; @@ -184,21 +178,6 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } -static int32_t dec_alu_typeb_imm(DisasContext *dc) -{ - tcg_debug_assert(dc->type_b); - return typeb_imm(dc, (int16_t)dc->imm); -} - -static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) -{ - if (dc->type_b) { - tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); - return &cpu_imm; - } - return &cpu_R[dc->rb]; -} - static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { if (likely(reg != 0)) { @@ -1094,7 +1073,7 @@ static bool setup_dslot(DisasContext *dc) } dc->tb_flags_to_set |= D_FLAG; - if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + if (dc->tb_flags & IMM_FLAG) { dc->tb_flags_to_set |= BIMM_FLAG; } return false; @@ -1576,16 +1555,6 @@ static void do_rte(DisasContext *dc) dc->tb_flags &= ~DRTE_FLAG; } -static void dec_null(DisasContext *dc) -{ - if (trap_illegal(dc, true)) { - return; - } - qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", - (uint32_t)dc->base.pc_next, dc->opcode); - dc->abort_at_next_insn = 1; -} - /* Insns connected to FSL or AXI stream attached devices. */ static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl) { @@ -1651,46 +1620,6 @@ static bool trans_putd(DisasContext *dc, arg_putd *arg) return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl); } -static struct decoder_info { - struct { - uint32_t bits; - uint32_t mask; - }; - void (*dec)(DisasContext *dc); -} decinfo[] = { - {{0, 0}, dec_null} -}; - -static void old_decode(DisasContext *dc, uint32_t ir) -{ - int i; - - dc->ir = ir; - - if (ir == 0) { - trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); - /* Don't decode nop/zero instructions any further. */ - return; - } - - /* bit 2 seems to indicate insn type. */ - dc->type_b = ir & (1 << 29); - - dc->opcode = EXTRACT_FIELD(ir, 26, 31); - dc->rd = EXTRACT_FIELD(ir, 21, 25); - dc->ra = EXTRACT_FIELD(ir, 16, 20); - dc->rb = EXTRACT_FIELD(ir, 11, 15); - dc->imm = EXTRACT_FIELD(ir, 0, 15); - - /* Large switch for all insns. */ - for (i = 0; i < ARRAY_SIZE(decinfo); i++) { - if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { - decinfo[i].dec(dc); - break; - } - } -} - static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); @@ -1757,7 +1686,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) ir = cpu_ldl_code(env, dc->base.pc_next); if (!decode(dc, ir)) { - old_decode(dc, ir); + trap_illegal(dc, true); } if (dc->r0) { From patchwork Tue Aug 25 20:59:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248336 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp20220ejn; Tue, 25 Aug 2020 14:49:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw6BbudlhMw7OW2mI3fG7BWV2qsvr+NIqvJqSqnKJzSSGh5bN4175z2QsShYrUxP84BAiXz X-Received: by 2002:a5b:486:: with SMTP id n6mr16467140ybp.432.1598392161132; Tue, 25 Aug 2020 14:49:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598392161; cv=none; d=google.com; s=arc-20160816; b=ynxiDIz8i4LAIVjES3DgEvHA5xvCDyai+xnC3w/LFivcSYMErMkp3Ek2u/kNYAQb2s /sofn6B10zf07eagdWuwClf7ZnoAwBgIqA9cXK+dIEUJwFSl5IQuhy992hjqWrVV+Gg7 I+95/fRGIO/cbvhgniugj4RgUCygvVBw3tJGbHiiWFrD6Ts98jeVMDv3XFyz0vyZuofF fqdN99FKqujS6M/TYXOWIozSsOm2O66XfAJ2Zlh/P1NH5a8u/m4MovzFu43wNuCTZrNE MWvdVOKmNi2RY2gDjWBD407/Yr9iojYcEy3XQueSvg2tHm1WnH+FNgKclQvc+3bOAmmr cFeQ== ARC-Message-Signature: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 75/77] target/microblaze: Remove cpu_R[0] Date: Tue, 25 Aug 2020 13:59:48 -0700 Message-Id: <20200825205950.730499-76-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not initialize cpu_R[0], as this should be totally unused. The cpu_for_read and cpu_for_write functions use a local temp. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2df22e8c2a..c8eb68ce4b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1875,7 +1875,13 @@ void mb_tcg_init(void) static const struct { TCGv_i32 *var; int ofs; char name[8]; } i32s[] = { - R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), + /* + * Note that r0 is handled specially in reg_for_read + * and reg_for_write. Nothing should touch cpu_R[0]. + * Leave that element NULL, which will assert quickly + * inside the tcg generator functions. + */ + R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), From patchwork Tue Aug 25 20:59:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248331 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp17449ejn; Tue, 25 Aug 2020 14:42:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxkhmcdEZtR5LfEFtci/y5r9slzefXkmI3tSsYHe9GrRUCDZ1+2c0JfWWMvQOOXA/rUHvUB X-Received: by 2002:a25:c0c7:: with SMTP id c190mr17462650ybf.34.1598391775094; Tue, 25 Aug 2020 14:42:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598391775; cv=none; d=google.com; s=arc-20160816; b=LBs0QS13rAPMQBRgAqdlCP0PmlK3Co67+L7Trj/m4yUwxHM7E0tMpTdusFizVCqAfk GCPtPgK+aF8oC4UMlsX95GWDjbtUv8xU+aHJPxgdO38/LO1cRDXIHK1Wvw2az9kYrG5b wEJODSHqaUUzCU46RqOwSFvLtc3jIwJseoKxJ4TQC/vQoYPXnrJcMczvlTPbACD2U2zO ih8GfJakT8cmojuNdwnkRJmvl9xKjX8PcrJL8JwXNH1rkocwR2YuBDTXoGgs0szUA752 A3azM6/Ge6yFR1vci4BfQuubz7oe95rJuLMLw4nTwY9PSZH9TbAGiAF1gDLZDqRHGUQy vEQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/v81xo2Oa10INQECM2V7ceku/8UgY141rA25N+r+rLA=; b=p7dlT8kDox1Gs6N81LZrcQUT7wYoR65hVsVHsWr44Qxs1Y3wv5wRqe1zgAeh7j7/34 flQHmjI7uzhMVG41mR+Ip51Gdmk/zKmKKN8RpNyXtIYqUIyPzYRr6rFciMHZfX5Fz8kf WBPdOSgxnDqk/EcgeyI6Rtx57Jck7jCiJ+tMZu+IpQWke9dfPJQb07EBS60ZdYR1cHzv UBa20Nn6Y6/xilTpuin77t06CoGuFXg2gcQGqXRpwihqD4yRvTk4f8WWGgiUFspSkyPC 7mK2Swv3nML1VqN26aXf+ktO4Zqn++ZTn1FQzgSAmFcwkcTZMXIs+HQG3caSIcSsbrog ru3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D4Zrkdna; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 76/77] target/microblaze: Add flags markup to some helpers Date: Tue, 25 Aug 2020 13:59:49 -0700 Message-Id: <20200825205950.730499-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The mmu_read, mmu_write, get, and put helpers do not touch the general registers, or any of the other variables managed by tcg. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 3980fba797..f740835fcb 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -21,11 +21,11 @@ DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_3(mmu_read, i32, env, i32, i32) -DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32) #endif DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_2(get, i32, i32, i32) -DEF_HELPER_3(put, void, i32, i32, i32) +DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32) +DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32) From patchwork Tue Aug 25 20:59:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248337 Delivered-To: patch@linaro.org Received: by 2002:a17:906:6447:0:0:0:0 with SMTP id l7csp20891ejn; Tue, 25 Aug 2020 14:50:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxd1WiAXwRbEDW9DcwhixFfQro946h704ywqM2sERbY4fDJjbzAM0eF2s4qqJxAU0Ljrr0D X-Received: by 2002:a25:aa72:: with SMTP id s105mr16107645ybi.463.1598392253603; Tue, 25 Aug 2020 14:50:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598392253; cv=none; d=google.com; s=arc-20160816; b=oqgc1tTqi2ShbVgNfEKRJmG5JxI1DUijSaXl4JE2QFIzcFNDVKu8GE0nXzno1qNHwy 4ixAikSdHwXZDQTiXTqi8SfVTl4c6AN+/3EjNp2jKIDAbDR68lVZNGCB27byYTWih0XS QmFk7i5PgVD4W9BlSAZpONw0fD/n/Gy/JV/mM+d3j0lsNvbFesT6JVi17EG/9RCEpisT U4qsBWxw5wA6ipMJ4ORaPbUSJF5GeVUBOH3HOyHKXq0yWrPKoCEEio3FSAws5LrvRHip qBVMzq4pymiGGWroIoyNL/oT8fWVIkH98xDxukj8dGkCC5GgYADhYkILOIUHCpnx2uPp OlEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eRFId6Ea30idq3xTokmsUXGS84tzittdNxqSsVZitX8=; b=iB7/O55SkUUZBOLdSdTs21eq9Z/3IqE2tU23HOq3Ypf8IPYPUop11hgISj4Wxzg//2 aTDUgc/AmitFOKk4EN4tscNOIvdw6HPtNfGLyA9pkvQwukz3LhHQIEkf8VCmd8pq6Thp fqtSfTdIV8HILqnMQBSfqqVh1El85HqpeffrisMKLAUCaYihWI2ig+GO3NxlMjUiV93t WsruewA+1x2EKJ3afG+e/1KxY8s9H6uj3T7iXXQLUyYAqKw99vDbj4NoGqFO+z55hEWi lAAtVsd+SmqNBWOPHLsE0mF8vYGU0T//QDk5iiqfd8vf40h4mTo7W1JJqZCa47UqDTRN WLmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hdRjDgcn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 77/77] target/microblaze: Reduce linux-user address space to 32-bit Date: Tue, 25 Aug 2020 13:59:50 -0700 Message-Id: <20200825205950.730499-78-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" User-space programs cannot use the 64-bit lwea/swea instructions. We can improve code generation and runtime by restricting the user-only address space to 32-bit. Signed-off-by: Richard Henderson --- target/microblaze/cpu-param.h | 15 +++++++++++++++ target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/translate.c | 28 +++++++++++++++++++++++++++- 4 files changed, 45 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 4abbc62d50..4d8297fa94 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -8,9 +8,24 @@ #ifndef MICROBLAZE_CPU_PARAM_H #define MICROBLAZE_CPU_PARAM_H 1 +/* + * While system mode can address up to 64 bits of address space, + * this is done via the lea/sea instructions, which are system-only + * (as they also bypass the mmu). + * + * We can improve the user-only experience by only exposing 32 bits + * of address space. + */ +#ifdef CONFIG_USER_ONLY +#define TARGET_LONG_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#else #define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 +#endif + /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 #define NB_MMU_MODES 3 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 4298f242a6..d11b6fa995 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint32_t pc; uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ - uint64_t ear; + target_ulong ear; uint32_t esr; uint32_t fsr; uint32_t btr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 1667822fb7..48547385b0 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -303,8 +303,8 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, iflags = cpu->env.iflags; qemu_log_mask(CPU_LOG_INT, - "Unaligned access addr=" TARGET_FMT_lx - " pc=%x iflags=%x\n", addr, cpu->env.pc, iflags); + "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n", + (target_ulong)addr, cpu->env.pc, iflags); esr = ESR_EC_UNALIGNED_DATA; if (likely(iflags & ESR_ESS_FLAG)) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c8eb68ce4b..f6e16b7f5a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -729,6 +729,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) return ret; } +#ifndef CONFIG_USER_ONLY static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) { int addr_size = dc->cpu->cfg.addr_size; @@ -754,6 +755,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) } return ret; } +#endif static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) @@ -818,8 +820,12 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +#endif } static bool trans_lbui(DisasContext *dc, arg_typeb *arg) @@ -845,8 +851,12 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +#endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) @@ -872,8 +882,12 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +#endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) @@ -952,8 +966,12 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +#endif } static bool trans_sbi(DisasContext *dc, arg_typeb *arg) @@ -979,8 +997,12 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +#endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) @@ -1006,8 +1028,12 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +#endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) @@ -1851,7 +1877,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n" - "ear=0x%016" PRIx64 " slr=0x%x shr=0x%x\n", + "ear=0x" TARGET_FMT_lx " slr=0x%x shr=0x%x\n", env->esr, env->fsr, env->btr, env->edr, env->ear, env->slr, env->shr);