From patchwork Mon Aug 24 18:35:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 248238 Delivered-To: patch@linaro.org Received: by 2002:a17:906:b105:0:0:0:0 with SMTP id u5csp1893738ejy; Mon, 24 Aug 2020 11:36:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7zzVa65NZfBOpNMFR2AAzgkwBVfRoPNyW9hLHEf61BfQKVC3H6+ZG+NGkF3oOCKoHjj3C X-Received: by 2002:a50:be82:: with SMTP id b2mr6746885edk.303.1598294171862; Mon, 24 Aug 2020 11:36:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598294171; cv=none; d=google.com; s=arc-20160816; b=0jJPNkRPv+4DojNMcbitHbh1TnyXKcQk6GdFedxzeHKvwjCgIY4aDQOUKP+B7WYCh/ wCh2s3xl6WTi4NnG0+gW2O2Nvg6k/Srg0wSTPcCNKF4imc0/cPXhbYN4TDPdgeEwUbUT eWYsqtVlXy+6n6zqESOxdzGSLePWpCv5V5xKuljKZtDCtnVHKWKrb01yh2M4hzfzw4ki 0iAXvsPMMJgJyUwnHgZtrLaisN0TGhnWnVcSiTphg8pWWqfa9YHJowGKVZ8I4rC6+3KU aDdYaZq/16jiUFWkkB8WeAa4MH94xN8fpRPAwPzMSUDTazPnVy5j4WuHR46oi7C6odwc sBXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=LjiJ694sqeXItqprsgR0LHqp1yHVdqalRgKn46ETCXI=; b=AHQZyiT1bBoUE6QU8r8ihElPC+KVsg+q+mmpCfMry1UwEXmQpCcRf8JON+rqxuentS 5wPMwFcu4Ge0Ya2cxtIFgBHYdP7GyUcRIzOfmn2RYhlAIep4FPAF8zkr8uAAmB0gdVdE dqwDZEiSNqpTsRnJua4ajyETUQmgqy+IviYWX7mlh+BP3hxN4ltrHD8W8DPzXhExAlxO A70bCtMxp3/lA7mil+QRYztbS4m2bmS6GloyyRxVFgm0uPCXOe3bHyPsgPS07+sZuA3n JuE0cjdqm512X8yB7tyzPPIIUfr8pe6q5DXOGlyECTxnJ5jO9L7gHpI18p/L5RyLoRGY rcUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=eBGn38EU; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j27si3085885ejf.106.2020.08.24.11.36.11; Mon, 24 Aug 2020 11:36:11 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=eBGn38EU; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726813AbgHXSgK (ORCPT + 15 others); Mon, 24 Aug 2020 14:36:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726303AbgHXSgD (ORCPT ); Mon, 24 Aug 2020 14:36:03 -0400 Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61C8CC061573; Mon, 24 Aug 2020 11:36:03 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id o13so4994315pgf.0; Mon, 24 Aug 2020 11:36:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LjiJ694sqeXItqprsgR0LHqp1yHVdqalRgKn46ETCXI=; b=eBGn38EUCTexlJXnoZmr8djhQNZgb+tpdJHMK20k2uAeo6cD1cl8Ej2Oz/sX7NrqyS owwxqMroLhvs2ntsRaB/8+kjbhrgpD9kqBA+cXYjksnxa4O7B1KRWWZnZdoHW3xJxDXI cjshW3ufvn47v+N/y4fWxQNHRjQRUGTh1Nx77fA9ZRPMk/QF2qp6v8Ctz1lCY3KyNCkK iim5kqaUDijLOdT2yumz/g8YLw9aZ3g5F+hTo6Np0/SQ//QTl1EPJljH9eJAYDJR6Bkr 17lLh8/sKD3JmhYi6GCmaRR0UdrdLWEEyYM+EJnC8xD+B2Rq28cdW43gG1+74dBFe1/e zBcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LjiJ694sqeXItqprsgR0LHqp1yHVdqalRgKn46ETCXI=; b=AJdbRJS4AcJ0UMbQfTjkb/39Ahcef112HdgnRv1mwlki3HlZm+/UCynuPCrhr7lhY1 nBt6YmT8sGpdu0YvoSQlOhnAENR2vgFzxExxqF7LOZ5Cng/z5LwXLdILymBHAoWBbT8t yXfDSF05hb6XzBYII70FNF/n2E1/QztLYR1w5Jh+IRxSHp1IZ8MoDTaz0O/MUx4DIAKc MVDZIMJmWGXR+0K+4gukmkJ1jp/yPuibcL+sAGtp1KM6RE//KDwF85zSMeOT3Rhm8gz+ IraIjZ8RO5rK8k3YVeYpMH8ym0+DQ9K8vIX7j3E2I0wd6Urq8fah+h9fNIOMUIWq82+z VOdw== X-Gm-Message-State: AOAM532cbEc1b7Alx1MQanVcElzIQ04NvDSejY+KVyNC73QWErlhZB1O 9pUs80Tb10nuRYjEEheUR8M= X-Received: by 2002:a17:902:a703:: with SMTP id w3mr4876394plq.259.1598294162686; Mon, 24 Aug 2020 11:36:02 -0700 (PDT) Received: from stbirv-lnx-3.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id j10sm12167900pff.171.2020.08.24.11.36.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 24 Aug 2020 11:36:02 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Cc: Will Deacon , Florian Fainelli , Greg KH , Will Deacon , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , James Morse , Julien Thierry , Suzuki K Poulose , Mark Rutland , Mark Brown , Kristina Martsenko , Sami Tolvanen , Andrew Jones , Ard Biesheuvel , Nick Desaulniers , Fangrui Song , open list , "open list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)" Subject: [PATCH stable 4.19 v2 1/2] arm64: Add support for SB barrier and patch in over DSB; ISB sequences Date: Mon, 24 Aug 2020 11:35:11 -0700 Message-Id: <1598294112-19197-2-git-send-email-f.fainelli@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598294112-19197-1-git-send-email-f.fainelli@gmail.com> References: <1598294112-19197-1-git-send-email-f.fainelli@gmail.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit bd4fb6d270bc423a9a4098108784f7f9254c4e6d upstream We currently use a DSB; ISB sequence to inhibit speculation in set_fs(). Whilst this works for current CPUs, future CPUs may implement a new SB barrier instruction which acts as an architected speculation barrier. On CPUs that support it, patch in an SB; NOP sequence over the DSB; ISB sequence and advertise the presence of the new instruction to userspace. Signed-off-by: Will Deacon [florian: adjust conflicts in cpucaps.h and cpufeature.c] Signed-off-by: Florian Fainelli --- arch/arm64/include/asm/assembler.h | 13 +++++++++++++ arch/arm64/include/asm/barrier.h | 4 ++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/sysreg.h | 6 ++++++ arch/arm64/include/asm/uaccess.h | 3 +-- arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 12 ++++++++++++ arch/arm64/kernel/cpuinfo.c | 1 + 8 files changed, 40 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 5a97ac853168..45ca06f3ddcb 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -127,6 +127,19 @@ .endm /* + * Speculation barrier + */ + .macro sb +alternative_if_not ARM64_HAS_SB + dsb nsh + isb +alternative_else + SB_BARRIER_INSN + nop +alternative_endif + .endm + +/* * Sanitise a 64-bit bounded index wrt speculation, returning zero if out * of bounds. */ diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 822a9192c551..f66bb04fdf2d 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -34,6 +34,10 @@ #define psb_csync() asm volatile("hint #17" : : : "memory") #define csdb() asm volatile("hint #20" : : : "memory") +#define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \ + SB_BARRIER_INSN"nop\n", \ + ARM64_HAS_SB)) + #define mb() dsb(sy) #define rmb() dsb(ld) #define wmb() dsb(st) diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index df8fe8ecc37e..383451eca5c6 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -54,7 +54,8 @@ #define ARM64_WORKAROUND_1463225 33 #define ARM64_SSBS 34 #define ARM64_WORKAROUND_1542419 35 +#define ARM64_HAS_SB 36 -#define ARM64_NCAPS 36 +#define ARM64_NCAPS 37 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ed99d941c462..582075fad6c5 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -97,6 +97,11 @@ #define SET_PSTATE_SSBS(x) __emit_inst(0xd5000000 | REG_PSTATE_SSBS_IMM | \ (!!x)<<8 | 0x1f) +#define __SYS_BARRIER_INSN(CRm, op2, Rt) \ + __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) + +#define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) + #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) @@ -521,6 +526,7 @@ #define ID_AA64ISAR0_AES_SHIFT 4 /* id_aa64isar1 */ +#define ID_AA64ISAR1_SB_SHIFT 36 #define ID_AA64ISAR1_LRCPC_SHIFT 20 #define ID_AA64ISAR1_FCMA_SHIFT 16 #define ID_AA64ISAR1_JSCVT_SHIFT 12 diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index e66b0fca99c2..3c3bf4171f3b 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -46,8 +46,7 @@ static inline void set_fs(mm_segment_t fs) * Prevent a mispredicted conditional call to set_fs from forwarding * the wrong address limit to access_ok under speculation. */ - dsb(nsh); - isb(); + spec_bar(); /* On user-mode return, check fs is correct */ set_thread_flag(TIF_FSCHECK); diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 2bcd6e4f3474..7784f7cba16c 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -49,5 +49,6 @@ #define HWCAP_ILRCPC (1 << 26) #define HWCAP_FLAGM (1 << 27) #define HWCAP_SSBS (1 << 28) +#define HWCAP_SB (1 << 29) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index ac3126aba036..9cc917277a82 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -138,6 +138,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), @@ -1336,6 +1337,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .cpu_enable = cpu_enable_ssbs, }, #endif + { + .desc = "Speculation barrier (SB)", + .capability = ARM64_HAS_SB, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64ISAR1_EL1, + .field_pos = ID_AA64ISAR1_SB_SHIFT, + .sign = FTR_UNSIGNED, + .min_field_value = 1, + }, {}, }; @@ -1390,6 +1401,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SB), HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index dce971f2c167..63a49a66a28c 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -82,6 +82,7 @@ static const char *const hwcap_str[] = { "ilrcpc", "flagm", "ssbs", + "sb", NULL }; From patchwork Mon Aug 24 18:35:12 2020 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id x17si6671818edi.428.2020.08.24.11.36.58; Mon, 24 Aug 2020 11:36:59 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=vc6dI0Sk; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726853AbgHXSgK (ORCPT + 15 others); Mon, 24 Aug 2020 14:36:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726818AbgHXSgF (ORCPT ); Mon, 24 Aug 2020 14:36:05 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10605C061574; Mon, 24 Aug 2020 11:36:05 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id m71so5307620pfd.1; Mon, 24 Aug 2020 11:36:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=addwi+DuL+3In4jU8eTGvwYHm2hYzX6lkO3UYwBb/tE=; b=vc6dI0Skbh92KdhKcVQmbgbIz8zrp7NX2TL+pDNCWRMOmhEq78EETPi0jYncIEg8pE GJfJEHHqPbG+aH5PsJ4KsQr0tfA57DSH9u8qxqFgY5j4zsod+ze93XXmjQSi7/qkAPv5 poTsfxPpPQ+4mngHTY8zKO+9i4qbkPbKQGwbFgMktJ2NMUGSBv0fysS12rcL5n5fuFLA w/HSd9dqXG8DPhu1aRRFZBmnV32qEeGH7XDfjOs10EIqrB93FK8NWlB7vqnsLaDKvBvf g39Rz2PADypNU5TC4Col2JevZqeextTMdln1yA4oun1QHSfSCL2et1kgcMfngQxF9U4d EqtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=addwi+DuL+3In4jU8eTGvwYHm2hYzX6lkO3UYwBb/tE=; b=B4ofwAUgLXpepel2SgB34IekMqllWkQIC1i+znzYeLUp9CbmNAEwSW9PP354mWF0nf fHGfAwvNWt87GdDpvB7ZB76I+BjjMqcy1LGYnvhkaWfUvIcQ7US9YCoO1LDwqcznUpIf PbqYRAXItLvfzPKYfgHFr65mmXBSPZ/52dTh5ua0ymS5rUoJBzFRddw6dHvLaIg6yhU5 4ez9177dRZUQSBKOUb31Kv5Z+Vh3ynnoQQCE/fuvHB0V8eDlt0qBFOEeU2wYVhnEVyFu 0Nia6aFP0aJgMtwM6RTMOGAAIQWrNprFUGmYqc4dqLjEwCVykZX8dzDkjvbOfof8UEkA S58A== X-Gm-Message-State: AOAM5303FRQsvUyAGdx+j+9V+lm2m1FeKtOH7UiirUUkFwe8l2LTVHb0 Dp91LOU/5ZY43oIaQPKoL6E= X-Received: by 2002:a17:902:788e:: with SMTP id q14mr4624503pll.140.1598294164572; Mon, 24 Aug 2020 11:36:04 -0700 (PDT) Received: from stbirv-lnx-3.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id j10sm12167900pff.171.2020.08.24.11.36.02 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 24 Aug 2020 11:36:03 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Cc: Will Deacon , Florian Fainelli , Greg KH , Will Deacon , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , James Morse , Julien Thierry , Suzuki K Poulose , Mark Rutland , Mark Brown , Kristina Martsenko , Sami Tolvanen , Andrew Jones , Ard Biesheuvel , Nick Desaulniers , Fangrui Song , open list , "open list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)" Subject: [PATCH stable 4.19 v2 2/2] arm64: entry: Place an SB sequence following an ERET instruction Date: Mon, 24 Aug 2020 11:35:12 -0700 Message-Id: <1598294112-19197-3-git-send-email-f.fainelli@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598294112-19197-1-git-send-email-f.fainelli@gmail.com> References: <1598294112-19197-1-git-send-email-f.fainelli@gmail.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 679db70801da9fda91d26caf13bf5b5ccc74e8e8 upstream Some CPUs can speculate past an ERET instruction and potentially perform speculative accesses to memory before processing the exception return. Since the register state is often controlled by a lower privilege level at the point of an ERET, this could potentially be used as part of a side-channel attack. This patch emits an SB sequence after each ERET so that speculation is held up on exception return. Signed-off-by: Will Deacon Signed-off-by: Florian Fainelli --- arch/arm64/kernel/entry.S | 2 ++ arch/arm64/kvm/hyp/entry.S | 1 + arch/arm64/kvm/hyp/hyp-entry.S | 4 ++++ 3 files changed, 7 insertions(+) -- 2.7.4 diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 5f800384cb9a..49f80b5627fa 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -363,6 +363,7 @@ alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 .else eret .endif + sb .endm .macro irq_stack_entry @@ -994,6 +995,7 @@ alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 mrs x30, far_el1 .endif eret + sb .endm .align 11 diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S index fad1e164fe48..675fdc186e3b 100644 --- a/arch/arm64/kvm/hyp/entry.S +++ b/arch/arm64/kvm/hyp/entry.S @@ -83,6 +83,7 @@ ENTRY(__guest_enter) // Do not touch any register after this! eret + sb ENDPROC(__guest_enter) ENTRY(__guest_exit) diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S index 24b4fbafe3e4..e35abf84eb96 100644 --- a/arch/arm64/kvm/hyp/hyp-entry.S +++ b/arch/arm64/kvm/hyp/hyp-entry.S @@ -96,6 +96,7 @@ el1_sync: // Guest trapped into EL2 do_el2_call eret + sb el1_hvc_guest: /* @@ -146,6 +147,7 @@ wa_epilogue: mov x0, xzr add sp, sp, #16 eret + sb el1_trap: get_vcpu_ptr x1, x0 @@ -185,6 +187,7 @@ el2_error: b.ne __hyp_panic mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT) eret + sb ENTRY(__hyp_do_panic) mov lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ @@ -193,6 +196,7 @@ ENTRY(__hyp_do_panic) ldr lr, =panic msr elr_el2, lr eret + sb ENDPROC(__hyp_do_panic) ENTRY(__hyp_panic)