From patchwork Tue Oct 10 10:16:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 115382 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3572589qgn; Tue, 10 Oct 2017 03:16:25 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAmeHNtI9Qs7tydYcmiq/6irlDO9qabLU6rGCIMfyYc6AkZnTc4+uzQBHP7syWNsMljmVqH X-Received: by 10.84.253.134 with SMTP id a6mr11546976plm.193.1507630585782; Tue, 10 Oct 2017 03:16:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507630585; cv=none; d=google.com; s=arc-20160816; b=UhbmnNhFl/VgmkslZL08SwfbRvBn2Y37wmygQZXwDDCnt+8X90JqhRQ9PVkqvelhEK chMOsn7VqBvl7PyNZ++0QHgE0EYID204RCw59isuiTRMdIUHlggY4f5uaSNbLw0wxJP1 IL91R9XvAupARYyvE0TL65Vtwc8wmqEAWaOITesStfG+kTzY8CUSbgifmcycJgZpD13D H+Z8ThPwPomYZXXb4IIHI7xv/tLCOfkBza8tb8fisVFHrrdwctsoz/c7t6Oi6KmlMwpd RTzbaVIHa6aoE7Oqq9p4pFSEaquP2fy9XSj8ecx+VgGH7qjybRlL+pKu8r2qEnmkXcsG 85RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=yKAVzGBWQ4vPF3VupNAiDE6/jdxYaONLi/xPJz/sJ5o=; b=nzfIr9pYrmIwh4GncKUIkKYIvHNOtcFHUEl9rzDmUJvYkVl3MEnjgkUV3etfsFGZxF qCj3j1CKiFfUyGa4FmYxaH5S3DCqJeeAl5ZYvj6X2NAQ+WRwfKI3oxfYNIaMkOyg5zIG X3GU7VVohjZ+eIc/AAY1qO1YtKlDavsjRHdL5cfzZMME/k4RmzG7N+7m6H2K3lf3cuQn Rhfc8ip8hS3xVWW9skLh+1fwWysFKwd+NijR5GhpvQtdJnKbkenmXxcughPN5N0l2d6S 3ymd9FqTTD9Fx9ArPNjPXxrLFChOe06ZAFC8XKQcfnAq0QO9GMCyrnFmJbrZCs7G8EyX 7f2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=J4CICszh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x5si8818271plm.625.2017.10.10.03.16.25; Tue, 10 Oct 2017 03:16:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=J4CICszh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756044AbdJJKQX (ORCPT + 26 others); Tue, 10 Oct 2017 06:16:23 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:25047 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751398AbdJJKQU (ORCPT ); Tue, 10 Oct 2017 06:16:20 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9AAGEBq005493; Tue, 10 Oct 2017 05:16:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507630574; bh=c+G/43m7goMlgZwwASxfPz7pRMgekRCZOH3LPDAn3kw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=J4CICszh8dzzilJ1o3wO+LCmYCS4whLbIxmzK8SZbH5XNG/gQLfv09DWxehg6rfRA k5Kn7ASnjNodNyjtfs3ifNlUJyZupB1gzE0yizKjy9QWytkuRul/aPgieqhH+HjsOa o9m6KVBPKL7qYUkX8jSWxNzVPg27XlmjsK7aWRT0= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAGE38013135; Tue, 10 Oct 2017 05:16:14 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 10 Oct 2017 05:16:14 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 10 Oct 2017 05:16:14 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAG8ui025359; Tue, 10 Oct 2017 05:16:12 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Mark Rutland CC: Kishon Vijay Abraham I , , , , , Subject: [PATCH 1/4] dt-bindings: PCI: dra7xx: Add SoC specific compatible strings Date: Tue, 10 Oct 2017 15:46:03 +0530 Message-ID: <20171010101606.15951-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171010101606.15951-1-kishon@ti.com> References: <20171010101606.15951-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add new compatible strings for dra74x SoC (also used by dra76x) and dra72x. This can be used to perform SoC specific configuration (like configuring PCIe in x2 lane mode). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- Documentation/devicetree/bindings/pci/ti-pci.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 7f7af3044016..82cb875e4cec 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -1,8 +1,12 @@ TI PCI Controllers PCIe DesignWare Controller - - compatible: Should be "ti,dra7-pcie" for RC - Should be "ti,dra7-pcie-ep" for EP + - compatible: Should be "ti,dra7-pcie" for RC (deprecated) + Should be "ti,dra7-pcie-ep" for EP (deprecated) + Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode + Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode + Should be "ti,dra726-pcie-rc" for dra72x in RC mode + Should be "ti,dra726-pcie-ep" for dra72x in EP mode - phys : list of PHY specifiers (used by generic PHY framework) - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the number of PHYs as specified in *phys* property. From patchwork Tue Oct 10 10:16:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 115384 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3573015qgn; Tue, 10 Oct 2017 03:16:52 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAQfDSdC4x/7IKJ9MkxTb3XyEAJiF7ha+gIWHpUefm35Hqy79S5eDDBRY/6fGdBkR3dsY++ X-Received: by 10.99.117.10 with SMTP id q10mr11495514pgc.288.1507630612670; Tue, 10 Oct 2017 03:16:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507630612; cv=none; d=google.com; s=arc-20160816; b=QqXHSy0EFP918s9h+tqjgDVh1ygq83iPH34DndMBIOh/nRugp9g8POJr8WxBeMeRGb hHFAjjhN6sKyo8JxZmpJ/Y6QWM7w5MbNAG+6isYgIfKwlfQDgZgDQHaFLEW3s80p4uVy K9B1VqTDIlX1qmt2voZCdtqxT4YltzeHE0hb/kjPbGC5uF7iU7q5wbfUGRh3zpOOslYc OQhelXYT/bbyoj43EiWO/soCe1JPB1SrhbsQOt3Ec3A6hkjb7De/kRw3bBk05VpVkeXN uRIc7y7ePxdEIVBC9eykpfceo8+AMJlixb+Zpg9ARf7BFMro9/tTLU85TmhO/D2A+12v faEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=E+Rjo63ToNGMoympoKHXkQ2sYNvGEGjEh+B/SoGEcTE=; b=rX38TvnaT42Ss/O+x5oZpnN8DMDrYebrvFGV1CgPFeFkVLtJcoWlPCI12lT8PMF2Tf Hl67L7Dl01lmqfebSF1/EH8mgZ68zfa5UlQWaRW4fwoRThk3SAmNUpVUukUwz318Krxs 7UiQRPazSlxGOnyuzOz2XYTxUkHgOsVER9tzYCORG0rKwLkN9rGKFQQM+RNZJTOLdirQ fmbOoC3oT7Oun2Z3xeO9TRF14iXYddVAhibTdZb0pPEVwfiEXN0sh3co+RXs6wWVRFD2 zDpKIXaSWL7xETelufOsX4c+6e2bxUs+Oz0q+eerl4/vaunKsG5isVJiV3SXw39g2nRM 46vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tNMGM4Kc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b8si1167690pfh.564.2017.10.10.03.16.52; Tue, 10 Oct 2017 03:16:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tNMGM4Kc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756077AbdJJKQv (ORCPT + 26 others); Tue, 10 Oct 2017 06:16:51 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:32510 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755871AbdJJKQW (ORCPT ); Tue, 10 Oct 2017 06:16:22 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9AAGHsD023842; Tue, 10 Oct 2017 05:16:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507630577; bh=/Z+kTpajQhSfkRmVd7pqZCx1dFCAqF8vjBEsFpH9i2M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tNMGM4KcxCcNnhDOUXjhvE4bNYdtlQ1zXGpNNPAVoGF0R5aeB0PYyRlTyVZR4kpKI /9xBoO3G7vJ5AbdXyiSjuO3+zP+68AgZXfYijw1Mkue73a9Uv3Bi+TOtFh814gOuMK n/R5FE4KqGvJlMxlGuDVp4VUoa9VXN40JkkNtGXQ= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAGHU0006454; Tue, 10 Oct 2017 05:16:17 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 10 Oct 2017 05:16:17 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 10 Oct 2017 05:16:17 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAG8uj025359; Tue, 10 Oct 2017 05:16:14 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Mark Rutland CC: Kishon Vijay Abraham I , , , , , Subject: [PATCH 2/4] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Date: Tue, 10 Oct 2017 15:46:04 +0530 Message-ID: <20171010101606.15951-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171010101606.15951-1-kishon@ti.com> References: <20171010101606.15951-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add syscon properties required for configuring PCIe in x2 lane mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 82cb875e4cec..455cb74a475c 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -13,6 +13,10 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt + - syscon-lane-conf : phandle/offset pair. Phandle to the system control module and the + register offset to specify 1 lane or 2 lane. + - syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the + register offset to specify lane selection. HOST MODE ========= From patchwork Tue Oct 10 10:16:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 115385 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3573409qgn; Tue, 10 Oct 2017 03:17:15 -0700 (PDT) X-Google-Smtp-Source: AOwi7QC/wZ5BTwfl7vj9PoXuC/oZkxvC/84/G8xv7/1KgKPcrLLVSOC89wWngj78OTpLQ1rLz5dc X-Received: by 10.101.67.137 with SMTP id m9mr11976840pgp.63.1507630635570; Tue, 10 Oct 2017 03:17:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507630635; cv=none; d=google.com; s=arc-20160816; b=AymRA+S2IAYwHkdBe5KZNGLFaiSfz6to1rrG+SHjxrz1XX06quWJVQS12cL+Wv0YI/ c8ufVYHbjZY56kR63OF5f03x2epSOz1S4ujG3irQsZ8rlFr8c+vL0LxUN9vCKlIJRyCt z609C7ZjE7cKwxCNQVRXSJDdPlOow59TbSbVFmGDx4BwHqRei+CHUeq7Qiujex/e+Drr vV3+IwN4EycnCNnPKRiJUUDK4fcp4jqw3RI4XkC6MlUL6cr1Nt/4qmmbDRx4iGtKLqxm rt2JKN7dGmbdVNZjWMQnUgL/8X/JOpAGtE3D++FHGo7rTQc4VYBJyrzQp9yDcA+eGBeD oF0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=Atdlfc6T3QlBgZijwjJ8IuXuf7XGm4UNEDgxUIleNyI=; b=hjCmm/UGz0xInt1b2QGvO+Eo4VwlNypj/0XM6AhWP9CnIW0SQEg2RuUiAqUQjephE4 mHIKK+cf2MYlDaeCqCaWoYzxRw019kZ58a3/YvDlemXXAHFZ27iY8wpa7MoJaeiqikMF tpDaFIwtmGVnkTKvJYlZjkyf6eb0CDCbpZfBO6QRE/1oAE6/C6JLntMW0xiMmcMQG3YO pwb/nBHIaTaKjSTogAAGS3T2Js31/VjHmFXwnmKKF7ozuz7spVWu08WHPyL3oQRszniv LfU9sh4d2whb6gO/9zBeKkm+Fan9yf7z2ASWt6DqpmK0GQtzmlAQ5HOEvDL16j5lci8y sr3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=imG29VCU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s36si8868135pld.502.2017.10.10.03.17.15; Tue, 10 Oct 2017 03:17:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=imG29VCU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755967AbdJJKRO (ORCPT + 26 others); Tue, 10 Oct 2017 06:17:14 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:32281 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754416AbdJJKRK (ORCPT ); Tue, 10 Oct 2017 06:17:10 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9AAGPCV011495; Tue, 10 Oct 2017 05:16:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507630585; bh=upBTM2RVAPnVNMsbc14f8HIV+fpYjZ7Y3XBMS6bkb2o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=imG29VCUevKAruLPOWLwVz+1BfMZU/RmjykTfH05es4F0mqlAaj1lWBalbZ/N0fst 2gvLUfTcB0BTYpjjtWXTR8R/wUCxiAyjbzFe9qYUgSEZgX3RkfsVj0qOdo2vnBRwbf efu+gJ0r0Wou+SiqsPrmsqCn5pu69e/iG+isv8hg= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAGKVt006513; Tue, 10 Oct 2017 05:16:20 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 10 Oct 2017 05:16:20 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 10 Oct 2017 05:16:20 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAG8uk025359; Tue, 10 Oct 2017 05:16:17 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Mark Rutland CC: Kishon Vijay Abraham I , , , , , Subject: [PATCH 3/4] PCI: dwc: dra7xx: Add support for SoC specific compatible strings Date: Tue, 10 Oct 2017 15:46:05 +0530 Message-ID: <20171010101606.15951-4-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171010101606.15951-1-kishon@ti.com> References: <20171010101606.15951-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org dra74x/dra76x and dra72x has separate compatible strings. Add support for these compatible strings in pci-dra7xx driver. This is a preparatory patch for adding 2-lane mode support and dra74/dra72 should add it's own driver data for 2-lane mode configuration. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/pci/dwc/pci-dra7xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.11.0 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 362607f727ee..78a87a8f1362 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -542,6 +542,22 @@ static const struct of_device_id of_dra7xx_pcie_match[] = { .compatible = "ti,dra7-pcie-ep", .data = &dra7xx_pcie_ep_of_data, }, + { + .compatible = "ti,dra746-pcie-rc", + .data = &dra7xx_pcie_rc_of_data, + }, + { + .compatible = "ti,dra746-pcie-ep", + .data = &dra7xx_pcie_ep_of_data, + }, + { + .compatible = "ti,dra726-pcie-rc", + .data = &dra7xx_pcie_rc_of_data, + }, + { + .compatible = "ti,dra726-pcie-ep", + .data = &dra7xx_pcie_ep_of_data, + }, {}, }; From patchwork Tue Oct 10 10:16:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 115383 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3572697qgn; Tue, 10 Oct 2017 03:16:33 -0700 (PDT) X-Google-Smtp-Source: AOwi7QC94T5u4a9Du7zhhmslqsjnTQTd67kB/n30wd64FZYfmQDk5SVGH/18Mepti4c/drMBnLM7 X-Received: by 10.84.248.135 with SMTP id q7mr6472977pll.79.1507630593685; Tue, 10 Oct 2017 03:16:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507630593; cv=none; d=google.com; s=arc-20160816; b=vIHO0e4W9pQeSw001NmymBNaxzpZDEX32VwT+yYQJ4zEy5fIkHIUjJxRUU7lmmg+z4 OecJvGWlWqMOy+jKm5UAguleOoK4pOty88wcH/arRcudX/eYoDmhUo7fr/JIKOTWNpgC 7YbfeiQVHDM70/sSYeBybKHwPh95N6cuVAn+cJ304dRu2Gn/gKbCFG5nUP+xVYdtq4E1 O8chzeoBhm8mIIcKCvcM1X7nCeEszJDHzw7n6WEsK2ns5du87V1N23APlob0LcTvnbWZ s1akVyQo3s7GdemS3W73pJJcoz6/ZLn/R2EIoH9KigKJ5JPXUH94nuIkju6GycUXvyix 44xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=2R+ZvrGn15e7rQAOBiNn9VK6j5dDyT8UvezjgdtwUpc=; b=lSlh/A5/8URfx7UkOzN74JkkDO0gngCnQU44XtAg8ruOG7e1xDObgs+XSNmnaMT1MY FycdvzXnpz08+bRjsYqc9C8RjBHJqeqhDzQ0aH9S5OE6y0bBiFjLxaIqWDVCzfTrCro3 TWqix2/dNWn90v3D/lHr3L7QAbLRbhAlys52X0nZcSVBTs0Htn/SOKFHmNJAbtkNKKj/ 73tWl1LXG3oyMsIhudSc3ClHBirkb5E6tmUiYFvHdcUXZmDx1tuoCwRRv+4V67H+41jj JKUmxoQ9x0cq44w6slk9g2ulhNADU7ofLmAltNDRTMcn/lqzDe+9nyUFbokeBcLEXBA9 MpRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=L7HECNoA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d19si8134113pgn.805.2017.10.10.03.16.33; Tue, 10 Oct 2017 03:16:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=L7HECNoA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756065AbdJJKQc (ORCPT + 26 others); Tue, 10 Oct 2017 06:16:32 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:36070 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751398AbdJJKQ3 (ORCPT ); Tue, 10 Oct 2017 06:16:29 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9AAGN9i021037; Tue, 10 Oct 2017 05:16:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507630583; bh=xl0yCLpAyGS/2QK2anUNdHehhD01vqDdG4Sb9/Nqlpk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L7HECNoAi6xLIah3u8IgoHerPMIBsMpznsWDyF3rFhq2PKZCHGCJsbnnayxTD/vii DT8bZ2w7i7pxym0muhc4JQQGP5OUOb0sz+AVy6gvVuHVUmIvhLpUoy/hsmHWIapD+s FhjKPtaT9Z2i+zuEfu5n4Glm8TnwBd1dOYATtA2I= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAGNPr006552; Tue, 10 Oct 2017 05:16:23 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 10 Oct 2017 05:16:23 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 10 Oct 2017 05:16:23 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAG8ul025359; Tue, 10 Oct 2017 05:16:20 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Mark Rutland CC: Kishon Vijay Abraham I , , , , , Subject: [PATCH 4/4] PCI: dwc: pci-dra7xx: Enable x2 mode support Date: Tue, 10 Oct 2017 15:46:06 +0530 Message-ID: <20171010101606.15951-5-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171010101606.15951-1-kishon@ti.com> References: <20171010101606.15951-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Perform syscon configurations to get x2 mode to working in dra74x (and dra76x). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/pci/dwc/pci-dra7xx.c | 68 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 78a87a8f1362..a43c904310f3 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -83,6 +84,9 @@ #define MSI_REQ_GRANT BIT(0) #define MSI_VECTOR_SHIFT 7 +#define PCIE_1LANE_2LANE_SELECTION BIT(13) +#define PCIE_B1C0_MODE_SEL BIT(2) + struct dra7xx_pcie { struct dw_pcie *pci; void __iomem *base; /* DT ti_conf */ @@ -95,6 +99,10 @@ struct dra7xx_pcie { struct dra7xx_pcie_of_data { enum dw_pcie_device_mode mode; + u32 b1co_mode_sel_mask; +}; + +struct dra7xx_pcie_data { }; #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) @@ -533,6 +541,16 @@ static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = { .mode = DW_PCIE_EP_TYPE, }; +static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = { + .b1co_mode_sel_mask = BIT(2), + .mode = DW_PCIE_RC_TYPE, +}; + +static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = { + .b1co_mode_sel_mask = BIT(2), + .mode = DW_PCIE_EP_TYPE, +}; + static const struct of_device_id of_dra7xx_pcie_match[] = { { .compatible = "ti,dra7-pcie", @@ -544,11 +562,11 @@ static const struct of_device_id of_dra7xx_pcie_match[] = { }, { .compatible = "ti,dra746-pcie-rc", - .data = &dra7xx_pcie_rc_of_data, + .data = &dra746_pcie_rc_of_data, }, { .compatible = "ti,dra746-pcie-ep", - .data = &dra7xx_pcie_ep_of_data, + .data = &dra746_pcie_ep_of_data, }, { .compatible = "ti,dra726-pcie-rc", @@ -603,6 +621,44 @@ static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev) return ret; } +static int dra7xx_pcie_configure_two_lane(struct device *dev, + u32 b1co_mode_sel_mask) +{ + struct device_node *np = dev->of_node; + struct regmap *pcie_syscon; + unsigned int pcie_reg; + + pcie_syscon = syscon_regmap_lookup_by_phandle(np, "syscon-lane-conf"); + if (IS_ERR(pcie_syscon)) { + dev_err(dev, "unable to get syscon-lane-conf\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "syscon-lane-conf", 1, &pcie_reg)) { + dev_err(dev, "couldn't get lane configuration reg offset\n"); + return -EINVAL; + } + + regmap_update_bits(pcie_syscon, pcie_reg, PCIE_1LANE_2LANE_SELECTION, + PCIE_1LANE_2LANE_SELECTION); + + pcie_syscon = syscon_regmap_lookup_by_phandle(np, "syscon-lane-sel"); + if (IS_ERR(pcie_syscon)) { + dev_err(dev, "unable to get syscon-lane-sel\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "syscon-lane-sel", 1, &pcie_reg)) { + dev_err(dev, "couldn't get lane selection reg offset\n"); + return -EINVAL; + } + + regmap_update_bits(pcie_syscon, pcie_reg, b1co_mode_sel_mask, + PCIE_B1C0_MODE_SEL); + + return 0; +} + static int __init dra7xx_pcie_probe(struct platform_device *pdev) { u32 reg; @@ -624,6 +680,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) const struct of_device_id *match; const struct dra7xx_pcie_of_data *data; enum dw_pcie_device_mode mode; + u32 b1co_mode_sel_mask; match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev); if (!match) @@ -631,6 +688,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) data = (struct dra7xx_pcie_of_data *)match->data; mode = (enum dw_pcie_device_mode)data->mode; + b1co_mode_sel_mask = data->b1co_mode_sel_mask; dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); if (!dra7xx) @@ -689,6 +747,12 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) dra7xx->pci = pci; dra7xx->phy_count = phy_count; + if (phy_count == 2) { + ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask); + if (ret < 0) + goto err_link; + } + ret = dra7xx_pcie_enable_phy(dra7xx); if (ret) { dev_err(dev, "failed to enable phy\n");