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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id u10sm425301lfo.39.2020.08.21.07.44.21 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Aug 2020 07:44:21 -0700 (PDT) From: Grzegorz Jaszczyk To: ssantosh@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, santosh.shilimkar@oracle.com, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, tony@atomide.com, Roger Quadros Subject: [PATCH v2 1/7] dt-bindings: soc: ti: Add TI PRUSS bindings Date: Fri, 21 Aug 2020 16:42:38 +0200 Message-Id: <1598020964-29877-2-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598020964-29877-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1598020964-29877-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org This patch adds the bindings for the Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) present on various TI SoCs. The IP is present on multiple TI SoC architecture families including the OMAP architecture SoCs such as AM33xx, AM437x and AM57xx; and on a Keystone 2 architecture based 66AK2G SoC. It is also present on the Davinci based OMAPL138 SoCs and K3 architecture based AM65x and J721E SoCs as well. The IP has a number of sub-modules some of which are represented as their own devices. This binding covers only the top-level sub-system devices, and some sub-modules like MDIO, MII_RT (Ethernet MII_RT module with MII ports) and IEP (Industrial Ethernet Peripheral). The remaining sub-modules bindings shall be defined in the respective driver subsystem bindings folders. Couple of full examples have also been added demonstrating the devices on AM335x and AM437x SoCs. Signed-off-by: Suman Anna Signed-off-by: Roger Quadros Signed-off-by: Grzegorz Jaszczyk --- v1-v2 (requested by Rob): - Add unit address pattern for all sub-nodes. - Add "additionalProperties: false" to all sub-nodes and entire description. This allow to catch and fix some issues like missing "#address-cells" property description. - Drop ranges description. - Fix compatible name in example binding for AM43xx. - Drop the *.yaml references from description as they are not merged yet and therefore they can't be converted to $ref. - Drop reviewed-by tag due to introduced changes. --- .../devicetree/bindings/soc/ti/ti,pruss.yaml | 320 +++++++++++++++++++++ 1 file changed, 320 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml -- 2.7.4 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml new file mode 100644 index 0000000..a13e4df --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -0,0 +1,320 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: |+ + TI Programmable Real-Time Unit and Industrial Communication Subsystem + +maintainers: + - Suman Anna + +description: |+ + + The Programmable Real-Time Unit and Industrial Communication Subsystem + (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x, + Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC + cores (Programmable Real-Time Units, or PRUs), shared RAM, data and + instruction RAMs, some internal peripheral modules to facilitate industrial + communication, and an interrupt controller. + + The programmable nature of the PRUs provide flexibility to implement custom + peripheral interfaces, fast real-time responses, or specialized data handling. + The common peripheral modules include the following, + - an Ethernet MII_RT module with two MII ports + - an MDIO port to control external Ethernet PHYs + - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial + Ethernet functions + - an Enhanced Capture Module (eCAP) + - an Industrial Ethernet Timer with 7/9 capture and 16 compare events + - a 16550-compatible UART to support PROFIBUS + - Enhanced GPIO with async capture and serial support + + A PRU-ICSS subsystem can have up to three shared data memories. A PRU core + acts on a primary Data RAM (there are usually 2 Data RAMs) at its address + 0x0, but also has access to a secondary Data RAM (primary to the other PRU + core) at its address 0x2000. A shared Data RAM, if present, can be accessed + by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are + common to both the PRU cores. Each PRU core also has a private instruction + RAM, and specific register spaces for Control and Debug functionalities. + + Various sub-modules within a PRU-ICSS subsystem are represented as individual + nodes and are defined using a parent-child hierarchy depending on their + integration within the IP and the SoC. These nodes are described in the + following sections. + + + PRU-ICSS Node + ============== + Each PRU-ICSS instance is represented as its own node with the individual PRU + processor cores, the memories node, an INTC node and an MDIO node represented + as child nodes within this PRUSS node. This node shall be a child of the + corresponding interconnect bus nodes or target-module nodes. + + See ../../mfd/syscon.yaml for generic SysCon binding details. + + +properties: + $nodename: + pattern: "^(pruss|icssg)@[0-9a-f]+$" + + compatible: + enum: + - ti,am3356-pruss # for AM335x SoC family + - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0 + - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1 + - ti,am5728-pruss # for AM57xx SoC family + - ti,k2g-pruss # for 66AK2G SoC family + - ti,am654-icssg # for K3 AM65x SoC family + - ti,j721e-icssg # for K3 J721E SoC family + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + maxItems: 1 + + power-domains: + description: | + This property is as per sci-pm-domain.txt. + +patternProperties: + + memories@[a-f0-9]+$: + description: | + The various Data RAMs within a single PRU-ICSS unit are represented as a + single node with the name 'memories'. + + type: object + + properties: + reg: + minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM. + maxItems: 3 + items: + - description: Address and size of the Data RAM0. + - description: Address and size of the Data RAM1. + - description: | + Address and size of the Shared Data RAM. Note that on AM437x one + of two PRUSS units don't contain Shared RAM, while the second one + has it. + + reg-names: + minItems: 2 + maxItems: 3 + items: + - const: dram0 + - const: dram1 + - const: shrdram2 + + required: + - reg + - reg-names + + additionalProperties: false + + cfg@[a-f0-9]+$: + description: | + PRU-ICSS configuration space. CFG sub-module represented as a SysCon. + + type: object + + properties: + compatible: + items: + - const: ti,pruss-cfg + - const: syscon + + reg: + maxItems: 1 + + additionalProperties: false + + iep@[a-f0-9]+$: + description: | + Industrial Ethernet Peripheral to manage/generate Industrial Ethernet + functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x, + AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x & J721E SoCs ). IEP + is used for creating PTP clocks and generating PPS signals. + + type: object + + mii-rt@[a-f0-9]+$: + description: | + Real-Time Ethernet to support multiple industrial communication protocols. + MII-RT sub-module represented as a SysCon. + + type: object + + properties: + compatible: + items: + - const: ti,pruss-mii + - const: syscon + + reg: + maxItems: 1 + + additionalProperties: false + + mii-g-rt@[a-f0-9]+$: + description: | + The Real-time Media Independent Interface to support multiple industrial + communication protocols (G stands for Gigabit). MII-G-RT sub-module + represented as a SysCon. + + type: object + + properties: + compatible: + items: + - const: ti,pruss-mii-g + - const: syscon + + reg: + maxItems: 1 + + additionalProperties: false + + interrupt-controller@[a-f0-9]+$: + description: | + PRUSS INTC Node. Each PRUSS has a single interrupt controller instance + that is common to all the PRU cores. This should be represented as an + interrupt-controller node. + + type: object + + mdio@[a-f0-9]+$: + description: | + MDIO Node. Each PRUSS has an MDIO module that can be used to control + external PHYs. The MDIO module used within the PRU-ICSS is an instance of + the MDIO Controller used in TI Davinci SoCs. + + allOf: + - $ref: /schemas/net/ti,davinci-mdio.yaml# + + type: object + + "^(pru|rtu|txpru)@[0-9a-f]+$": + description: | + PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc + device through a PRU child node each. Each node can optionally be rendered + inactive by using the standard DT string property, "status". The ICSSG IP + present on K3 SoCs have additional auxiliary PRU cores with slightly + different IP integration. + + type: object + +required: + - compatible + - reg + - ranges + +additionalProperties: false + +# Due to inability of correctly verifying sub-nodes with an @address through +# the "required" list, the required sub-nodes below are commented out for now. + +#required: +# - memories +# - interrupt-controller +# - pru + +if: + properties: + compatible: + contains: + enum: + - ti,k2g-pruss + - ti,am654-icssg + - ti,j721e-icssg +then: + required: + - power-domains + +examples: + - | + + /* Example 1 AM33xx PRU-ICSS */ + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x3000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pruss_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + }; + + pruss_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + - | + + /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */ + #include + pruss1: pruss@0 { + compatible = "ti,am4376-pruss1"; + reg = <0x0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss1_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x8000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pruss1_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + }; + + pruss1_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + +... 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id u10sm425301lfo.39.2020.08.21.07.44.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Aug 2020 07:44:27 -0700 (PDT) From: Grzegorz Jaszczyk To: ssantosh@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, santosh.shilimkar@oracle.com, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, tony@atomide.com Subject: [PATCH v2 4/7] soc: ti: pruss: Add support for PRU-ICSS subsystems on AM57xx SoCs Date: Fri, 21 Aug 2020 16:42:41 +0200 Message-Id: <1598020964-29877-5-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598020964-29877-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1598020964-29877-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Suman Anna The AM57xx family of SoCs supports two PRU-ICSS instances, each of which has two PRU processor cores. The two PRU-ICSS instances are identical to each other, and are very similar to the PRU-ICSS1 of AM33xx/AM43xx except for a few minor differences like the RAM sizes and the number of interrupts coming into the MPU INTC. They do not have a programmable module reset line unlike those present on AM33xx/AM43xx SoCs. The modules are reset just like any other IP with the SoC's global cold/warm resets. Each PRU-ICSS's INTC is also preceded by a Crossbar that enables multiple external events to be routed to a specific number of input interrupt events. Any interrupt event directed towards PRUSS needs this crossbar to be setup properly on the firmware side. The existing PRUSS platform driver has been enhanced to support these AM57xx PRU-ICSS instances through new AM57xx specific compatible for properly probing and booting all the different PRU cores in each PRU-ICSS processor subsystem. A build dependency with SOC_DRA7XX is also added to enable the driver to be built in AM57xx-only configuration (there is no separate Kconfig option for AM57xx vs DRA7xx). Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v1->v2: - No changes. --- drivers/soc/ti/Kconfig | 2 +- drivers/soc/ti/pruss.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 40d6a22..99dbc14 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -103,7 +103,7 @@ config TI_K3_SOCINFO config TI_PRUSS tristate "TI PRU-ICSS Subsystem Platform drivers" - depends on SOC_AM33XX || SOC_AM43XX + depends on SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX select MFD_SYSCON help TI PRU-ICSS Subsystem platform specific support. diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 04938ba..5df4caa 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -161,6 +161,7 @@ static const struct of_device_id pruss_of_match[] = { { .compatible = "ti,am3356-pruss" }, { .compatible = "ti,am4376-pruss0", .data = &am437x_pruss0_data, }, { .compatible = "ti,am4376-pruss1", .data = &am437x_pruss1_data, }, + { .compatible = "ti,am5728-pruss" }, {}, }; MODULE_DEVICE_TABLE(of, pruss_of_match); From patchwork Fri Aug 21 14:42:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 248129 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp413716ils; Fri, 21 Aug 2020 07:45:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzI/3q2KIUv01iV0gLiwjGFSV9VgA90dWxx5Zk4CFLp76LlNC2qJXhvejL/evoTNRJoIWkS X-Received: by 2002:a17:906:3890:: with SMTP id q16mr3128213ejd.107.1598021132577; Fri, 21 Aug 2020 07:45:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598021132; cv=none; d=google.com; s=arc-20160816; b=Qr92ORgbJAf/i5Yn611zbttpZxPDFiEGKH+iql5TbuaJf2ILfwkHOtSbvc4rPImT+h 5Fm7jTA8/1BiuE0Ma+8o/DiGNMHPjdnvcgSMIcLu1Z4I2ptjiV+lE7cNDTmMn2m/X13A cOheA1tEaSFCMVDCOeJoGOAaeclEOlrocDdhta7wi9Tl/EFt2+kirEz1nZEEOoEZr6yc L5gD5GJwkA/dPXU+HC/cejZl5+DS8CKGLwYMN7OWqXhd4/oX/5GIdyP+5biZve57NjLv tRATIUK6z0pllElaVn49WWsY2lAZyBxSn7aVfbr2NdFyI3luWu/ova+wYCfU9W0AZD+W 9JtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Pnk1PBdCwskgZo11wlcqoxMsr/2QaWdSpSmHykFS18k=; b=Uf9Gw1Hp3CyO+0GjguFAXp7BLWCwrqudsB3Fw3ai9Tpaa20Vng0vfhZhejtUqgk/cq Jxia55Zplnbot9u7C3kQInCMrFGmAPV83gcjGjie945VU6jSerpEo3zdmxpMNEWmFR2Y o8oIQLVp0nmvXZgWOV2bQCylSQbQ4MCF4BDnI0tmcZ0UL3qCFjsPyKZZyAxBbTiSEcXO ognGYqHS1kZMGiNV1qPk2MvN+JPkTkWrmeLALdOt9FSrY/tju9sEbqsgABnl+XoLgYwk AlayAnCF4QNXq05MgjnZtvDguKCfeB5iSPhL5YELGMwxBinH5Z7sR7/mUi70hj3XBPB3 cOIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oxt7DyZL; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id u10sm425301lfo.39.2020.08.21.07.44.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Aug 2020 07:44:30 -0700 (PDT) From: Grzegorz Jaszczyk To: ssantosh@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, santosh.shilimkar@oracle.com, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, tony@atomide.com, "Andrew F . Davis" Subject: [PATCH v2 5/7] soc: ti: pruss: Add support for PRU-ICSS subsystems on 66AK2G SoC Date: Fri, 21 Aug 2020 16:42:42 +0200 Message-Id: <1598020964-29877-6-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598020964-29877-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1598020964-29877-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Suman Anna The 66AK2G SoC supports two PRU-ICSS instances, named PRUSS0 and PRUSS1, each of which has two PRU processor cores. The two PRU-ICSS instances are identical to each other with few minor SoC integration differences, and are very similar to the PRU-ICSS1 of AM57xx/AM43xx. The Shared Data RAM size is larger and the number of interrupts coming into MPU INTC is like the instances on AM437x. There are also few other differences attributing to integration in Keystone architecture (like no SYSCFG register or PRCM handshake protocols). Other IP level differences include different constant table, differences in system event interrupt input sources etc. They also do not have a programmable module reset line like those present on AM33xx/AM43xx SoCs. The modules are reset just like any other IP with the SoC's global cold/warm resets. The existing PRUSS platform driver has been enhanced to support these 66AK2G PRU-ICSS instances through new 66AK2G specific compatible for properly probing and booting all the different PRU cores in each PRU-ICSS processor subsystem. A build dependency with ARCH_KEYSTONE is added to enable the driver to be built in K2G-only configuration. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v1->v2: - No changes. --- drivers/soc/ti/Kconfig | 2 +- drivers/soc/ti/pruss.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 99dbc14..c290343 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -103,7 +103,7 @@ config TI_K3_SOCINFO config TI_PRUSS tristate "TI PRU-ICSS Subsystem Platform drivers" - depends on SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX + depends on SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE select MFD_SYSCON help TI PRU-ICSS Subsystem platform specific support. diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 5df4caa..d5f128e 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -162,6 +162,7 @@ static const struct of_device_id pruss_of_match[] = { { .compatible = "ti,am4376-pruss0", .data = &am437x_pruss0_data, }, { .compatible = "ti,am4376-pruss1", .data = &am437x_pruss1_data, }, { .compatible = "ti,am5728-pruss" }, + { .compatible = "ti,k2g-pruss" }, {}, }; MODULE_DEVICE_TABLE(of, pruss_of_match); From patchwork Fri Aug 21 14:42:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 256602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DA5EC433E5 for ; Fri, 21 Aug 2020 14:45:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 35F042086A for ; Fri, 21 Aug 2020 14:45:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GmKcGM6U" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728023AbgHUOpW (ORCPT ); Fri, 21 Aug 2020 10:45:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727976AbgHUOoi (ORCPT ); Fri, 21 Aug 2020 10:44:38 -0400 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B55F8C061574 for ; Fri, 21 Aug 2020 07:44:37 -0700 (PDT) Received: by mail-lf1-x142.google.com with SMTP id x64so93361lff.0 for ; Fri, 21 Aug 2020 07:44:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dCxd2Q4l5lkrNLliGFJQWYHxizvRKPbrS09MX/RoHLM=; b=GmKcGM6UHhTOSrzyGoon8fimsUsJsoCmfRi2IX7drBYlygMYxMH+UN27VCNCU1t3AG C6uS7uOwqapSy69YRq29pHHahyG3Z+49HchV+3KC25FAyTZasPEnxRLa1PdHVU0WJ0Gq mm25ZZImCfybEp8lRAcrSSJ5lEoxK9ctEzOKnJirmpymflqtczwRXdrIlNPawPiSb30n OGdx7u9DWqzbahDTGzZdXsXrvGScFStGCRT/0+COD3hX8YlG3C3msC8Us3RoQYrROPCY Ked5yYkGMsOAXVN/IFfl8JrXSg5XwrYlEXFQV6Cxcg2VnqycEwfx5+61IBjaOG1Fyhvm Z0QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dCxd2Q4l5lkrNLliGFJQWYHxizvRKPbrS09MX/RoHLM=; b=ba+AzIOzNalh5sPjEADr8AAvgEQt4sckEqGV3LrPnnAEump1QKQcjHTUOBhX/VqUij J6Jgbt1DUk41A5NOCmrH0rzpT4Gx9jTyiqGtfYrd1BJRHCSQic8R30y6Ln8sWEo5vNwM 51AIa9bc0i+OmiwVe+QBqDToExIQDRIAfVBOCG1XLqjQ0o0gI2NLLpevHpElq1V+5KVS X9JQ3te2LLpyYKgjsVJbu5TFFRHKy+08Ij0dogPJYLZBdVaEPxcTw5stpA8cS4vpNN8d nNmD42tSHKMJL3wnOjRh5QThohCOvgm2u6WP6n9QKZfhqhcorhSmo7SGNWMNpa154BFJ MCpQ== X-Gm-Message-State: AOAM533fCHgkiSAMcDlEd5/qC92egMtybqrjsPJTGh9OptMoCCahOjEM vLU8lbwr7qVYz3sdJe4HRPQURA== X-Google-Smtp-Source: ABdhPJy+O9TCor1YYjDT1vPpSOc3rLR+SybCootz5q6qINXbs623zAq/NPoBXcSDtFn6O6eD3oRHSQ== X-Received: by 2002:ac2:4881:: with SMTP id x1mr1621731lfc.162.1598021075745; Fri, 21 Aug 2020 07:44:35 -0700 (PDT) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id u10sm425301lfo.39.2020.08.21.07.44.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Aug 2020 07:44:35 -0700 (PDT) From: Grzegorz Jaszczyk To: ssantosh@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, santosh.shilimkar@oracle.com, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, tony@atomide.com Subject: [PATCH v2 7/7] soc: ti: pruss: Enable support for ICSSG subsystems on K3 J721E SoCs Date: Fri, 21 Aug 2020 16:42:44 +0200 Message-Id: <1598020964-29877-8-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598020964-29877-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1598020964-29877-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Suman Anna The K3 J721E family of SoCs have a revised version of the PRU-ICSS (ICSSG) processor subsystem present on K3 AM65x SoCs. These SoCs contain typically two ICSSG instances named ICSSG0 and ICSSG1. The two ICSSGs are identical to each other for the most part with minor SoC integration differences and capabilities. The ICSSG1 supports slightly enhanced features like SGMII mode Ethernet, while the ICSSG0 instance is limited to MII mode only. There is no change in the Interrupt Controller w.r.t AM65x. All other integration aspects are very similar to the ICSSGs on AM65x SoCs. The existing pruss platform driver has been updated to support these new ICSSG instances through new J721E specific compatibles. Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v1->v2: - New patch which was not present in v1. --- drivers/soc/ti/pruss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index ccc9783..37df543 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -164,6 +164,7 @@ static const struct of_device_id pruss_of_match[] = { { .compatible = "ti,am5728-pruss" }, { .compatible = "ti,k2g-pruss" }, { .compatible = "ti,am654-icssg" }, + { .compatible = "ti,j721e-icssg" }, {}, }; MODULE_DEVICE_TABLE(of, pruss_of_match);