From patchwork Fri May 29 06:44:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pragnesh Patel X-Patchwork-Id: 246820 List-Id: U-Boot discussion From: pragnesh.patel at sifive.com (Pragnesh Patel) Date: Fri, 29 May 2020 12:14:51 +0530 Subject: [PATCH 1/2] riscv: sifive: fu540: enable all cache ways from U-Boot proper In-Reply-To: <20200529064452.7735-1-pragnesh.patel@sifive.com> References: <20200529064452.7735-1-pragnesh.patel@sifive.com> Message-ID: <20200529064452.7735-2-pragnesh.patel@sifive.com> Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/cpu/fu540/Makefile | 1 + arch/riscv/cpu/fu540/cache.c | 53 +++++++++++++++++++++++ arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++ arch/riscv/include/asm/arch-fu540/cache.h | 14 ++++++ board/sifive/fu540/fu540.c | 10 ++++- 5 files changed, 81 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/cpu/fu540/cache.c create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 043fb961a5..088205ef57 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -8,4 +8,5 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o +obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c new file mode 100644 index 0000000000..9ee364b509 --- /dev/null +++ b/arch/riscv/cpu/fu540/cache.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 SiFive, Inc + * + * Authors: + * Pragnesh Patel + */ + +#include +#include +#include + +/* Register offsets */ +#define L2_CACHE_CONFIG 0x000 +#define L2_CACHE_ENABLE 0x008 + +#define MASK_NUM_WAYS GENMASK(15, 8) +#define NUM_WAYS_SHIFT 8 + +DECLARE_GLOBAL_DATA_PTR; + +int cache_enable_ways(void) +{ + const void *blob = gd->fdt_blob; + int node = (-FDT_ERR_NOTFOUND); + fdt_addr_t base; + u32 config; + u32 ways; + + volatile u32 *enable; + + node = fdt_node_offset_by_compatible(blob, -1, + "sifive,fu540-c000-ccache"); + + if (node < 0) + return node; + + base = fdtdec_get_addr(blob, node, "reg"); + if (base == FDT_ADDR_T_NONE) + return FDT_ADDR_T_NONE; + + config = readl((volatile u32 *)base + L2_CACHE_CONFIG); + ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; + + enable = (volatile u32 *)(base + L2_CACHE_ENABLE); + + /* memory barrier */ + mb(); + (*enable) = ways - 1; + /* memory barrier */ + mb(); + return 0; +} diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 9bba554f9d..6e07c09f9f 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -87,3 +87,7 @@ assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; assigned-clock-rates = <125000000>; }; + +&l2cache { + status = "okay"; +}; diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h new file mode 100644 index 0000000000..135a17c679 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/cache.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 SiFive, Inc. + * + * Authors: + * Pragnesh Patel + */ + +#ifndef _CACHE_SIFIVE_H +#define _CACHE_SIFIVE_H + +int cache_enable_ways(void); + +#endif /* _CACHE_SIFIVE_H */ diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index fa705dea71..27ff52f903 100644 --- a/board/sifive/fu540/fu540.c +++ b/board/sifive/fu540/fu540.c @@ -15,6 +15,7 @@ #include #include #include +#include /* * This define is a value used for error/unknown serial. @@ -114,7 +115,14 @@ int misc_init_r(void) int board_init(void) { - /* For now nothing to do here. */ + int ret; + + /* enable all cache ways */ + ret = cache_enable_ways(); + if (ret) { + debug("%s: could not enable cache ways\n", __func__); + return ret; + } return 0; } From patchwork Fri May 29 06:44:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pragnesh Patel X-Patchwork-Id: 246821 List-Id: U-Boot discussion From: pragnesh.patel at sifive.com (Pragnesh Patel) Date: Fri, 29 May 2020 12:14:52 +0530 Subject: [PATCH 2/2] riscv: sifive: fu540: Enable SiFive PWM driver In-Reply-To: <20200529064452.7735-1-pragnesh.patel@sifive.com> References: <20200529064452.7735-1-pragnesh.patel@sifive.com> Message-ID: <20200529064452.7735-3-pragnesh.patel@sifive.com> This patch enables SiFive PWM driver for the SiFive Unleashed board. Signed-off-by: Pragnesh Patel --- board/sifive/fu540/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 86193d7668..683668d059 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -65,5 +65,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SMP imply MISC imply SIFIVE_OTP + imply DM_PWM + imply PWM_SIFIVE endif