From patchwork Mon Oct 9 13:26:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115229 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2562043qgn; Mon, 9 Oct 2017 06:30:32 -0700 (PDT) X-Received: by 10.159.229.130 with SMTP id az2mr9363368plb.113.1507555832543; Mon, 09 Oct 2017 06:30:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555832; cv=none; d=google.com; s=arc-20160816; b=Vfou16NAlwR14nY7HtqXmkK/C4FPryG5oJS4jvfIGCFqFnw886dPGvnC4bXNkxKSMe uKBhtplmn3Xy4PcNkUYp1dmH9EU2NlizTD5H+GzRkTAFIWCNpQDAlPh7Fb2sI2/fWDDh CK/RFd2Je1jYynIcLBwhTTbUS/vA+BbvEY9Wgm8aIHIShKwPFxHP/Xd1RU0BZR6Hjvtv 9fw5yZoqKCyRQlOlIOIUr2QnOTxS+AohEzA/0xDEOx7/JAnrgw0uofArPlEH3L3FhkI7 0ZWKi3bDF2Dj7nKaWR+1TgSCfppfrwTaLyUxj2tY8x63jQWjZEiF5C7xLdrDS6tVnFPV Virg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=8k62d4914PQiINiygZjU/XJP/IgpIAVS5tK/heScP0U=; b=b49PCeSU3rhEyNRmFzAXei/ziFa4ufeLjSblfhIJT/FA65p1e8/cYWyeWfWXHj/TWN 2CxJ+uoLEDPJYX5MsiESDSZgczvHn4y/LH6w77aWwa8YobaJO1srhXTcfi/EINGS4uEe CFI6jQX5zkSU6hkDpB8BdU9XbW0PbIxkYFWk28z2RhQQs2fDRaKzkeCb4xRI9iy7pFq9 5HYrORvYJWZIqoJ29ZrJxRkyOa4F4dcXqCm6/ANrz6p2slmS2qnW8u/MRVBffarFYH3K OPi9B3NfGKA2ORiTiDlSkJSfOsAIjSjS7hPwKjBn/5tossI/GDtZZoNR7m8bXe9pDaLm ipUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L0K4gAGy; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:50 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Masahiro Yamada Subject: [PATCH 01/12] nvmem: imx-iim: use stack for nvmem_config instead of malloc'ing it Date: Mon, 9 Oct 2017 15:26:30 +0200 Message-Id: <20171009132641.27169-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Masahiro Yamada nvmem_register() copies all the members of nvmem_config to nvmem_device. So, nvmem_config is one-time use data during probing. There is no point to keep it until the driver detach. Using stack should be no problem because nvmem_config is pretty small. Signed-off-by: Masahiro Yamada Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/imx-iim.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) -- 2.11.0 diff --git a/drivers/nvmem/imx-iim.c b/drivers/nvmem/imx-iim.c index 52ff65e0673f..a5992602709a 100644 --- a/drivers/nvmem/imx-iim.c +++ b/drivers/nvmem/imx-iim.c @@ -34,7 +34,6 @@ struct imx_iim_drvdata { struct iim_priv { void __iomem *base; struct clk *clk; - struct nvmem_config nvmem; }; static int imx_iim_read(void *context, unsigned int offset, @@ -108,7 +107,7 @@ static int imx_iim_probe(struct platform_device *pdev) struct resource *res; struct iim_priv *iim; struct nvmem_device *nvmem; - struct nvmem_config *cfg; + struct nvmem_config cfg = {}; const struct imx_iim_drvdata *drvdata = NULL; iim = devm_kzalloc(dev, sizeof(*iim), GFP_KERNEL); @@ -130,19 +129,17 @@ static int imx_iim_probe(struct platform_device *pdev) if (IS_ERR(iim->clk)) return PTR_ERR(iim->clk); - cfg = &iim->nvmem; - - cfg->name = "imx-iim", - cfg->read_only = true, - cfg->word_size = 1, - cfg->stride = 1, - cfg->owner = THIS_MODULE, - cfg->reg_read = imx_iim_read, - cfg->dev = dev; - cfg->size = drvdata->nregs; - cfg->priv = iim; - - nvmem = nvmem_register(cfg); + cfg.name = "imx-iim", + cfg.read_only = true, + cfg.word_size = 1, + cfg.stride = 1, + cfg.owner = THIS_MODULE, + cfg.reg_read = imx_iim_read, + cfg.dev = dev; + cfg.size = drvdata->nregs; + cfg.priv = iim; + + nvmem = nvmem_register(&cfg); if (IS_ERR(nvmem)) return PTR_ERR(nvmem); From patchwork Mon Oct 9 13:26:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115228 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2562021qgn; Mon, 9 Oct 2017 06:30:31 -0700 (PDT) X-Received: by 10.84.233.70 with SMTP id k6mr2130453plt.134.1507555831299; Mon, 09 Oct 2017 06:30:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555831; cv=none; d=google.com; s=arc-20160816; b=k0B0UHoixIv3q4uOMfJCu7PtlQl1dsHV6THcUN9DfbePQcb1VRONp8j5HTGj92dJun cwOWQK0uR3hPPgbcN5/xocg6mu9E7FWL/7UPjkI/4+6e/6qGJBKDrQEHVydEveyUj5eI TS8LjMwHceijeeewr7iAjvX2amD7Sme7WV3OCOOebvRxK9IQ6AiwQY7Pt2pPwfc9RPxE NwMwnc3898t56g3Qq6XIAL/DgD9a7gpfmHl4xBaHtjAfDR82FfRpR5mq9V13Zzrve6xl UxI+C3SAglcrrpOVOhg6l8cotzFsAPU3RVFBU7KUD/6ACf3r0mgRdVHJVJolwv1ohOpZ caMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=TEky1py+uh8A+8Vus2+2O72KeL6FEWP3YZJc2PcVjMk=; b=gLhAbCu6oR7U5t/YqFbeLmM3tWbF7RQqnEZUWqJFHhXkYpOJmVKJKcrpqxOt80swEQ 5LhHlGEkcgx1XT6EYnIl/ClAjvYxZ4jK/55VBPy0VM7O4Zr3Wi9OQyQEhf9PlE88hH8Z F1i4BYp3fx1dvcvbZ6uIFCiQTVPjsCXnApXJJKi6cz5kvmWhzSSdm20bL+TxDnyeI11k SuUTOj7pv243Ajg/obH/SLEL4JLSEXmc+12Vsd80Ir1nQbcruPa2Itas7ASm4ifc4SrU fAcypvhAdGMCXas/qIotXbz0FhJMb2c1xmzlLdM1hJ7zZ4x1THxe9pkB1IHrdmwRPcrF KZhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JCNvPdL+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:51 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Masahiro Yamada Subject: [PATCH 02/12] nvmem: mtk-efuse: use stack for nvmem_config instead of malloc'ing it Date: Mon, 9 Oct 2017 15:26:31 +0200 Message-Id: <20171009132641.27169-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Masahiro Yamada nvmem_register() copies all the members of nvmem_config to nvmem_device. So, nvmem_config is one-time use data during probing. There is no point to keep it until the driver detach. Using stack should be no problem because nvmem_config is pretty small. Signed-off-by: Masahiro Yamada Acked-by: Sean Wang Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/mtk-efuse.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) -- 2.11.0 diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c index 32fd572e18c5..fa7a0f66b37e 100644 --- a/drivers/nvmem/mtk-efuse.c +++ b/drivers/nvmem/mtk-efuse.c @@ -49,7 +49,7 @@ static int mtk_efuse_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct resource *res; struct nvmem_device *nvmem; - struct nvmem_config *econfig; + struct nvmem_config econfig = {}; void __iomem *base; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -57,19 +57,15 @@ static int mtk_efuse_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - econfig = devm_kzalloc(dev, sizeof(*econfig), GFP_KERNEL); - if (!econfig) - return -ENOMEM; - - econfig->stride = 4; - econfig->word_size = 4; - econfig->reg_read = mtk_reg_read; - econfig->reg_write = mtk_reg_write; - econfig->size = resource_size(res); - econfig->priv = base; - econfig->dev = dev; - econfig->owner = THIS_MODULE; - nvmem = nvmem_register(econfig); + econfig.stride = 4; + econfig.word_size = 4; + econfig.reg_read = mtk_reg_read; + econfig.reg_write = mtk_reg_write; + econfig.size = resource_size(res); + econfig.priv = base; + econfig.dev = dev; + econfig.owner = THIS_MODULE; + nvmem = nvmem_register(&econfig); if (IS_ERR(nvmem)) return PTR_ERR(nvmem); From patchwork Mon Oct 9 13:26:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115230 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2563715qgn; Mon, 9 Oct 2017 06:32:00 -0700 (PDT) X-Received: by 10.99.177.75 with SMTP id g11mr6291548pgp.326.1507555816302; Mon, 09 Oct 2017 06:30:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555816; cv=none; d=google.com; s=arc-20160816; b=T3kplY7uG3nsVda7BDiUL3/3Ap8R3bf4hx3H1rgobWHWkXNWPuoDx3A7P/Kn33OF9U CGNPT3sA4e2O3K44rst9r9vCfnedY9RqDWP/y0WUM1CW217t/HfOoj6JvmloFP8il2vQ f5TDSzTU4VfaKNseUmeuJNL0pQKWemitOXzazjZgI3ZPxuIHda1RzA2b6IjwrwJNbqNy JRKmWg5sR45/QjEyaaQhh4OGDUQXGrorLZj7h6exwI+epQMhEM4vI4ynP1BmYFA6Beml yvOoJ7I/P4QWJYVFImUX+RNISXoIKqC5GIs5oUnk7fbGoq2OKG3A5w3SU2rOXToyqzvT ctPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=l+vi4NNAjVk/ovvtN3R1RIkCmMchBeCMxQSJdmHVLbE=; b=LuuHxFB9XkErCXhbOMxLF7oIyGAecLjCJBxT50ZFCiSloYx3lam6CZIgLzVpzzZMC+ 0Xnw7Wqn+5NEQ/Ys9gX7ayRQWSQ0LRQSBUbnBVjcddxFd/SEd3Hpxiu4Q7G9GqhNH4S+ ggQrSL1PmtZq5yO2jdPlCQw5AvN4mp0WXVxky0Ftj8sTVDH53chs/t+2B/vJXcBJlqkQ R94NY70Fc0TUk8mPvsRpiQJS/vemCoRL8woMTTP4J/F777Zkjsq0h4e6PmkxxYotStMR sroOvFxUWsDWODYb4UKfOMX7qygwgBhstc0dzHvs9hhlXXXda1cjhMcIyYg8zoAI3HG2 7IkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=av+pB3RF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:52 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Masahiro Yamada Subject: [PATCH 03/12] nvmem: mtk-efuse: fix different address space warnings of sparse Date: Mon, 9 Oct 2017 15:26:32 +0200 Message-Id: <20171009132641.27169-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Masahiro Yamada Fix the following sparse warnings: drivers/nvmem/mtk-efuse.c:24:30: warning: incorrect type in initializer (different address spaces) drivers/nvmem/mtk-efuse.c:24:30: expected void [noderef] *base drivers/nvmem/mtk-efuse.c:24:30: got void *context drivers/nvmem/mtk-efuse.c:37:30: warning: incorrect type in initializer (different address spaces) drivers/nvmem/mtk-efuse.c:37:30: expected void [noderef] *base drivers/nvmem/mtk-efuse.c:37:30: got void *context drivers/nvmem/mtk-efuse.c:69:23: warning: incorrect type in assignment (different address spaces) drivers/nvmem/mtk-efuse.c:69:23: expected void *priv drivers/nvmem/mtk-efuse.c:69:23: got void [noderef] *[assigned] base The type of nvmem_config->priv is (void *), so sparse complains about assignment of the base address with (void __iomem *) type. Even if we cast it out, sparse still warns: warning: cast removes address space of expression Of course, we can shut up the sparse by marking __force, but a more correct way is to put the base address into driver private data. Signed-off-by: Masahiro Yamada Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/mtk-efuse.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) -- 2.11.0 diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c index fa7a0f66b37e..c4058b598703 100644 --- a/drivers/nvmem/mtk-efuse.c +++ b/drivers/nvmem/mtk-efuse.c @@ -18,15 +18,19 @@ #include #include +struct mtk_efuse_priv { + void __iomem *base; +}; + static int mtk_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) { - void __iomem *base = context; + struct mtk_efuse_priv *priv = context; u32 *val = _val; int i = 0, words = bytes / 4; while (words--) - *val++ = readl(base + reg + (i++ * 4)); + *val++ = readl(priv->base + reg + (i++ * 4)); return 0; } @@ -34,12 +38,12 @@ static int mtk_reg_read(void *context, static int mtk_reg_write(void *context, unsigned int reg, void *_val, size_t bytes) { - void __iomem *base = context; + struct mtk_efuse_priv *priv = context; u32 *val = _val; int i = 0, words = bytes / 4; while (words--) - writel(*val++, base + reg + (i++ * 4)); + writel(*val++, priv->base + reg + (i++ * 4)); return 0; } @@ -50,19 +54,23 @@ static int mtk_efuse_probe(struct platform_device *pdev) struct resource *res; struct nvmem_device *nvmem; struct nvmem_config econfig = {}; - void __iomem *base; + struct mtk_efuse_priv *priv; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); econfig.stride = 4; econfig.word_size = 4; econfig.reg_read = mtk_reg_read; econfig.reg_write = mtk_reg_write; econfig.size = resource_size(res); - econfig.priv = base; + econfig.priv = priv; econfig.dev = dev; econfig.owner = THIS_MODULE; nvmem = nvmem_register(&econfig); From patchwork Mon Oct 9 13:26:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115227 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2561124qgn; Mon, 9 Oct 2017 06:29:44 -0700 (PDT) X-Received: by 10.84.194.3 with SMTP id g3mr9332423pld.246.1507555784870; Mon, 09 Oct 2017 06:29:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555784; cv=none; d=google.com; s=arc-20160816; b=le9T1dQv+9onR7naFYAd7fuUi2f/J9AiqHsedTI1Lg38v5OOmGolMo1uFy35Eh0pP7 nXa7wy+olZotfGg4l4lFta3b1aMIeRPiMl2ToQ5nZDB+A7D0Hcvkqno3joQTtYPbvglP c8nv8zeWfXCv20v02efjZfnC94UEOcba22nFVK8Q7y3Tmo0QwSSb1CzbKM13PgLzppZv +KKx1qBIa60cD+bMEiq1tQgdO4c48G5Yi7ura8gZvOiTCESDbM2rJJUQEgN8DqD0WXwp OmEr8v+C4/45FCyR5qOgLKEDgU4zvTv6WTOcxUTt4gQsfTi8vj9iQU+LAcYYQqkKRt1c kEsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=BKyfWudeTmrJrYhwZLyr0RG0OC0Ttj7QOFrNHXRlVSQ=; b=ndZd5kflr8Y8PRNOLbdMjtTk0OwRWamocA2a1YyPYpWrMBYJtYdtQVed9+mhuQnqw+ rUesm7aUC1SvwMRppXtZo+Q62vemCJkt7uSykJF6zV02aunBVpFq1mjV8Ei9mbiSxSK/ G5nVhJG0VWtEKlt67Uhp9CmjEBn/k5qhG6VE8S7nCfhgulCm+NYfdUUTeYYPnYYJz+c1 9qa9Qejw3HSSV4Rt3q94EunEGiWci1yvFjyVfeaddOJ6p2dG6wAbAg1XqwRupbiQmRKS q6o+JyoB+0axdPyipUgrO+UvJU9IZXCURlvG98ZavfSkmwTvNF3uKvrrkxN8Ymynf9TP yU+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kzTRRsZK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:53 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Masahiro Yamada Subject: [PATCH 04/12] nvmem: qfprom: fix different address space warnings of sparse Date: Mon, 9 Oct 2017 15:26:33 +0200 Message-Id: <20171009132641.27169-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Masahiro Yamada Fix the following sparse warnings: drivers/nvmem/qfprom.c:23:30: warning: incorrect type in initializer (different address spaces) drivers/nvmem/qfprom.c:23:30: expected void [noderef] *base drivers/nvmem/qfprom.c:23:30: got void *context drivers/nvmem/qfprom.c:36:30: warning: incorrect type in initializer (different address spaces) drivers/nvmem/qfprom.c:36:30: expected void [noderef] *base drivers/nvmem/qfprom.c:36:30: got void *context drivers/nvmem/qfprom.c:76:22: warning: incorrect type in assignment (different address spaces) drivers/nvmem/qfprom.c:76:22: expected void *static [toplevel] [assigned] priv drivers/nvmem/qfprom.c:76:22: got void [noderef] *[assigned] base The type of nvmem_config->priv is (void *), so sparse complains about assignment of the base address with (void __iomem *) type. Even if we cast it out, sparse still warns: warning: cast removes address space of expression Of course, we can shut up the sparse by marking __force, but a more correct way is to put the base address into driver private data. Signed-off-by: Masahiro Yamada Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/qfprom.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) -- 2.11.0 diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index 2bdb6c389328..b96730e99580 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -17,15 +17,19 @@ #include #include +struct qfprom_priv { + void __iomem *base; +}; + static int qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) { - void __iomem *base = context; + struct qfprom_priv *priv = context; u8 *val = _val; int i = 0, words = bytes; while (words--) - *val++ = readb(base + reg + i++); + *val++ = readb(priv->base + reg + i++); return 0; } @@ -33,12 +37,12 @@ static int qfprom_reg_read(void *context, static int qfprom_reg_write(void *context, unsigned int reg, void *_val, size_t bytes) { - void __iomem *base = context; + struct qfprom_priv *priv = context; u8 *val = _val; int i = 0, words = bytes; while (words--) - writeb(*val++, base + reg + i++); + writeb(*val++, priv->base + reg + i++); return 0; } @@ -64,16 +68,20 @@ static int qfprom_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct resource *res; struct nvmem_device *nvmem; - void __iomem *base; + struct qfprom_priv *priv; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); econfig.size = resource_size(res); econfig.dev = dev; - econfig.priv = base; + econfig.priv = priv; nvmem = nvmem_register(&econfig); if (IS_ERR(nvmem)) From patchwork Mon Oct 9 13:26:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115221 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2558565qgn; Mon, 9 Oct 2017 06:27:12 -0700 (PDT) X-Received: by 10.99.111.5 with SMTP id k5mr9291119pgc.364.1507555632710; Mon, 09 Oct 2017 06:27:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555632; cv=none; d=google.com; s=arc-20160816; b=O5KFCLr+OENhp+sOfjlrp9F7op0I9aM1b5neRnS0qr/jp+PQmm8ZJTg/A8WP/yh3vJ rTCzp3lvpBQw5P8XPOdKI4B3ulj79Q400HY6x5KHcosxOsJ1neZurKyXfDvf5wUvJoQt k6RHG/OqLPWZgb3MAwAj/8hiGLMV0IRAiNelXqEYHO6iRqYCdGPa+DAdsFuWdXQ3DBuZ iaLUHJQbIaM+09sgLPVoGD+0PVRKTqKMtdU5c6AHzaJvrWfMfIR1K8sunL1/53R3AS41 Ayy0Obgb8WnHuEjgwCg6dnqr2mXFE5e2JeWd8PefJLqxcf2yZa8UfIO8mgu43iPf2K/u PIMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Nmfd1BiRIL/4yNwiRgSXS41AxrndZZy2m4DfQUu3GMw=; b=mMwJz9KTwR7s7Fxm73D0KcrIXjaYWzUiroTzFL4va5NCquOs3iERTTIN2r4R8FpqTH SqG4jp6SR4ctL5zVJIbfWljtQ4BPg+dddIv0gih60by7qEiAhKpUvMR2y+FaG4otSC8r iFjCDz/c3+D0/wkjIG3IT2DOlGHjZ9CPIvSFMWUsmrqw74XeAYIpp4whH1+7WGbWxcr+ 0VhNNINFusfILtLVSV7TItoQB7vaLNPVL4fgKG1qCWgSp512VqNEQp6IhR2qtzUZTftv 7PjZZI+JGmimcLh3x1/2Yznz7U05PZX9Ws4FM8c5Ke0oT7bqLRcenxaCRyT5KUbJh1GK PTKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jWjqNsgR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:54 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Masahiro Yamada Subject: [PATCH 05/12] nvmem: set nvmem->owner to nvmem->dev->driver->owner if unset Date: Mon, 9 Oct 2017 15:26:34 +0200 Message-Id: <20171009132641.27169-6-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Masahiro Yamada All nvmem drivers are supposed to set the owner field of struct nvmem_config, but this matches nvmem->dev->driver->owner. As far as I see in drivers/nvmem/ directory, all the drivers are the case. So, make nvmem_register() set the nvmem's owner to the associated driver's owner unless nvmem_config sets otherwise. Remove .owner settings in the drivers that are now redundant. Signed-off-by: Masahiro Yamada Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/bcm-ocotp.c | 1 - drivers/nvmem/core.c | 2 ++ drivers/nvmem/imx-iim.c | 1 - drivers/nvmem/imx-ocotp.c | 1 - drivers/nvmem/lpc18xx_eeprom.c | 1 - drivers/nvmem/lpc18xx_otp.c | 1 - drivers/nvmem/meson-efuse.c | 1 - drivers/nvmem/mtk-efuse.c | 1 - drivers/nvmem/mxs-ocotp.c | 1 - drivers/nvmem/qfprom.c | 1 - drivers/nvmem/rockchip-efuse.c | 1 - drivers/nvmem/sunxi_sid.c | 1 - drivers/nvmem/vf610-ocotp.c | 1 - 13 files changed, 2 insertions(+), 12 deletions(-) -- 2.11.0 diff --git a/drivers/nvmem/bcm-ocotp.c b/drivers/nvmem/bcm-ocotp.c index 3c56e3b2bd65..5e9e324427f9 100644 --- a/drivers/nvmem/bcm-ocotp.c +++ b/drivers/nvmem/bcm-ocotp.c @@ -232,7 +232,6 @@ static struct nvmem_config bcm_otpc_nvmem_config = { .read_only = false, .word_size = 4, .stride = 4, - .owner = THIS_MODULE, .reg_read = bcm_otpc_read, .reg_write = bcm_otpc_write, }; diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 0a3464f647a4..e5f5df783898 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -462,6 +462,8 @@ struct nvmem_device *nvmem_register(const struct nvmem_config *config) nvmem->id = rval; nvmem->owner = config->owner; + if (!nvmem->owner && config->dev->driver) + nvmem->owner = config->dev->driver->owner; nvmem->stride = config->stride; nvmem->word_size = config->word_size; nvmem->size = config->size; diff --git a/drivers/nvmem/imx-iim.c b/drivers/nvmem/imx-iim.c index a5992602709a..52cfe91d9762 100644 --- a/drivers/nvmem/imx-iim.c +++ b/drivers/nvmem/imx-iim.c @@ -133,7 +133,6 @@ static int imx_iim_probe(struct platform_device *pdev) cfg.read_only = true, cfg.word_size = 1, cfg.stride = 1, - cfg.owner = THIS_MODULE, cfg.reg_read = imx_iim_read, cfg.dev = dev; cfg.size = drvdata->nregs; diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 193ca8fd350a..e57e2a57aa3f 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -303,7 +303,6 @@ static struct nvmem_config imx_ocotp_nvmem_config = { .read_only = false, .word_size = 4, .stride = 4, - .owner = THIS_MODULE, .reg_read = imx_ocotp_read, .reg_write = imx_ocotp_write, }; diff --git a/drivers/nvmem/lpc18xx_eeprom.c b/drivers/nvmem/lpc18xx_eeprom.c index 6c7e2c424a4e..b1af966206a6 100644 --- a/drivers/nvmem/lpc18xx_eeprom.c +++ b/drivers/nvmem/lpc18xx_eeprom.c @@ -159,7 +159,6 @@ static struct nvmem_config lpc18xx_nvmem_config = { .word_size = 4, .reg_read = lpc18xx_eeprom_read, .reg_write = lpc18xx_eeprom_gather_write, - .owner = THIS_MODULE, }; static int lpc18xx_eeprom_probe(struct platform_device *pdev) diff --git a/drivers/nvmem/lpc18xx_otp.c b/drivers/nvmem/lpc18xx_otp.c index be8d07403ffc..95268db155e9 100644 --- a/drivers/nvmem/lpc18xx_otp.c +++ b/drivers/nvmem/lpc18xx_otp.c @@ -64,7 +64,6 @@ static struct nvmem_config lpc18xx_otp_nvmem_config = { .read_only = true, .word_size = LPC18XX_OTP_WORD_SIZE, .stride = LPC18XX_OTP_WORD_SIZE, - .owner = THIS_MODULE, .reg_read = lpc18xx_otp_read, }; diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c index 70bfc9839bb2..dbedfcea4e05 100644 --- a/drivers/nvmem/meson-efuse.c +++ b/drivers/nvmem/meson-efuse.c @@ -37,7 +37,6 @@ static int meson_efuse_read(void *context, unsigned int offset, static struct nvmem_config econfig = { .name = "meson-efuse", - .owner = THIS_MODULE, .stride = 1, .word_size = 1, .read_only = true, diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c index c4058b598703..9ee3479cfc7b 100644 --- a/drivers/nvmem/mtk-efuse.c +++ b/drivers/nvmem/mtk-efuse.c @@ -72,7 +72,6 @@ static int mtk_efuse_probe(struct platform_device *pdev) econfig.size = resource_size(res); econfig.priv = priv; econfig.dev = dev; - econfig.owner = THIS_MODULE; nvmem = nvmem_register(&econfig); if (IS_ERR(nvmem)) return PTR_ERR(nvmem); diff --git a/drivers/nvmem/mxs-ocotp.c b/drivers/nvmem/mxs-ocotp.c index d26dd03cec80..7018e2ef5714 100644 --- a/drivers/nvmem/mxs-ocotp.c +++ b/drivers/nvmem/mxs-ocotp.c @@ -118,7 +118,6 @@ static struct nvmem_config ocotp_config = { .name = "mxs-ocotp", .stride = 16, .word_size = 4, - .owner = THIS_MODULE, .reg_read = mxs_ocotp_read, }; diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index b96730e99580..cb3b48b47d64 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -56,7 +56,6 @@ static int qfprom_remove(struct platform_device *pdev) static struct nvmem_config econfig = { .name = "qfprom", - .owner = THIS_MODULE, .stride = 1, .word_size = 1, .reg_read = qfprom_reg_read, diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c index 63e3eb55f3ac..e292bbe6bb68 100644 --- a/drivers/nvmem/rockchip-efuse.c +++ b/drivers/nvmem/rockchip-efuse.c @@ -149,7 +149,6 @@ static int rockchip_rk3399_efuse_read(void *context, unsigned int offset, static struct nvmem_config econfig = { .name = "rockchip-efuse", - .owner = THIS_MODULE, .stride = 1, .word_size = 1, .read_only = true, diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c index 0d6648be93b8..1c3b5cf89212 100644 --- a/drivers/nvmem/sunxi_sid.c +++ b/drivers/nvmem/sunxi_sid.c @@ -40,7 +40,6 @@ static struct nvmem_config econfig = { .read_only = true, .stride = 4, .word_size = 1, - .owner = THIS_MODULE, }; struct sunxi_sid_cfg { diff --git a/drivers/nvmem/vf610-ocotp.c b/drivers/nvmem/vf610-ocotp.c index 72e4faabce29..5ae9e002f195 100644 --- a/drivers/nvmem/vf610-ocotp.c +++ b/drivers/nvmem/vf610-ocotp.c @@ -206,7 +206,6 @@ static int vf610_ocotp_read(void *context, unsigned int offset, static struct nvmem_config ocotp_config = { .name = "ocotp", - .owner = THIS_MODULE, .stride = 4, .word_size = 4, .reg_read = vf610_ocotp_read, From patchwork Mon Oct 9 13:26:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115219 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2558408qgn; Mon, 9 Oct 2017 06:27:04 -0700 (PDT) X-Received: by 10.84.133.164 with SMTP id f33mr9006997plf.73.1507555624089; Mon, 09 Oct 2017 06:27:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555624; cv=none; d=google.com; s=arc-20160816; b=Xdfgds+TDl3tlrwqVE0EFBISibVc39LZYjyiGJ64DCEzwGr0NjJNp/6HBSVOSxZMPG RcKDllYADH5dInbAjgKaYIK6O7ay3HMy3sD6/5/CDzqgVp8C55GSG7S8CVHCYoJfTaNa kRWTpaA1Sogk0ZTTkg113vWzNMAgKhpm1vPFiWZ5HO+zgJFVBBZXcuusMoaiMthqp8U3 P+TfmtueeuNP1RTvruYL8rrCzEIW8BVqpR/vW7UBxnfAkMAyPons1GHGTvp0my8HD0ZU zi8Nunn2UZAZNjhNmNsoAppB7P+E0K2EOQ5aIJjqlmLxpVcs95FCDFHvOxkXnXz4tpFY chNA== ARC-Message-Signature: i=1; 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:55 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Icenowy Zheng Subject: [PATCH 06/12] nvmem: sunxi-sid: add support for A64/H5's SID controller Date: Mon, 9 Oct 2017 15:26:35 +0200 Message-Id: <20171009132641.27169-7-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Icenowy Zheng Allwinner A64/H5 SoCs come with a SID controller like the one in H3, but without the silicon bug that makes the initial value at 0x200 wrong, so the value at 0x200 can be directly read. Add support for this kind of SID controller. Signed-off-by: Icenowy Zheng Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt | 1 + drivers/nvmem/sunxi_sid.c | 6 ++++++ 2 files changed, 7 insertions(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt index ef06d061913c..6ea0836939ee 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt @@ -5,6 +5,7 @@ Required properties: "allwinner,sun4i-a10-sid" "allwinner,sun7i-a20-sid" "allwinner,sun8i-h3-sid" + "allwinner,sun50i-a64-sid" - reg: Should contain registers location and length diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c index 1c3b5cf89212..99bd54d85fcb 100644 --- a/drivers/nvmem/sunxi_sid.c +++ b/drivers/nvmem/sunxi_sid.c @@ -198,10 +198,16 @@ static const struct sunxi_sid_cfg sun8i_h3_cfg = { .need_register_readout = true, }; +static const struct sunxi_sid_cfg sun50i_a64_cfg = { + .value_offset = 0x200, + .size = 0x100, +}; + static const struct of_device_id sunxi_sid_of_match[] = { { .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg }, { .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg }, { .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg }, + { .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg }, {/* sentinel */}, }; MODULE_DEVICE_TABLE(of, sunxi_sid_of_match); From patchwork Mon Oct 9 13:26:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115222 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2558938qgn; Mon, 9 Oct 2017 06:27:36 -0700 (PDT) X-Received: by 10.101.81.137 with SMTP id h9mr9415539pgq.347.1507555656042; Mon, 09 Oct 2017 06:27:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555656; cv=none; d=google.com; s=arc-20160816; b=WOxJCgJ+loqvzcH9CjddPJ0l0vVbKBnE5bRAk89COZpCiaI6foZAuNlqaliRwW2Cst kpo87242bgC3yvzsy0eDDe5TlmD78EUOy+DHyIuD9+mNSpbZRpiLAV7gOHwQv6cdgLWA O0ji3L7UVeksU5uq3SWKxA6q1jL3THAZnNlloWNklHomUe3KKCucE2QCPAiXH6a4XryR N6v4HpB/DlD86vfrCtE8+yyUampJxvRAWutHnUTa5SxEJMWt6JFrEk4jCO0OQxbdSwdo kBCrweQfk/zfK5pPPULdmqrFYgNJGq/TAG3ALeWTzTwFtzKXi6VwFyYbKjECdBui96LI XtdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=mszscZRfWiIVoD8JvrN75cDhejbhLMVXLlQLWf1aHbk=; b=IeEytvWbbAF6fgV+zh0L2TsGeX+1eRauNMjinGWq9hrLgsXEDlmjxEzcVZ5Q04iEBo AM65Ck6uPvSeXXzwq+KJr7+6u/aVIwCvGHaQtrPHHHHqPFUZ+8AkAemuTzKHg+qftMZp q1rcWyx70En5GFme9+6WnctyZtMVgjgBYeUijOnO3tYovuAfYXRngI2dOHmrRbn5YOgv IT4p23i8YML1E7+hxrlkNpBVU2NcP7glxqZ2Pzbz6VfRisTz/dRs0u3zaxJ1svi/9lad W+wzS5X6lONot84ow8w94Z5RS1w3ivL/x1o40TT6vKlvk+zmVVzm7dNTNuXbHyOvV9xP +cag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WhUZmj4R; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:56 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Keiji Hayashibara Subject: [PATCH 07/12] dt-bindings: nvmem: add description for UniPhier eFuse Date: Mon, 9 Oct 2017 15:26:36 +0200 Message-Id: <20171009132641.27169-8-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Keiji Hayashibara Add uniphier-efuse dt-bindings documentation. Signed-off-by: Keiji Hayashibara Signed-off-by: Srinivas Kandagatla --- .../devicetree/bindings/nvmem/uniphier-efuse.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt -- 2.11.0 diff --git a/Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt b/Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt new file mode 100644 index 000000000000..1a394e5f71dd --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt @@ -0,0 +1,49 @@ += UniPhier eFuse device tree bindings = + +This UniPhier eFuse must be under soc-glue. + +Required properties: +- compatible: should be "socionext,uniphier-efuse" +- reg: should contain the register location and length + += Data cells = +Are child nodes of efuse, bindings of which as described in +bindings/nvmem/nvmem.txt + +Example: + + soc-glue@5f900000 { + compatible = "socionext,uniphier-ld20-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + usb_mon: usb_mon { + reg = <0x54 0xc>; + }; + }; + }; + += Data consumers = +Are device nodes which consume nvmem data cells. + +Example: + + usb { + ... + nvmem-cells = <&usb_mon>; + nvmem-cell-names = "usb_mon"; + } From patchwork Mon Oct 9 13:26:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115220 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2558473qgn; Mon, 9 Oct 2017 06:27:07 -0700 (PDT) X-Received: by 10.99.62.207 with SMTP id l198mr9051851pga.376.1507555627877; Mon, 09 Oct 2017 06:27:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555627; cv=none; d=google.com; s=arc-20160816; b=ZNh2QKHrkm3UXR0YJw0oxY94ka+3TsVDnMZCBw9sFctKk8xsr4b8pBb1rJOmo6WfkL pBf8SLzHgxl+EUgfrBjKNVXIKImLV47QlWEjpFg1wdbF4hQgo2XF0PRfPZzXL2uPUbSQ g95+ZR3dRCXOKxpEuyifedAhvU7O4SUBqlLRmHDV4640apSMyf42+Q8baTHFVaNn0qMV e1bK3bepZ5b6FQOI0e8nK7WbZEqWbzAObfBZBN5UMXTxzUYdiKvfPkfU1U/EGkDgbqYm WJJEd2XZIMyE5m4yr7FiYBzSImc12+WcndOKE05kO35xtvIDDLU2cS9y8hoJjm0WUsey focA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=rRMKRCIn81sJ0DdGA1k7zavi0t6YyjThSM9IKcydWsY=; b=N/1IypDnp0dueGqzD42EOSNxCHynYkwQOlThOv/nMTr/CYUmHb4dBmcleU7LafKzbL Vyn05zr1h7czSAUHfik8tBX2akQMctpW2Ou8hUcSQKBm/aDzJVRxjFOoZpYEXJDdE/wX irvNAozWo/iHbEHDJecJ2f0Pi8v9HvJwEz/Lzu7z+BQfPDQjNXYNP2kYKTL9up0rT8R1 lIf2mHDcK/Ih+1U6vU1gkhLB6YfxrwELRU71v82bxyQVbxorZ4XbF4CcdC1MxbWHYS8H sgLp+1+CDcEwGPT5pBAakrdtxTTemsoUTck3qxFNdviJerrvua/7pDRsooG74YPytowd +CAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AqRrBhSs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:56 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Keiji Hayashibara Subject: [PATCH 08/12] nvmem: uniphier: add UniPhier eFuse driver Date: Mon, 9 Oct 2017 15:26:37 +0200 Message-Id: <20171009132641.27169-9-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Keiji Hayashibara Add eFuse driver for Socionext UniPhier series SoC. Note that eFuse device is under soc-glue and this register implements as read only. Signed-off-by: Keiji Hayashibara Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 11 +++++ drivers/nvmem/Makefile | 2 + drivers/nvmem/uniphier-efuse.c | 97 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 drivers/nvmem/uniphier-efuse.c -- 2.11.0 diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index ea3044c5d6ee..2755df8f6e9b 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -123,6 +123,17 @@ config NVMEM_SUNXI_SID This driver can also be built as a module. If so, the module will be called nvmem_sunxi_sid. +config UNIPHIER_EFUSE + tristate "UniPhier SoCs eFuse support" + depends on ARCH_UNIPHIER || COMPILE_TEST + depends on HAS_IOMEM + help + This is a simple driver to dump specified values of UniPhier SoC + from eFuse. + + This driver can also be built as a module. If so, the module + will be called nvmem-uniphier-efuse. + config NVMEM_VF610_OCOTP tristate "VF610 SoC OCOTP support" depends on SOC_VF610 || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 4c589184acee..11825353f729 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -26,6 +26,8 @@ obj-$(CONFIG_ROCKCHIP_EFUSE) += nvmem_rockchip_efuse.o nvmem_rockchip_efuse-y := rockchip-efuse.o obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o nvmem_sunxi_sid-y := sunxi_sid.o +obj-$(CONFIG_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o +nvmem-uniphier-efuse-y := uniphier-efuse.o obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o nvmem-vf610-ocotp-y := vf610-ocotp.o obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o diff --git a/drivers/nvmem/uniphier-efuse.c b/drivers/nvmem/uniphier-efuse.c new file mode 100644 index 000000000000..2bb45c42fd6b --- /dev/null +++ b/drivers/nvmem/uniphier-efuse.c @@ -0,0 +1,97 @@ +/* + * UniPhier eFuse driver + * + * Copyright (C) 2017 Socionext Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +struct uniphier_efuse_priv { + void __iomem *base; +}; + +static int uniphier_reg_read(void *context, + unsigned int reg, void *_val, size_t bytes) +{ + struct uniphier_efuse_priv *priv = context; + u32 *val = _val; + int offs; + + for (offs = 0; offs < bytes; offs += sizeof(u32)) + *val++ = readl(priv->base + reg + offs); + + return 0; +} + +static int uniphier_efuse_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct nvmem_device *nvmem; + struct nvmem_config econfig ={}; + struct uniphier_efuse_priv *priv; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + econfig.stride = 4; + econfig.word_size = 4; + econfig.read_only = true; + econfig.reg_read = uniphier_reg_read; + econfig.size = resource_size(res); + econfig.priv = priv; + econfig.dev = dev; + nvmem = nvmem_register(&econfig); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); + + platform_set_drvdata(pdev, nvmem); + + return 0; +} + +static int uniphier_efuse_remove(struct platform_device *pdev) +{ + struct nvmem_device *nvmem = platform_get_drvdata(pdev); + + return nvmem_unregister(nvmem); +} + +static const struct of_device_id uniphier_efuse_of_match[] = { + { .compatible = "socionext,uniphier-efuse",}, + {/* sentinel */}, +}; +MODULE_DEVICE_TABLE(of, uniphier_efuse_of_match); + +static struct platform_driver uniphier_efuse_driver = { + .probe = uniphier_efuse_probe, + .remove = uniphier_efuse_remove, + .driver = { + .name = "uniphier-efuse", + .of_match_table = uniphier_efuse_of_match, + }, +}; +module_platform_driver(uniphier_efuse_driver); + +MODULE_AUTHOR("Keiji Hayashibara "); +MODULE_DESCRIPTION("UniPhier eFuse driver"); +MODULE_LICENSE("GPL v2"); From patchwork Mon Oct 9 13:26:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115225 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2560217qgn; Mon, 9 Oct 2017 06:28:48 -0700 (PDT) X-Received: by 10.98.66.139 with SMTP id h11mr1237479pfd.174.1507555727918; Mon, 09 Oct 2017 06:28:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555727; cv=none; d=google.com; s=arc-20160816; b=gE+FEcJXSkmXrYeRnrSseOG5sVcsPjEUjSOw3KSeN0ZUZEIXH7w0XlueG09xaLA3jl a2JPi9gKHObS+nTZ5ZO21UF1LRopsWAQsIJ+Gyv8ZlEDzwBPoqQ2FRbHboJDa51KzloP DXKu6olOVr5dNspQGZVfOGrefTqG3Bk/O6vURVOub6wfppDqUn/ZhidDKWA4blM4IdvN G5iLkgZekLiDXvBJ4F5DbhLpwMk3Hm60tafoaJfkCJmVE3o3fxS7FUCxLArswlgb9eM0 Ijq3WScFwH/rabKT5QESXYRDEIo5zw2K1xCYCiuDiUyOzeBim12GcWsW1QJbYjyLO1Rj +ldQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=O6S4gSAqYYl1/jBTCSXMxbS+fE5oeT8RG7W9zvCyCeg=; b=P86C4Ycflyhg6z04g78wTEFf7buy9+mQizpBDFy9EHCYMznS0p5FXj0+lqpGyMLYuY +WX0fVEqbomBfgkL57uTe3cGCvUDzTstMy/XIU1g2TD4Ax9nJdf8c5Dg4HowT6vxYBaf zEB7WlWIJsEU/MJ4mtc/2vnqKBc1CGmm0IHc/WfbiYX6kfNFByjT+YXz6wol0SjBjOk1 bx0uw5YjV9qJMC/WM6RAuyXf6KdCatYhw9cL7pfI7OpkyaE5Rk6jb8cgoD1TtWgpgZgg AfjaCfZpj7rcWyeViZ6sIhoUL689pM2ASB5F4WBnRmwyO2+ciCHT8mqXcpF2zZ+3v+0z K4LQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Oy9VJmKa; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:57 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Romain Perier Subject: [PATCH 09/12] nvmem: rockchip: add support for RK3368 Date: Mon, 9 Oct 2017 15:26:38 +0200 Message-Id: <20171009132641.27169-10-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Romain Perier This adds the necessary function for handling support on RK3368 SoCs Signed-off-by: Romain Perier Acked-by: Rob Herring Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt | 1 + drivers/nvmem/rockchip-efuse.c | 4 ++++ 2 files changed, 5 insertions(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt index 1ff02afdc55a..60bec4782806 100644 --- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt @@ -6,6 +6,7 @@ Required properties: - "rockchip,rk3188-efuse" - for RK3188 SoCs. - "rockchip,rk3228-efuse" - for RK3228 SoCs. - "rockchip,rk3288-efuse" - for RK3288 SoCs. + - "rockchip,rk3368-efuse" - for RK3368 SoCs. - "rockchip,rk3399-efuse" - for RK3399 SoCs. - reg: Should contain the registers location and exact eFuse size - clocks: Should be the clock id of eFuse diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c index e292bbe6bb68..123de77ca5d6 100644 --- a/drivers/nvmem/rockchip-efuse.c +++ b/drivers/nvmem/rockchip-efuse.c @@ -177,6 +177,10 @@ static const struct of_device_id rockchip_efuse_match[] = { .data = (void *)&rockchip_rk3288_efuse_read, }, { + .compatible = "rockchip,rk3368-efuse", + .data = (void *)&rockchip_rk3288_efuse_read, + }, + { .compatible = "rockchip,rk3399-efuse", .data = (void *)&rockchip_rk3399_efuse_read, }, From patchwork Mon Oct 9 13:26:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115226 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2560773qgn; Mon, 9 Oct 2017 06:29:22 -0700 (PDT) X-Received: by 10.159.198.11 with SMTP id f11mr9155987plo.290.1507555762511; Mon, 09 Oct 2017 06:29:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555762; cv=none; d=google.com; s=arc-20160816; b=YNFtJBZHhXSQD0EwA7FJJBP+qLiVqRZDaqYur6u5Rbic8dxUQbuOSSpQHufXPYBWc2 kX870WyO7tWMN28rrdCb9/27Pvn4uVKOsOh6/ktXqhrz5L8/6HJbNuQ5ftA172fLvJAS VhGPCB22chHNDvQ+xRW3niqvnrhb6oX8AO4LeqRDUuSq6C/Xyx9IxW7tnOHA5HxqzR2v DQIo01qEIdGbIQvtCNAt0Q5am1Ip90r5jCGME3HY0S6mucw0KF61kzvmajRs9fkfbfAv ripsH6OgiEKG1ptPxMUCayiNFh7eKcuvB/KVi7OAfN9uAhMyUu1aAXwkCEwc1Wd6W7jx FVXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Xx+WV2NGyd6Fuaz4QLiinURpRfFsqEH3KMYQE4j9SRs=; b=d9ksEwx2U6Eh4ramnS3H9GuYGaiD2fqgo5+zT+U6P4y6LSRCN0y//JmoeDgLlkmnOk OzEsdC8kmYPbRN5qeUpPPZlsNtVLUDGew5kvzmEUlYLXsmz4WkqofD7kFv1BHMZNU11x RLGlShqW34Wl5NW1c/nhgKBQxaqDYDB1AkNPQ2tPqJJpbmekbYmBI67ng8Ccg9JkFMCS tY1B7IdfHpAQYi0gaOjhhyNxS9TnRjCXXoyYf8JBVzocsEWm0edACG8Sn06v1/MZenro Gv3nK2NFdI+pyUki2Smn8B69cD8lgufvbtgxqt1OgVNiyGPaTZknWzgBtRbJpFZwVoJn /q5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JdV5Fx8M; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:58 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Martin Blumenstingl Subject: [PATCH 10/12] dt-bindings: nvmem: Describe the Amlogic Meson6/Meson8/Meson8b efuse Date: Mon, 9 Oct 2017 15:26:39 +0200 Message-Id: <20171009132641.27169-11-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Martin Blumenstingl Amlogic Meson6, Meson8 and Meson8b SoCs have an efuse which contains calibration data from the factory (for the internal temperature sensor and some CVBS connector settings). Some manufacturers also store the MAC address or serial number in the efuse. This documents the devicetree bindings for the efuse on these SoCs. Signed-off-by: Martin Blumenstingl Signed-off-by: Srinivas Kandagatla --- .../bindings/nvmem/amlogic-meson-mx-efuse.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt -- 2.11.0 diff --git a/Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt b/Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt new file mode 100644 index 000000000000..a3c63954a1a4 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt @@ -0,0 +1,22 @@ +Amlogic Meson6/Meson8/Meson8b efuse + +Required Properties: +- compatible: depending on the SoC this should be one of: + - "amlogic,meson6-efuse" + - "amlogic,meson8-efuse" + - "amlogic,meson8b-efuse" +- reg: base address and size of the efuse registers +- clocks: a reference to the efuse core gate clock +- clock-names: must be "core" + +All properties and sub-nodes as well as the consumer bindings +defined in nvmem.txt in this directory are also supported. + + +Example: + efuse: nvmem@0 { + compatible = "amlogic,meson8-efuse"; + reg = <0x0 0x2000>; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "core"; + }; From patchwork Mon Oct 9 13:26:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115224 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2560195qgn; Mon, 9 Oct 2017 06:28:46 -0700 (PDT) X-Received: by 10.84.252.132 with SMTP id y4mr3713786pll.431.1507555726340; Mon, 09 Oct 2017 06:28:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555726; cv=none; d=google.com; s=arc-20160816; b=v3crmAYHBEQM7h3BMp3D0sGr9ydba1nm83fJA4pa70n6xip86FdbbV2XYZiJFcGcMT lDUEffeSbGWMlL/+3BPzZED9p44XCL63n9B0MwX0PQv6+cUsqJfq+/7VBxHjZ4AE9nOh OK4Cxz3qRmzO69+2EQ9o+mSwey3W2jWjx9IsZ9GQeE2LA0ddHSoDyiB5fCihofcyKisB 8g+2ufAT8I1LiUbq49hs8wz0cjnxwkr5atOUdCzqC95sBV/ZRpAh/V32lS7eD+HjnAqS dyFgprU0ldCaLpvueqeqNx1UuLnmcMcfxBCSG7oTgInt/S7MvIF+wKCAsxCMkGtx3BIP +9vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=fO31IOpYgPE0F0/o14oRPa6Zt6ZbhcrDqkb5c5Bfkvk=; b=TXiRmfDuGwbehYySR7Lq5qCK8yP/zIFSuV8BM1ptVOyuXomKUZBORIstAREu8agtzf /ES6NnlIFeryGhveB9tHWhTrHWGa6i3AAc579Gha/kaTTXg27CcB47ZQalfaa33u4BD9 ZCYvnai6mnmjsuKTqnS52btwGzty9kDjTnscX6p8u+6zeX+nhvAuag/Q2n/vqiy7i2+e r5TZ+N1Ky8ZIpXzsR2s5Ynh/P1wzDBopE9NebR8gix8jbeBncCQKidA/+WIwsB/XFvXf QkKtQr7jTCLngy5rWVUVDqIu6WFZUHioI1/3qLYDUepz2csMZ284PWZXL1iHao3XaM9f fPtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ECP9v3mE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.26.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:26:59 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Martin Blumenstingl Subject: [PATCH 11/12] nvmem: meson-efuse: indicate that this driver is only for Meson GX SoCs Date: Mon, 9 Oct 2017 15:26:40 +0200 Message-Id: <20171009132641.27169-12-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Martin Blumenstingl The current Amlogic Meson eFuse driver only supports the 64-bit SoCs (GXBB and newer). Older SoCs cannot be supported by the same driver because they do not use the meson secure monitor firmware to access the hardware. Signed-off-by: Martin Blumenstingl Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt | 2 +- drivers/nvmem/Kconfig | 4 ++-- drivers/nvmem/meson-efuse.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt index fafd85bd67a6..e3298e18de26 100644 --- a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt @@ -1,4 +1,4 @@ -= Amlogic eFuse device tree bindings = += Amlogic Meson GX eFuse device tree bindings = Required properties: - compatible: should be "amlogic,meson-gxbb-efuse" diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 2755df8f6e9b..e364c925e10c 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -146,11 +146,11 @@ config NVMEM_VF610_OCOTP be called nvmem-vf610-ocotp. config MESON_EFUSE - tristate "Amlogic eFuse Support" + tristate "Amlogic Meson GX eFuse Support" depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM help This is a driver to retrieve specific values from the eFuse found on - the Amlogic Meson SoCs. + the Amlogic Meson GX SoCs. This driver can also be built as a module. If so, the module will be called nvmem_meson_efuse. diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c index dbedfcea4e05..a43c68f90937 100644 --- a/drivers/nvmem/meson-efuse.c +++ b/drivers/nvmem/meson-efuse.c @@ -1,5 +1,5 @@ /* - * Amlogic eFuse Driver + * Amlogic Meson GX eFuse Driver * * Copyright (c) 2016 Endless Computers, Inc. * Author: Carlo Caione @@ -88,5 +88,5 @@ static struct platform_driver meson_efuse_driver = { module_platform_driver(meson_efuse_driver); MODULE_AUTHOR("Carlo Caione "); -MODULE_DESCRIPTION("Amlogic Meson NVMEM driver"); +MODULE_DESCRIPTION("Amlogic Meson GX NVMEM driver"); MODULE_LICENSE("GPL v2"); From patchwork Mon Oct 9 13:26:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 115223 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2559012qgn; Mon, 9 Oct 2017 06:27:40 -0700 (PDT) X-Received: by 10.98.16.149 with SMTP id 21mr3556607pfq.182.1507555660262; Mon, 09 Oct 2017 06:27:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507555660; cv=none; d=google.com; s=arc-20160816; b=a/pYmttY3ceCU5yQepBRuDKYEwm4zB9kgLYSMGYr3jpexvfPNLO6QCJ4QgPhuLAqmu CNn3Zh/39p5WvRt7lrvwfSeqmOYKIwekd61nExtuyppkziXpmYZGkZ2SGdvttA/A9dnz WhT4zGAoEJkNKDz0UbSq1m1OJ+9gtJPK5SF2JZz8S25DfxBady5P74SmfPf83Di19RNQ smhXijR3QxxBu6qOzM/yPRuks24R6NeD2QTWhA58dwigGDgtjMvbf9uEVvQaYPBeXEFS Q+2XcCxmuhp/u+pQiNvfTDYRNR1DvcfmyFav5RKMbq8K1ow/s25rZZCqSr+JpSIK49aO 3Fnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+nTgZeYRGXWL482jZbce3dVgajCw7/0aoU0K5meQcIQ=; b=CdZMiFLUGN4yX2a68V7vY1xGtpwKGLcWG8h5Eyyh8LgvRCAe+1F2ta73MwEOCgGEuF jilgNb3gHVq+Ny8q5QZDLysPZ/SjoE+Ubf59zyBb9XiYTcsvxti3QrtJpTFFcuR1SQeB PgLhy0Qnt1/JQNU/z3rBfBRFYbGlXo1CKZybScS8dHpf3igyvs5kqcmmWNGH0FCE7V0Y Oh0q1sZpx1frIS9r+rKPONOJ7ed1/BHtXh4pkdxhtOQCNA051au2oWjXNejqsrmBV7bF ntxuLpVA9AYCsgxPRZf2Q5lRxI1U5BFZ671Z6PGGxSlJZfDaDfy2ExecErow9dGKWj91 A0Tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k2/x8gDE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id 31sm3775340wrm.0.2017.10.09.06.27.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Oct 2017 06:27:01 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Martin Blumenstingl Subject: [PATCH 12/12] nvmem: add a driver for the Amlogic Meson6/Meson8/Meson8b SoCs Date: Mon, 9 Oct 2017 15:26:41 +0200 Message-Id: <20171009132641.27169-13-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> References: <20171009132641.27169-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Martin Blumenstingl This adds a driver to access the efuse on Amlogic Meson6, Meson8 and Meson8b SoCs. These SoCs are accessing the efuse IP block directly through the registers in the "secbus" region. This makes it different from the Meson GX efuse driver which uses the "secure monitor" firmware to access the efuse. The efuse on Meson6 can only read one byte at a time, while the efuse on Meson8 and Meson8b always reads 4 bytes at a time. The new driver supports both, but due to lack of hardware Meson6 support was not tested. The hardware also supports writing. However, this is currently not supported by the driver. Signed-off-by: Martin Blumenstingl Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/meson-mx-efuse.c | 265 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 drivers/nvmem/meson-mx-efuse.c -- 2.11.0 diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index e364c925e10c..ff505af064ba 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -155,6 +155,16 @@ config MESON_EFUSE This driver can also be built as a module. If so, the module will be called nvmem_meson_efuse. +config MESON_MX_EFUSE + tristate "Amlogic Meson6/Meson8/Meson8b eFuse Support" + depends on ARCH_MESON || COMPILE_TEST + help + This is a driver to retrieve specific values from the eFuse found on + the Amlogic Meson6, Meson8 and Meson8b SoCs. + + This driver can also be built as a module. If so, the module + will be called nvmem_meson_mx_efuse. + config NVMEM_SNVS_LPGPR tristate "Support for Low Power General Purpose Register" depends on SOC_IMX6 || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 11825353f729..64849e946d50 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -32,5 +32,7 @@ obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o nvmem-vf610-ocotp-y := vf610-ocotp.o obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o nvmem_meson_efuse-y := meson-efuse.o +obj-$(CONFIG_MESON_MX_EFUSE) += nvmem_meson_mx_efuse.o +nvmem_meson_mx_efuse-y := meson-mx-efuse.o obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o nvmem_snvs_lpgpr-y := snvs_lpgpr.o diff --git a/drivers/nvmem/meson-mx-efuse.c b/drivers/nvmem/meson-mx-efuse.c new file mode 100644 index 000000000000..a346b4923550 --- /dev/null +++ b/drivers/nvmem/meson-mx-efuse.c @@ -0,0 +1,265 @@ +/* + * Amlogic Meson6, Meson8 and Meson8b eFuse Driver + * + * Copyright (c) 2017 Martin Blumenstingl + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MESON_MX_EFUSE_CNTL1 0x04 +#define MESON_MX_EFUSE_CNTL1_PD_ENABLE BIT(27) +#define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY BIT(26) +#define MESON_MX_EFUSE_CNTL1_AUTO_RD_START BIT(25) +#define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE BIT(24) +#define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA GENMASK(23, 16) +#define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY BIT(14) +#define MESON_MX_EFUSE_CNTL1_AUTO_WR_START BIT(13) +#define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE BIT(12) +#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET BIT(11) +#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK GENMASK(10, 0) + +#define MESON_MX_EFUSE_CNTL2 0x08 + +#define MESON_MX_EFUSE_CNTL4 0x10 +#define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE BIT(10) + +struct meson_mx_efuse_platform_data { + const char *name; + unsigned int word_size; +}; + +struct meson_mx_efuse { + void __iomem *base; + struct clk *core_clk; + struct nvmem_device *nvmem; + struct nvmem_config config; +}; + +static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg, + u32 mask, u32 set) +{ + u32 data; + + data = readl(efuse->base + reg); + data &= ~mask; + data |= (set & mask); + + writel(data, efuse->base + reg); +} + +static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse) +{ + int err; + + err = clk_prepare_enable(efuse->core_clk); + if (err) + return err; + + /* power up the efuse */ + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, + MESON_MX_EFUSE_CNTL1_PD_ENABLE, 0); + + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4, + MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE, 0); + + return 0; +} + +static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse) +{ + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, + MESON_MX_EFUSE_CNTL1_PD_ENABLE, + MESON_MX_EFUSE_CNTL1_PD_ENABLE); + + clk_disable_unprepare(efuse->core_clk); +} + +static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse, + unsigned int addr, u32 *value) +{ + int err; + u32 regval; + + /* write the address to read */ + regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr); + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, + MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval); + + /* inform the hardware that we changed the address */ + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, + MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET, + MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET); + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, + MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET, 0); + + /* start the read process */ + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, + MESON_MX_EFUSE_CNTL1_AUTO_RD_START, + MESON_MX_EFUSE_CNTL1_AUTO_RD_START); + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, + MESON_MX_EFUSE_CNTL1_AUTO_RD_START, 0); + + /* + * perform a dummy read to ensure that the HW has the RD_BUSY bit set + * when polling for the status below. + */ + readl(efuse->base + MESON_MX_EFUSE_CNTL1); + + err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1, + regval, + (!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)), + 1, 1000); + if (err) { + dev_err(efuse->config.dev, + "Timeout while reading efuse address %u\n", addr); + return err; + } + + *value = readl(efuse->base + MESON_MX_EFUSE_CNTL2); + + return 0; +} + +static int meson_mx_efuse_read(void *context, unsigned int offset, + void *buf, size_t bytes) +{ + struct meson_mx_efuse *efuse = context; + u32 tmp; + int err, i, addr; + + err = meson_mx_efuse_hw_enable(efuse); + if (err) + return err; + + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, + MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE, + MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE); + + for (i = offset; i < offset + bytes; i += efuse->config.word_size) { + addr = i / efuse->config.word_size; + + err = meson_mx_efuse_read_addr(efuse, addr, &tmp); + if (err) + break; + + memcpy(buf + i, &tmp, efuse->config.word_size); + } + + meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, + MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE, 0); + + meson_mx_efuse_hw_disable(efuse); + + return err; +} + +static const struct meson_mx_efuse_platform_data meson6_efuse_data = { + .name = "meson6-efuse", + .word_size = 1, +}; + +static const struct meson_mx_efuse_platform_data meson8_efuse_data = { + .name = "meson8-efuse", + .word_size = 4, +}; + +static const struct meson_mx_efuse_platform_data meson8b_efuse_data = { + .name = "meson8b-efuse", + .word_size = 4, +}; + +static const struct of_device_id meson_mx_efuse_match[] = { + { .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data }, + { .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data }, + { .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, meson_mx_efuse_match); + +static int meson_mx_efuse_probe(struct platform_device *pdev) +{ + const struct meson_mx_efuse_platform_data *drvdata; + struct meson_mx_efuse *efuse; + struct resource *res; + + drvdata = of_device_get_match_data(&pdev->dev); + if (!drvdata) + return -EINVAL; + + efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL); + if (!efuse) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + efuse->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(efuse->base)) + return PTR_ERR(efuse->base); + + efuse->config.name = devm_kstrdup(&pdev->dev, drvdata->name, + GFP_KERNEL); + efuse->config.owner = THIS_MODULE; + efuse->config.dev = &pdev->dev; + efuse->config.priv = efuse; + efuse->config.stride = drvdata->word_size; + efuse->config.word_size = drvdata->word_size; + efuse->config.size = SZ_512; + efuse->config.read_only = true; + efuse->config.reg_read = meson_mx_efuse_read; + + efuse->core_clk = devm_clk_get(&pdev->dev, "core"); + if (IS_ERR(efuse->core_clk)) { + dev_err(&pdev->dev, "Failed to get core clock\n"); + return PTR_ERR(efuse->core_clk); + } + + efuse->nvmem = nvmem_register(&efuse->config); + if (IS_ERR(efuse->nvmem)) + return PTR_ERR(efuse->nvmem); + + platform_set_drvdata(pdev, efuse); + + return 0; +} + +static int meson_mx_efuse_remove(struct platform_device *pdev) +{ + struct meson_mx_efuse *efuse = platform_get_drvdata(pdev); + + return nvmem_unregister(efuse->nvmem); +} + +static struct platform_driver meson_mx_efuse_driver = { + .probe = meson_mx_efuse_probe, + .remove = meson_mx_efuse_remove, + .driver = { + .name = "meson-mx-efuse", + .of_match_table = meson_mx_efuse_match, + }, +}; + +module_platform_driver(meson_mx_efuse_driver); + +MODULE_AUTHOR("Martin Blumenstingl "); +MODULE_DESCRIPTION("Amlogic Meson MX eFuse NVMEM driver"); +MODULE_LICENSE("GPL v2");