From patchwork Mon Oct 9 09:03:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 115194 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2319601qgn; Mon, 9 Oct 2017 02:04:17 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCklIZxyQAKmgE6iMP7z19mNdLuiH5h/8tnDGnIs9FRtKdYAm+PFIcmc578CLBv3mpkRRhr X-Received: by 10.84.212.22 with SMTP id d22mr8500184pli.255.1507539857327; Mon, 09 Oct 2017 02:04:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507539857; cv=none; d=google.com; s=arc-20160816; b=cC2FixR7/glRyzXuuQPS76FZ40VhEeR9DsRx6qs9zONnsmEmcRfNduKmTw31Xo8I5M ijAiCcTxEv4+RjV2n/BEVgIjKnQaALVhvHPqvDROfcvKlGtMmsH9lB8XY+q3OuSKAmir Mfhp0+cAGJG3n/h0fFbAH+5vNOTVUkIiDgVerXHHTnOV9DxNxVAtwD/7ZPec7OdEVYLF b8Rj4CWgldXogDNrPyn+iorwntHKy7mxo34HPuamgKwSFS2M9QowuBzoqniqf+Ir4DuB 6cehLepBmhe+wGXnoXBueChNgLTcisxqUG8Vy65LsdvzDS63WAfecJ1p8Yyz6J474hsN 5APg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=MmY10VZihWYw59h7FNKdqgcmzIHtuhYT1/+9gYcKqUQ=; b=TGV9GsK2/XsL18eizXhFHHiyN+rwm0TkmA3LFHUQfednrjvg4VlZduObKkfpwjW5IZ 5qs/TyCmZ2WYm0ZULUODw9fg/B34BEyLCfWr5PhIJ8Zv/K+29G9hf9mF65t0P9RERgub 2okLz7n6jzsFqLOLL6u43Qak4hWfVgQ9D7CFx0oS+KdraE3fPRl2KtJsXtlGeqLHhg4T VzXKeYri2mcy1mQLloUjzZCcGtZTWVE0epYxERq9I/ibKMdupg5YmOEuq0uBZof2J0Ng K5JCjcphC1KdWOy9abX7zOaZNIIG7U2zRbUafQHcV2daI6dDY2AWfxy1ArJePYQP+fnV jfpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MrZ6t141; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n28si5938036pgf.389.2017.10.09.02.04.17; Mon, 09 Oct 2017 02:04:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MrZ6t141; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754029AbdJIJEP (ORCPT + 26 others); Mon, 9 Oct 2017 05:04:15 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:45712 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751550AbdJIJEL (ORCPT ); Mon, 9 Oct 2017 05:04:11 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9993omd026089; Mon, 9 Oct 2017 04:03:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507539830; bh=KwqqWg6axBpY1al4puFq8DQiD5OpiQ4i2NH7tNyI9wk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MrZ6t14152k7T+GfS/8huRrJffBSpPqi31JRhNpu6AoWYSXqN88VFan2RdWbe4W7O 0SyGy6Y/NfcA1ffNg4HXtUw7gud3Ip1UeKgWWRelXXYnM/fBEa/MESVFxlnmCbg5Hu HWS/69ZH+HZjTvyPZIedmDs6l51JXmm9CYgou5mY= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9993jFI020530; Mon, 9 Oct 2017 04:03:45 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 9 Oct 2017 04:03:45 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 9 Oct 2017 04:03:45 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9993eJY002737; Mon, 9 Oct 2017 04:03:43 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Bjorn Helgaas CC: Roger Quadros , , , , Subject: [PATCH 1/2] PCI: dwc: dra7xx: Create functional dependency between PCIe and PHY Date: Mon, 9 Oct 2017 14:33:37 +0530 Message-ID: <20171009090338.26033-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009090338.26033-1-kishon@ti.com> References: <20171009090338.26033-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCI core access configuration space registers in resume_noirq callbacks. In the case of dra7xx, PIPE3 PHY connected to PCIe controller has to be enabled before accessing configuration space registers. Since PIPE3 PHY is enabled by only configuring control module registers, no aborts has been observed so far (though during noirq stage, interface clock of PIPE3 PHY is not enabled). With new TRM updates, PIPE3 PHY has to be initialized (PIPE3 PHY registers has to be accessed) as well which requires the interface clock of PIPE3 PHY to be enabled. The interface clock of PIPE3 PHY is derived from OCP2SCP and hence PCIe PHY is modeled as a child of OCP2SCP. Since pm_runtime is not enabled during noirq stage, pm_runtime_get_sync done in phy_init doesn't enable OCP2SCP clocks resulting in abort when PIPE3 PHY registers are accessed. Create a function dependency between PCIe and PHY here to make sure PCIe is suspended before PCIe PHY/OCP2SCP and resumed after PCIe PHY/OCP2SCP. Suggested-by: Grygorii Strashko Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/pci/dwc/pci-dra7xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.11.0 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 34427a6a15af..362607f727ee 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -594,6 +595,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) int i; int phy_count; struct phy **phy; + struct device_link **link; void __iomem *base; struct resource *res; struct dw_pcie *pci; @@ -649,11 +651,21 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) if (!phy) return -ENOMEM; + link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL); + if (!link) + return -ENOMEM; + for (i = 0; i < phy_count; i++) { snprintf(name, sizeof(name), "pcie-phy%d", i); phy[i] = devm_phy_get(dev, name); if (IS_ERR(phy[i])) return PTR_ERR(phy[i]); + + link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); + if (!link[i]) { + ret = -EINVAL; + goto err_link; + } } dra7xx->base = base; @@ -732,6 +744,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) pm_runtime_disable(dev); dra7xx_pcie_disable_phy(dra7xx); +err_link: + while (--i >= 0) + device_link_del(link[i]); + return ret; } From patchwork Mon Oct 9 09:03:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 115193 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2319342qgn; Mon, 9 Oct 2017 02:03:55 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBiBMN1+nD0vlKOuYUUO0G2yQWDJAJg/pHWcqwn8YSELl4Vc19m3BFlZUdYUUPwxjpe1wxd X-Received: by 10.99.36.133 with SMTP id k127mr3127601pgk.171.1507539835656; Mon, 09 Oct 2017 02:03:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507539835; cv=none; d=google.com; s=arc-20160816; b=PsQ7mZ98kXhxCdahpkUsk55ghpWvfFv7oHA68nmq9DCoLjwXc5x+IbD8Km5XWrEbUs lb75nBAOtAF6InaoJv1Vsr1wbkX+zX/8RxvxSqKjpK10uCCJLw5w8QByi7nXZzNQhYyC o1ZxmPr/1w9tlep9hrzB2ihCWcN6V5deOLGwEoSDGBrUwpo1rVgfdVKis2RxIndenKPk CqD15tLGtWbuklzPP8ESpLA5JWj4PWpfuEOJqzDdDd9hxJeRSEApNblEzgMepTo3DlbT 2QDJ7KxG5bUPWX5h/kZVj5/WCKAv1QmJJbaOo6KJPh4zzdZTts/B2uztRZyuSdFI67x2 Xf6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=yb4IqJufJZmlA9wekWNoNu3Kb4USSze9g03uiy5RQSY=; b=XiGXie0N4eH9VHPgh5rK7/niNH8TrOaLgZRliA2h4kVa+ezXeHYr56vByrjzs2ctVL BaqJlFPFGdGXtZuUv4xJDEcuTO+VM12W11oWJ2jqoRoi1h2BLiBoeYPQ4LCgNbouF3FG SpFV3G19hzmytDf8q7jDrZEI9bgOqoVyGC/6ybVdSMUZg/GbIkyjcnjPExvPcxhQL4f2 IKXnCNveXV/rgZFmiN/CGG80JvKVVahJAJqo36ABVX2ktxf/oDQvGmfoVqbv6UifAhQQ npj3QG71AE0579zhRb2tsyp51YIzqQHrCWiOclAhZUQ9cdNsQNkiyf8D8yhR/z47o7mE 2jzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sltTWQ37; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w14si4687138pfi.426.2017.10.09.02.03.55; Mon, 09 Oct 2017 02:03:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sltTWQ37; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753962AbdJIJDx (ORCPT + 26 others); Mon, 9 Oct 2017 05:03:53 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:22973 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753842AbdJIJDt (ORCPT ); Mon, 9 Oct 2017 05:03:49 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9993mZL014601; Mon, 9 Oct 2017 04:03:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507539828; bh=VZyb3bHzCwiP+b6I7rBJVbP0/N0i+RIWhCK6RUOMS+8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sltTWQ37GEYRPNO4S3BqvCqbjSl6GhVdHnXy6eBIWRHCfrAVM485ASpMyIOMyXJqn H4PqBVb78nub8w7pb/QTMkJM8N8IQjxyUOOIeGipzlCzidv00w1TKGRHUWfqnVgOiD GHhBMs6prxctbaxy1r0uwAEFKvouyCy9YZXZiPcw= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9993mPx027605; Mon, 9 Oct 2017 04:03:48 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 9 Oct 2017 04:03:47 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 9 Oct 2017 04:03:48 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9993eJZ002737; Mon, 9 Oct 2017 04:03:45 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Bjorn Helgaas CC: Roger Quadros , , , , , Vignesh R Subject: [PATCH 2/2] phy: ti-pipe3: Update pcie phy settings Date: Mon, 9 Oct 2017 14:33:38 +0530 Message-ID: <20171009090338.26033-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009090338.26033-1-kishon@ti.com> References: <20171009090338.26033-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the PCIe phy settings based on new settings available in AM572x Technical Reference Manual[1] Revision I, revised April 2017 in Table 26-62 "Preferred PCIe_PHY_RX SCP Register Settings". [1] http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf Cc: Vignesh R Signed-off-by: Kishon Vijay Abraham I [nsekhar@ti.com: commit message updates] Signed-off-by: Sekhar Nori --- drivers/phy/ti/phy-ti-pipe3.c | 101 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index 0e564f32749f..68ce4a082b9b 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -68,6 +68,40 @@ #define PCIE_PCS_MASK 0xFF0000 #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10 +#define PCIEPHYRX_ANA_PROGRAMMABILITY 0x0000000C +#define INTERFACE_MASK GENMASK(31, 27) +#define INTERFACE_SHIFT 27 +#define LOSD_MASK GENMASK(17, 14) +#define LOSD_SHIFT 14 +#define MEM_PLLDIV GENMASK(6, 5) + +#define PCIEPHYRX_TRIM 0x0000001C +#define MEM_DLL_TRIM_SEL GENMASK(31, 30) +#define MEM_DLL_TRIM_SHIFT 30 + +#define PCIEPHYRX_DLL 0x00000024 +#define MEM_DLL_PHINT_RATE GENMASK(31, 30) + +#define PCIEPHYRX_DIGITAL_MODES 0x00000028 +#define MEM_CDR_FASTLOCK BIT(23) +#define MEM_CDR_LBW GENMASK(22, 21) +#define MEM_CDR_STEPCNT GENMASK(20, 19) +#define MEM_CDR_STL_MASK GENMASK(18, 16) +#define MEM_CDR_STL_SHIFT 16 +#define MEM_CDR_THR_MASK GENMASK(15, 13) +#define MEM_CDR_THR_SHIFT 13 +#define MEM_CDR_THR_MODE BIT(12) +#define MEM_CDR_CDR_2NDO_SDM_MODE BIT(11) +#define MEM_OVRD_HS_RATE BIT(26) + +#define PCIEPHYRX_EQUALIZER 0x00000038 +#define MEM_EQLEV GENMASK(31, 16) +#define MEM_EQFTC GENMASK(15, 11) +#define MEM_EQCTL GENMASK(10, 7) +#define MEM_EQCTL_SHIFT 7 +#define MEM_OVRD_EQLEV BIT(2) +#define MEM_OVRD_EQFTC BIT(1) + /* * This is an Empirical value that works, need to confirm the actual * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status @@ -91,6 +125,8 @@ struct pipe3_dpll_map { struct ti_pipe3 { void __iomem *pll_ctrl_base; + void __iomem *phy_rx; + void __iomem *phy_tx; struct device *dev; struct device *control_dev; struct clk *wkupclk; @@ -261,6 +297,37 @@ static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) return ti_pipe3_dpll_wait_lock(phy); } +static void ti_pipe3_calibrate(struct ti_pipe3 *phy) +{ + u32 val; + + val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY); + val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV); + val = (0x1 << INTERFACE_SHIFT | 0xA << LOSD_SHIFT); + ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY, val); + + val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES); + val &= ~(MEM_CDR_STEPCNT | MEM_CDR_STL_MASK | MEM_CDR_THR_MASK | + MEM_CDR_CDR_2NDO_SDM_MODE | MEM_OVRD_HS_RATE); + val |= (MEM_CDR_FASTLOCK | MEM_CDR_LBW | 0x3 << MEM_CDR_STL_SHIFT | + 0x1 << MEM_CDR_THR_SHIFT | MEM_CDR_THR_MODE); + ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES, val); + + val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_TRIM); + val &= ~MEM_DLL_TRIM_SEL; + val |= 0x2 << MEM_DLL_TRIM_SHIFT; + ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_TRIM, val); + + val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DLL); + val |= MEM_DLL_PHINT_RATE; + ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DLL, val); + + val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_EQUALIZER); + val &= ~(MEM_EQLEV | MEM_EQCTL | MEM_OVRD_EQLEV | MEM_OVRD_EQFTC); + val |= MEM_EQFTC | 0x1 << MEM_EQCTL_SHIFT; + ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_EQUALIZER, val); +} + static int ti_pipe3_init(struct phy *x) { struct ti_pipe3 *phy = phy_get_drvdata(x); @@ -282,7 +349,12 @@ static int ti_pipe3_init(struct phy *x) val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, PCIE_PCS_MASK, val); - return ret; + if (ret) + return ret; + + ti_pipe3_calibrate(phy); + + return 0; } /* Bring it out of IDLE if it is IDLE */ @@ -513,6 +585,29 @@ static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) return 0; } +static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) +{ + struct resource *res; + struct device *dev = phy->dev; + struct device_node *node = dev->of_node; + struct platform_device *pdev = to_platform_device(dev); + + if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) + return 0; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "phy_rx"); + phy->phy_rx = devm_ioremap_resource(dev, res); + if (IS_ERR(phy->phy_rx)) + return PTR_ERR(phy->phy_rx); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "phy_tx"); + phy->phy_tx = devm_ioremap_resource(dev, res); + + return PTR_ERR_OR_ZERO(phy->phy_tx); +} + static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) { struct resource *res; @@ -559,6 +654,10 @@ static int ti_pipe3_probe(struct platform_device *pdev) if (ret) return ret; + ret = ti_pipe3_get_tx_rx_base(phy); + if (ret) + return ret; + ret = ti_pipe3_get_sysctrl(phy); if (ret) return ret;