From patchwork Mon May 18 13:17:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 245954 List-Id: U-Boot discussion From: m.szyprowski at samsung.com (Marek Szyprowski) Date: Mon, 18 May 2020 15:17:59 +0200 Subject: [RFC PATCH v3 1/3] arm: provide a function for boards init code to modify MMU virtual-physical map In-Reply-To: <20200518131801.465-1-m.szyprowski@samsung.com> References: <20200518131801.465-1-m.szyprowski@samsung.com> Message-ID: <20200518131801.465-2-m.szyprowski@samsung.com> Provide a function for setting arbitrary virtual-physical MMU mapping for the given region. Signed-off-by: Marek Szyprowski --- arch/arm/include/asm/mmu.h | 8 ++++++++ arch/arm/include/asm/system.h | 11 +++++++++++ arch/arm/lib/cache-cp15.c | 24 ++++++++++++++++++------ 3 files changed, 37 insertions(+), 6 deletions(-) create mode 100644 arch/arm/include/asm/mmu.h diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h new file mode 100644 index 0000000..fe3d793 --- /dev/null +++ b/arch/arm/include/asm/mmu.h @@ -0,0 +1,8 @@ +#ifndef __ASM_ARM_MMU_H +#define __ASM_ARM_MMU_H + +#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif + +#endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 81ccead..5b9f31c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -573,6 +573,17 @@ s32 psci_features(u32 function_id, u32 psci_fid); void save_boot_params_ret(void); /** + * Change the virt/phys mapping and cache settings for a region. + * + * \param virt virtual start address of memory region to change + * \param phys physical address for the memory region to set + * \param size size of memory region to change + * \param option dcache option to select + */ +void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys, + size_t size, enum dcache_option option); + +/** * Change the cache settings for a region. * * \param start start address of memory region to change diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f8d2096..84ddad3 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -24,7 +24,8 @@ __weak void arm_init_domains(void) { } -void set_section_dcache(int section, enum dcache_option option) +static void set_section_phys(int section, phys_addr_t phys, + enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -36,7 +37,7 @@ void set_section_dcache(int section, enum dcache_option option) #endif /* Add the page offset */ - value |= ((u32)section << MMU_SECTION_SHIFT); + value |= phys; /* Add caching bits */ value |= option; @@ -45,13 +46,18 @@ void set_section_dcache(int section, enum dcache_option option) page_table[section] = value; } +void set_section_dcache(int section, enum dcache_option option) +{ + set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option); +} + __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) { debug("%s: Warning: not implemented\n", __func__); } -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option) +void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, + size_t size, enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -70,8 +76,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size, option); #endif - for (upto = start; upto < end; upto++) - set_section_dcache(upto, option); + for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE) + set_section_phys(upto, phys, option); /* * Make sure range is cache line aligned @@ -86,6 +92,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, mmu_page_table_flush(startpt, stoppt); } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + mmu_set_region_dcache_behaviour_phys(start, start, size, option); +} + __weak void dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; From patchwork Mon May 18 13:18:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 245957 List-Id: U-Boot discussion From: m.szyprowski at samsung.com (Marek Szyprowski) Date: Mon, 18 May 2020 15:18:00 +0200 Subject: [RFC PATCH v3 2/3] mmc: bcm283x: fix int to pointer cast In-Reply-To: <20200518131801.465-1-m.szyprowski@samsung.com> References: <20200518131801.465-1-m.szyprowski@samsung.com> Message-ID: <20200518131801.465-3-m.szyprowski@samsung.com> From: Seung-Woo Kim On build with 32 bit, there is a warning for int-to-pointer-cast. Fix the int to pointer cast by using uintptr_t. Signed-off-by: Seung-Woo Kim Signed-off-by: Marek Szyprowski --- drivers/mmc/bcm2835_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 39c93db..c31f099 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -209,7 +209,7 @@ static int bcm2835_sdhci_probe(struct udevice *dev) priv->last_write = 0; host->name = dev->name; - host->ioaddr = (void *)base; + host->ioaddr = (void *)(uintptr_t)base; host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT; host->max_clk = emmc_freq; From patchwork Mon May 18 13:18:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 245956 List-Id: U-Boot discussion From: m.szyprowski at samsung.com (Marek Szyprowski) Date: Mon, 18 May 2020 15:18:01 +0200 Subject: [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) In-Reply-To: <20200518131801.465-1-m.szyprowski@samsung.com> References: <20200518131801.465-1-m.szyprowski@samsung.com> Message-ID: <20200518131801.465-4-m.szyprowski@samsung.com> Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski --- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++ arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++ include/configs/rpi.h | 7 +++++++ 4 files changed, 36 insertions(+) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 00419bf..bcb7f1d 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae398..4ccaf69 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -8,4 +8,12 @@ extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +#ifdef CONFIG_TARGET_RPI_4_32B +#include +#define phys_to_virt addrmap_phys_to_virt +#define virt_to_phys addrmap_virt_to_phys +#endif +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 9f5bca3..008b312 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -145,6 +145,26 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE +#ifdef CONFIG_TARGET_RPI_4_32B +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL +#include + +void init_addr_map(void) +{ + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + DCACHE_OFF); + + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */ + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0); + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */ + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1); +} +#endif + void enable_caches(void) { dcache_enable(); diff --git a/include/configs/rpi.h b/include/configs/rpi.h index b53a4b6..296e8ee 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -63,6 +63,13 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M #endif +#ifdef CONFIG_ARMV7_LPAE +#ifdef CONFIG_TARGET_RPI_4_32B +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 2 +#endif +#endif + /* Devices */ /* GPIO */ #define CONFIG_BCM2835_GPIO