From patchwork Mon May 11 06:18:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 245530 List-Id: U-Boot discussion From: peng.fan at nxp.com (Peng Fan) Date: Mon, 11 May 2020 14:18:29 +0800 Subject: [PATCH 1/2] imx: imx8mp_evk: fix boot issue Message-ID: <20200511061830.20580-1-peng.fan@nxp.com> The u-boot-spl.bin pad with ddr firmware conflicts with the CONFIG_MALLOC_F_ADDR area, the ddr firmware will be overwritten by malloc in SPL stage and cause ddr initialization not able to finish. So update the related addresses to fix the issue. Reported-by: Fabio Estevam Signed-off-by: Peng Fan --- include/configs/imx8mp_evk.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 80e5738961..b90a4f6932 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -23,15 +23,15 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_STACK 0x990000 -#define CONFIG_SPL_BSS_START_ADDR 0x0095e000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SPL_STACK 0x98fc00 +#define CONFIG_SPL_BSS_START_ADDR 0x0098fc00 +#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_MALLOC_F_ADDR 0x940000 +#define CONFIG_MALLOC_F_ADDR 0x950000 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE From patchwork Mon May 11 06:18:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 245529 List-Id: U-Boot discussion From: peng.fan at nxp.com (Peng Fan) Date: Mon, 11 May 2020 14:18:30 +0800 Subject: [PATCH 2/2] imx8mp_evk: simplify board spl code In-Reply-To: <20200511061830.20580-1-peng.fan@nxp.com> References: <20200511061830.20580-1-peng.fan@nxp.com> Message-ID: <20200511061830.20580-2-peng.fan@nxp.com> Simplify board SPL code - BSS area will be cleared by crt0_64.S - No need to get ccm device in spl_board_init - Use spl_early_init, not spl_init - timer_init has been invoked in arch_cpu_init Signed-off-by: Peng Fan --- board/freescale/imx8mp_evk/spl.c | 28 ++-------------------------- 1 file changed, 2 insertions(+), 26 deletions(-) diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index c5f640dc7b..5f3ea0b6a1 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -25,11 +25,6 @@ #include #include -#include -#include -#include -#include - DECLARE_GLOBAL_DATA_PTR; int spl_board_boot_device(enum boot_device boot_dev_spl) @@ -44,16 +39,7 @@ void spl_dram_init(void) void spl_board_init(void) { - struct udevice *dev; - int ret; - puts("Normal Boot\n"); - - ret = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller at 30380000", - &dev); - if (ret < 0) - printf("Failed to find clock node. Check device tree\n"); } #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) @@ -114,6 +100,7 @@ int board_fit_config_name_match(const char *name) } #endif +/* Do not use BSS area in this phase */ void board_init_f(ulong dummy) { int ret; @@ -124,19 +111,10 @@ void board_init_f(ulong dummy) board_early_init_f(); - timer_init(); + spl_early_init(); preloader_console_init(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); - if (ret) { - debug("spl_init() failed: %d\n", ret); - hang(); - } - enable_tzc380(); setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); @@ -145,6 +123,4 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); - - board_init_r(NULL, 0); }