From patchwork Fri Oct 6 16:39:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 115092 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1994565qgn; Fri, 6 Oct 2017 09:39:57 -0700 (PDT) X-Received: by 10.159.249.9 with SMTP id bf9mr2499611plb.311.1507307997794; Fri, 06 Oct 2017 09:39:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507307997; cv=none; d=google.com; s=arc-20160816; b=rNA0ACKGZDoNOsH4DeR78hPOAzS2jmN9VT3DMAFjxiEjr634vHksBN+7BTmbWmSTC3 WtHfmzkxc1DyBnS+QQ+UPc1OduXKJiKyEutZMf3FHGKbYSLyA4X07ddJ8OnTs38CeYrr EtdAT1dJfciq6eJUddBVoLZNPuZOXnY6eZLxpBEIayW0BQEIDexYmNNESuCfHTrkmVbe nB378jimLUU1B+IDI9aNvPsi40rjGt2m9kdjYMD8X1Jqeq03X25UxQrMhVuDoCR0v3mS wlaZMClJR4RndtdiwFmHNtiNniO41tcEQ/Z+BIbXh40CKNEX6qnXzULRZcJEVcRGg6Dc 8JvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=VnLcXa3a4OXL5SHoEMnGS9xOO1BWa1UfDZrAGpOINeE=; b=oiJL/xzSyzcdPo6/95UEU7j+kUoifuXDI3Bb+tL+f7j8i2+ZZR5A1nh1O/o2MH1xfM uAs6P/HvU7LY6m1EblvHqfk0kO0QDfaq9hOxE8VJvKrvMochgC9yyE2Fg8fDAim/kt48 5ZZosdcWb7oQKDKvBHFU+w/f577Wa/KfibgmeYvl8/QNKkSwKxFXyKbdlyVtE0dM+Xbg nvSiY4bK3orUMrQU4vnPogBeqc26yOsIwZgBNlf1+VqQ/cYsANKqEudNoMLGo5Dcy5LV pXF5SsTXba6so1Qj7PHvKVNU5POKkTIKDP/Nr0pjtwYPutiSoIfjmlU+lACalW6vbEQX DDRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HqPUzMLk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si1514585plk.126.2017.10.06.09.39.57; Fri, 06 Oct 2017 09:39:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HqPUzMLk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752514AbdJFQj4 (ORCPT + 26 others); Fri, 6 Oct 2017 12:39:56 -0400 Received: from mail-wm0-f51.google.com ([74.125.82.51]:50605 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751618AbdJFQjt (ORCPT ); Fri, 6 Oct 2017 12:39:49 -0400 Received: by mail-wm0-f51.google.com with SMTP id u138so8595636wmu.5 for ; Fri, 06 Oct 2017 09:39:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VnLcXa3a4OXL5SHoEMnGS9xOO1BWa1UfDZrAGpOINeE=; b=HqPUzMLkPUjbbolFPamK7kEl2IX+Wt3rqAvKqSMFYKT9OvyJ1K7afXtj9hnEP07YpG fHTAbtF7K+dT477WbM4MxkNeQqlPaji9UHAWSNF1/v5BTkUsqiKhHkh8Po0z202jE3LA 3Uw0pGp/CWDxq0R8GqApzbYKzwY2VAhRGjRlg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VnLcXa3a4OXL5SHoEMnGS9xOO1BWa1UfDZrAGpOINeE=; b=WrrkiFOwYVnDTbbGVuCVf01DGJDtd8Zap3kTTDcJo7vL0tw1kIbis+FsH848jMZaI2 XFab2b/4YGrt1ksudQ84BxQuir4yaeub2TDuIqFj2z8+EpAxcwCawj4pCO+ayrM84r9l Uob1WIu9V59d1MIDPbgVfuiKtP9JOfi+YG85w16y7bXto4L5/jqwxZUCgxDga8CebOHt bcq4EGNcaKeVn+lk9/JGzZ5FjJYPacLSjnCcnqbxtpUfm4DsNpGdg9kY5V5ql6cxabey VOf7MEgWpWUS7yNw3EP5prMCCXR6/wmzRUjOivLrtzoo6zZQCaCO3VBS0Gon6I4/FYnA TQ4A== X-Gm-Message-State: AMCzsaWk9xaPGy13uckfm13Od6sC/P1Ny/lx2PBdms8gNqy57U32wV/z nXNdhbYi8F6dqob805K2d5eFow== X-Google-Smtp-Source: AOwi7QCxEexl4Xpo6u6VGEpNDQp7glKH58Wv7ZZHSp0RTwj5624iHRT/tDyqWneckvetvPVE3jFN7A== X-Received: by 10.28.156.67 with SMTP id f64mr2160131wme.42.1507307988162; Fri, 06 Oct 2017 09:39:48 -0700 (PDT) Received: from localhost.localdomain ([160.90.203.54]) by smtp.gmail.com with ESMTPSA id b190sm2873023wma.41.2017.10.06.09.39.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 09:39:45 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Bjorn Helgaas , Rob Herring , Will Deacon Subject: [PATCH v4 1/2] PCI: pci-host-generic: add support for Synopsys DesignWare RC in ECAM mode Date: Fri, 6 Oct 2017 17:39:18 +0100 Message-Id: <20171006163919.14898-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006163919.14898-1-ard.biesheuvel@linaro.org> References: <20171006163919.14898-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some implementations of the Synopsys DesignWare PCIe controller implement a so-called ECAM shift mode, which allows a static memory window to be configured that covers the configuration space of the entire bus range. Usually, when the firmware performs all the low level configuration that is required to expose this controller in a fully ECAM compatible manner, we can simply describe it as "pci-host-ecam-generic" and be done with it. However, in some cases (e.g., the Marvell Armada 80x0 as well as the Socionext SynQuacer Soc), the IP was synthesized with an ATU window granularity that does not allow the first bus to be mapped in a way that prevents the device on the downstream port from appearing more than once, and so we still need special handling in software to drive this static almost-ECAM configuration. So extend the pci-host-generic driver so it can support these controllers as well, by adding special config space accessors that take the above quirk into account. Note that, unlike most drivers for this IP, this driver does not expose a fake bridge device at B/D/F 00:00.0. There is no point in doing so, given that this is not a true bridge, and does not require any windows to be configured in order for the downstream device to operate correctly. Omitting it also prevents the PCI resource allocation routines from handing out BAR space to it unnecessarily. Signed-off-by: Ard Biesheuvel --- drivers/pci/host/pci-host-generic.c | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 2.11.0 Acked-by: Will Deacon diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c index 7d709a7e0aa8..01e81a30e303 100644 --- a/drivers/pci/host/pci-host-generic.c +++ b/drivers/pci/host/pci-host-generic.c @@ -35,6 +35,43 @@ static struct pci_ecam_ops gen_pci_cfg_cam_bus_ops = { } }; +static int pci_dw_ecam_config_read(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct pci_config_window *cfg = bus->sysdata; + + /* + * The Synopsys DesignWare PCIe controller in ECAM mode will not filter + * type 0 config TLPs sent to devices 1 and up on its downstream port, + * resulting in devices appearing multiple times on bus 0 unless we + * filter out those accesses here. + */ + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return pci_generic_config_read(bus, devfn, where, size, val); +} + +static int pci_dw_ecam_config_write(struct pci_bus *bus, u32 devfn, int where, + int size, u32 val) +{ + struct pci_config_window *cfg = bus->sysdata; + + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return pci_generic_config_write(bus, devfn, where, size, val); +} + +static struct pci_ecam_ops pci_dw_ecam_bus_ops = { + .bus_shift = 20, + .pci_ops = { + .map_bus = pci_ecam_map_bus, + .read = pci_dw_ecam_config_read, + .write = pci_dw_ecam_config_write, + } +}; + static const struct of_device_id gen_pci_of_match[] = { { .compatible = "pci-host-cam-generic", .data = &gen_pci_cfg_cam_bus_ops }, @@ -42,6 +79,15 @@ static const struct of_device_id gen_pci_of_match[] = { { .compatible = "pci-host-ecam-generic", .data = &pci_generic_ecam_ops }, + { .compatible = "marvell,armada8k-pcie-ecam", + .data = &pci_dw_ecam_bus_ops }, + + { .compatible = "socionext,synquacer-pcie-ecam", + .data = &pci_dw_ecam_bus_ops }, + + { .compatible = "snps,dw-pcie-ecam", + .data = &pci_dw_ecam_bus_ops }, + { }, }; From patchwork Fri Oct 6 16:39:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 115093 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1994734qgn; Fri, 6 Oct 2017 09:40:09 -0700 (PDT) X-Received: by 10.98.31.215 with SMTP id l84mr2841544pfj.36.1507308009633; Fri, 06 Oct 2017 09:40:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507308009; cv=none; d=google.com; s=arc-20160816; b=tuPtH6boML3YXvK4XAWDzf/oElM1hRyPOAScgMNubFWMlhdkJCtNyo1gGqo+sJPusS BVkMlQ6vOXCQkKXgolJqhqo5DzAKauw+dcKXd+CAL9IsA8TAeCNbnhZhUIrgQB4ILxBS LTAgAqo5lRAqxZxdp5vhqbY5Be9wTCVMOp7g8uh1gQhpyHxET9/HxVTVM/NXzEBPmq64 xD6ck+YEnee0AYUZPIa2XunCxL0qXFw/AxEsCj5UebiF0op2zWqix4azZpBaN5pYQuTz Gbj3xDNq721htar6hFlXVBD86+qYMeYiF8S7yvQJQPbqbc1uhvBHZN8gCL1mc/GZ7hNo k+BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=4D8J4X59CFYhIaQncuIXv1e01SjU+/ZZUbj0qDqaxsM=; b=Jch49QNCAlLEIpKX+GLMUvTJwNmwuQv9HXu0PCIh3Y+LeIYAlhqLKN2CgU/mJlFg6x q+TX3cuk3UmTRNeBtGzRRFub3jAhMTX2I3i4j7skonIjVaTBTVDKmx+qdhXYQlCHMjRW UXt33Abvu1ugc73NVC2ietLQ1YQIYi9wILj9AmS1EZhXPizTHhAThQcAx86OLPOsXqEP 5Q+/32yZm92ViC9+VY6sEED95H7tD1ye/QCQXWy+Rd/JrMNuAi7aEKHfP4eJX/fvqOXm 9k4YKItuCPcZ6uAW1/UAdUFNgNGhl3NIFNS8QtV4hoUKHttRDQH/eBUCM+hsR3ntbIJP nSSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ByhmfIU+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si1514585plk.126.2017.10.06.09.40.09; Fri, 06 Oct 2017 09:40:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ByhmfIU+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752440AbdJFQjy (ORCPT + 26 others); Fri, 6 Oct 2017 12:39:54 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:43246 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751423AbdJFQjv (ORCPT ); Fri, 6 Oct 2017 12:39:51 -0400 Received: by mail-wm0-f44.google.com with SMTP id m72so3313070wmc.0 for ; Fri, 06 Oct 2017 09:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4D8J4X59CFYhIaQncuIXv1e01SjU+/ZZUbj0qDqaxsM=; b=ByhmfIU+WD5SnLUFznLaNTgiahOHa8wlGs4xacpK8AI8Q2/ejBv4eKFAnK6YIhM8/3 AMn3TXfmVtlGj3u+NCdOMt80IiBpTxji7S4rZlt+8oSEypGwGyUQjnhIHnvVqu7jjgwh qtpg1xYSFiQU+0VBjk3jG2XXkbZo2CKa8aWns= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4D8J4X59CFYhIaQncuIXv1e01SjU+/ZZUbj0qDqaxsM=; b=V+SfJKFKSEq0wGMg9jUWcXFoZBOfL6rluxiAx6FouEC1VaFQjwtb6QWWBfzIMLZY97 SkrONxKpmutFggseY61ZjvoUAY2O4aofQU8V6Uv/q+4wvTY4Dzq8F/Q6oTG6692cATTl UlnhDunRMOgIrhTRP36EF3DeMhZ9+2K6WWXkXD/BfmDmQLFmk8njQ7OXwScYaZQbcodS jd68bP0jH1+QfcubAYB8oDrQxEsmOKpwRx6rAcfLD5pr4uiqIx4Pm2ceYcqeK2GBPipi CfYmyq+nzRwvhEV6U9YURLQ7K5hWAB4oAqF4jINdsCzfgeOSEYmlOmh65UBWtdzgu5z7 Pwnw== X-Gm-Message-State: AMCzsaVIEneILaESQux3GxprOxcq4c3dMqCfzOOZPd403mf1747VN/6f 82nwrRkkRLQPIO1b84i6T/oWTA== X-Google-Smtp-Source: AOwi7QCzSn8iy5P/7XRazeOGIKAxaqYb1tRHqwkMe8lV2d9R0EbDok3R5P7mQSzjkENGA2atG80Ujg== X-Received: by 10.28.236.25 with SMTP id k25mr2457861wmh.146.1507307990423; Fri, 06 Oct 2017 09:39:50 -0700 (PDT) Received: from localhost.localdomain ([160.90.203.54]) by smtp.gmail.com with ESMTPSA id b190sm2873023wma.41.2017.10.06.09.39.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 09:39:49 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Bjorn Helgaas , Rob Herring , Will Deacon Subject: [PATCH v4 2/2] dt-bindings: designware: add binding for Designware PCIe in ECAM mode Date: Fri, 6 Oct 2017 17:39:19 +0100 Message-Id: <20171006163919.14898-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006163919.14898-1-ard.biesheuvel@linaro.org> References: <20171006163919.14898-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Describe the binding for firmware-configured instances of the Synopsys DesignWare PCIe controller in RC mode, that are almost but not quite ECAM compliant. Acked-by: Rob Herring Signed-off-by: Ard Biesheuvel --- Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt | 42 ++++++++++++++++++++ 1 file changed, 42 insertions(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt new file mode 100644 index 000000000000..515b2f9542e5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt @@ -0,0 +1,42 @@ +* Synopsys DesignWare PCIe root complex in ECAM shift mode + +In some cases, firmware may already have configured the Synopsys DesignWare +PCIe controller in RC mode with static ATU window mappings that cover all +config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. +In this case, there is no need for the OS to perform any low level setup +of clocks, PHYs or device registers, nor is there any reason for the driver +to reconfigure ATU windows for config and/or IO space accesses at runtime. + +In cases where the IP was synthesized with a minimum ATU window size of +64 KB, it cannot be supported by the generic ECAM driver, because it +requires special config space accessors that filter accesses to device #1 +and beyond on the first bus. + +Required properties: +- compatible: "marvell,armada8k-pcie-ecam" or + "socionext,synquacer-pcie-ecam" or + "snps,dw-pcie-ecam" (must be preceded by a more specific match) + +Please refer to the binding document of "pci-host-ecam-generic" in the +file host-generic-pci.txt for a description of the remaining required +and optional properties. + +Example: + + pcie1: pcie@7f000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x7f000000 0x0 0xf00000>; + bus-range = <0x0 0xe>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>, + <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>, + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>; + msi-map = <0x0 &its 0x0 0x10000>; + dma-coherent; + };