From patchwork Fri May 1 08:28:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Biwen Li \(OSS\)" X-Patchwork-Id: 244692 List-Id: U-Boot discussion From: biwen.li at oss.nxp.com (Biwen Li) Date: Fri, 1 May 2020 16:28:11 +0800 Subject: [RESEND 1/4] powerpc: Enable device tree support for P1010RDB Message-ID: <20200501082814.45691-1-biwen.li@oss.nxp.com> From: Hou Zhiqiang Add device tree for P1010RDB boards and enable CONFIG_OF_CONTROL so that device tree can be compiled. Signed-off-by: Hou Zhiqiang --- arch/powerpc/dts/Makefile | 2 + arch/powerpc/dts/p1010rdb-pa.dts | 17 +++ arch/powerpc/dts/p1010rdb-pa_36b.dts | 17 +++ arch/powerpc/dts/p1010rdb-pb.dts | 17 +++ arch/powerpc/dts/p1010rdb-pb_36b.dts | 17 +++ arch/powerpc/dts/p1010rdb_32b.dtsi | 22 ++++ arch/powerpc/dts/p1010rdb_36b.dtsi | 22 ++++ arch/powerpc/dts/p1010si-post.dtsi | 46 +++++++ arch/powerpc/dts/p1010si-pre.dtsi | 27 ++++ configs/P1010RDB-PA_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 4 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 3 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 3 +- configs/P1010RDB-PA_NAND_defconfig | 3 +- configs/P1010RDB-PA_NOR_defconfig | 4 +- configs/P1010RDB-PA_SDCARD_defconfig | 3 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 3 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 4 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 3 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 3 +- configs/P1010RDB-PB_NAND_defconfig | 3 +- configs/P1010RDB-PB_NOR_defconfig | 4 +- configs/P1010RDB-PB_SDCARD_defconfig | 3 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 3 +- p1010rdb-pb.dts | 123 +++++++++++++++++++ 26 files changed, 346 insertions(+), 16 deletions(-) create mode 100644 arch/powerpc/dts/p1010rdb-pa.dts create mode 100644 arch/powerpc/dts/p1010rdb-pa_36b.dts create mode 100644 arch/powerpc/dts/p1010rdb-pb.dts create mode 100644 arch/powerpc/dts/p1010rdb-pb_36b.dts create mode 100644 arch/powerpc/dts/p1010rdb_32b.dtsi create mode 100644 arch/powerpc/dts/p1010rdb_36b.dtsi create mode 100644 arch/powerpc/dts/p1010si-post.dtsi create mode 100644 arch/powerpc/dts/p1010si-pre.dtsi create mode 100644 p1010rdb-pb.dts diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 3195351c9c..7eb005f450 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb +dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb +dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts new file mode 100644 index 0000000000..c66c4923ac --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pa.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB"; + compatible = "fsl,P1010RDB"; + + /include/ "p1010rdb_32b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts new file mode 100644 index 0000000000..b943de7cbb --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB"; + compatible = "fsl,P1010RDB"; + + /include/ "p1010rdb_36b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pb.dts b/arch/powerpc/dts/p1010rdb-pb.dts new file mode 100644 index 0000000000..2675d5d92b --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB-PB"; + compatible = "fsl,P1010RDB-PB"; + + /include/ "p1010rdb_32b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pb_36b.dts b/arch/powerpc/dts/p1010rdb-pb_36b.dts new file mode 100644 index 0000000000..45ccf91c41 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pb_36b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB-PB"; + compatible = "fsl,P1010RDB-PB"; + + /include/ "p1010rdb_36b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb_32b.dtsi b/arch/powerpc/dts/p1010rdb_32b.dtsi new file mode 100644 index 0000000000..5da790da5e --- /dev/null +++ b/arch/powerpc/dts/p1010rdb_32b.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +soc: soc at ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; +}; + +pci1: pcie at ffe09000 { + reg = <0 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +}; + +pci0: pcie at ffe0a000 { + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +}; diff --git a/arch/powerpc/dts/p1010rdb_36b.dtsi b/arch/powerpc/dts/p1010rdb_36b.dtsi new file mode 100644 index 0000000000..54dd16e43b --- /dev/null +++ b/arch/powerpc/dts/p1010rdb_36b.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +soc: soc at fffe00000 { + ranges = <0x0 0xf 0xffe00000 0x100000>; +}; + +pci1: pcie at fffe09000 { + reg = <0xf 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +}; + +pci0: pcie at fffe0a000 { + reg = <0xf 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +}; diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi new file mode 100644 index 0000000000..e24b5e4063 --- /dev/null +++ b/arch/powerpc/dts/p1010si-post.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2020 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p1010-immr", "simple-bus"; + bus-frequency = <0>; + + mpic: pic at 40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; + +/* controller at 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* controller at 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p1010si-pre.dtsi b/arch/powerpc/dts/p1010si-pre.dtsi new file mode 100644 index 0000000000..9d7bb6c95d --- /dev/null +++ b/arch/powerpc/dts/p1010si-pre.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2020 NXP + */ + +/dts-v1/; + +/include/ "e500v2_power_isa.dtsi" + +/ { + compatible = "fsl,P1010"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,P1010 at 0 { + device_type = "cpu"; + reg = <0x0>; + }; + }; +}; diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 85b97d1e15..b0dd5f8f7e 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" @@ -76,6 +78,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index e1109637c1..93042f8cc8 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -57,6 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 4b8ddd997c..657b10033b 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -70,6 +72,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 2975f404fc..396921722d 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -72,6 +74,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 632ecd7af5..b080bb726b 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y @@ -75,6 +77,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 037fe0ab89..a5296a53a5 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -56,6 +59,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 48a1d34cc9..1df83cefe3 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -69,6 +71,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index f43c60011c..6bff366f81 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -71,6 +73,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index dd7d689163..abf8882f21 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" @@ -76,6 +78,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 7e8c150603..beb8f098c4 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -57,6 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 7996490e93..7244dacec0 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -70,6 +72,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 4291002d34..1d40aa054b 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -72,6 +74,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 4a216dd55b..0d9df36ea1 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y @@ -75,6 +77,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 2cc52ed76d..653c89bfdd 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -56,6 +59,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index d90cc8e7bb..7bc05e57ba 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -69,6 +71,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index e6833d43e3..16976e4a88 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -71,6 +73,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/p1010rdb-pb.dts b/p1010rdb-pb.dts new file mode 100644 index 0000000000..7e9a6e17d8 --- /dev/null +++ b/p1010rdb-pb.dts @@ -0,0 +1,123 @@ +/dts-v1/; + +/ { + compatible = "fsl,P1010RDB-PB"; + #address-cells = <0x2>; + #size-cells = <0x2>; + interrupt-parent = <0x1>; + model = "fsl,P1010RDB-PB"; + + cpus { + power-isa-version = "2.03"; + power-isa-b; + power-isa-e; + power-isa-atb; + power-isa-cs; + power-isa-e.le; + power-isa-e.pm; + power-isa-ecl; + power-isa-mmc; + power-isa-sp; + power-isa-sp.fd; + power-isa-sp.fs; + power-isa-sp.fv; + mmu-type = "power-embedded"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + PowerPC,P1010 at 0 { + device_type = "cpu"; + reg = <0x0>; + }; + }; + + soc at ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + device_type = "soc"; + compatible = "fsl,p1010-immr", "simple-bus"; + bus-frequency = <0x0>; + + pic at 40000 { + interrupt-controller; + #address-cells = <0x0>; + #interrupt-cells = <0x4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <0xff>; + phandle = <0x1>; + }; + + i2c at 3000 { + #address-cells = <0x1>; + #size-cells = <0x0>; + cell-index = <0x0>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x3000 0x100>; + interrupts = <0x2b 0x2 0x0 0x0>; + + rtc at 68 { + compatible = "pericom,pt7c4338"; + reg = <0x68>; + }; + }; + + i2c at 3100 { + #address-cells = <0x1>; + #size-cells = <0x0>; + cell-index = <0x1>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x3100 0x100>; + interrupts = <0x2b 0x2 0x0 0x0>; + }; + }; + + pcie at ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; + ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000 0x1000000 0x0 0x0 0x0 0xffc10000 0x0 0x10000>; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <0x1>; + #address-cells = <0x3>; + #size-cells = <0x2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + }; + + pcie at ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0x0 0xffc00000 0x0 0x10000>; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <0x2>; + #address-cells = <0x3>; + #size-cells = <0x2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + }; + + binman { + filename = "u-boot-with-dtb.bin"; + skip-at-start = <0xeff40000>; + sort-by-offset; + pad-byte = <0xff>; + size = <0xc0000>; + + u-boot-with-ucode-ptr { + offset = <0xeff40000>; + optional-ucode; + }; + + u-boot-dtb-with-ucode { + align = <0x100>; + }; + + powerpc-mpc85xx-bootpg-resetvec { + offset = <0xeffff000>; + }; + }; +}; From patchwork Fri May 1 08:28:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Biwen Li \(OSS\)" X-Patchwork-Id: 244691 List-Id: U-Boot discussion From: biwen.li at oss.nxp.com (Biwen Li) Date: Fri, 1 May 2020 16:28:12 +0800 Subject: [RESEND 2/4] powerpc: P1010RDB: Compile legacy PCIe routines conditionally In-Reply-To: <20200501082814.45691-1-biwen.li@oss.nxp.com> References: <20200501082814.45691-1-biwen.li@oss.nxp.com> Message-ID: <20200501082814.45691-2-biwen.li@oss.nxp.com> From: Hou Zhiqiang Compile the legacy PCIe initialization reoutines for P1010RDB boards only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang --- board/freescale/p1010rdb/p1010rdb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index f49e679d01..11165d79c5 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -125,7 +125,7 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -612,7 +612,7 @@ int ft_board_setup(void *blob, bd_t *bd) base = env_get_bootm_low(); size = env_get_bootm_size(); -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) FT_FSL_PCI_SETUP; #endif From patchwork Fri May 1 08:28:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Biwen Li \(OSS\)" X-Patchwork-Id: 244693 List-Id: U-Boot discussion From: biwen.li at oss.nxp.com (Biwen Li) Date: Fri, 1 May 2020 16:28:13 +0800 Subject: [RESEND 3/4] powerpc: P1010RDB: Disable legacy PCIe driver when DM_PCI is enabled In-Reply-To: <20200501082814.45691-1-biwen.li@oss.nxp.com> References: <20200501082814.45691-1-biwen.li@oss.nxp.com> Message-ID: <20200501082814.45691-3-biwen.li@oss.nxp.com> From: Hou Zhiqiang Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled for P1010RDB board. Signed-off-by: Hou Zhiqiang --- include/configs/P1010RDB.h | 42 +++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 41dbbedecc..ce48ae1ef9 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -114,8 +114,6 @@ #if defined(CONFIG_PCI) #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* @@ -123,19 +121,13 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else @@ -143,27 +135,45 @@ #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ +#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + #if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" #elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" #endif -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ From patchwork Fri May 1 08:28:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Biwen Li \(OSS\)" X-Patchwork-Id: 244694 List-Id: U-Boot discussion From: biwen.li at oss.nxp.com (Biwen Li) Date: Fri, 1 May 2020 16:28:14 +0800 Subject: [RESEND 4/4] configs: P1010RDB: Enable PCIe driver In-Reply-To: <20200501082814.45691-1-biwen.li@oss.nxp.com> References: <20200501082814.45691-1-biwen.li@oss.nxp.com> Message-ID: <20200501082814.45691-4-biwen.li@oss.nxp.com> From: Hou Zhiqiang Enable the DM PCIe driver in P1010RDB defconfigs. Signed-off-by: Hou Zhiqiang --- configs/P1010RDB-PA_36BIT_NAND_defconfig | 4 ++++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 4 ++++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 4 ++++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 4 ++++ configs/P1010RDB-PA_NAND_defconfig | 4 ++++ configs/P1010RDB-PA_NOR_defconfig | 4 ++++ configs/P1010RDB-PA_SDCARD_defconfig | 4 ++++ configs/P1010RDB-PA_SPIFLASH_defconfig | 4 ++++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 4 ++++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 4 ++++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 4 ++++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 4 ++++ configs/P1010RDB-PB_NAND_defconfig | 4 ++++ configs/P1010RDB-PB_NOR_defconfig | 4 ++++ configs/P1010RDB-PB_SDCARD_defconfig | 4 ++++ configs/P1010RDB-PB_SPIFLASH_defconfig | 4 ++++ 16 files changed, 64 insertions(+) diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index b0dd5f8f7e..5280a1d070 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -71,6 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 93042f8cc8..b83e99f8f7 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -53,6 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 657b10033b..a1b08b17f9 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -65,6 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 396921722d..2b336f4a92 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -67,6 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index b080bb726b..6062fd8d0f 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -70,6 +70,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index a5296a53a5..4ee53e85f7 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -52,6 +52,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 1df83cefe3..f4e89592b8 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -64,6 +64,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 6bff366f81..6d4175e2d1 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -66,6 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index abf8882f21..123c044cf7 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -71,6 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index beb8f098c4..1e149f965d 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -53,6 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 7244dacec0..aeb7e16467 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -65,6 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 1d40aa054b..7b6aaf64cb 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -67,6 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 0d9df36ea1..37346087ce 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -70,6 +70,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 653c89bfdd..1df2f4c46d 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -52,6 +52,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 7bc05e57ba..d373cd2890 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -64,6 +64,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 16976e4a88..88fc5fe5ae 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -66,6 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y