From patchwork Tue Mar 31 00:48:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244615 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:38 +0200 Subject: [PATCH V2 01/14] ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96 In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-2-marex@denx.de> The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{}; became pins1{};pins2{};, however the SPL extras were not updated to reflect that change. Fix this. This fixes booting from SD1 X9 slot on the AV96 board. Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- V2: Adjust patch subject --- arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index d6dc746365..8dcd8866e8 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -152,7 +152,10 @@ &sdmmc1_dir_pins_a { u-boot,dm-spl; - pins { + pins1 { + u-boot,dm-spl; + }; + pins2 { u-boot,dm-spl; }; }; From patchwork Tue Mar 31 00:48:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244619 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:39 +0200 Subject: [PATCH V2 02/14] ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pins In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-3-marex@denx.de> Add another mux option for SDMMC1 direction pins, in particular SDMMC1_D123DIR, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- V2: New patch --- arch/arm/dts/stm32mp157-pinctrl.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 81a363d93d..6842d4cdca 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -832,6 +832,30 @@ }; }; + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = , /* SDMMC2_D0 */ From patchwork Tue Mar 31 00:48:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244616 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:40 +0200 Subject: [PATCH V2 03/14] ARM: dts: stm32: Repair SDMMC1 operation on AV96 In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-4-marex@denx.de> The SD uses different pinmux for the D123DIRline, use such a pinmux, otherwise there is a pinmux collision on the AV96. Add missing SD voltage regulator switch and enable SDR104 operation. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- V2: New patch --- .../arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 2 +- arch/arm/dts/stm32mp157a-avenger96.dts | 25 ++++++++++++++++--- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 8dcd8866e8..47bfbb8d77 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -150,7 +150,7 @@ }; }; -&sdmmc1_dir_pins_a { +&sdmmc1_dir_pins_b { u-boot,dm-spl; pins1 { u-boot,dm-spl; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3065593bf2..1e9b45b69d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -76,6 +76,20 @@ default-state = "off"; }; }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; }; ðernet0 { @@ -296,15 +310,18 @@ &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; + disable-wp; st,sig-dir; st,neg-edge; st,use-ckin; + sd-uhs-sdr104; bus-width = <4>; vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; status = "okay"; }; From patchwork Tue Mar 31 00:48:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244617 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:41 +0200 Subject: [PATCH V2 04/14] ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7 In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-5-marex@denx.de> Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- V2: Use correct pin AFs --- arch/arm/dts/stm32mp157-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 6842d4cdca..964e4910ec 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -931,6 +931,27 @@ }; }; + sdmmc2_d47_pins_b: sdmmc2-d47-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = ; /* SPDIF_IN1 */ From patchwork Tue Mar 31 00:48:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244618 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:42 +0200 Subject: [PATCH V2 05/14] ARM: dts: stm32: Repair SDMMC2 operation In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-6-marex@denx.de> The eMMC uses different pinmux for the top four data lines, use such a pinmux, otherwise it takes a very long time until the test for 8bit operation times out. And this is the correct pinmux per schematic too. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay Reviewed-by: Patrick Delaunay --- V2: Update also the -u-boot.dtsi to match this change --- arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 2 +- arch/arm/dts/stm32mp157a-avenger96.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 47bfbb8d77..2c7dc509a3 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -174,7 +174,7 @@ }; }; -&sdmmc2_d47_pins_a { +&sdmmc2_d47_pins_b { u-boot,dm-spl; pins { u-boot,dm-spl; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 1e9b45b69d..3fca1ed56d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -327,7 +327,7 @@ &sdmmc2 { pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; non-removable; no-sd; no-sdio; From patchwork Tue Mar 31 00:48:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244620 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:43 +0200 Subject: [PATCH V2 06/14] ARM: dts: stm32: Add QSPI NOR on AV96 In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-7-marex@denx.de> The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard --- V2: Drop the explicit flash type in DT node, use spi-flash --- arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3fca1ed56d..512ef5f7bb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -20,6 +20,7 @@ mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7; + spi0 = &qspi; }; chosen { @@ -300,6 +301,25 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; }; +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash at 0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + &rng1 { status = "okay"; }; From patchwork Tue Mar 31 00:48:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244626 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:44 +0200 Subject: [PATCH V2 07/14] ARM: dts: stm32: Use DT alias for the configuration EEPROM In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-8-marex@denx.de> Use DT /aliases node to establish a stable phandle to the configuration EEPROM. This permits the configuration EEPROM to be moved e.g. to a different address or a different bus. Adjust the board code to handle new phandle lookup. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- V2: No change --- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 6 +++++- board/dhelectronics/dh_stm32mp1/board.c | 15 +++++++-------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index bed69c97b6..e5be0a79ac 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -10,6 +10,10 @@ #include / { + aliases { + eeprom0 = &eeprom0; + }; + memory at c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>; @@ -187,7 +191,7 @@ }; }; - eeprom at 50 { + eeprom0: eeprom at 50 { compatible = "atmel,24c02"; reg = <0x50>; pagesize = <16>; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 109d9ec935..a3458a2623 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -78,22 +78,21 @@ DECLARE_GLOBAL_DATA_PTR; int setup_mac_address(void) { - struct udevice *dev; - ofnode eeprom; unsigned char enetaddr[6]; - int ret; + struct udevice *dev; + int off, ret; ret = eth_env_get_enetaddr("ethaddr", enetaddr); if (ret) /* ethaddr is already set */ return 0; - eeprom = ofnode_path("/soc/i2c at 5c002000/eeprom at 50"); - if (!ofnode_valid(eeprom)) { - printf("Invalid hardware path to EEPROM!\n"); - return -ENODEV; + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); + if (off < 0) { + printf("%s: No eeprom0 path offset\n", __func__); + return off; } - ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); if (ret) { printf("Cannot find EEPROM!\n"); return ret; From patchwork Tue Mar 31 00:48:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244625 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:45 +0200 Subject: [PATCH V2 08/14] ARM: dts: stm32: Add configuration EEPROM on AV96 In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-9-marex@denx.de> The board has an EEPROM on the same I2C bus as PMIC, at address 0x53. The EEPROM contains the board MAC address. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- V2: No change --- arch/arm/dts/stm32mp157a-avenger96.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 512ef5f7bb..bcd5827258 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -289,6 +289,12 @@ status = "disabled"; }; }; + + eeprom at 53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; &iwdg2 { From patchwork Tue Mar 31 00:48:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244621 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:46 +0200 Subject: [PATCH V2 09/14] ARM: dts: stm32: Add alternate pinmux for ethernet RGMII In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-10-marex@denx.de> Add another mux option for DWMAC RGMII, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- V2: No change --- arch/arm/dts/stm32mp157-pinctrl.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 964e4910ec..422dad1ddd 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -288,6 +288,57 @@ }; }; + ethernet0_rgmii_pins_b: rgmii-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ From patchwork Tue Mar 31 00:48:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244627 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:47 +0200 Subject: [PATCH V2 10/14] ARM: dts: stm32: Repair ethernet operation on AV96 In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-11-marex@denx.de> The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2 and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- V2: No change --- arch/arm/dts/stm32mp157a-avenger96.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index bcd5827258..fb8f0021b3 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -95,8 +95,8 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii"; max-speed = <1000>; From patchwork Tue Mar 31 00:48:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244622 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:48 +0200 Subject: [PATCH V2 11/14] ARM: dts: stm32: Add missing ethernet PHY reset on AV96 In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-12-marex@denx.de> Add PHY reset GPIO on AV96 ethernet PHY. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard --- V2: No change --- arch/arm/dts/stm32mp157a-avenger96.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index fb8f0021b3..7a4b6e6a2c 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -101,6 +101,7 @@ phy-mode = "rgmii"; max-speed = <1000>; phy-handle = <&phy0>; + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; mdio0 { #address-cells = <1>; From patchwork Tue Mar 31 00:48:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244623 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:49 +0200 Subject: [PATCH V2 12/14] ARM: dts: stm32: Repair PMIC configuration on AV96 In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-13-marex@denx.de> The core and vdd PMIC buck regulators were misconfigured, which caused instability of the board and malfunction of high-speed interfaces, like the RGMII. Configure the PMIC correctly to repair these problems. Also, model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard --- V2: - Model the Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator - Adjust the PMIC voltages further --- arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 7a4b6e6a2c..4fa20bc31d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -91,6 +91,17 @@ states = <1800000 0x1>, <2900000 0x0>; }; + + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; }; ðernet0 { @@ -167,7 +178,7 @@ vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; @@ -185,8 +196,8 @@ vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; regulator-always-on; st,mask_reset; regulator-initial-mode = <0>; @@ -268,6 +279,7 @@ regulator-name = "vbus_otg"; interrupts = ; interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { @@ -304,7 +316,7 @@ }; &pwr_regulators { - vdd-supply = <&vdd>; + vdd-supply = <&vdd_io>; vdd_3v3_usbfs-supply = <&vdd_usb>; }; From patchwork Tue Mar 31 00:48:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244624 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:50 +0200 Subject: [PATCH V2 13/14] ARM: dts: stm32: Adjust PLL4 settings on AV96 In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-14-marex@denx.de> The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which can not easily divide the clock down to e.g. 50 MHz for high speed SD and eMMC devices, so those devices end up running at 30 MHz as that is 120 MHz / 4. Adjust the PLL4 settings such that both PLL4P and PLL4R run at 100 MHz instead, which is easy to divide to 50MHz for optimal operation of both SD and eMMC, SPDIF clock are not that much slower and FDCAN is also unaffected. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- V2: Move this patch before the split of AV96 into SoM and carrier --- arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 2c7dc509a3..320132a01e 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -130,11 +130,11 @@ u-boot,dm-pre-reloc; }; - /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ + /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */ pll4: st,pll at 3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 1 39 3 11 4 PQR(1,1,1) >; + cfg = < 1 49 5 11 5 PQR(1,1,1) >; u-boot,dm-pre-reloc; }; }; From patchwork Tue Mar 31 00:48:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244628 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 31 Mar 2020 02:48:51 +0200 Subject: [PATCH V2 14/14] ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board In-Reply-To: <20200331004851.282583-1-marex@denx.de> References: <20200331004851.282583-1-marex@denx.de> Message-ID: <20200331004851.282583-15-marex@denx.de> The AV96 is in fact an assembly of DH Electronics DHCOR SoM on top of an AV96 reference board. Split the DTs to reflect that and make sure to DHCOR SoM can be reused on other boards easily. It is also highly recommended to configure the board for the DHCOM make stm32mp15_dhcom_basic_defconfig make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 as that permits reusing the board code for the DH components, like accessing and reading out the ethernet MAC from EEPROM. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard --- V2: No change --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32mp157a-avenger96.dts | 421 +----------------- .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 80 ++++ arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 211 +++++++++ ...oot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} | 79 +--- arch/arm/dts/stm32mp15xx-dhcor.dtsi | 231 ++++++++++ doc/board/st/stm32mp1.rst | 8 +- 7 files changed, 535 insertions(+), 498 deletions(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts rename arch/arm/dts/{stm32mp157a-avenger96-u-boot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} (75%) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c593b2c98..2564f790de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -884,7 +884,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \ - stm32mp15xx-dhcom-pdk2.dtb + stm32mp15xx-dhcom-pdk2.dtb \ + stm32mp15xx-dhcor-avenger96.dtb dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 4fa20bc31d..9c165104fb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -4,422 +4,5 @@ * Author: Manivannan Sadhasivam */ -/dts-v1/; - -#include "stm32mp157c.dtsi" -#include "stm32mp157xac-pinctrl.dtsi" -#include -#include - -/ { - model = "Arrow Electronics STM32MP157A Avenger96 board"; - compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - spi0 = &qspi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory at c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x40000000>; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "green:user1"; - gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user2"; - gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user3"; - gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user3"; - gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - - led5 { - label = "yellow:wifi"; - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led6 { - label = "blue:bt"; - gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; - - /* Enpirion EP3A8LQI U2 on the DHCOR */ - vdd_io: regulator-buck-io { - compatible = "regulator-fixed"; - regulator-name = "buck-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd>; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_b>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy at 7 { - reg = <7>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic at 33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - st,main-control-register = <0x04>; - st,vin-control-register = <0xc0>; - st,usb-control-register = <0x30>; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - st,mask_reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-enable-ramp-delay = <300000>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-active-discharge = <1>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; - - eeprom at 53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd_io>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: spi-flash at 0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - sd-uhs-sdr104; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; -}; - -&uart4 { - /* On Low speed expansion header */ - label = "LS-UART1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - status = "okay"; -}; - -&uart7 { - /* On Low speed expansion header */ - label = "LS-UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; +/* This is kept for backward compatibility and will be removed */ +#include "stm32mp15xx-dhcor-avenger96.dts" diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi new file mode 100644 index 0000000000..4207a96618 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + */ + +#include "stm32mp15xx-dhcor-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + usb0 = &usbotg_hs; + }; + + config { + u-boot,boot-led = "led1"; + u-boot,error-led = "led4"; + }; +}; + +&sdmmc1 { + u-boot,dm-spl; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc1_dir_pins_b { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2 { + u-boot,dm-spl; +}; + +&sdmmc2_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2_d47_pins_b { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_b { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; +}; + +&usbotg_hs { + u-boot,force-b-session-valid; + hnp-srp-disable; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts new file mode 100644 index 0000000000..9d859e1d09 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +/dts-v1/; + +#include "stm32mp15xx-dhcor.dtsi" +#include "stm32mp15xx-dhcor-avenger96-u-boot.dtsi" + +/ { + model = "Arrow Electronics STM32MP15xx Avenger96 board"; + compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x"; + + aliases { + eeprom0 = &eeprom0; + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "green:user1"; + gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user3"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led5 { + label = "yellow:wifi"; + gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led6 { + label = "blue:bt"; + gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy at 7 { + reg = <7>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + eeprom0: eeprom at 53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + status = "okay"; +}; + +&uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi similarity index 75% rename from arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi rename to arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 320132a01e..02dad81b0b 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -4,25 +4,13 @@ * * Copyright (C) Linaro Ltd 2019 - All Rights Reserved * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut */ #include #include "stm32mp157-u-boot.dtsi" #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" -/ { - aliases { - mmc0 = &sdmmc1; - mmc1 = &sdmmc2; - usb0 = &usbotg_hs; - }; - - config { - u-boot,boot-led = "led1"; - u-boot,error-led = "led4"; - }; -}; - &i2c4 { u-boot,dm-pre-reloc; }; @@ -38,6 +26,10 @@ u-boot,dm-pre-reloc; }; +&qspi { + u-boot,dm-spl; +}; + &rcc { st,clksrc = < CLK_MPU_PLL1P @@ -139,67 +131,6 @@ }; }; -&sdmmc1 { - u-boot,dm-spl; -}; - -&sdmmc1_b4_pins_a { - u-boot,dm-spl; - pins { - u-boot,dm-spl; - }; -}; - -&sdmmc1_dir_pins_b { - u-boot,dm-spl; - pins1 { - u-boot,dm-spl; - }; - pins2 { - u-boot,dm-spl; - }; -}; - -&sdmmc2 { - u-boot,dm-spl; -}; - -&sdmmc2_b4_pins_a { - u-boot,dm-spl; - pins1 { - u-boot,dm-spl; - }; - pins2 { - u-boot,dm-spl; - }; -}; - -&sdmmc2_d47_pins_b { - u-boot,dm-spl; - pins { - u-boot,dm-spl; - }; -}; - -&uart4 { - u-boot,dm-pre-reloc; -}; - -&uart4_pins_b { - u-boot,dm-pre-reloc; - pins1 { - u-boot,dm-pre-reloc; - }; - pins2 { - u-boot,dm-pre-reloc; - }; -}; - -&usbotg_hs { - u-boot,force-b-session-valid; - hnp-srp-disable; -}; - &v3v3 { regulator-always-on; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor.dtsi b/arch/arm/dts/stm32mp15xx-dhcor.dtsi new file mode 100644 index 0000000000..9d4e92ebb1 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; + +#include "stm32mp157c.dtsi" +#include "stm32mp157xac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + spi0 = &qspi; + }; + + memory at c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x40000000>; + }; + + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic at 33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + st,main-control-register = <0x04>; + st,vin-control-register = <0xc0>; + st,usb-control-register = <0x30>; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + st,mask_reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + interrupt-parent = <&pmic>; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + interrupt-parent = <&pmic>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + interrupt-parent = <&pmic>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + interrupt-parent = <&pmic>; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + interrupt-parent = <&pmic>; + regulator-enable-ramp-delay = <300000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + interrupt-parent = <&pmic>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd_io>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash at 0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 1640bf910e..73195134f1 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -43,11 +43,11 @@ And the necessary drivers Currently the following boards are supported: - + stm32mp157a-avenger96.dts + stm32mp157a-dk1.dts + stm32mp157c-dk2.dts + stm32mp157c-ed1.dts + stm32mp157c-ev1.dts + + stm32mp15xx-dhcor-avenger96.dts Boot Sequences -------------- @@ -145,9 +145,9 @@ the supported device trees for STM32MP15x are: + stm32mp157c-dk2 -+ avenger96: Avenger96 board from Arrow Electronics ++ avenger96: Avenger96 board from Arrow Electronics based on DH Elec. DHCOR SoM - + stm32mp157a-avenger96 + + stm32mp15xx-dhcor-avenger96 Build Procedure --------------- @@ -229,7 +229,7 @@ Build Procedure # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig - # make DEVICE_TREE=stm32mp157a-avenger96 all + # make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 all 6. Output files