From patchwork Sat Mar 21 16:10:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244047 List-Id: U-Boot discussion From: marek.vasut at gmail.com (Marek Vasut) Date: Sat, 21 Mar 2020 17:10:47 +0100 Subject: [PATCH 1/3] ARM: dts: rmobile: Add IIC3 node on Gen2 R8A7792 V2H Message-ID: <20200321161049.64558-1-marek.vasut+renesas@gmail.com> Add IIC3 node from mainline Linux DT. This will be further updated in subsequent DT sync, however adding this node for now is sufficient and minimal change. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/r8a7792.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi index 8e9eb4b704..6fd80e3541 100644 --- a/arch/arm/dts/r8a7792.dtsi +++ b/arch/arm/dts/r8a7792.dtsi @@ -444,6 +444,23 @@ status = "disabled"; }; + iic3: i2c at e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7792", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + dmac0: dma-controller at e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; From patchwork Sat Mar 21 16:10:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244048 List-Id: U-Boot discussion From: marek.vasut at gmail.com (Marek Vasut) Date: Sat, 21 Mar 2020 17:10:48 +0100 Subject: [PATCH 2/3] ARM: dts: rmobile: Enable IIC3 on V2H Blanche In-Reply-To: <20200321161049.64558-1-marek.vasut+renesas@gmail.com> References: <20200321161049.64558-1-marek.vasut+renesas@gmail.com> Message-ID: <20200321161049.64558-2-marek.vasut+renesas@gmail.com> Enable IIC3 to permit access to the PMIC. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/r8a7792-blanche-u-boot.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/r8a7792-blanche-u-boot.dts b/arch/arm/dts/r8a7792-blanche-u-boot.dts index 3555663d64..30b27040f5 100644 --- a/arch/arm/dts/r8a7792-blanche-u-boot.dts +++ b/arch/arm/dts/r8a7792-blanche-u-boot.dts @@ -8,6 +8,10 @@ #include "r8a7792-blanche.dts" #include "r8a7792-u-boot.dtsi" +&iic3 { + status = "okay"; +}; + &scif0 { u-boot,dm-pre-reloc; }; From patchwork Sat Mar 21 16:10:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 244049 List-Id: U-Boot discussion From: marek.vasut at gmail.com (Marek Vasut) Date: Sat, 21 Mar 2020 17:10:49 +0100 Subject: [PATCH 3/3] ARM: rmobile: Implement PMIC reset on V2H Blanche In-Reply-To: <20200321161049.64558-1-marek.vasut+renesas@gmail.com> References: <20200321161049.64558-1-marek.vasut+renesas@gmail.com> Message-ID: <20200321161049.64558-3-marek.vasut+renesas@gmail.com> Add code to reset the board through PMIC, by writing the required PMIC registers in the CPU reset handler. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- board/renesas/blanche/blanche.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c index 7232370d6f..0807967d6e 100644 --- a/board/renesas/blanche/blanche.c +++ b/board/renesas/blanche/blanche.c @@ -355,4 +355,23 @@ int dram_init_banksize(void) void reset_cpu(ulong addr) { + struct udevice *dev; + const u8 pmic_bus = 6; + const u8 pmic_addr = 0x58; + u8 data; + int ret; + + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); + + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); + + data |= BIT(1); + + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); }