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[209.132.180.67]) by mx.google.com with ESMTP id b5si624962pgc.623.2017.10.06.00.14.21; Fri, 06 Oct 2017 00:14:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=abHYs3Vn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751744AbdJFHOT (ORCPT + 26 others); Fri, 6 Oct 2017 03:14:19 -0400 Received: from mail-wm0-f41.google.com ([74.125.82.41]:46012 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751474AbdJFHOR (ORCPT ); Fri, 6 Oct 2017 03:14:17 -0400 Received: by mail-wm0-f41.google.com with SMTP id q124so5825583wmb.0 for ; Fri, 06 Oct 2017 00:14:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=L+aEOgvH3gtAeS2VEmN/hK0koS8CCa1rHEVfcp59YXU=; b=abHYs3VnHJDCk+JuQ27oKbiNZgOdZtvPN27YzMywLoLslCKn24g0tGcxfyRUHixVJn sLW6bo5rlmlypIZfODMhXGQASxFNoygprxuBpdX9dK5tcSJGjyJgkvbJeSzARN5/Q7jS eFY169QW6Y0+URo5Oc+jO4oye/dyWFhja9omg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=L+aEOgvH3gtAeS2VEmN/hK0koS8CCa1rHEVfcp59YXU=; b=Bd89eRGZBd2kuDzr2Q3BPdiwB6HjD9bPl3rW8Y5eIUYeNjetyMC24h5FD9ZFAzo1Gq 6nA/5PIKBBxYAvDSpfKlYb1WSFRYdUlEASg2E0eYE/EUmH79ah1/smzsKXJuaklCDXSf 4scrhtkr6/ypCqQ0MvoWqP1MsOBT13qWQkmaBxF7jErxynPdWWKNSdGwGB9dRCCCyXRx QCxxjB9ZoI7ciVTgWxPXOePQg5rM/l7vfUhuFCZ6VZ+dEkxIlKQZNhhKQwsCK0Rky95h XGbRnjbTNdznp4lBM4BsUEUzDvYbhCAk07zUOR0uLM/5lyn0h8eFoAE/TscWJZZepvp7 YGIg== X-Gm-Message-State: AMCzsaWHMJzo8gzsXkFkw0S/DEBiLHzkJaz6ogPIAFbsdWPJgQBHov1B VXmzeNazMwl2lyfdRtDfddB9tA== X-Google-Smtp-Source: AOwi7QANj3aiOdcFireI01ptPCfCQT1YHVOI6qbW/aY+eb4ywjG2stp1AjrhKmQLuIJt2NvhHDyRSA== X-Received: by 10.28.9.130 with SMTP id 124mr724622wmj.65.1507274056445; Fri, 06 Oct 2017 00:14:16 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.98.52]) by smtp.gmail.com with ESMTPSA id i16sm1548919wrf.19.2017.10.06.00.14.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 Oct 2017 00:14:15 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard , Benjamin Gaignard Subject: [PATCH v2] ARM: dts: stm32: add Timers driver for stm32f746 MCU Date: Fri, 6 Oct 2017 09:14:10 +0200 Message-Id: <1507274050-14510-1-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Timers and it sub-nodes into DT for stm32f746 family. Signed-off-by: Benjamin Gaignard --- version 2: - without ltdc node arch/arm/boot/dts/stm32f746.dtsi | 260 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 260 insertions(+) -- 2.7.4 diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 4506eb9..d0deee2 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -82,6 +82,27 @@ status = "disabled"; }; + timers2: timers@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + }; + timer3: timer@40000400 { compatible = "st,stm32-timer"; reg = <0x40000400 0x400>; @@ -90,6 +111,27 @@ status = "disabled"; }; + timers3: timers@40000400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + timer4: timer@40000800 { compatible = "st,stm32-timer"; reg = <0x40000800 0x400>; @@ -98,6 +140,27 @@ status = "disabled"; }; + timers4: timers@40000800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,6 +168,27 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; + timers5: timers@40000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + }; + timer6: timer@40001000 { compatible = "st,stm32-timer"; reg = <0x40001000 0x400>; @@ -113,6 +197,22 @@ status = "disabled"; }; + timers6: timers@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; + clock-names = "int"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + timer7: timer@40001400 { compatible = "st,stm32-timer"; reg = <0x40001400 0x400>; @@ -121,6 +221,73 @@ status = "disabled"; }; + timers7: timers@40001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; + clock-names = "int"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + timers12: timers@40001800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timers@40001c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers14: timers@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; @@ -183,6 +350,48 @@ status = "disabled"; }; + timers1: timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + }; + + timers8: timers@40010400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + }; + usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; @@ -212,6 +421,57 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; }; + timers9: timers@40014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@8 { + compatible = "st,stm32-timer-trigger"; + reg = <8>; + status = "disabled"; + }; + }; + + timers10: timers@40014400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers11: timers@40014800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014800 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>;