From patchwork Fri Mar 6 16:24:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe REYNES X-Patchwork-Id: 243305 List-Id: U-Boot discussion From: philippe.reynes at softathome.com (Philippe Reynes) Date: Fri, 6 Mar 2020 17:24:56 +0100 Subject: [PATCH 1/6] bcm6750: add initial support Message-ID: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> This add the initial support of the broadcom bcm6750 SoC family. Signed-off-by: Philippe Reynes --- arch/arm/Kconfig | 7 ++ arch/arm/dts/bcm6750.dtsi | 193 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 200 insertions(+) create mode 100644 arch/arm/dts/bcm6750.dtsi diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8d9f7fc..568b95a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -633,6 +633,13 @@ config ARCH_BCM63158 select OF_CONTROL imply CMD_DM +config ARCH_BCM6750 + bool "Broadcom BCM6750 family" + select CPU_V7A + select DM + select OF_CONTROL + imply CMD_DM + config ARCH_BCM68360 bool "Broadcom BCM68360 family" select DM diff --git a/arch/arm/dts/bcm6750.dtsi b/arch/arm/dts/bcm6750.dtsi new file mode 100644 index 0000000..108a8b3 --- /dev/null +++ b/arch/arm/dts/bcm6750.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes + */ + +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6750"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu0: cpu at 0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu1: cpu at 1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x1>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu2: cpu at 2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x2>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + l2: l2-cache0 { + compatible = "cache"; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + u-boot,dm-pre-reloc; + }; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + uart0: serial at ff812000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xff812000 0x1000>; + clock = <50000000>; + + status = "disabled"; + }; + + wdt1: watchdog at ff800480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0xff800480 0x14>; + clocks = <&refclk50mhz>; + }; + + wdt2: watchdog at ff8004c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0xff8004c0 0x14>; + clocks = <&refclk50mhz>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; + + gpio0: gpio-controller at 0xff800500 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xff800500 0x4>, + <0xff800520 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio1: gpio-controller at 0xff800504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xff800504 0x4>, + <0xff800524 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio2: gpio-controller at 0xff800508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xff800508 0x4>, + <0xff800528 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio3: gpio-controller at 0xff80050c { + compatible = "brcm,bcm6345-gpio"; + reg = <0xff80050c 0x4>, + <0xff80052c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio4: gpio-controller at 0xff800510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xff800510 0x4>, + <0xff800530 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio5: gpio-controller at 0xff800514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xff800514 0x4>, + <0xff800534 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio6: gpio-controller at 0xff800518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xff800518 0x4>, + <0xff800538 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio7: gpio-controller at 0xff80051c { + compatible = "brcm,bcm6345-gpio"; + reg = <0xff80051c 0x4>, + <0xff80053c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + nand: nand-controller at ff801800 { + compatible = "brcm,nand-bcm6750", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0xff801800 0x180>, + <0xff802000 0x10>, + <0xff801c00 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; + }; +}; From patchwork Fri Mar 6 16:24:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe REYNES X-Patchwork-Id: 243304 List-Id: U-Boot discussion From: philippe.reynes at softathome.com (Philippe Reynes) Date: Fri, 6 Mar 2020 17:24:57 +0100 Subject: [PATCH 2/6] gpio: do not include on ARCH_BCM6750 In-Reply-To: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> References: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> Message-ID: <1583511901-10930-2-git-send-email-philippe.reynes@softathome.com> As no gpio.h is defined for this architecture, to avoid compilation failure, do not include for arch bcm6750. Signed-off-by: Philippe Reynes --- arch/arm/include/asm/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 84e5cb4..cc178eb 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -5,7 +5,7 @@ !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_U8500) && \ - !defined(CONFIG_CORTINA_PLATFORM) + !defined(CONFIG_CORTINA_PLATFORM) && !defined(CONFIG_ARCH_BCM6750) #include #endif #include From patchwork Fri Mar 6 16:24:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe REYNES X-Patchwork-Id: 243307 List-Id: U-Boot discussion From: philippe.reynes at softathome.com (Philippe Reynes) Date: Fri, 6 Mar 2020 17:24:58 +0100 Subject: [PATCH 3/6] gpio: bcm6345: allow to use this driver on arm bcm6750 In-Reply-To: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> References: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> Message-ID: <1583511901-10930-3-git-send-email-philippe.reynes@softathome.com> This IP is also used on some arm SoC, so we allow to use it on arm bcm6750 too. Signed-off-by: Philippe Reynes --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f751a8b..3a595b8 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -55,7 +55,7 @@ config ALTERA_PIO config BCM6345_GPIO bool "BCM6345 GPIO driver" - depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM68360 || \ + depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM6750 || ARCH_BCM68360 || \ ARCH_BCM6858 || ARCH_BCM63158) help This driver supports the GPIO banks on BCM6345 SoCs. From patchwork Fri Mar 6 16:24:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe REYNES X-Patchwork-Id: 243309 List-Id: U-Boot discussion From: philippe.reynes at softathome.com (Philippe Reynes) Date: Fri, 6 Mar 2020 17:24:59 +0100 Subject: [PATCH 4/6] nand: brcmnand: add bcm6750 support In-Reply-To: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> References: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> Message-ID: <1583511901-10930-4-git-send-email-philippe.reynes@softathome.com> This adds the nand support for chipset bcm6750. Signed-off-by: Philippe Reynes --- drivers/mtd/nand/raw/Kconfig | 6 ++ drivers/mtd/nand/raw/brcmnand/Makefile | 1 + drivers/mtd/nand/raw/brcmnand/bcm6750_nand.c | 123 +++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 drivers/mtd/nand/raw/brcmnand/bcm6750_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 23201ca..3912337 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -78,6 +78,12 @@ config NAND_BRCMNAND_6368 help Enable support for broadcom nand driver on bcm6368. +config NAND_BRCMNAND_6750 + bool "Support Broadcom NAND controller on bcm6750" + depends on NAND_BRCMNAND && ARCH_BCM6750 + help + Enable support for broadcom nand driver on bcm6750. + config NAND_BRCMNAND_68360 bool "Support Broadcom NAND controller on bcm68360" depends on NAND_BRCMNAND && ARCH_BCM68360 diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile index 5d9e7e3..d3b7325 100644 --- a/drivers/mtd/nand/raw/brcmnand/Makefile +++ b/drivers/mtd/nand/raw/brcmnand/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o +obj-$(CONFIG_NAND_BRCMNAND_6750) += bcm6750_nand.o obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6750_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6750_nand.c new file mode 100644 index 0000000..22355fb --- /dev/null +++ b/drivers/mtd/nand/raw/brcmnand/bcm6750_nand.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "brcmnand.h" + +struct bcm6750_nand_soc { + struct brcmnand_soc soc; + void __iomem *base; +}; + +#define BCM6750_NAND_INT 0x00 +#define BCM6750_NAND_STATUS_SHIFT 0 +#define BCM6750_NAND_STATUS_MASK (0xfff << BCM6750_NAND_STATUS_SHIFT) + +#define BCM6750_NAND_INT_EN 0x04 +#define BCM6750_NAND_ENABLE_SHIFT 0 +#define BCM6750_NAND_ENABLE_MASK (0xffff << BCM6750_NAND_ENABLE_SHIFT) + +enum { + BCM6750_NP_READ = BIT(0), + BCM6750_BLOCK_ERASE = BIT(1), + BCM6750_COPY_BACK = BIT(2), + BCM6750_PAGE_PGM = BIT(3), + BCM6750_CTRL_READY = BIT(4), + BCM6750_DEV_RBPIN = BIT(5), + BCM6750_ECC_ERR_UNC = BIT(6), + BCM6750_ECC_ERR_CORR = BIT(7), +}; + +static bool bcm6750_nand_intc_ack(struct brcmnand_soc *soc) +{ + struct bcm6750_nand_soc *priv = + container_of(soc, struct bcm6750_nand_soc, soc); + void __iomem *mmio = priv->base + BCM6750_NAND_INT; + u32 val = brcmnand_readl(mmio); + + if (val & (BCM6750_CTRL_READY << BCM6750_NAND_STATUS_SHIFT)) { + /* Ack interrupt */ + val &= ~BCM6750_NAND_STATUS_MASK; + val |= BCM6750_CTRL_READY << BCM6750_NAND_STATUS_SHIFT; + brcmnand_writel(val, mmio); + return true; + } + + return false; +} + +static void bcm6750_nand_intc_set(struct brcmnand_soc *soc, bool en) +{ + struct bcm6750_nand_soc *priv = + container_of(soc, struct bcm6750_nand_soc, soc); + void __iomem *mmio = priv->base + BCM6750_NAND_INT_EN; + u32 val = brcmnand_readl(mmio); + + /* Don't ack any interrupts */ + val &= ~BCM6750_NAND_STATUS_MASK; + + if (en) + val |= BCM6750_CTRL_READY << BCM6750_NAND_ENABLE_SHIFT; + else + val &= ~(BCM6750_CTRL_READY << BCM6750_NAND_ENABLE_SHIFT); + + brcmnand_writel(val, mmio); +} + +static int bcm6750_nand_probe(struct udevice *dev) +{ + struct udevice *pdev = dev; + struct bcm6750_nand_soc *priv = dev_get_priv(dev); + struct brcmnand_soc *soc; + struct resource res; + + soc = &priv->soc; + + dev_read_resource_byname(pdev, "nand-int-base", &res); + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + soc->ctlrdy_ack = bcm6750_nand_intc_ack; + soc->ctlrdy_set_enabled = bcm6750_nand_intc_set; + + /* Disable and ack all interrupts */ + brcmnand_writel(0, priv->base + BCM6750_NAND_INT_EN); + brcmnand_writel(0, priv->base + BCM6750_NAND_INT); + + return brcmnand_probe(pdev, soc); +} + +static const struct udevice_id bcm6750_nand_dt_ids[] = { + { + .compatible = "brcm,nand-bcm6750", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6750_nand) = { + .name = "bcm6750-nand", + .id = UCLASS_MTD, + .of_match = bcm6750_nand_dt_ids, + .probe = bcm6750_nand_probe, + .priv_auto_alloc_size = sizeof(struct bcm6750_nand_soc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(bcm6750_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); +} From patchwork Fri Mar 6 16:25:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe REYNES X-Patchwork-Id: 243306 List-Id: U-Boot discussion From: philippe.reynes at softathome.com (Philippe Reynes) Date: Fri, 6 Mar 2020 17:25:00 +0100 Subject: [PATCH 5/6] watchdog: bcm6345: allow to use this driver on arm bcm6750 In-Reply-To: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> References: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> Message-ID: <1583511901-10930-5-git-send-email-philippe.reynes@softathome.com> This IP is also used on some arm SoC, so we allow to use it on arm bcm6750 too. Signed-off-by: Philippe Reynes --- drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d24c1e4..2dca5f6 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -93,7 +93,7 @@ config WDT_AT91 config WDT_BCM6345 bool "BCM6345 watchdog timer support" - depends on WDT && (ARCH_BMIPS || ARCH_BCM68360 || \ + depends on WDT && (ARCH_BMIPS || ARCH_BCM6750 || ARCH_BCM68360 || \ ARCH_BCM6858 || ARCH_BCM63158) help Select this to enable watchdog timer for BCM6345 SoCs. From patchwork Fri Mar 6 16:25:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe REYNES X-Patchwork-Id: 243308 List-Id: U-Boot discussion From: philippe.reynes at softathome.com (Philippe Reynes) Date: Fri, 6 Mar 2020 17:25:01 +0100 Subject: [PATCH 6/6] bcm96750ref1: add initial support In-Reply-To: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> References: <1583511901-10930-1-git-send-email-philippe.reynes@softathome.com> Message-ID: <1583511901-10930-6-git-send-email-philippe.reynes@softathome.com> This add the initial support of the broadcom reference board bcm968360bg with a bcm68360 SoC. This board has 1 GB of RAM, 512 MB of flash (nand), 2 USB port, 1 UART, and 4 ethernet ports. Signed-off-by: Philippe Reynes --- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 3 ++ arch/arm/dts/bcm96750ref1.dts | 78 ++++++++++++++++++++++++++++++ board/broadcom/bcm96750ref1/Kconfig | 16 ++++++ board/broadcom/bcm96750ref1/MAINTAINERS | 6 +++ board/broadcom/bcm96750ref1/Makefile | 3 ++ board/broadcom/bcm96750ref1/bcm96750ref1.c | 44 +++++++++++++++++ configs/bcm96750ref1_ram_defconfig | 68 ++++++++++++++++++++++++++ include/configs/broadcom_bcm96750ref1.h | 40 +++++++++++++++ 9 files changed, 259 insertions(+) create mode 100644 arch/arm/dts/bcm96750ref1.dts create mode 100644 board/broadcom/bcm96750ref1/Kconfig create mode 100644 board/broadcom/bcm96750ref1/MAINTAINERS create mode 100644 board/broadcom/bcm96750ref1/Makefile create mode 100644 board/broadcom/bcm96750ref1/bcm96750ref1.c create mode 100644 configs/bcm96750ref1_ram_defconfig create mode 100644 include/configs/broadcom_bcm96750ref1.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 568b95a..a3e9130 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1839,6 +1839,7 @@ source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcm963158/Kconfig" source "board/broadcom/bcm968360bg/Kconfig" +source "board/broadcom/bcm96750ref1/Kconfig" source "board/broadcom/bcm968580xref/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c593b2..e3dcd89 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -871,6 +871,9 @@ dtb-$(CONFIG_ARCH_BCM63158) += \ dtb-$(CONFIG_ARCH_BCM68360) += \ bcm968360bg.dtb +dtb-$(CONFIG_ARCH_BCM6750) += \ + bcm96750ref1.dtb + dtb-$(CONFIG_ARCH_BCM6858) += \ bcm968580xref.dtb diff --git a/arch/arm/dts/bcm96750ref1.dts b/arch/arm/dts/bcm96750ref1.dts new file mode 100644 index 0000000..ac607b4 --- /dev/null +++ b/arch/arm/dts/bcm96750ref1.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +/dts-v1/; + +#include "bcm6750.dtsi" + +/ { + model = "Broadcom bcm6750ref1"; + compatible = "broadcom,bcm6750ref1", "brcm,bcm6750"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio6 { + status = "okay"; +}; + +&gpio7 { + status = "okay"; +}; + +&nand { + status = "okay"; + write-protect = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nandcs at 0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <27>; + }; +}; diff --git a/board/broadcom/bcm96750ref1/Kconfig b/board/broadcom/bcm96750ref1/Kconfig new file mode 100644 index 0000000..e76e2be --- /dev/null +++ b/board/broadcom/bcm96750ref1/Kconfig @@ -0,0 +1,16 @@ +if ARCH_BCM6750 + +config SYS_VENDOR + default "broadcom" + +config SYS_BOARD + default "bcm96750ref1" + +config SYS_CONFIG_NAME + default "broadcom_bcm96750ref1" + +endif + +config TARGET_BCM96750REF1 + bool "Support Broadcom bcm96750ref1" + depends on ARCH_BCM6750 diff --git a/board/broadcom/bcm96750ref1/MAINTAINERS b/board/broadcom/bcm96750ref1/MAINTAINERS new file mode 100644 index 0000000..e7a5c9c --- /dev/null +++ b/board/broadcom/bcm96750ref1/MAINTAINERS @@ -0,0 +1,6 @@ +BCM96750REF1 BOARD +M: Philippe Reynes +S: Maintained +F: board/broadcom/bcm96750ref1 +F: include/configs/broadcom_bcm96750ref1.h +F: configs/bcm96750ref1_ram_defconfig diff --git a/board/broadcom/bcm96750ref1/Makefile b/board/broadcom/bcm96750ref1/Makefile new file mode 100644 index 0000000..ac4ffae --- /dev/null +++ b/board/broadcom/bcm96750ref1/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += bcm96750ref1.o diff --git a/board/broadcom/bcm96750ref1/bcm96750ref1.c b/board/broadcom/bcm96750ref1/bcm96750ref1.c new file mode 100644 index 0000000..4e26cfa --- /dev/null +++ b/board/broadcom/bcm96750ref1/bcm96750ref1.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +#include +#include +#include +#include + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + printf("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int print_cpuinfo(void) +{ + return 0; +} + +void enable_caches(void) +{ +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) + icache_enable(); +#endif +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) + dcache_enable(); +#endif +} diff --git a/configs/bcm96750ref1_ram_defconfig b/configs/bcm96750ref1_ram_defconfig new file mode 100644 index 0000000..714077a --- /dev/null +++ b/configs/bcm96750ref1_ram_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_SYS_ARCH_TIMER=y +CONFIG_ARCH_BCM6750=y +CONFIG_SYS_TEXT_BASE=0x60100000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ARMV7_LPAE=y +CONFIG_TARGET_BCM96750REF1=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y +CONFIG_FIT_CIPHER=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SILENT_CONSOLE=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_HUSH_PARSER=y +# CONFIG_AUTOBOOT is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set +CONFIG_DEFAULT_DEVICE_TREE="bcm96750ref1" +# CONFIG_NET is not set +CONFIG_CLK=y +CONFIG_BCM6345_GPIO=y +# CONFIG_INPUT is not set +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_6750=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_BCM6345=y +CONFIG_REGEX=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/broadcom_bcm96750ref1.h b/include/configs/broadcom_bcm96750ref1.h new file mode 100644 index 0000000..fde4a5b --- /dev/null +++ b/include/configs/broadcom_bcm96750ref1.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +#include + +/* + * common + */ + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* + * 6750 + */ + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* U-Boot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif /* CONFIG_MTD_RAW_NAND */ + +/* + * 96750ref1 + */