From patchwork Mon Jun 22 13:17:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Kochetkov X-Patchwork-Id: 242750 List-Id: U-Boot discussion From: al.kochet at gmail.com (Alexander Kochetkov) Date: Mon, 22 Jun 2020 16:17:09 +0300 Subject: [PATCH 1/2] rockchip: clk: rk3188: change APLL to safe 600MHz In-Reply-To: <20200622131710.31168-1-al.kochet@gmail.com> References: <20200622131710.31168-1-al.kochet@gmail.com> Message-ID: <20200622131710.31168-2-al.kochet@gmail.com> The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver") changed ARM clock from 600MHz to 1600MHz. It made boot unstable due to the fact that PMIC at the start generates insufficient voltage for operation. See also: commit f4f57c58b589 ("rockchip: rk3188: Setup the armclk in spl"). Fixes commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver"). Signed-off-by: Alexander Kochetkov Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3188.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index b193ac913e..4fc5c78563 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -564,7 +564,8 @@ static int rk3188_clk_probe(struct udevice *dev) rkclk_init(priv->cru, priv->grf, priv->has_bwadj); /* Init CPU frequency */ - rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj); + rkclk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ, + priv->has_bwadj); #endif return 0; From patchwork Mon Jun 22 13:17:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Kochetkov X-Patchwork-Id: 242751 List-Id: U-Boot discussion From: al.kochet at gmail.com (Alexander Kochetkov) Date: Mon, 22 Jun 2020 16:17:10 +0300 Subject: [PATCH 2/2] rockchip: clk: rk3188: enable bwadj for rk3188 DPLL In-Reply-To: <20200622131710.31168-1-al.kochet@gmail.com> References: <20200622131710.31168-1-al.kochet@gmail.com> Message-ID: <20200622131710.31168-3-al.kochet@gmail.com> Empirically, I found that DPLL on rk3188 has bwadj registers. Configuring DPLL with bwadj increase DPLL stability. Because of DPLL provide clock for ethernet, enabling bwaj reduces the number of errors on the ethernet. Signed-off-by: Alexander Kochetkov --- drivers/clk/rockchip/clk_rk3188.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 4fc5c78563..ee5782d25d 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -117,7 +117,7 @@ static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, } static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, - unsigned int hz, bool has_bwadj) + unsigned int hz) { static const struct pll_div dpll_cfg[] = { {.nf = 75, .nr = 1, .no = 6}, @@ -149,7 +149,8 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, DPLL_MODE_SLOW << DPLL_MODE_SHIFT); - rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); + /* rk3188 and rk3188a DPLL has bwadj */ + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], 1); /* wait for pll lock */ while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) @@ -504,8 +505,7 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) priv->has_bwadj); break; case CLK_DDR: - new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, - priv->has_bwadj); + new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); break; case HCLK_EMMC: case HCLK_SDMMC: