From patchwork Mon Jun 8 03:28:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiang Zhao X-Patchwork-Id: 241907 List-Id: U-Boot discussion From: qiang.zhao at nxp.com (Qiang Zhao) Date: Mon, 8 Jun 2020 11:28:24 +0800 Subject: [PATCH 1/2] armv8: dts: fsl-lx2160a: add flash node under dspi to qds dts Message-ID: <20200608032825.23674-1-qiang.zhao@nxp.com> From: Zhao Qiang Add flash node under dspi into fsl-lx2160a-qds.dtsi Signed-off-by: Zhao Qiang --- arch/arm/dts/fsl-lx2160a-qds.dtsi | 99 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index 129cf82..96c9800 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -20,6 +20,105 @@ phy-connection-type = "rgmii-id"; }; +&dspi0 { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dflash3: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash4: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash5: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&dspi2 { + bus-num = <0>; + status = "okay"; + + dflash6: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash7: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash8: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + &emdio1 { status = "okay"; }; From patchwork Mon Jun 8 03:28:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiang Zhao X-Patchwork-Id: 241908 List-Id: U-Boot discussion From: qiang.zhao at nxp.com (Qiang Zhao) Date: Mon, 8 Jun 2020 11:28:25 +0800 Subject: [PATCH 2/2] config: lx2160/2a: enable dspi In-Reply-To: <20200608032825.23674-1-qiang.zhao@nxp.com> References: <20200608032825.23674-1-qiang.zhao@nxp.com> Message-ID: <20200608032825.23674-2-qiang.zhao@nxp.com> From: Zhao Qiang Enable dspi in lx2160aqds tfa defconfig Enable CONFIG_SPI_FLASH_SST/EON in config file. Signed-off-by: Zhao Qiang --- configs/lx2160aqds_tfa_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 716c089..4fb0c76 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -52,8 +52,10 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y @@ -76,6 +78,7 @@ CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y +CONFIG_FSL_DSPI=y CONFIG_DM_SPI=y CONFIG_NXP_FSPI=y CONFIG_USB=y