From patchwork Sat Jun 6 17:15:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 241846 List-Id: U-Boot discussion From: ardb at kernel.org (Ard Biesheuvel) Date: Sat, 6 Jun 2020 19:15:30 +0200 Subject: [PATCH 1/5] arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK In-Reply-To: <20200606171534.736365-1-ardb@kernel.org> References: <20200606171534.736365-1-ardb@kernel.org> Message-ID: <20200606171534.736365-2-ardb@kernel.org> The LPAE version of DCACHE_WRITEBACK is currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read. Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/system.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 7a40b56acdca..21b26557d28b 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -445,7 +445,7 @@ static inline void set_dacr(unsigned int val) * Memory types */ #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \ - (0xcc << (2 * 8)) | (0xff << (3 * 8))) + (0xee << (2 * 8)) | (0xff << (3 * 8))) /* options available for data cache on each page */ enum dcache_option { From patchwork Sat Jun 6 17:15:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 241847 List-Id: U-Boot discussion From: ardb at kernel.org (Ard Biesheuvel) Date: Sat, 6 Jun 2020 19:15:31 +0200 Subject: [PATCH 2/5] arm: qemu: enable LPAE on 32-bit In-Reply-To: <20200606171534.736365-1-ardb@kernel.org> References: <20200606171534.736365-1-ardb@kernel.org> Message-ID: <20200606171534.736365-3-ardb@kernel.org> QEMU's mach-virt machine only supports selecting CPU models that implement the virtualization extensions, and are therefore guaranteed to support LPAE as well. Initially, QEMU would not allow emulating these CPUs running in HYP mode (or EL2, for AArch64), but today, it also contains a complete implementation of the virtualization extensions themselves. This means we could be running U-Boot in HYP mode, in which case the LPAE long descriptor page table format is the only format that is supported. If we are not running in HYP mode, we can use either. So let's enable CONFIG_ARMV7_LPAE for qemu_arm_defconfig so that we get the best support for running with the MMU and caches enabled at any privilege level. Signed-off-by: Ard Biesheuvel Acked-by: Heinrich Schuchardt X-Patchwork-Id: 241848 List-Id: U-Boot discussion From: ardb at kernel.org (Ard Biesheuvel) Date: Sat, 6 Jun 2020 19:15:32 +0200 Subject: [PATCH 3/5] arm: qemu: implement enable_caches() In-Reply-To: <20200606171534.736365-1-ardb@kernel.org> References: <20200606171534.736365-1-ardb@kernel.org> Message-ID: <20200606171534.736365-4-ardb@kernel.org> Add an override for enable_caches to enable the I and D caches, along with the cached 1:1 mapping of all of DRAM. This is needed for running U-Boot under virtualization with QEMU/kvm. Signed-off-by: Ard Biesheuvel --- board/emulation/qemu-arm/qemu-arm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 69e8ef46f1f5..1b0d543b93c1 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -94,6 +95,12 @@ void *board_fdt_blob_setup(void) return (void *)CONFIG_SYS_SDRAM_BASE; } +void enable_caches(void) +{ + icache_enable(); + dcache_enable(); +} + #if defined(CONFIG_EFI_RNG_PROTOCOL) #include #include From patchwork Sat Jun 6 17:15:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 241849 List-Id: U-Boot discussion From: ardb at kernel.org (Ard Biesheuvel) Date: Sat, 6 Jun 2020 19:15:33 +0200 Subject: [PATCH 4/5] arm: qemu: disable the EFI workaround for older GRUB In-Reply-To: <20200606171534.736365-1-ardb@kernel.org> References: <20200606171534.736365-1-ardb@kernel.org> Message-ID: <20200606171534.736365-5-ardb@kernel.org> The QEMU/mach-virt targeted port of u-boot currently only runs on QEMU under TCG emulation, which does not model the caches at all, and so no users can exist that are relying on the GRUB hack for EFI boot. We will shortly enable support for running under KVM, but the GRUB hack (which disables all caches without doing cache cleaning by VA during ExitBootServices()) is likely to cause more problems than it solves, given that KVM hosts require correct maintenance if they incorporate non-architected system caches. So let's disable the GRUB hack by default on the QEMU/mach-virt port. Signed-off-by: Ard Biesheuvel Reviewed-by: Heinrich Schuchardt --- configs/qemu_arm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 75bdce7708c7..1d2b4437cb07 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -47,3 +47,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y +# CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set From patchwork Sat Jun 6 17:15:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 241850 List-Id: U-Boot discussion From: ardb at kernel.org (Ard Biesheuvel) Date: Sat, 6 Jun 2020 19:15:34 +0200 Subject: [PATCH 5/5] arm: qemu: override flash accessors to use virtualizable instructions In-Reply-To: <20200606171534.736365-1-ardb@kernel.org> References: <20200606171534.736365-1-ardb@kernel.org> Message-ID: <20200606171534.736365-6-ardb@kernel.org> Some instructions in the ARM ISA have multiple output registers, such as ldrd/ldp (load pair), where two registers are loaded from memory, but also ldr with indexing, where the memory base register is incremented as well when the value is loaded to the destination register. MMIO emulation under KVM is based on using the architecturally defined syndrome information that is provided when an exception is taken to the hypervisor. This syndrome information describes whether the instruction that triggered the exception is a load or a store, what the faulting address was, and which register was the destination register. This syndrome information can only describe one destination register, and when the trapping instruction is one with multiple outputs, KVM throws an error like kvm [615929]: Data abort outside memslots with no valid syndrome info on the host and kills the QEMU process with the following error: U-Boot 2020.07-rc3-00208-g88bd5b179360-dirty (Jun 06 2020 - 11:59:22 +0200) DRAM: 1 GiB Flash: error: kvm run failed Function not implemented R00=00000001 R01=00000040 R02=7ee0ce20 R03=00000000 R04=7ffd9eec R05=00000004 R06=7ffda3f8 R07=00000055 R08=7ffd9eec R09=7ef0ded0 R10=7ee0ce20 R11=00000000 R12=00000004 R13=7ee0cdf8 R14=00000000 R15=7ff72d08 PSR=200001d3 --C- A svc32 QEMU: Terminated This means that, in order to run U-Boot in QEMU under KVM, we need to avoid such instructions when accessing emulated devices. For the flash in particular, which is a hybrid between a ROM (backed by a memslot) when in array mode, and an emulated MMIO device (when in write mode), we need to take care to only use instructions that KVM can deal with when they trap. So override the flash accessors that are used when running on QEMU. Note that the write accessors are included for completeness, but the read accessors are the ones that need this special care. Signed-off-by: Ard Biesheuvel --- board/emulation/qemu-arm/qemu-arm.c | 55 ++++++++++++++++++++ include/configs/qemu-arm.h | 1 + 2 files changed, 56 insertions(+) diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 1b0d543b93c1..32e18fd8b985 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -142,3 +142,58 @@ efi_status_t platform_get_rng_device(struct udevice **dev) return EFI_SUCCESS; } #endif /* CONFIG_EFI_RNG_PROTOCOL */ + +#ifdef CONFIG_ARM64 +#define __W "w" +#else +#define __W +#endif + +void flash_write8(u8 value, void *addr) +{ + asm("strb %" __W "1, %0" : "=m"(*(u8 *)addr) : "r"(value)); +} + +void flash_write16(u16 value, void *addr) +{ + asm("strh %" __W "1, %0" : "=m"(*(u16 *)addr) : "r"(value)); +} + +void flash_write32(u32 value, void *addr) +{ + asm("str %" __W "1, %0" : "=m"(*(u32 *)addr) : "r"(value)); +} + +void flash_write64(u64 value, void *addr) +{ + BUG(); /* FLASH_CFI_64BIT is not implemented by QEMU */ +} + +u8 flash_read8(void *addr) +{ + u8 ret; + + asm("ldrb %" __W "0, %1" : "=r"(ret) : "m"(*(u8 *)addr)); + return ret; +} + +u16 flash_read16(void *addr) +{ + u16 ret; + + asm("ldrh %" __W "0, %1" : "=r"(ret) : "m"(*(u16 *)addr)); + return ret; +} + +u32 flash_read32(void *addr) +{ + u32 ret; + + asm("ldr %" __W "0, %1" : "=r"(ret) : "m"(*(u32 *)addr)); + return ret; +} + +u64 flash_read64(void *addr) +{ + BUG(); /* FLASH_CFI_64BIT is not implemented by QEMU */ +} diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 1ef75a87836b..bc8b7c5c1238 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -53,5 +53,6 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 2 #endif #define CONFIG_SYS_MAX_FLASH_SECT 256 /* Sector: 256K, Bank: 64M */ +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #endif /* __CONFIG_H */