From patchwork Tue Jul 7 20:04:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "shiva.linuxworks at gmail.com" X-Patchwork-Id: 240929 List-Id: U-Boot discussion From: shiva.linuxworks at gmail.com (shiva.linuxworks at gmail.com) Date: Tue, 7 Jul 2020 22:04:08 +0200 Subject: [PATCH 1/6] mtd: spinand: micron: Generalize the OOB layout structure and function names In-Reply-To: <20200707200413.9724-1-sshivamurthy@micron.com> References: <20200707200413.9724-1-sshivamurthy@micron.com> Message-ID: <20200707200413.9724-2-sshivamurthy@micron.com> From: Shivamurthy Shastri In order to add new Micron SPI NAND devices, we generalized the OOB layout structure and function names. Signed-off-by: Shivamurthy Shastri --- drivers/mtd/nand/spi/micron.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 04de51cb4667..c37b152ba29e 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -38,38 +38,38 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); -static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) +static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) { if (section) return -ERANGE; - region->offset = 64; - region->length = 64; + region->offset = mtd->oobsize / 2; + region->length = mtd->oobsize / 2; return 0; } -static int mt29f2g01abagd_ooblayout_free(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) +static int micron_8_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) { if (section) return -ERANGE; /* Reserve 2 bytes for the BBM. */ region->offset = 2; - region->length = 62; + region->length = (mtd->oobsize / 2) - 2; return 0; } -static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = { - .ecc = mt29f2g01abagd_ooblayout_ecc, - .rfree = mt29f2g01abagd_ooblayout_free, +static const struct mtd_ooblayout_ops micron_8_ooblayout = { + .ecc = micron_8_ooblayout_ecc, + .rfree = micron_8_ooblayout_free, }; -static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand, - u8 status) +static int micron_8_ecc_get_status(struct spinand_device *spinand, + u8 status) { switch (status & MICRON_STATUS_ECC_MASK) { case STATUS_ECC_NO_BITFLIPS: @@ -102,8 +102,8 @@ static const struct spinand_info micron_spinand_table[] = { &write_cache_variants, &update_cache_variants), 0, - SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout, - mt29f2g01abagd_ecc_get_status)), + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), }; static int micron_spinand_detect(struct spinand_device *spinand) From patchwork Tue Jul 7 20:04:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "shiva.linuxworks at gmail.com" X-Patchwork-Id: 240930 List-Id: U-Boot discussion From: shiva.linuxworks at gmail.com (shiva.linuxworks at gmail.com) Date: Tue, 7 Jul 2020 22:04:09 +0200 Subject: [PATCH 2/6] mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD In-Reply-To: <20200707200413.9724-1-sshivamurthy@micron.com> References: <20200707200413.9724-1-sshivamurthy@micron.com> Message-ID: <20200707200413.9724-3-sshivamurthy@micron.com> From: Shivamurthy Shastri Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage details as a comment. Signed-off-by: Shivamurthy Shastri --- drivers/mtd/nand/spi/micron.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index c37b152ba29e..93b0e2c07e79 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -95,6 +95,7 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand, } static const struct spinand_info micron_spinand_table[] = { + /* M79A 2Gb 3.3V */ SPINAND_INFO("MT29F2G01ABAGD", 0x24, NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), NAND_ECCREQ(8, 512), From patchwork Tue Jul 7 20:04:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "shiva.linuxworks at gmail.com" X-Patchwork-Id: 240931 List-Id: U-Boot discussion From: shiva.linuxworks at gmail.com (shiva.linuxworks at gmail.com) Date: Tue, 7 Jul 2020 22:04:10 +0200 Subject: [PATCH 3/6] mtd: spinand: micron: Add new Micron SPI NAND devices In-Reply-To: <20200707200413.9724-1-sshivamurthy@micron.com> References: <20200707200413.9724-1-sshivamurthy@micron.com> Message-ID: <20200707200413.9724-4-sshivamurthy@micron.com> From: Shivamurthy Shastri Add device table for M79A and M78A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri --- drivers/mtd/nand/spi/micron.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 93b0e2c07e79..c58082c16c3c 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -105,6 +105,36 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), + /* M79A 2Gb 1.8V */ + SPINAND_INFO("MT29F2G01ABBGD", 0x25, + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), + /* M78A 1Gb 3.3V */ + SPINAND_INFO("MT29F1G01ABAFD", 0x14, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), + /* M78A 1Gb 1.8V */ + SPINAND_INFO("MT29F1G01ABAFD", 0x15, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), }; static int micron_spinand_detect(struct spinand_device *spinand) From patchwork Tue Jul 7 20:04:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "shiva.linuxworks at gmail.com" X-Patchwork-Id: 240932 List-Id: U-Boot discussion From: shiva.linuxworks at gmail.com (shiva.linuxworks at gmail.com) Date: Tue, 7 Jul 2020 22:04:11 +0200 Subject: [PATCH 4/6] mtd: spinand: micron: identify SPI NAND device with Continuous Read mode In-Reply-To: <20200707200413.9724-1-sshivamurthy@micron.com> References: <20200707200413.9724-1-sshivamurthy@micron.com> Message-ID: <20200707200413.9724-5-sshivamurthy@micron.com> From: Shivamurthy Shastri Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri --- drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++ include/linux/mtd/spinand.h | 1 + 2 files changed, 17 insertions(+) diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index c58082c16c3c..508088b8b483 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -22,6 +22,8 @@ #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) +#define MICRON_CFG_CR BIT(0) + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -157,8 +159,22 @@ static int micron_spinand_detect(struct spinand_device *spinand) return 1; } +static int micron_spinand_init(struct spinand_device *spinand) +{ + /* + * M70A device series enable Continuous Read feature at Power-up, + * which is not supported. Disable this bit to avoid any possible + * failure. + */ + if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT) + return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0); + + return 0; +} + static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { .detect = micron_spinand_detect, + .init = micron_spinand_init, }; const struct spinand_manufacturer micron_spinand_manufacturer = { diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 83eafb184e65..88bacde91e53 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -246,6 +246,7 @@ struct spinand_ecc_info { }; #define SPINAND_HAS_QE_BIT BIT(0) +#define SPINAND_HAS_CR_FEAT_BIT BIT(1) /** * struct spinand_info - Structure used to describe SPI NAND chips From patchwork Tue Jul 7 20:04:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "shiva.linuxworks at gmail.com" X-Patchwork-Id: 240933 List-Id: U-Boot discussion From: shiva.linuxworks at gmail.com (shiva.linuxworks at gmail.com) Date: Tue, 7 Jul 2020 22:04:12 +0200 Subject: [PATCH 5/6] mtd: spinand: micron: Add M70A series Micron SPI NAND devices In-Reply-To: <20200707200413.9724-1-sshivamurthy@micron.com> References: <20200707200413.9724-1-sshivamurthy@micron.com> Message-ID: <20200707200413.9724-6-sshivamurthy@micron.com> From: Shivamurthy Shastri Add device table for M70A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri --- drivers/mtd/nand/spi/micron.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 508088b8b483..fe91349999c6 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -137,6 +137,26 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), + /* M70A 4Gb 3.3V */ + SPINAND_INFO("MT29F4G01ABAFD", 0x34, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_CR_FEAT_BIT, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), + /* M70A 4Gb 1.8V */ + SPINAND_INFO("MT29F4G01ABBFD", 0x35, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_CR_FEAT_BIT, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), }; static int micron_spinand_detect(struct spinand_device *spinand) From patchwork Tue Jul 7 20:04:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "shiva.linuxworks at gmail.com" X-Patchwork-Id: 240934 List-Id: U-Boot discussion From: shiva.linuxworks at gmail.com (shiva.linuxworks at gmail.com) Date: Tue, 7 Jul 2020 22:04:13 +0200 Subject: [PATCH 6/6] mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies In-Reply-To: <20200707200413.9724-1-sshivamurthy@micron.com> References: <20200707200413.9724-1-sshivamurthy@micron.com> Message-ID: <20200707200413.9724-7-sshivamurthy@micron.com> From: Shivamurthy Shastri Add device table for new Micron SPI NAND devices, which have multiple dies. Also, enable support to select the dies. Signed-off-by: Shivamurthy Shastri --- drivers/mtd/nand/spi/micron.c | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index fe91349999c6..6bacf14aafea 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -24,6 +24,14 @@ #define MICRON_CFG_CR BIT(0) +/* + * As per datasheet, die selection is done by the 6th bit of Die + * Select Register (Address 0xD0). + */ +#define MICRON_DIE_SELECT_REG 0xD0 + +#define MICRON_SELECT_DIE(x) ((x) << 6) + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -70,6 +78,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = { .rfree = micron_8_ooblayout_free, }; +static int micron_select_target(struct spinand_device *spinand, + unsigned int target) +{ + struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG, + spinand->scratchbuf); + + if (target > 1) + return -EINVAL; + + *spinand->scratchbuf = MICRON_SELECT_DIE(target); + + return spi_mem_exec_op(spinand->slave, &op); +} + static int micron_8_ecc_get_status(struct spinand_device *spinand, u8 status) { @@ -137,6 +159,17 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), + /* M79A 4Gb 3.3V */ + SPINAND_INFO("MT29F4G01ADAGD", 0x36, + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), /* M70A 4Gb 3.3V */ SPINAND_INFO("MT29F4G01ABAFD", 0x34, NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), @@ -157,6 +190,28 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), + /* M70A 8Gb 3.3V */ + SPINAND_INFO("MT29F8G01ADAFD", 0x46, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_CR_FEAT_BIT, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), + /* M70A 8Gb 1.8V */ + SPINAND_INFO("MT29F8G01ADBFD", 0x47, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_CR_FEAT_BIT, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), }; static int micron_spinand_detect(struct spinand_device *spinand)