From patchwork Mon Jul 6 02:16:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 240747 List-Id: U-Boot discussion From: sjg at chromium.org (Simon Glass) Date: Sun, 5 Jul 2020 20:16:52 -0600 Subject: [PATCH 1/2] spi: Remove unnecessary #ifdefs in header file Message-ID: <20200706021653.2146278-1-sjg@chromium.org> These prevent use of compile-time checks such as: if (CONFIG_IS_ENABLED(DM_SPI)) since, for example, if CONFIG_SPL_DM_SPI is not enabled then the definitions are not included by spi.h and the C code will not build. The #ifdefs are unnecessary since there are no conflicts with the pre-DM code. In any case we have almost switched over to driver model for SPI. Drop these #ifdefs from spi.h to fix a build warning on chromebook_coral in the following patch. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/spi.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/spi.h b/include/spi.h index 9b4fb8dc0b..7fca646759 100644 --- a/include/spi.h +++ b/include/spi.h @@ -39,7 +39,6 @@ #define SPI_DEFAULT_WORDLEN 8 -#if CONFIG_IS_ENABLED(DM_SPI) /* TODO(sjg at chromium.org): Remove this and use max_hz from struct spi_slave */ struct dm_spi_bus { uint max_hz; @@ -65,8 +64,6 @@ struct dm_spi_slave_platdata { uint mode; }; -#endif /* CONFIG_DM_SPI */ - /** * enum spi_clock_phase - indicates the clock phase to use for SPI (CPHA) * @@ -317,7 +314,6 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len); */ int spi_cs_is_valid(unsigned int bus, unsigned int cs); -#if !CONFIG_IS_ENABLED(DM_SPI) /** * Activate a SPI chipselect. * This function is provided by the board code when using a driver @@ -343,7 +339,6 @@ void spi_cs_deactivate(struct spi_slave *slave); * @hz: The transfer speed */ void spi_set_speed(struct spi_slave *slave, uint hz); -#endif /** * Write 8 bits, then read 8 bits. @@ -367,8 +362,6 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) return ret < 0 ? ret : din[1]; } -#if CONFIG_IS_ENABLED(DM_SPI) - /** * struct spi_cs_info - Information about a bus chip select * @@ -717,6 +710,5 @@ int dm_spi_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep, /* Access the operations for a SPI device */ #define spi_get_ops(dev) ((struct dm_spi_ops *)(dev)->driver->ops) #define spi_emul_get_ops(dev) ((struct dm_spi_emul_ops *)(dev)->driver->ops) -#endif /* CONFIG_DM_SPI */ #endif /* _SPI_H_ */ From patchwork Mon Jul 6 02:16:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 240748 List-Id: U-Boot discussion From: sjg at chromium.org (Simon Glass) Date: Sun, 5 Jul 2020 20:16:53 -0600 Subject: [PATCH 2/2] x86: apl: Re-enable loading of SPL In-Reply-To: <20200706021653.2146278-1-sjg@chromium.org> References: <20200706021653.2146278-1-sjg@chromium.org> Message-ID: <20200706021653.2146278-2-sjg@chromium.org> At present the SPL loader is not included in the TPL image so SPL cannot be loaded. Fix it by including this file for both SPL and TPL. Signed-off-by: Simon Glass Fixes: c87f9ce2273 ("x86: Don't build some unused objects in TPL") Reviewed-by: Bin Meng --- arch/x86/cpu/apollolake/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 11621256ae..3aa2a55676 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -3,6 +3,7 @@ # Copyright 2019 Google LLC obj-$(CONFIG_SPL_BUILD) += cpu_spl.o +obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o obj-y += cpu_common.o @@ -11,7 +12,6 @@ obj-y += cpu.o obj-y += punit.o obj-y += fsp_bindings.o ifdef CONFIG_SPL_BUILD -obj-y += spl.o obj-y += fsp_m.o endif endif