From patchwork Wed Jul 1 11:37:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfgang Wallner X-Patchwork-Id: 240553 List-Id: U-Boot discussion From: wolfgang.wallner at br-automation.com (Wolfgang Wallner) Date: Wed, 1 Jul 2020 13:37:23 +0200 Subject: [PATCH v3 1/2] drivers: p2sb: replace Primary-to-Sideband Bus with Primary to Sideband Bridge In-Reply-To: <20200701113724.255226-1-wolfgang.wallner@br-automation.com> References: <20200701113724.255226-1-wolfgang.wallner@br-automation.com> Message-ID: <20200701113724.255226-2-wolfgang.wallner@br-automation.com> In Intel's documentation the term P2SB stands for "Primary to Sideband Bridge". Signed-off-by: Wolfgang Wallner Reviewed-by: Simon Glass --- Changes in v3: - Replaced the term in two more places drivers/misc/Kconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 6bb5bc77e9..b67e906a76 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -243,10 +243,10 @@ config NUVOTON_NCT6102D in the Nuvoton Super IO chips on X86 platforms. config P2SB - bool "Intel Primary-to-Sideband Bus" + bool "Intel Primary to Sideband Bridge" depends on X86 || SANDBOX help - This enables support for the Intel Primary-to-Sideband bus, + This enables support for the Intel Primary to Sideband Bridge, abbreviated to P2SB. The P2SB is used to access various peripherals such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI space. The space is segmented into different channels and peripherals @@ -256,20 +256,20 @@ config P2SB devices - see pcr_readl(), etc. config SPL_P2SB - bool "Intel Primary-to-Sideband Bus in SPL" + bool "Intel Primary to Sideband Bridge in SPL" depends on SPL && (X86 || SANDBOX) help - The Primary-to-Sideband bus is used to access various peripherals + The Primary to Sideband Bridge is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is segmented into different channels and peripherals are accessed by device-specific means within those channels. Devices should be added in the device tree as subnodes of the p2sb. config TPL_P2SB - bool "Intel Primary-to-Sideband Bus in TPL" + bool "Intel Primary to Sideband Bridge in TPL" depends on TPL && (X86 || SANDBOX) help - The Primary-to-Sideband bus is used to access various peripherals + The Primary to Sideband Bridge is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is segmented into different channels and peripherals are accessed by device-specific means within those channels. Devices should be added From patchwork Wed Jul 1 11:37:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfgang Wallner X-Patchwork-Id: 240554 List-Id: U-Boot discussion From: wolfgang.wallner at br-automation.com (Wolfgang Wallner) Date: Wed, 1 Jul 2020 13:37:24 +0200 Subject: [PATCH v3 2/2] x86: p2sb: make P2SB driver depend on P2SB uclass In-Reply-To: <20200701113724.255226-1-wolfgang.wallner@br-automation.com> References: <20200701113724.255226-1-wolfgang.wallner@br-automation.com> Message-ID: <20200701113724.255226-3-wolfgang.wallner@br-automation.com> Currently it is possible to select the P2SB driver without selecting the P2SB uclass, which can't work. Fix this by adding a "depends on" in Kconfig. Signed-off-by: Wolfgang Wallner Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Fixed cover letter arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c8eae24c07..27295ef384 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -717,6 +717,7 @@ config HAVE_ITSS config HAVE_P2SB bool "Enable P2SB" + depends on P2SB help Select this to include the driver for the Primary to Sideband Bridge (P2SB) which is found on several Intel