From patchwork Tue Jan 21 11:31:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: MarkLee X-Patchwork-Id: 239878 List-Id: U-Boot discussion From: Mark-MC.Lee at mediatek.com (MarkLee) Date: Tue, 21 Jan 2020 19:31:57 +0800 Subject: [U-boot, 1/4] eth: mtk-eth: add sgmii mode support in mediatek eth driver In-Reply-To: <20200121113200.24259-1-Mark-MC.Lee@mediatek.com> References: <20200121113200.24259-1-Mark-MC.Lee@mediatek.com> Message-ID: <20200121113200.24259-2-Mark-MC.Lee@mediatek.com> This patch add sgmii init part for the mediatek SoC that support sgmii mode. It is a must for mt7622. Signed-off-by: MarkLee --- drivers/net/mtk_eth.c | 44 +++++++++++++++++++++++++++++++++++++++++++ drivers/net/mtk_eth.h | 15 +++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index c22e590387..8354e82244 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -151,6 +151,7 @@ struct mtk_eth_priv { void __iomem *fe_base; void __iomem *gmac_base; void __iomem *ethsys_base; + void __iomem *sgmii_base; struct mii_dev *mdio_bus; int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); @@ -750,6 +751,24 @@ static int mtk_phy_probe(struct udevice *dev) return 0; } +static void mtk_sgmii_init(struct mtk_eth_priv *priv) +{ + /* Set SGMII GEN2 speed(2.5G) */ + clrsetbits_le32(priv->sgmii_base + SGMSYS_GEN2_SPEED, + SGMSYS_SPEED_2500, SGMSYS_SPEED_2500); + + /* Disable SGMII AN */ + clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, + SGMII_AN_ENABLE, 0); + + /* SGMII force mode setting */ + writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); + + /* Release PHYA power down state */ + clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, + SGMII_PHYA_PWD, 0); +} + static void mtk_mac_init(struct mtk_eth_priv *priv) { int i, ge_mode = 0; @@ -758,8 +777,13 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) switch (priv->phy_interface) { case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII: + ge_mode = GE_MODE_RGMII; + break; case PHY_INTERFACE_MODE_SGMII: ge_mode = GE_MODE_RGMII; + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, + SYSCFG0_SGMII_SEL(priv->gmac_id)); + mtk_sgmii_init(priv); break; case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -1104,6 +1128,26 @@ static int mtk_eth_ofdata_to_platdata(struct udevice *dev) } } + if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) { + /* get corresponding sgmii phandle */ + ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", + NULL, 0, 0, &args); + if (ret) + return ret; + + regmap = syscon_node_to_regmap(args.node); + + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + priv->sgmii_base = regmap_get_range(regmap, 0); + + if (!priv->sgmii_base) { + dev_err(dev, "Unable to find sgmii\n"); + return -ENODEV; + } + } + /* check for switch first, otherwise phy will be used */ priv->sw = SW_NONE; priv->switch_init = NULL; diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index fe89a03739..9bb037d440 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -20,6 +20,8 @@ #define ETHSYS_SYSCFG0_REG 0x14 #define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2)) #define SYSCFG0_GE_MODE_M 0x3 +#define SYSCFG0_SGMII_SEL_M (0x3 << 8) +#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) #define ETHSYS_CLKCFG0_REG 0x2c #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) @@ -30,6 +32,19 @@ #define GE_MODE_MII_PHY 2 #define GE_MODE_RMII 3 +/* SGMII subsystem config registers */ +#define SGMSYS_PCS_CONTROL_1 0x0 +#define SGMII_AN_ENABLE BIT(12) + +#define SGMSYS_SGMII_MODE 0x20 +#define SGMII_FORCE_MODE 0x31120019 + +#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 +#define SGMII_PHYA_PWD BIT(4) + +#define SGMSYS_GEN2_SPEED 0x2028 +#define SGMSYS_SPEED_2500 BIT(2) + /* Frame Engine Registers */ /* PDMA */ From patchwork Tue Jan 21 11:31:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: MarkLee X-Patchwork-Id: 239880 List-Id: U-Boot discussion From: Mark-MC.Lee at mediatek.com (MarkLee) Date: Tue, 21 Jan 2020 19:31:58 +0800 Subject: [U-boot, 2/4] eth: mtk-eth: add mt7622 support in mediatek eth driver In-Reply-To: <20200121113200.24259-1-Mark-MC.Lee@mediatek.com> References: <20200121113200.24259-1-Mark-MC.Lee@mediatek.com> Message-ID: <20200121113200.24259-3-Mark-MC.Lee@mediatek.com> This patch add mt7622 support in mediatek eth driver Signed-off-by: MarkLee --- drivers/net/mtk_eth.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 7721ffb46c..85bbc2a3c5 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -136,7 +136,8 @@ enum mtk_switch { enum mtk_soc { SOC_MT7623, - SOC_MT7629 + SOC_MT7629, + SOC_MT7622 }; struct mtk_eth_priv { @@ -1196,6 +1197,7 @@ static int mtk_eth_ofdata_to_platdata(struct udevice *dev) static const struct udevice_id mtk_eth_ids[] = { { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 }, { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 }, + { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 }, {} }; From patchwork Tue Jan 21 11:31:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: MarkLee X-Patchwork-Id: 239879 List-Id: U-Boot discussion From: Mark-MC.Lee at mediatek.com (MarkLee) Date: Tue, 21 Jan 2020 19:31:59 +0800 Subject: [U-boot, 3/4] arm: dts: mediatek: add ethernet and sgmii dts node for mt7622 In-Reply-To: <20200121113200.24259-1-Mark-MC.Lee@mediatek.com> References: <20200121113200.24259-1-Mark-MC.Lee@mediatek.com> Message-ID: <20200121113200.24259-4-Mark-MC.Lee@mediatek.com> This patch add eth and sgmii dts node for mt7622 to support ethernet Signed-off-by: MarkLee --- arch/arm/dts/mt7622-rfb.dts | 13 +++++++++++ arch/arm/dts/mt7622.dtsi | 45 +++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts index ec30f5c6eb..f05c3fe14d 100644 --- a/arch/arm/dts/mt7622-rfb.dts +++ b/arch/arm/dts/mt7622-rfb.dts @@ -178,3 +178,16 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 7dcca5c6af..1e8ec9b48b 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -7,6 +7,9 @@ #include #include #include +#include +#include +#include / { compatible = "mediatek,mt7622"; @@ -182,4 +185,46 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + ethsys: syscon at 1b000000 { + compatible = "mediatek,mt7622-ethsys", "syscon"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet at 1b100000 { + compatible = "mediatek,mt7622-eth", "syscon"; + reg = <0x1b100000 0x20000>; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <ðsys CLK_ETH_ESW_EN>, + <ðsys CLK_ETH_GP0_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_GP2_EN>, + <&sgmiisys CLK_SGMII_TX250M_EN>, + <&sgmiisys CLK_SGMII_RX250M_EN>, + <&sgmiisys CLK_SGMII_CDR_REF>, + <&sgmiisys CLK_SGMII_CDR_FB>, + <&topckgen CLK_TOP_SGMIIPLL>, + <&apmixedsys CLK_APMIXED_ETH2PLL>; + clock-names = "ethif", "esw", "gp0", "gp1", "gp2", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", + "eth2pll"; + power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>; + resets = <ðsys ETHSYS_FE_RST>; + reset-names = "fe"; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sgmiisys: sgmiisys at 1b128000 { + compatible = "mediatek,mt7622-sgmiisys", "syscon"; + reg = <0x1b128000 0x3000>; + #clock-cells = <1>; + }; + }; From patchwork Tue Jan 21 11:32:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: MarkLee X-Patchwork-Id: 239882 List-Id: U-Boot discussion From: Mark-MC.Lee at mediatek.com (MarkLee) Date: Tue, 21 Jan 2020 19:32:00 +0800 Subject: [U-boot,4/4] configs: mediatek: enable mt7622 ethernet support In-Reply-To: <20200121113200.24259-1-Mark-MC.Lee@mediatek.com> References: <20200121113200.24259-1-Mark-MC.Lee@mediatek.com> Message-ID: <20200121113200.24259-5-Mark-MC.Lee@mediatek.com> This patch enable mt7622 ethernet support in its defconfig Signed-off-by: MarkLee --- configs/mt7622_rfb_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index e1917e70e7..806087a3d6 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -34,6 +34,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y +CONFIG_PHY_FIXED=y +CONFIG_MEDIATEK_ETH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CMD_PING=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_MT7622=y