From patchwork Mon Jan 20 01:32:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luis Araneda X-Patchwork-Id: 239777 List-Id: U-Boot discussion From: luaraneda at gmail.com (Luis Araneda) Date: Sun, 19 Jan 2020 22:32:19 -0300 Subject: [U-Boot] [PATCH] arm: zynq: zybo z7: fix SPL uart init bitrate Message-ID: <20200120013219.8648-1-luaraneda@gmail.com> From: Milan Obuch The board uses 100 MHz clock for UART bitrate generator, but is configured as 50 MHz on defconfig. This produces wrong console output. The first message, "Debug uart enabled" is received as: "������b" Fix the issue by configuring the correct clock for the UART baudrate generator Signed-off-by: Milan Obuch Signed-off-by: Luis Araneda --- This changes were originally sent by Milan Obuch using a diff format. As he didn't know how to properly send git patches to the mailing list, I converted them to a git commit, rephrased the commit message and added the Signed-off-by tags. Milan Obuch then review and approved the current state of the patch. Tested on a zybo z7-20 board by me configs/zynq_zybo_z7_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index 7129e2b5f3..f41d6574f7 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -5,7 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y