From patchwork Thu Jan 9 10:07:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 239301 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Thu, 9 Jan 2020 11:07:52 +0100 Subject: [PATCH 1/3] mtd: rawnand: denali-spl: Add missing hardware init Message-ID: <20200109100754.1007705-1-marex@denx.de> While the Denali NAND is initialized by the BootROM in SPL, there are still a couple of settings which are missing. These can trigger subtle corruption of the data read out of the NAND. Fill these settings in just like they are filled in by the full Denali NAND driver in denali_hw_init(). Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mtd/nand/raw/denali_spl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index dbaba3cab2..b8b29812aa 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -173,6 +173,13 @@ void nand_init(void) page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); + + /* Do as denali_hw_init() does. */ + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, + denali_flash_reg + SPARE_AREA_SKIP_BYTES); + writel(0x0F, denali_flash_reg + RB_PIN_ENABLED); + writel(CHIP_EN_DONT_CARE__FLAG, denali_flash_reg + CHIP_ENABLE_DONT_CARE); + writel(0xffff, denali_flash_reg + SPARE_AREA_MARKER); } int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) From patchwork Thu Jan 9 10:07:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 239302 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Thu, 9 Jan 2020 11:07:53 +0100 Subject: [PATCH 2/3] mtd: rawnand: denali: Allow operation without clock driver In-Reply-To: <20200109100754.1007705-1-marex@denx.de> References: <20200109100754.1007705-1-marex@denx.de> Message-ID: <20200109100754.1007705-2-marex@denx.de> The SoCFPGA Gen5 does not have a clock driver yet, let the NAND driver work without a clock driver by falling back to the default frequencies. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mtd/nand/raw/denali_dt.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 0ce81324b9..2c9e249ab6 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -62,7 +62,6 @@ static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; - struct clk clk, clk_x, clk_ecc; struct resource res; int ret; @@ -87,11 +86,14 @@ static int denali_dt_probe(struct udevice *dev) denali->host = devm_ioremap(dev, res.start, resource_size(&res)); +#if CONFIG_IS_ENABLED(CLK) + struct clk clk, clk_x, clk_ecc; + ret = clk_get_by_name(dev, "nand", &clk); if (ret) ret = clk_get_by_index(dev, 0, &clk); if (ret) - return ret; + clk.dev = NULL; ret = clk_get_by_name(dev, "nand_x", &clk_x); if (ret) @@ -117,10 +119,12 @@ static int denali_dt_probe(struct udevice *dev) return ret; } - if (clk_x.dev) { + if (clk.dev && clk_x.dev) { denali->clk_rate = clk_get_rate(&clk); denali->clk_x_rate = clk_get_rate(&clk_x); - } else { + } else +#endif + { /* * Hardcode the clock rates for the backward compatibility. * This works for both SOCFPGA and UniPhier. From patchwork Thu Jan 9 10:07:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 239303 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Thu, 9 Jan 2020 11:07:54 +0100 Subject: [PATCH 3/3] mtd: rawnand: denali: Do not reset the block on SoCFPGA In-Reply-To: <20200109100754.1007705-1-marex@denx.de> References: <20200109100754.1007705-1-marex@denx.de> Message-ID: <20200109100754.1007705-3-marex@denx.de> Legacy kernel versions for SoCFPGA may not implement proper reset handling. Apply the same approach as SoCFPGA reset driver, check environment variable "socfpga_legacy_reset_compat", and if it is set, do not reset the IP before booting Linux. This way, even the older kernel versions can be booted by up to date U-Boot. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mtd/nand/raw/denali_dt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 2c9e249ab6..d35f2a3543 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -148,6 +148,18 @@ static int denali_dt_remove(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); +#if CONFIG_IS_ENABLED(ARCH_SOCFPGA) + /* + * Legacy kernel versions do not implement proper reset handling on + * SoCFPGA. To let those older kernel versions work, reuse the same + * approach as the SoCFPGA reset driver does -- check environment + * variable socfpga_legacy_reset_compat and avoid resetting the IP + * before booting the kernel if it is set to 1. + */ + if (env_get_ulong("socfpga_legacy_reset_compat", 10, 0)) + return 0; +#endif + return reset_release_bulk(&denali->resets); }