From patchwork Tue Jan 7 07:15:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 239183 List-Id: U-Boot discussion From: kever.yang at rock-chips.com (Kever Yang) Date: Tue, 7 Jan 2020 15:15:20 +0800 Subject: [PATCH 1/3] ram: rk3328: only do data traning for cs0 Message-ID: <20200107071523.9369-1-kever.yang@rock-chips.com> No need to do twice data training for rk3328 ddr sdram, we re-use the setting for both channel. And adjust the sdram_init properly for correct init flow. Signed-off-by: Kever Yang Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3328.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 69521cef69..8329f4a352 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -377,16 +377,12 @@ static int sdram_init(struct dram_info *dram, printf("data training error\n"); return -1; } - if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { - printf("data training error\n"); - return -1; - } if (sdram_params->base.dramtype == DDR4) pctl_write_vrefdq(dram->pctl, 0x3, 5670, sdram_params->base.dramtype); - if (pre_init == 0) { + if (pre_init != 0) { rx_deskew_switch_adjust(dram); tx_deskew_switch_adjust(dram); } @@ -482,7 +478,7 @@ static int sdram_init_detect(struct dram_info *dram, memcpy(&sdram_ch, &sdram_params->ch, sizeof(struct rk3328_sdram_channel)); - sdram_init(dram, sdram_params, 1); + sdram_init(dram, sdram_params, 0); dram_detect_cap(dram, sdram_params, 0); /* modify bw, cs related timing */ @@ -495,7 +491,7 @@ static int sdram_init_detect(struct dram_info *dram, sdram_ch.noc_timings.ddrtiming.b.bwratio = 1; /* reinit sdram by real dram cap */ - sdram_init(dram, sdram_params, 0); + sdram_init(dram, sdram_params, 1); /* redetect cs1 row */ sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); From patchwork Tue Jan 7 07:15:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 239184 List-Id: U-Boot discussion From: kever.yang at rock-chips.com (Kever Yang) Date: Tue, 7 Jan 2020 15:15:21 +0800 Subject: [PATCH 2/3] ram: rk3328: add support ddr4 init In-Reply-To: <20200107071523.9369-1-kever.yang@rock-chips.com> References: <20200107071523.9369-1-kever.yang@rock-chips.com> Message-ID: <20200107151447.2.I7c15dbe939b0dfcdec27f6a58409e2ec9cb337a8@changeid> From: YouMin Chen Add rk3328-sdram-ddr4-666.dtsi for support ddr4 init. Signed-off-by: YouMin Chen Signed-off-by: Kever Yang --- arch/arm/dts/rk3328-sdram-ddr4-666.dtsi | 216 ++++++++++++++++++++++++ 1 file changed, 216 insertions(+) create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-666.dtsi diff --git a/arch/arm/dts/rk3328-sdram-ddr4-666.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-666.dtsi new file mode 100644 index 0000000000..0859649a69 --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-ddr4-666.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xA + 0x2 + 0x1 + 0x0 + 0x0 + 0x11 + 0x0 + 0x11 + 0x0 + 0 + + 0x94291288 + 0x00000000 + 0x00000027 + 0x00000462 + 0x00000015 + 0x00000242 + 0x000000ff + + 333 + 0 + 1 + 0 + 0 + + 0x00000000 + 0x43049010 + 0x00000064 + 0x0028003b + 0x000000d0 + 0x00020053 + 0x000000d4 + 0x00220000 + 0x000000d8 + 0x00000100 + 0x000000dc + 0x00040000 + 0x000000e0 + 0x00000000 + 0x000000e4 + 0x00110000 + 0x000000e8 + 0x00000420 + 0x000000ec + 0x00000400 + 0x000000f4 + 0x000f011f + 0x00000100 + 0x09060b06 + 0x00000104 + 0x00020209 + 0x00000108 + 0x0505040a + 0x0000010c + 0x0040400c + 0x00000110 + 0x05030206 + 0x00000114 + 0x03030202 + 0x00000120 + 0x03030b03 + 0x00000124 + 0x00020208 + 0x00000180 + 0x01000040 + 0x00000184 + 0x00000000 + 0x00000190 + 0x07030003 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x06000604 + 0x00000244 + 0x00000201 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000c + 0x00000028 + 0x0000000a + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000009 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; From patchwork Tue Jan 7 07:15:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 239185 List-Id: U-Boot discussion From: kever.yang at rock-chips.com (Kever Yang) Date: Tue, 7 Jan 2020 15:15:22 +0800 Subject: [PATCH 3/3] ram: rk3328: update lpddr3 setting In-Reply-To: <20200107071523.9369-1-kever.yang@rock-chips.com> References: <20200107071523.9369-1-kever.yang@rock-chips.com> Message-ID: <20200107151447.3.Ic6fab4d884350c13bcbc50d5a7b2c6d7a652a9cf@changeid> From: YouMin Chen update lpddr3 setting for fix init fail about "col error". Signed-off-by: YouMin Chen Signed-off-by: Kever Yang --- arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi index b9d3b3b948..df42bb29ce 100644 --- a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi +++ b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi @@ -18,7 +18,7 @@ 0x10 0 - 0x0c48a18a + 0x8c48a18a 0x00000000 0x00000021 0x00000482 @@ -33,7 +33,7 @@ 0 0x00000000 - 0xc3040008 + 0x43041008 0x00000064 0x00140023 0x000000d0 @@ -48,6 +48,8 @@ 0x00010000 0x000000e4 0x00070003 + 0x000000f4 + 0x000f011f 0x00000100 0x06090b07 0x00000104 @@ -90,8 +92,6 @@ 0xffffffff 0xffffffff 0xffffffff - 0xffffffff - 0xffffffff 0x00000004 0x0000000b