From patchwork Mon Oct 2 12:08:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 114582 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp605914qgn; Mon, 2 Oct 2017 05:10:27 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBRertcNDNyu7c5lkzysUWKkVU8t92L8fHfBfrdVkTGXcJogbhb/tDHAfAlfDL234Eub+yC X-Received: by 10.99.152.68 with SMTP id l4mr3618881pgo.443.1506946227220; Mon, 02 Oct 2017 05:10:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506946227; cv=none; d=google.com; s=arc-20160816; b=ZfpoEY24x+5UeT54snoeeA8fJS9yEEQDefD93hxDRbDhuYJVbc+kOczQyjwZYhEd5M 0YUIuHw9Cy2R0c0B+p6u1JO8Ekl/jXuzpGOj796TX3741ZvisWfolCPA50epRCzgXrUm JJFcGzqsHPnxjDH43BUnbNJID3rJ8YsW0EVUHLHwSXlyG8+Rzk1qPUHUw2/goyqlq2eM xbE4qws2Uwv84lj9f6jK7lB1prWJ0bkFZaKFHotGh8LsFfMkZRey0Z8VwcO6FAzua2p8 b+hlSbcqE1MirzvQwhGjfNynW1d6xlbnLyXWZrjR6QuKRZfKnjK3Y7386YupVZ63bmtq at2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=hHfTQ4fzKp062jF+0F3ZaGPIX7Zo79lqqs/uQzXj8Zg=; b=Jf9ZYKD2C6qWO3wNRSE3kbOpERzAcUYfyrRdHPaK4vBgv9B07uj0kw4xV8thFbgFMg ycZ6pOcaGkmlYrU+wbhdyQanVQywkxHK4VFW+CVmhWX2HLZLP3lreOsZ3qylsLinXhgB BI3kePmRl3LwuTofUiwmos6eAjQ6kR3n1EffX7os8EBv4yQI2DPQBC9UG3I3gTNxSD7U zYR3XrsM16wMIMSt3SQl0ucuE4RzaglgQNjQLuta4kHFvpbRgI3FQJ4NvgrBKJHe9xLq yL5twaKyUH+lVyjb8ML2D+wM6s58qQzCVzjkhW4zTYcZ8Z1y9s2XFeCMgnagaElWXlLQ AIlw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z11si4124332plo.149.2017.10.02.05.10.26; Mon, 02 Oct 2017 05:10:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751474AbdJBMKL (ORCPT + 26 others); Mon, 2 Oct 2017 08:10:11 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45529 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751188AbdJBMKE (ORCPT ); Mon, 2 Oct 2017 08:10:04 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id B79EE20A19; Mon, 2 Oct 2017 14:10:01 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 58B4720A16; Mon, 2 Oct 2017 14:10:01 +0200 (CEST) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v3 02/12] pinctrl: axp209: add pinctrl features Date: Mon, 2 Oct 2017 14:08:44 +0200 Message-Id: <20171002120854.5212-3-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002120854.5212-1-quentin.schulz@free-electrons.com> References: <20171002120854.5212-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The X-Powers AXP209 has 3 GPIOs. GPIO0/1 can each act either as a GPIO, an ADC or a LDO regulator. GPIO2 can only act as a GPIO. This adds the pinctrl features to the driver so GPIO0/1 can be used as ADC or LDO regulator. Signed-off-by: Quentin Schulz --- .../devicetree/bindings/pinctrl/pinctrl-axp209.txt | 28 +- drivers/pinctrl/pinctrl-axp209.c | 293 +++++++++++++++++++-- 2 files changed, 300 insertions(+), 21 deletions(-) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-axp209.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-axp209.txt index a6611304dd3c..388c04492afd 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-axp209.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-axp209.txt @@ -1,4 +1,4 @@ -AXP209 GPIO controller +AXP209 GPIO & pinctrl controller This driver follows the usual GPIO bindings found in Documentation/devicetree/bindings/gpio/gpio.txt @@ -28,3 +28,29 @@ axp209: pmic@34 { #gpio-cells = <2>; }; }; + +The GPIOs can be muxed to other functions and therefore, must be a subnode of +axp_gpio. + +Example: + +&axp_gpio { + gpio0_adc: gpio0_adc { + pins = "GPIO0"; + function = "adc"; + }; +}; + +&example_node { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_adc>; +}; + +GPIOs and their functions +------------------------- + +GPIO | Functions +------------------------ +GPIO0 | gpio_in, gpio_out, ldo, adc +GPIO1 | gpio_in, gpio_out, ldo, adc +GPIO2 | gpio_in, gpio_out diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index 4a346b7b4172..96ef0cc28762 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -1,7 +1,8 @@ /* - * AXP20x GPIO driver + * AXP20x pinctrl and GPIO driver * * Copyright (C) 2016 Maxime Ripard + * Copyright (C) 2017 Quentin Schulz * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -22,14 +23,57 @@ #include #include +#include +#include +#include + #define AXP20X_GPIO_FUNCTIONS 0x7 #define AXP20X_GPIO_FUNCTION_OUT_LOW 0 #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1 #define AXP20X_GPIO_FUNCTION_INPUT 2 +#define AXP20X_FUNC_GPIO_OUT 0 +#define AXP20X_FUNC_GPIO_IN 1 +#define AXP20X_FUNC_LDO 2 +#define AXP20X_FUNC_ADC 3 +#define AXP20X_FUNCS_NB 4 + +struct axp20x_pctrl_desc { + const struct pinctrl_pin_desc *pins; + unsigned int npins; + /* Stores the pins supporting LDO function. Bit offset is pin number. */ + unsigned int ldo_mask; + /* Stores the pins supporting ADC function. Bit offset is pin number. */ + unsigned int adc_mask; +}; + +struct axp20x_pinctrl_function { + const char *name; + unsigned int muxval; + const char **groups; + unsigned int ngroups; +}; + struct axp20x_gpio { struct gpio_chip chip; struct regmap *regmap; + struct pinctrl_dev *pctl_dev; + struct device *dev; + const struct axp20x_pctrl_desc *desc; + struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB]; +}; + +static const struct pinctrl_pin_desc axp209_pins[] = { + PINCTRL_PIN(0, "GPIO0"), + PINCTRL_PIN(1, "GPIO1"), + PINCTRL_PIN(2, "GPIO2"), +}; + +static const struct axp20x_pctrl_desc axp20x_data = { + .pins = axp209_pins, + .npins = ARRAY_SIZE(axp209_pins), + .ldo_mask = BIT(0) | BIT(1), + .adc_mask = BIT(0) | BIT(1), }; static int axp20x_gpio_get_reg(unsigned offset) @@ -48,16 +92,7 @@ static int axp20x_gpio_get_reg(unsigned offset) static int axp20x_gpio_input(struct gpio_chip *chip, unsigned offset) { - struct axp20x_gpio *gpio = gpiochip_get_data(chip); - int reg; - - reg = axp20x_gpio_get_reg(offset); - if (reg < 0) - return reg; - - return regmap_update_bits(gpio->regmap, reg, - AXP20X_GPIO_FUNCTIONS, - AXP20X_GPIO_FUNCTION_INPUT); + return pinctrl_gpio_direction_input(chip->base + offset); } static int axp20x_gpio_get(struct gpio_chip *chip, unsigned offset) @@ -105,29 +140,210 @@ static int axp20x_gpio_get_direction(struct gpio_chip *chip, unsigned offset) static int axp20x_gpio_output(struct gpio_chip *chip, unsigned offset, int value) { + chip->set(chip, offset, value); + + return 0; +} + +static void axp20x_gpio_set(struct gpio_chip *chip, unsigned offset, + int value) +{ struct axp20x_gpio *gpio = gpiochip_get_data(chip); int reg; reg = axp20x_gpio_get_reg(offset); if (reg < 0) + return; + + regmap_update_bits(gpio->regmap, reg, + AXP20X_GPIO_FUNCTIONS, + value ? AXP20X_GPIO_FUNCTION_OUT_HIGH : + AXP20X_GPIO_FUNCTION_OUT_LOW); +} + +static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset, + u8 config) +{ + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + int reg; + + reg = axp20x_gpio_get_reg(offset); + if (reg < 0) return reg; - return regmap_update_bits(gpio->regmap, reg, - AXP20X_GPIO_FUNCTIONS, - value ? AXP20X_GPIO_FUNCTION_OUT_HIGH - : AXP20X_GPIO_FUNCTION_OUT_LOW); + return regmap_update_bits(gpio->regmap, reg, AXP20X_GPIO_FUNCTIONS, + config); } -static void axp20x_gpio_set(struct gpio_chip *chip, unsigned offset, - int value) +static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev) +{ + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + + return ARRAY_SIZE(gpio->funcs); +} + +static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) { - axp20x_gpio_output(chip, offset, value); + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + + return gpio->funcs[selector].name; +} + +static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int *num_groups) +{ + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + + *groups = gpio->funcs[selector].groups; + *num_groups = gpio->funcs[selector].ngroups; + + return 0; +} + +static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + unsigned int mask; + + /* Every pin supports GPIO_OUT and GPIO_IN functions */ + if (function <= AXP20X_FUNC_GPIO_IN) + return axp20x_pmx_set(pctldev, group, + gpio->funcs[function].muxval); + + if (function == AXP20X_FUNC_LDO) + mask = gpio->desc->ldo_mask; + else + mask = gpio->desc->adc_mask; + + if (!(BIT(group) & mask)) + return -EINVAL; + + return axp20x_pmx_set(pctldev, group, gpio->funcs[function].muxval); +} + +static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + + if (input) + return axp20x_pmx_set(pctldev, offset, + gpio->funcs[AXP20X_FUNC_GPIO_IN].muxval); + + return axp20x_pmx_set(pctldev, offset, + gpio->funcs[AXP20X_FUNC_GPIO_OUT].muxval); +} + +static const struct pinmux_ops axp20x_pmx_ops = { + .get_functions_count = axp20x_pmx_func_cnt, + .get_function_name = axp20x_pmx_func_name, + .get_function_groups = axp20x_pmx_func_groups, + .set_mux = axp20x_pmx_set_mux, + .gpio_set_direction = axp20x_pmx_gpio_set_direction, + .strict = true, +}; + +static int axp20x_groups_cnt(struct pinctrl_dev *pctldev) +{ + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + + return gpio->desc->npins; +} + +static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned int *)&gpio->desc->pins[selector]; + *num_pins = 1; + + return 0; +} + +static const char *axp20x_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + + return gpio->desc->pins[selector].name; +} + +static const struct pinctrl_ops axp20x_pctrl_ops = { + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinconf_generic_dt_free_map, + .get_groups_count = axp20x_groups_cnt, + .get_group_name = axp20x_group_name, + .get_group_pins = axp20x_group_pins, +}; + +static void axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask, + unsigned int mask_len, + struct axp20x_pinctrl_function *func, + const struct pinctrl_pin_desc *pins) +{ + unsigned long int mask_cpy = mask; + const char **group; + unsigned int ngroups = hweight8(mask); + int bit; + + func->ngroups = ngroups; + if (func->ngroups > 0) { + func->groups = devm_kzalloc(dev, ngroups * sizeof(const char *), + GFP_KERNEL); + group = func->groups; + for_each_set_bit(bit, &mask_cpy, mask_len) { + *group = pins[bit].name; + group++; + } + } +} + +static void axp20x_build_funcs_groups(struct platform_device *pdev) +{ + struct axp20x_gpio *gpio = platform_get_drvdata(pdev); + int i, pin; + + gpio->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out"; + gpio->funcs[AXP20X_FUNC_GPIO_OUT].muxval = 0x0; + gpio->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in"; + gpio->funcs[AXP20X_FUNC_GPIO_IN].muxval = 0x2; + gpio->funcs[AXP20X_FUNC_LDO].name = "ldo"; + gpio->funcs[AXP20X_FUNC_LDO].muxval = 0x3; + gpio->funcs[AXP20X_FUNC_ADC].name = "adc"; + gpio->funcs[AXP20X_FUNC_ADC].muxval = 0x4; + + /* Every pin supports GPIO_OUT and GPIO_IN functions */ + for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) { + gpio->funcs[i].ngroups = gpio->desc->npins; + gpio->funcs[i].groups = devm_kzalloc(&pdev->dev, + gpio->desc->npins * sizeof(const char *), + GFP_KERNEL); + for (pin = 0; pin < gpio->desc->npins; pin++) + gpio->funcs[i].groups[pin] = gpio->desc->pins[pin].name; + } + + axp20x_funcs_groups_from_mask(&pdev->dev, gpio->desc->ldo_mask, + gpio->desc->npins, + &gpio->funcs[AXP20X_FUNC_LDO], + gpio->desc->pins); + + axp20x_funcs_groups_from_mask(&pdev->dev, gpio->desc->adc_mask, + gpio->desc->npins, + &gpio->funcs[AXP20X_FUNC_ADC], + gpio->desc->pins); } static int axp20x_gpio_probe(struct platform_device *pdev) { struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); struct axp20x_gpio *gpio; + struct pinctrl_desc *pctrl_desc; int ret; if (!of_device_is_available(pdev->dev.of_node)) @@ -144,6 +360,8 @@ static int axp20x_gpio_probe(struct platform_device *pdev) gpio->chip.base = -1; gpio->chip.can_sleep = true; + gpio->chip.request = gpiochip_generic_request; + gpio->chip.free = gpiochip_generic_free; gpio->chip.parent = &pdev->dev; gpio->chip.label = dev_name(&pdev->dev); gpio->chip.owner = THIS_MODULE; @@ -154,15 +372,49 @@ static int axp20x_gpio_probe(struct platform_device *pdev) gpio->chip.direction_output = axp20x_gpio_output; gpio->chip.ngpio = 3; + gpio->desc = &axp20x_data; + gpio->regmap = axp20x->regmap; + gpio->dev = &pdev->dev; + + platform_set_drvdata(pdev, gpio); + + axp20x_build_funcs_groups(pdev); + + pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL); + if (!pctrl_desc) + return -ENOMEM; + + pctrl_desc->name = dev_name(&pdev->dev); + pctrl_desc->owner = THIS_MODULE; + pctrl_desc->pins = gpio->desc->pins; + pctrl_desc->npins = gpio->desc->npins; + pctrl_desc->pctlops = &axp20x_pctrl_ops; + pctrl_desc->pmxops = &axp20x_pmx_ops; + + gpio->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, gpio); + if (IS_ERR(gpio->pctl_dev)) { + dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); + return PTR_ERR(gpio->pctl_dev); + } + ret = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); if (ret) { dev_err(&pdev->dev, "Failed to register GPIO chip\n"); return ret; } - dev_info(&pdev->dev, "AXP209 GPIO driver loaded\n"); + ret = gpiochip_add_pin_range(&gpio->chip, dev_name(&pdev->dev), + gpio->desc->pins->number, + gpio->desc->pins->number, + gpio->desc->npins); + if (ret) { + dev_err(&pdev->dev, "failed to add pin range\n"); + return ret; + } + + dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n"); return 0; } @@ -184,5 +436,6 @@ static struct platform_driver axp20x_gpio_driver = { module_platform_driver(axp20x_gpio_driver); MODULE_AUTHOR("Maxime Ripard "); -MODULE_DESCRIPTION("AXP20x PMIC GPIO driver"); +MODULE_AUTHOR("Quentin Schulz "); +MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver"); MODULE_LICENSE("GPL"); From patchwork Mon Oct 2 12:08:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 114591 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp608631qgn; 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[209.132.180.67]) by mx.google.com with ESMTP id f35si4426465plh.346.2017.10.02.05.13.05; Mon, 02 Oct 2017 05:13:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751926AbdJBMNC (ORCPT + 26 others); Mon, 2 Oct 2017 08:13:02 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45542 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751193AbdJBMKE (ORCPT ); Mon, 2 Oct 2017 08:10:04 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 0ED1520A1A; Mon, 2 Oct 2017 14:10:02 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id A756620824; Mon, 2 Oct 2017 14:10:01 +0200 (CEST) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v3 03/12] pinctrl: axp209: rename everything from gpio to pctl Date: Mon, 2 Oct 2017 14:08:45 +0200 Message-Id: <20171002120854.5212-4-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002120854.5212-1-quentin.schulz@free-electrons.com> References: <20171002120854.5212-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver used to do only GPIO features of the GPIOs in X-Powers AXP20X. Now that we have migrated everything to the pinctrl subsystem and added pinctrl features, rename everything related to pinctrl from gpio to pctl to ease the understanding of differences between GPIO and pinctrl features. Signed-off-by: Quentin Schulz --- drivers/pinctrl/pinctrl-axp209.c | 178 +++++++++++++++++++-------------------- 1 file changed, 89 insertions(+), 89 deletions(-) -- 2.11.0 diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index 96ef0cc28762..3ddeba45feed 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -54,7 +54,7 @@ struct axp20x_pinctrl_function { unsigned int ngroups; }; -struct axp20x_gpio { +struct axp20x_pctl { struct gpio_chip chip; struct regmap *regmap; struct pinctrl_dev *pctl_dev; @@ -97,11 +97,11 @@ static int axp20x_gpio_input(struct gpio_chip *chip, unsigned offset) static int axp20x_gpio_get(struct gpio_chip *chip, unsigned offset) { - struct axp20x_gpio *gpio = gpiochip_get_data(chip); + struct axp20x_pctl *pctl = gpiochip_get_data(chip); unsigned int val; int ret; - ret = regmap_read(gpio->regmap, AXP20X_GPIO20_SS, &val); + ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val); if (ret) return ret; @@ -110,7 +110,7 @@ static int axp20x_gpio_get(struct gpio_chip *chip, unsigned offset) static int axp20x_gpio_get_direction(struct gpio_chip *chip, unsigned offset) { - struct axp20x_gpio *gpio = gpiochip_get_data(chip); + struct axp20x_pctl *pctl = gpiochip_get_data(chip); unsigned int val; int reg, ret; @@ -118,7 +118,7 @@ static int axp20x_gpio_get_direction(struct gpio_chip *chip, unsigned offset) if (reg < 0) return reg; - ret = regmap_read(gpio->regmap, reg, &val); + ret = regmap_read(pctl->regmap, reg, &val); if (ret) return ret; @@ -148,14 +148,14 @@ static int axp20x_gpio_output(struct gpio_chip *chip, unsigned offset, static void axp20x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - struct axp20x_gpio *gpio = gpiochip_get_data(chip); + struct axp20x_pctl *pctl = gpiochip_get_data(chip); int reg; reg = axp20x_gpio_get_reg(offset); if (reg < 0) return; - regmap_update_bits(gpio->regmap, reg, + regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS, value ? AXP20X_GPIO_FUNCTION_OUT_HIGH : AXP20X_GPIO_FUNCTION_OUT_LOW); @@ -164,30 +164,30 @@ static void axp20x_gpio_set(struct gpio_chip *chip, unsigned offset, static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset, u8 config) { - struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); int reg; reg = axp20x_gpio_get_reg(offset); if (reg < 0) return reg; - return regmap_update_bits(gpio->regmap, reg, AXP20X_GPIO_FUNCTIONS, + return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS, config); } static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev) { - struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); - return ARRAY_SIZE(gpio->funcs); + return ARRAY_SIZE(pctl->funcs); } static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev, unsigned int selector) { - struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); - return gpio->funcs[selector].name; + return pctl->funcs[selector].name; } static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev, @@ -195,10 +195,10 @@ static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev, const char * const **groups, unsigned int *num_groups) { - struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); - *groups = gpio->funcs[selector].groups; - *num_groups = gpio->funcs[selector].ngroups; + *groups = pctl->funcs[selector].groups; + *num_groups = pctl->funcs[selector].ngroups; return 0; } @@ -206,37 +206,37 @@ static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev, static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { - struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); unsigned int mask; /* Every pin supports GPIO_OUT and GPIO_IN functions */ if (function <= AXP20X_FUNC_GPIO_IN) return axp20x_pmx_set(pctldev, group, - gpio->funcs[function].muxval); + pctl->funcs[function].muxval); if (function == AXP20X_FUNC_LDO) - mask = gpio->desc->ldo_mask; + mask = pctl->desc->ldo_mask; else - mask = gpio->desc->adc_mask; + mask = pctl->desc->adc_mask; if (!(BIT(group) & mask)) return -EINVAL; - return axp20x_pmx_set(pctldev, group, gpio->funcs[function].muxval); + return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval); } static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset, bool input) { - struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); if (input) return axp20x_pmx_set(pctldev, offset, - gpio->funcs[AXP20X_FUNC_GPIO_IN].muxval); + pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval); return axp20x_pmx_set(pctldev, offset, - gpio->funcs[AXP20X_FUNC_GPIO_OUT].muxval); + pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval); } static const struct pinmux_ops axp20x_pmx_ops = { @@ -250,17 +250,17 @@ static const struct pinmux_ops axp20x_pmx_ops = { static int axp20x_groups_cnt(struct pinctrl_dev *pctldev) { - struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); - return gpio->desc->npins; + return pctl->desc->npins; } static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, const unsigned int **pins, unsigned int *num_pins) { - struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); - *pins = (unsigned int *)&gpio->desc->pins[selector]; + *pins = (unsigned int *)&pctl->desc->pins[selector]; *num_pins = 1; return 0; @@ -269,9 +269,9 @@ static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, static const char *axp20x_group_name(struct pinctrl_dev *pctldev, unsigned int selector) { - struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev); + struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); - return gpio->desc->pins[selector].name; + return pctl->desc->pins[selector].name; } static const struct pinctrl_ops axp20x_pctrl_ops = { @@ -306,43 +306,43 @@ static void axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask, static void axp20x_build_funcs_groups(struct platform_device *pdev) { - struct axp20x_gpio *gpio = platform_get_drvdata(pdev); + struct axp20x_pctl *pctl = platform_get_drvdata(pdev); int i, pin; - gpio->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out"; - gpio->funcs[AXP20X_FUNC_GPIO_OUT].muxval = 0x0; - gpio->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in"; - gpio->funcs[AXP20X_FUNC_GPIO_IN].muxval = 0x2; - gpio->funcs[AXP20X_FUNC_LDO].name = "ldo"; - gpio->funcs[AXP20X_FUNC_LDO].muxval = 0x3; - gpio->funcs[AXP20X_FUNC_ADC].name = "adc"; - gpio->funcs[AXP20X_FUNC_ADC].muxval = 0x4; + pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out"; + pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = 0x0; + pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in"; + pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = 0x2; + pctl->funcs[AXP20X_FUNC_LDO].name = "ldo"; + pctl->funcs[AXP20X_FUNC_LDO].muxval = 0x3; + pctl->funcs[AXP20X_FUNC_ADC].name = "adc"; + pctl->funcs[AXP20X_FUNC_ADC].muxval = 0x4; /* Every pin supports GPIO_OUT and GPIO_IN functions */ for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) { - gpio->funcs[i].ngroups = gpio->desc->npins; - gpio->funcs[i].groups = devm_kzalloc(&pdev->dev, - gpio->desc->npins * sizeof(const char *), + pctl->funcs[i].ngroups = pctl->desc->npins; + pctl->funcs[i].groups = devm_kzalloc(&pdev->dev, + pctl->desc->npins * sizeof(const char *), GFP_KERNEL); - for (pin = 0; pin < gpio->desc->npins; pin++) - gpio->funcs[i].groups[pin] = gpio->desc->pins[pin].name; + for (pin = 0; pin < pctl->desc->npins; pin++) + pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name; } - axp20x_funcs_groups_from_mask(&pdev->dev, gpio->desc->ldo_mask, - gpio->desc->npins, - &gpio->funcs[AXP20X_FUNC_LDO], - gpio->desc->pins); + axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask, + pctl->desc->npins, + &pctl->funcs[AXP20X_FUNC_LDO], + pctl->desc->pins); - axp20x_funcs_groups_from_mask(&pdev->dev, gpio->desc->adc_mask, - gpio->desc->npins, - &gpio->funcs[AXP20X_FUNC_ADC], - gpio->desc->pins); + axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask, + pctl->desc->npins, + &pctl->funcs[AXP20X_FUNC_ADC], + pctl->desc->pins); } -static int axp20x_gpio_probe(struct platform_device *pdev) +static int axp20x_pctl_probe(struct platform_device *pdev) { struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); - struct axp20x_gpio *gpio; + struct axp20x_pctl *pctl; struct pinctrl_desc *pctrl_desc; int ret; @@ -354,31 +354,31 @@ static int axp20x_gpio_probe(struct platform_device *pdev) return -EINVAL; } - gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); - if (!gpio) + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) return -ENOMEM; - gpio->chip.base = -1; - gpio->chip.can_sleep = true; - gpio->chip.request = gpiochip_generic_request; - gpio->chip.free = gpiochip_generic_free; - gpio->chip.parent = &pdev->dev; - gpio->chip.label = dev_name(&pdev->dev); - gpio->chip.owner = THIS_MODULE; - gpio->chip.get = axp20x_gpio_get; - gpio->chip.get_direction = axp20x_gpio_get_direction; - gpio->chip.set = axp20x_gpio_set; - gpio->chip.direction_input = axp20x_gpio_input; - gpio->chip.direction_output = axp20x_gpio_output; - gpio->chip.ngpio = 3; + pctl->chip.base = -1; + pctl->chip.can_sleep = true; + pctl->chip.request = gpiochip_generic_request; + pctl->chip.free = gpiochip_generic_free; + pctl->chip.parent = &pdev->dev; + pctl->chip.label = dev_name(&pdev->dev); + pctl->chip.owner = THIS_MODULE; + pctl->chip.get = axp20x_gpio_get; + pctl->chip.get_direction = axp20x_gpio_get_direction; + pctl->chip.set = axp20x_gpio_set; + pctl->chip.direction_input = axp20x_gpio_input; + pctl->chip.direction_output = axp20x_gpio_output; + pctl->chip.ngpio = 3; - gpio->desc = &axp20x_data; + pctl->desc = &axp20x_data; - gpio->regmap = axp20x->regmap; + pctl->regmap = axp20x->regmap; - gpio->dev = &pdev->dev; + pctl->dev = &pdev->dev; - platform_set_drvdata(pdev, gpio); + platform_set_drvdata(pdev, pctl); axp20x_build_funcs_groups(pdev); @@ -388,27 +388,27 @@ static int axp20x_gpio_probe(struct platform_device *pdev) pctrl_desc->name = dev_name(&pdev->dev); pctrl_desc->owner = THIS_MODULE; - pctrl_desc->pins = gpio->desc->pins; - pctrl_desc->npins = gpio->desc->npins; + pctrl_desc->pins = pctl->desc->pins; + pctrl_desc->npins = pctl->desc->npins; pctrl_desc->pctlops = &axp20x_pctrl_ops; pctrl_desc->pmxops = &axp20x_pmx_ops; - gpio->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, gpio); - if (IS_ERR(gpio->pctl_dev)) { + pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); + if (IS_ERR(pctl->pctl_dev)) { dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); - return PTR_ERR(gpio->pctl_dev); + return PTR_ERR(pctl->pctl_dev); } - ret = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); + ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl); if (ret) { dev_err(&pdev->dev, "Failed to register GPIO chip\n"); return ret; } - ret = gpiochip_add_pin_range(&gpio->chip, dev_name(&pdev->dev), - gpio->desc->pins->number, - gpio->desc->pins->number, - gpio->desc->npins); + ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev), + pctl->desc->pins->number, + pctl->desc->pins->number, + pctl->desc->npins); if (ret) { dev_err(&pdev->dev, "failed to add pin range\n"); return ret; @@ -419,21 +419,21 @@ static int axp20x_gpio_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id axp20x_gpio_match[] = { +static const struct of_device_id axp20x_pctl_match[] = { { .compatible = "x-powers,axp209-gpio" }, { } }; -MODULE_DEVICE_TABLE(of, axp20x_gpio_match); +MODULE_DEVICE_TABLE(of, axp20x_pctl_match); -static struct platform_driver axp20x_gpio_driver = { - .probe = axp20x_gpio_probe, +static struct platform_driver axp20x_pctl_driver = { + .probe = axp20x_pctl_probe, .driver = { .name = "axp20x-gpio", - .of_match_table = axp20x_gpio_match, + .of_match_table = axp20x_pctl_match, }, }; -module_platform_driver(axp20x_gpio_driver); +module_platform_driver(axp20x_pctl_driver); MODULE_AUTHOR("Maxime Ripard "); MODULE_AUTHOR("Quentin Schulz "); From patchwork Mon Oct 2 12:08:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 114588 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp608013qgn; Mon, 2 Oct 2017 05:12:28 -0700 (PDT) X-Google-Smtp-Source: AOwi7QD1SkhrsNyTu39rh1b6f4tWFM1i9fnFE4rLlQIVK6cFYDHXdkqN7fScBVaTRowrhO6+xklE X-Received: by 10.98.49.67 with SMTP id x64mr14697227pfx.11.1506946348211; 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[209.132.180.67]) by mx.google.com with ESMTP id 3si8068776pli.407.2017.10.02.05.12.27; Mon, 02 Oct 2017 05:12:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751875AbdJBMM0 (ORCPT + 26 others); Mon, 2 Oct 2017 08:12:26 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45582 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751214AbdJBMKG (ORCPT ); Mon, 2 Oct 2017 08:10:06 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id A791C20A1E; Mon, 2 Oct 2017 14:10:02 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 4820020A17; Mon, 2 Oct 2017 14:10:02 +0200 (CEST) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v3 05/12] pinctrl: axp209: add support for AXP813 GPIOs Date: Mon, 2 Oct 2017 14:08:47 +0200 Message-Id: <20171002120854.5212-6-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002120854.5212-1-quentin.schulz@free-electrons.com> References: <20171002120854.5212-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The AXP813 has only two GPIOs. GPIO0 can either be used as a GPIO, an LDO regulator or an ADC. GPIO1 can be used either as a GPIO or an LDO regulator. Moreover, the status bit of the GPIOs when in input mode is not offset by 4 unlike the AXP209. Signed-off-by: Quentin Schulz --- .../devicetree/bindings/pinctrl/pinctrl-axp209.txt | 13 ++++++++- drivers/pinctrl/pinctrl-axp209.c | 32 ++++++++++++++++------ 2 files changed, 36 insertions(+), 9 deletions(-) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-axp209.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-axp209.txt index 388c04492afd..a4e4dbef65d6 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-axp209.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-axp209.txt @@ -4,7 +4,9 @@ This driver follows the usual GPIO bindings found in Documentation/devicetree/bindings/gpio/gpio.txt Required properties: -- compatible: Should be "x-powers,axp209-gpio" +- compatible: Should be one of: + - "x-powers,axp209-gpio" + - "x-powers,axp813-gpio" - #gpio-cells: Should be two. The first cell is the pin number and the second is the GPIO flags. - gpio-controller: Marks the device node as a GPIO controller. @@ -49,8 +51,17 @@ Example: GPIOs and their functions ------------------------- +axp209 +------ GPIO | Functions ------------------------ GPIO0 | gpio_in, gpio_out, ldo, adc GPIO1 | gpio_in, gpio_out, ldo, adc GPIO2 | gpio_in, gpio_out + +axp813 +------ +GPIO | Functions +------------------------ +GPIO0 | gpio_in, gpio_out, ldo, adc +GPIO1 | gpio_in, gpio_out, ldo diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index 17146496b22a..4466b2541137 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -70,6 +71,11 @@ static const struct pinctrl_pin_desc axp209_pins[] = { PINCTRL_PIN(2, "GPIO2"), }; +static const struct pinctrl_pin_desc axp813_pins[] = { + PINCTRL_PIN(0, "GPIO0"), + PINCTRL_PIN(1, "GPIO1"), +}; + static const struct axp20x_pctrl_desc axp20x_data = { .pins = axp209_pins, .npins = ARRAY_SIZE(axp209_pins), @@ -78,6 +84,14 @@ static const struct axp20x_pctrl_desc axp20x_data = { .gpio_status_offset = 4, }; +static const struct axp20x_pctrl_desc axp813_data = { + .pins = axp813_pins, + .npins = ARRAY_SIZE(axp813_pins), + .ldo_mask = BIT(0) | BIT(1), + .adc_mask = BIT(0), + .gpio_status_offset = 0, +}; + static int axp20x_gpio_get_reg(unsigned offset) { switch (offset) { @@ -341,10 +355,18 @@ static void axp20x_build_funcs_groups(struct platform_device *pdev) pctl->desc->pins); } +static const struct of_device_id axp20x_pctl_match[] = { + { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, }, + { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, }, + { } +}; +MODULE_DEVICE_TABLE(of, axp20x_pctl_match); + static int axp20x_pctl_probe(struct platform_device *pdev) { struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); struct axp20x_pctl *pctl; + struct device *dev = &pdev->dev; struct pinctrl_desc *pctrl_desc; int ret; @@ -372,9 +394,9 @@ static int axp20x_pctl_probe(struct platform_device *pdev) pctl->chip.set = axp20x_gpio_set; pctl->chip.direction_input = axp20x_gpio_input; pctl->chip.direction_output = axp20x_gpio_output; - pctl->chip.ngpio = 3; + pctl->chip.ngpio = pctl->desc->npins; - pctl->desc = &axp20x_data; + pctl->desc = (struct axp20x_pctrl_desc *)of_device_get_match_data(dev); pctl->regmap = axp20x->regmap; @@ -421,12 +443,6 @@ static int axp20x_pctl_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id axp20x_pctl_match[] = { - { .compatible = "x-powers,axp209-gpio" }, - { } -}; -MODULE_DEVICE_TABLE(of, axp20x_pctl_match); - static struct platform_driver axp20x_pctl_driver = { .probe = axp20x_pctl_probe, .driver = { From patchwork Mon Oct 2 12:08:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 114589 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp608343qgn; Mon, 2 Oct 2017 05:12:46 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAebuTWAaOwl9AwtjObGNpcDj1uCRD1W7NpgU+eUyneV5RlFIpX8/cdlqGiFaqBwhwa1trE X-Received: by 10.98.15.211 with SMTP id 80mr685780pfp.24.1506946366118; Mon, 02 Oct 2017 05:12:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506946366; cv=none; d=google.com; s=arc-20160816; b=jAL3enNC3p0/U0ofyBpVbtMl3B66Bt/VRJ4RXk7ynt+tDLbZiG4K7UDIh2s+5/3tDw oiz//9Co7HYXf2S8nJVqc00u+afCZSzdlTQZINdTu+Jwz0yeAUrUKkeDCyQ6LUtlXmVF rpe2UIaVhkmNVPaC4QmXBdR0H+nLwDYA40I/QQCSvxUyK61opAQoRD0Ge+Bu0fD/nyC0 jWXuuq8qf8aIsNiLRUR7OqwJPmzYy1W59xKHrWlRkwhJswmIrhWwOt1IXIHIjiYz/tJg o/YWMdB+ZWPen3JMpXS/CzUTrzaZgsSIqpq/mID846UDo5FWCuaAQg6vL+4ypVkeZ1Bu oiqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=wWs8BpTfjiJ+xGsLpFTYmj90VSnLPpMYkdZTXKTmpYM=; b=oaoktH1cOX10+lancLkxRRf/7BSOvbfkOynpnkw7z7eLoe3RoRn1abanyd2c1vndUv skr26Z5Jh8Vd4Y82qBYMdCCMzy22KIHVuShdDTL6WZvdk26pkgcXORXJIXhwECELZ8Xm DoOA9qKb6qoNLBHlIq/cXjZPLBHyzpwDdw4Cz8xUumGkJ5uOkGq9yuN4n3S+NBTN7nls Vax1xF3ONb2p05FxhlTE1+71WIxmiad8t1bBq+88MrX/rEmP64u+/QRYtYDwgvESO32r yxA6b7K20rMjTdP6Z7+5ar3+tinw/hCFrfn475Alu23/HUOYHxsIkkBKfdJ76VXUwcm0 Sz6g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l7si7538000pgs.767.2017.10.02.05.12.45; Mon, 02 Oct 2017 05:12:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751891AbdJBMMn (ORCPT + 26 others); Mon, 2 Oct 2017 08:12:43 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45583 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751204AbdJBMKF (ORCPT ); Mon, 2 Oct 2017 08:10:05 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id E634520A23; Mon, 2 Oct 2017 14:10:02 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 8F31920A1C; Mon, 2 Oct 2017 14:10:02 +0200 (CEST) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v3 06/12] mfd: axp20x: add pinctrl cell for AXP813 Date: Mon, 2 Oct 2017 14:08:48 +0200 Message-Id: <20171002120854.5212-7-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002120854.5212-1-quentin.schulz@free-electrons.com> References: <20171002120854.5212-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As GPIO/pinctrl driver now supports AXP813, add a cell for it. Signed-off-by: Quentin Schulz --- drivers/mfd/axp20x.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.11.0 Acked-by: Maxime Ripard diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index 2468b431bb22..d8c92fbbd170 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -878,6 +878,9 @@ static struct mfd_cell axp813_cells[] = { .resources = axp803_pek_resources, }, { .name = "axp20x-regulator", + }, { + .name = "axp20x-gpio", + .of_compatible = "x-powers,axp813-gpio", } }; From patchwork Mon Oct 2 12:08:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 114587 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp607745qgn; Mon, 2 Oct 2017 05:12:13 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDTGGkNzisk5a6yKepfoRAFASrh8P0jK5Os0M9KlATCmVA7spPYVEmJX/3mF5sB0kMrLMlx X-Received: by 10.84.196.164 with SMTP id l33mr13992265pld.331.1506946333862; Mon, 02 Oct 2017 05:12:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506946333; cv=none; d=google.com; s=arc-20160816; b=tbLfzjYaefGboljC2o3m5kpuP7QrXujoa1Jt6SP3f40q25L+ESKor7dnlN2J1C5sec x0PaWp0FNUj2ybw+miZKllkl0PTVQBqnrEUAkm6cy3bds5Qig0Up3EY3yY71xGRjYicG zR3lF+hSsmcjV1NLAVeMxDKvbF+n+hmZAoCzdlqBlIStOmoEgO1TegNAWvP8P9J7Ay9f FPpDaUhbto0UiKFckpscJL8WeFbnw7mqpyr3g9aDzejpoSToRKCgWmjrdfwow1Ogj3xL RnqssP6sQBcqrVkQqx+t04WUj+tXKcvsq0DPvq7q9CFSs8+B0v3BJqz8PGZLnlfklb9h Y3hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=mgyLM+GwsRVJ2D7ZbbpJ9ppe6i+/KtSXvMTILtf6H3U=; b=So1jf16gAsz9QSCQ7FN9Tw+8Mp0s8fLtf5eq0K//iIlAitSum+fS5r6ApZZXuFB6E+ e3IvOtltxDRybUNkYopXy5RnEEoyp8rCc5lr6uHUCa3PcaWLh9Ky59PbSxkIQm6vPhQY edinoRZqyGlrquTJS82Zhe/5lK3ibPYgJ8vSN7k3eZnYGXxSbaDYfN0EId4LCvJ3C78W GUF2BEV264iwiKF8900xWdhiMGOIwilv+a5HS2IDEjPPOpLO5ZGiyihHGRZ85m6UBALG UMmU2qLCsCzPJpbDQfUc0Zn0nHBSpvD4HCU9qcLLXEol4qEinsGgVXcvZWvyAx/8yBlP htMg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si7605129pgd.273.2017.10.02.05.12.13; Mon, 02 Oct 2017 05:12:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751862AbdJBMMK (ORCPT + 26 others); Mon, 2 Oct 2017 08:12:10 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45592 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751250AbdJBMKG (ORCPT ); Mon, 2 Oct 2017 08:10:06 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 3FC3320A27; Mon, 2 Oct 2017 14:10:03 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id DF39420A20; Mon, 2 Oct 2017 14:10:02 +0200 (CEST) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v3 07/12] ARM: dts: sun8i: a711: include axp81x dtsi Date: Mon, 2 Oct 2017 14:08:49 +0200 Message-Id: <20171002120854.5212-8-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002120854.5212-1-quentin.schulz@free-electrons.com> References: <20171002120854.5212-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This board has an AXP813 PMIC so let's include its dtsi. Signed-off-by: Quentin Schulz --- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 723641f56a74..4f4db07ca19f 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -146,7 +146,7 @@ &r_rsb { status = "okay"; - axp813: pmic@3a3 { + axp81x: pmic@3a3 { compatible = "x-powers,axp813"; reg = <0x3a3>; interrupt-parent = <&r_intc>; @@ -179,6 +179,8 @@ }; +#include "axp81x.dtsi" + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From patchwork Mon Oct 2 12:08:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 114586 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp607261qgn; Mon, 2 Oct 2017 05:11:43 -0700 (PDT) X-Google-Smtp-Source: AOwi7QD2zHko+EwS5Olsxy8CfS9HwfuM26O24H+OQHk31L7tpZkSo3sfoC8aNPjIhSSYFxdn/VM8 X-Received: by 10.98.78.207 with SMTP id c198mr2667084pfb.20.1506946303844; Mon, 02 Oct 2017 05:11:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506946303; cv=none; d=google.com; s=arc-20160816; b=btOETrVANlRvw6zBQQSD/OBuPm4EmcjnB7gFyzxTjLU/J6YNsU94yQjd/614T2C4zI pjxP6kU6gojUrzukhHl3xut2zVp4lmadCpacMnsbzntGbpXVGsNRwC/5RFqxoFjx5BNW hwRU9WTThzepmQfP8UFO5RKbOdLmLb4XZ9btM/LMJyeH+D/TlAiC7ZLcEq0Qgo96tsGs OiTiPq8eNWnbKe8NCQ7x+KWEC7sa0FtlNVhXSJSd2KFiKnHHnpnAXENBEj26PofpFdUD fJ91KlCh+Zyeg5KKefwUfv6qKPkIpLEzrM3LNGsg3/BlA0DeTkTFdBTbHqbiEr337ESS b8kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=USKj7rNQdJwUDUonQ0rZXRqZM9qEsmOmfzwUDydTsXM=; b=PucOsOwvTfVmZb/8sQ7FUJTfsLUje8FkZS1lIhz+kq+XfLnEhdUt2IMw9frkCWTC1B 6VJH8y1TjCLQ0vTbufu66+tMxdpR8hNEEuRULCyJ0t2azUhwcU0XyGsw2NeNwdCuWU6N SMSXO1sjcm0gvWP79Lw+6H+zFDOs+CZT4nVI4jL4ztHon3W56Ghc8Fk8ePmSbszWBlR1 L1cgkZEWvg0Oxqf4ESJNEo/bm0MLM17mjEIc4pluTEiMlU/PO/YD13+ZeuZ6nqe0WtYE QwVTTRgw2JDKMyYYxEXK2F4JrfsUjOpn1Vy6pCgcEcTEtBAI7hOqEJl+TxPG6S0/1Jss RM6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p20si2949593pgc.351.2017.10.02.05.11.43; Mon, 02 Oct 2017 05:11:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751849AbdJBMLl (ORCPT + 26 others); Mon, 2 Oct 2017 08:11:41 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45583 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbdJBMKH (ORCPT ); Mon, 2 Oct 2017 08:10:07 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 13EE820A24; Mon, 2 Oct 2017 14:10:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 856A820A2A; Mon, 2 Oct 2017 14:10:03 +0200 (CEST) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v3 09/12] ARM: dts: sun8i: h8homlet-v2: include axp81x dtsi Date: Mon, 2 Oct 2017 14:08:51 +0200 Message-Id: <20171002120854.5212-10-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002120854.5212-1-quentin.schulz@free-electrons.com> References: <20171002120854.5212-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This board has an AXP818 PMIC so let's include its dtsi. Signed-off-by: Quentin Schulz --- arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 2 ++ 1 file changed, 2 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 1f0d60afb25b..222a983c3c6d 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -131,6 +131,8 @@ }; }; +#include "axp81x.dtsi" + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From patchwork Mon Oct 2 12:08:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 114584 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp606960qgn; Mon, 2 Oct 2017 05:11:26 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAz8wDAHhBtPt3MvbPTL/FNIzACX+51NITaizXIL1tAmtqBK5Jd7uRITqtB59DUpJQablkH X-Received: by 10.98.155.87 with SMTP id r84mr14302137pfd.66.1506946286667; Mon, 02 Oct 2017 05:11:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506946286; cv=none; d=google.com; s=arc-20160816; b=Y8nhWPA7py+KMMQ9aE9sYvSZrydjWbEb0nebWlNmDw3p9J5AaQuBBNWIj3TQ7wQ2yR iGMx2TtDObyC4pKcF5O6tjJF8yhhSSIYkKxhafqUS6Z0D0A6BEPmCcWaXkSeybKHsz14 SB+3rEeilTS+qlNeSo45fbc1HZUNMcNoAow28gevIRlYJMR1alx9/RqLwZeZngTRGjHN OVsSkcpRBvfqoV4Ioc2XGkBKXhfquRG7IkpdR77bmALb8SNnjBZPOBJy2xL8VPUZIgSP gMt6Vgls7KEINle/5Qth8C9vTjqD2TW9CDX4S8JDEGugqn7nkQKogT9tXywTxmDtaXBW NOWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=uEJN3aN7Pyr5DlMCsmmA1UR1q8DvuHu7/QNzud45m9A=; b=HJ+kXTirSEIILnhdbAab3uEGnhhBpB2AAOrW9m21bd4prAmnSIQCuqQzwzZPZfDn7e SBHPgQ/vgApP3gH9myPie8uxhAwGuFigGOzrEKkhz9fzZM5L3mBuK1lrCUZ2Hwb7VpgK NTDCAUB+eiqLsarwZYHUuKYBl61VbNCtMFHnMvTRsJbUObpsSvdWFo3ochL4P6LU3tY6 lSRca3hewHyaL2j8M9zXQB2YFlcFdipri1CFIkL6gQFx0rIZO0wDRI0ICAW6Y+rdfI17 7WK1YAYkhAcYTwBnlz398G9atTaOeAvuqlmC9sQbQrYGrDdX785UcodzutDZEuEfGwtj OJHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 72si8149196pla.325.2017.10.02.05.11.26; Mon, 02 Oct 2017 05:11:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751749AbdJBMLY (ORCPT + 26 others); Mon, 2 Oct 2017 08:11:24 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45628 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751102AbdJBMKH (ORCPT ); Mon, 2 Oct 2017 08:10:07 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 206E020A2A; Mon, 2 Oct 2017 14:10:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id DB92D20A2C; Mon, 2 Oct 2017 14:10:03 +0200 (CEST) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v3 10/12] ARM: dts: sun8i: cubietruck-plus: include axp81x dtsi Date: Mon, 2 Oct 2017 14:08:52 +0200 Message-Id: <20171002120854.5212-11-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002120854.5212-1-quentin.schulz@free-electrons.com> References: <20171002120854.5212-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This board has an AXP818 PMIC so let's include its dtsi. Signed-off-by: Quentin Schulz --- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 2 ++ 1 file changed, 2 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 716a205c6dbb..5bef16d949f6 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -179,6 +179,8 @@ }; }; +#include "axp81x.dtsi" + ®_usb1_vbus { gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ status = "okay"; From patchwork Mon Oct 2 12:08:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 114583 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp606654qgn; Mon, 2 Oct 2017 05:11:10 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCp3kaPEbty9ggeREyqVJnzASSDZrX/WoOl3DfsfGgTl6Hva2xr6ZjxULMAuqovU5TyzdVZ X-Received: by 10.84.132.4 with SMTP id 4mr14058541ple.449.1506946270073; Mon, 02 Oct 2017 05:11:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506946270; cv=none; d=google.com; s=arc-20160816; b=e6EyqLHOrOrDPC0XuY0w3YON5bi3KG8crP3oHIwhGtNAYLuCeKpcybyZ+vGnUDF0rZ 8TDRHZKTozNkzsZKKUd+RHh2gIuYVrPGdbuSU95Kzz+we/gpkUKhqTu7oJ7DJ94Qu3yN ceZzbPdU+/0/11Nmj6ujfPDCSLDU8j2kB/odIUR/JIde2nZ3HfD2Gx7TdNA0g8N4CEd+ 5Ua8KbicpVdiO8EhVWUorexbhM0BMFoFlE+EyIVAfi5uYf+WeO13CfV1ngxF4o7uH7wi iz7eP+QWLTymQmzcTCgb+FCLTwPXhpBOCrUVu8cqZdL4659gmyi6lQOeioWG2blxYg0L IfdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=uwb3NCg7sn41KsBhi3r6oH+Bfoqu3sO9jnboeCthO0Y=; b=DA2G+izoyKq9itvbhWMCYyExAzTVV55sYPhuBtFzERJ8vVsQcmvlDaAi7HF+pDLdNN iZ5CQ/1FH3hmW8lN7ABXCZINmyXzAjV3+Tk9RTANRG011MFxu0B8+cydErYyfLgeoW+h 13rJC8A9AKyD7KDym9CIQG9BtqJWwzaLloe6A/ShDCjAGpjUpedjAcA6vMRVL/LDDSVa TRMWenwH5BXQ1tAwev57EXGNzvxwqH/7nSZzZQAiHEwjo/ozxJNksX5NLY8Pngzuac1b DOeWegetFLAsmVT5yaOXWCkbrjRP3K5Z3dZS36pYPoCZ13W7oxGrw8BnsuCANjYU9l+Q l1Xg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 68si4173749pfe.267.2017.10.02.05.11.09; Mon, 02 Oct 2017 05:11:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751692AbdJBMLH (ORCPT + 26 others); Mon, 2 Oct 2017 08:11:07 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45644 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751291AbdJBMKH (ORCPT ); Mon, 2 Oct 2017 08:10:07 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 2F50120A2C; Mon, 2 Oct 2017 14:10:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 3A74220A31; Mon, 2 Oct 2017 14:10:04 +0200 (CEST) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v3 11/12] ARM: dtsi: axp81x: add GPIO DT node Date: Mon, 2 Oct 2017 14:08:53 +0200 Message-Id: <20171002120854.5212-12-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002120854.5212-1-quentin.schulz@free-electrons.com> References: <20171002120854.5212-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds DT node for the GPIO/pinctrl part present in AXP813/AXP818. Signed-off-by: Quentin Schulz --- arch/arm/boot/dts/axp81x.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi index 73b761f850c5..f90f257130d5 100644 --- a/arch/arm/boot/dts/axp81x.dtsi +++ b/arch/arm/boot/dts/axp81x.dtsi @@ -48,6 +48,12 @@ interrupt-controller; #interrupt-cells = <1>; + axp_gpio: axp_gpio { + compatible = "x-powers,axp813-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <3000>; From patchwork Mon Oct 2 12:08:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 114585 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp607248qgn; Mon, 2 Oct 2017 05:11:42 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDM7PzMdK1RaiGsuoHEg46njRexZCGYyr1RsVPUCuO+RWKR1RTb+Thc+6DwRku1PGi4JP3y X-Received: by 10.84.175.195 with SMTP id t61mr14145041plb.59.1506946302693; Mon, 02 Oct 2017 05:11:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506946302; cv=none; d=google.com; s=arc-20160816; b=IdoI3SG1pZmgottDFGf0K6dDtIaZOdx/vPcUp5Uk1ufLE17H+/J7EUe8bPc/O7HbXo Bu0yoUz7hopl5RmD7TWYZA2Dp1pzLKCp87X70HLFEEiXPBvYksU8KPRqGLAPNt7u6rWg LIp7HcOegFqjdB/tBK0R74QllBz6s/HctqXhIfZqWJb/ElWf+jOBAIO4V/xA1QhOHPdw LMdSTyTsjzCl0vPYW+gDOUQZ0VzrlQZ5209e1gfGIFxLtTj2bL7d1eVfGI62nii7znpK zqxy8/i2/FhYjUUsKeC3sIucO/pEn0Knw5t5jSqROuFWKcWP0zHCd3p1PmfPXNeOPxn0 ZtDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=pWTxAFqGU+fekvi8i8HfZDuCJi4FFX6p6rLVV76lj28=; b=XelbwCJZxfiXFnOTOysMlCitgWv5Pzmif3/7k8FTQGvW5V1z3c3MEfVrUKXozvlJ8H vtvBsd0w6Nt+glT+TAM0j2e7s2+gVB/ZdlIPkN97DA0o9O7hCT6v1JKP7nHAM3sq4Mn5 IzxVxfYGzKQ2Zu020FEso+GCgIrqmJJUWyOAzxoaiIXSGxyEYsssePKmrdYXo+FpznV0 SYkIYtB4PfdtS6yflHN+mZNYvhzM7wOqq0dhY9ML3/K/7TYRHi6M6oQPXl1SISGcXnEP OLMtGyauX41f0J2t0bqfAM6x+bP8vLMnv5b8XdSYhJ7lfjj0bDEFyPFJydOeQYmC5+is vc5A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s75si7744701pfj.57.2017.10.02.05.11.42; Mon, 02 Oct 2017 05:11:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751814AbdJBMLk (ORCPT + 26 others); Mon, 2 Oct 2017 08:11:40 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45582 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751281AbdJBMKH (ORCPT ); Mon, 2 Oct 2017 08:10:07 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 4B74920A21; Mon, 2 Oct 2017 14:10:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 84A6120A25; Mon, 2 Oct 2017 14:10:04 +0200 (CEST) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v3 12/12] ARM: dtsi: axp81x: set pinmux for GPIO0/1 when used as LDOs Date: Mon, 2 Oct 2017 14:08:54 +0200 Message-Id: <20171002120854.5212-13-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171002120854.5212-1-quentin.schulz@free-electrons.com> References: <20171002120854.5212-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On AXP813/818, GPIO0 and GPIO1 can be used as LDO as (respectively) ldo_io0 and ldo_io1. Let's add the pinctrl properties to the said regulators. Signed-off-by: Quentin Schulz --- arch/arm/boot/dts/axp81x.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi index f90f257130d5..099b0ddc1bbb 100644 --- a/arch/arm/boot/dts/axp81x.dtsi +++ b/arch/arm/boot/dts/axp81x.dtsi @@ -52,6 +52,16 @@ compatible = "x-powers,axp813-gpio"; gpio-controller; #gpio-cells = <2>; + + gpio0_ldo: gpio0_ldo { + pins = "GPIO0"; + function = "ldo"; + }; + + gpio1_ldo: gpio1_ldo { + pins = "GPIO1"; + function = "ldo"; + }; }; regulators { @@ -119,11 +129,15 @@ }; reg_ldo_io0: ldo-io0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_ldo>; /* Disable by default to avoid conflicts with GPIO */ status = "disabled"; }; reg_ldo_io1: ldo-io1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_ldo>; /* Disable by default to avoid conflicts with GPIO */ status = "disabled"; };