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Mon, 02 Oct 2017 11:48:24 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 1/4] clk: samsung: Instantiate Exynos4412 ISP clocks only when available Date: Mon, 02 Oct 2017 12:47:56 +0200 Message-id: <20171002104759.25944-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171002104759.25944-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOIsWRmVeSWpSXmKPExsWy7djP87qVkpciDf5eYLXYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6MVXu2MhXsU6zYeXkmYwPjLpkuRk4OCQETiZMTO5kgbDGJC/fWs4HYQgJL GSVm7g7vYuQCsj8zSuzafJwJpmHn0/msEEXLGCW2tEVBFDUwSTz59RkswSZgKNH1tgtskoiA g8TnT68ZQYqYBdqYJM4e2A82SVggSuJQz3NmEJtFQFVi76E2MJtXwFbi+qqfrBDb5CXeL7jP CGJzCthJNB9YyQIySEKgkU1i7aFnbBBFLhLbFr+HsoUlXh3fwg5hy0h0dhyEOrufUaKpVRvC nsEoce4tL4RtLXH4+EWwZcwCfBKTtk0HOoIDKM4r0dEmBFHiIfF/1jyoMY4S55YtY4f4fiKj xN65FRMYpRcwMqxiFEktLc5NTy020StOzC0uzUvXS87P3cQIjM7T/45/2cG4+JjVIUYBDkYl Hl4Nk4uRQqyJZcWVuYcYJTiYlUR4edkuRQrxpiRWVqUW5ccXleakFh9ilOZgURLntY1qixQS SE8sSc1OTS1ILYLJMnFwSjUwdtdGX6mYULdXKSdn84YP/QdeZmVMy/QP9Pj/yWX653llwvka W5qsP2jIR4p2s3bM29mwX0btdwb7qhm/eU+tKw8v2dHSfujm/siLs3f4dmkt++3BcXh1cZ1p epbK0r6CwovaCQt111q33JcTFlEPdnW9Up9UY6z0Z5rQ7oj4/fx8/1hj07cqsRRnJBpqMRcV JwIAWWLN7soCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplluLIzCtJLcpLzFFi42I5/e/4Vd0KyUuRBr/OqFlsnLGe1eL6l+es FpPuT2CxOH9+A7vFx557rBYzzu9jslh75C67xeE37awOHB6bVnWyefRtWcXo8XmTXABzFJdN SmpOZllqkb5dAlfGqj1bmQr2KVbsvDyTsYFxl0wXIyeHhICJxM6n81khbDGJC/fWs4HYQgJL GCXeXpODsJuYJC5/MAKx2QQMJbredoHViAg4SHz+9Jqxi5GLg1mgg0liz96HYAlhgSiJjvbp YENZBFQl9h5qYwaxeQVsJa6v+gm1TF7i/YL7jCA2p4CdRPOBlSwQy2wl5q7dzD6BkXcBI8Mq RpHU0uLc9NxiQ73ixNzi0rx0veT83E2MwEDaduzn5h2MlzYGH2IU4GBU4uHVMLkYKcSaWFZc mXuIUYKDWUmEl5ftUqQQb0piZVVqUX58UWlOavEhRmkOFiVx3t49qyOFBNITS1KzU1MLUotg skwcnFINjLOuS9kyybmk2V2JZHHtePF+1g5tlTWbPaYrCuXauccl1fz8tX6uT6Ti8TlBaSX2 nW/DZlz4n3I6euL2i1dcj3+cpSE9VeZGdNiPp/PMXl+prlXOfHxu3dS/Ny32WBXn7RVc4x91 VtVnm/AOrX858u0POHNC5+WyFF979ObtWrfSfVJMJXUquUosxRmJhlrMRcWJAGbIxaAgAgAA X-CMS-MailID: 20171002104824eucas1p1de6466888524f3f3f097086b1e2388ff X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20171002104824eucas1p1de6466888524f3f3f097086b1e2388ff X-RootMTR: 20171002104824eucas1p1de6466888524f3f3f097086b1e2388ff References: <20171002104759.25944-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Some additional registers for the ISP (Camera subsystem) clocks are partially located in the SOC area, which belongs to ISP power domain. Istatiate those clocks only when provided clock registers resource covers those registers. This is a preparation for adding a separate clock driver for ISP clocks, which will be intergated with power domain using runtime PM feature. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos4.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) -- 2.14.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Krzysztof Kozlowski diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e40b77583c47..bdd68247e054 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -822,6 +822,12 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), + DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), + DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), + DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), +}; + +static struct samsung_div_clock exynos4x12_isp_div_clks[] = { DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, CLK_GET_RATE_NOCACHE, 0), DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, @@ -831,9 +837,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { 4, 3, CLK_GET_RATE_NOCACHE, 0), DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3, CLK_GET_RATE_NOCACHE, 0), - DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), - DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), - DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), }; /* list of gate clocks supported in all exynos4 soc's */ @@ -1132,6 +1135,13 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { 0, 0), GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 0, 0), + GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), + GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), + GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, + 0), +}; + +static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, @@ -1184,10 +1194,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), - GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), - GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, - 0), }; static const struct samsung_clock_alias exynos4_aliases[] __initconst = { @@ -1522,6 +1528,8 @@ static void __init exynos4_clk_init(struct device_node *np, e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); } else { + struct resource res; + samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); samsung_clk_register_div(ctx, exynos4x12_div_clks, @@ -1533,6 +1541,15 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_fixed_factor(ctx, exynos4x12_fixed_factor_clks, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); + + of_address_to_resource(np, 0, &res); + if (resource_size(&res) > 0x18000) { + samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, + ARRAY_SIZE(exynos4x12_isp_div_clks)); + samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, + ARRAY_SIZE(exynos4x12_isp_gate_clks)); + } + if (of_machine_is_compatible("samsung,exynos4412")) { exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, From patchwork Mon Oct 2 10:47:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 114576 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp532727qgn; Mon, 2 Oct 2017 03:48:35 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBI1hbb3XIlhhyXe9bzQWb+VmN2xpTr8nIeCPR8g7pfywyuD16e3JbtkjWo9yKcIh9sHLRd X-Received: by 10.99.167.6 with SMTP id d6mr12122179pgf.414.1506941315823; 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Mon, 02 Oct 2017 11:48:26 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 3/4] ARM: dts: exynos: Add Exynos4412 ISP clock controller Date: Mon, 02 Oct 2017 12:47:58 +0200 Message-id: <20171002104759.25944-4-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171002104759.25944-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBIsWRmVeSWpSXmKPExsWy7djP87pVkpciDSZ91bDYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6Mp6f+Mhcc1avYs7yDpYFxjkoXIyeHhICJxJa/j1ggbDGJC/fWs3UxcnEI CSxllHj64iczSEJI4DOjxL1GPZiGT99fQRUtY5SY+esZlNPAJDGjdQMTSBWbgKFE19suNhBb RMBB4vOn14wgRcwCbUwSZw/sBysSFvCSWLT1EmsXIwcHi4CqxLQbsSBhXgFbiQ09HVAnyUu8 X3CfEcTmFLCTaD6wkgVkjoRAB5vEnH0nmSGKXCROHFgOZQtLvDq+hR3ClpG4PLkbalA/o0RT qzaEPYNR4txbXgjbWuLw8YusIDazAJ/EpG3TmUHukRDglehoE4Io8ZB4Mr8ParyjRMu3FhaI hycySkz7uYl9AqP0AkaGVYwiqaXFuempxUZ6xYm5xaV56XrJ+bmbGIHxefrf8Y87GN+fsDrE KMDBqMTDq2FyMVKINbGsuDL3EKMEB7OSCC8v26VIId6UxMqq1KL8+KLSnNTiQ4zSHCxK4ry2 UW2RQgLpiSWp2ampBalFMFkmDk6pBkbhdUktH84Ht/73eLjo/fnrHaIvX6++Ucb5hys2MmVH mhq7eF23nmSA4eTf3kyrqh9FaaVY5xz8tTvt6hxRiTVh81ZrPi5/sTHzzWWfuXaP0hwZ9j1a mRdbcXHL4h/+Yc8cZ9Snf+2I4xGKqF7JqvFS4oRq+KqUN3fKPDd/OKn/vev470sWaUpKLMUZ iYZazEXFiQDT1sNmywIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplluLIzCtJLcpLzFFi42I5/e/4Vd0qyUuRBid7uSw2zljPanH9y3NW i0n3J7BYnD+/gd3iY889VosZ5/cxWaw9cpfd4vCbdlYHDo9NqzrZPPq2rGL0+LxJLoA5issm JTUnsyy1SN8ugSvj6am/zAVH9Sr2LO9gaWCco9LFyMkhIWAi8en7KzYIW0ziwr31QDYXh5DA EkaJ03N3gCWEBJqYJCZ8jwex2QQMJbredoHFRQQcJD5/es0I0sAs0MEksWfvQ7CEsICXxKKt l1i7GDk4WARUJabdiAUJ8wrYSmzo6WCBWCYv8X7BfUYQm1PATqL5wEoWiF22EnPXbmafwMi7 gJFhFaNIamlxbnpusZFecWJucWleul5yfu4mRmAgbTv2c8sOxq53wYcYBTgYlXh4NUwuRgqx JpYVV+YeYpTgYFYS4eVluxQpxJuSWFmVWpQfX1Sak1p8iFGag0VJnLd3z+pIIYH0xJLU7NTU gtQimCwTB6dUA6PGzgaRpdI7lI2uavgc6fm9PiaW38fi6NLTkVymqYra6msLbC9+EW3SSnBd 69rW082ho7rzWaHF5bsugU7HJv+sUfS2S8v+/MLFwEqpafnWzUvqrD1kc67+5z4RcTH7kffy iG9O85qutOT+l2CdE3ukQP1ijYYVn0bg0b1cwTMrchwsup3zlFiKMxINtZiLihMBSrFZAyAC AAA= X-CMS-MailID: 20171002104826eucas1p15c0d0d9038e5b1119fd244ecab502d35 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20171002104826eucas1p15c0d0d9038e5b1119fd244ecab502d35 X-RootMTR: 20171002104826eucas1p15c0d0d9038e5b1119fd244ecab502d35 References: <20171002104759.25944-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos4412 ISP clock controller is located in the SOC area, which belongs to ISP power domain. This patch instantiates a separate clock driver for those clocks, updates all clients of ISP clocks and ensures that the driver is properly integrated in ISP power domin. This finally solves all the mysterious freezes in accessing ISP clocks when ISP power domain is disabled. Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos4412.dtsi | 71 ++++++++++++++++++++++++--------------- 1 file changed, 44 insertions(+), 27 deletions(-) -- 2.14.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7ff03a7e8fb9..2a2f1e596672 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -191,10 +191,19 @@ clock: clock-controller@10030000 { compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x20000>; + reg = <0x10030000 0x18000>; #clock-cells = <1>; }; + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; + mct@10050000 { compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; @@ -257,7 +266,7 @@ reg = <0x12390000 0x1000>; interrupts = ; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; clock-names = "flite"; iommus = <&sysmmu_fimc_lite0>; status = "disabled"; @@ -268,7 +277,7 @@ reg = <0x123A0000 0x1000>; interrupts = ; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE1>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; clock-names = "flite"; iommus = <&sysmmu_fimc_lite1>; status = "disabled"; @@ -280,29 +289,35 @@ interrupts = , ; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>, - <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, - <&clock CLK_PPMUISPMX>, + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE1>, + <&isp_clock CLK_ISP_PPMUISPX>, + <&isp_clock CLK_ISP_PPMUISPMX>, + <&isp_clock CLK_ISP_FIMC_ISP>, + <&isp_clock CLK_ISP_FIMC_DRC>, + <&isp_clock CLK_ISP_FIMC_FD>, + <&isp_clock CLK_ISP_MCUISP>, + <&isp_clock CLK_ISP_GICISP>, + <&isp_clock CLK_ISP_MCUCTL_ISP>, + <&isp_clock CLK_ISP_PWM_ISP>, + <&isp_clock CLK_ISP_DIV_ISP0>, + <&isp_clock CLK_ISP_DIV_ISP1>, + <&isp_clock CLK_ISP_DIV_MCUISP0>, + <&isp_clock CLK_ISP_DIV_MCUISP1>, <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, - <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, - <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, - <&clock CLK_PWM_ISP>, - <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, - <&clock CLK_DIV_MCUISP0>, - <&clock CLK_DIV_MCUISP1>, - <&clock CLK_UART_ISP_SCLK>, - <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, + <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK400_MCUISP>; + <&clock CLK_DIV_ACLK200>, + <&clock CLK_DIV_ACLK400_MCUISP>, + <&clock CLK_UART_ISP_SCLK>; clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "mpll", "isp", + "ppmuispmx", "isp", "drc", "fd", "mcuisp", "gicisp", "mcuctl_isp", "pwm_isp", "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "uart", "aclk200", - "div_aclk200", "aclk400mcuisp", - "div_aclk400mcuisp"; + "mcuispdiv1", "mpll", "aclk200", + "aclk400mcuisp", "div_aclk200", + "div_aclk400mcuisp", "uart"; iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; iommu-names = "isp", "drc", "fd", "mcuctl"; @@ -318,7 +333,7 @@ i2c1_isp: i2c-isp@12140000 { compatible = "samsung,exynos4212-i2c-isp"; reg = <0x12140000 0x100>; - clocks = <&clock CLK_I2C1_ISP>; + clocks = <&isp_clock CLK_ISP_I2C1_ISP>; clock-names = "i2c_isp"; #address-cells = <1>; #size-cells = <0>; @@ -355,7 +370,7 @@ interrupts = <16 2>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISP>; + clocks = <&isp_clock CLK_ISP_SMMU_ISP>; #iommu-cells = <0>; }; @@ -366,7 +381,7 @@ interrupts = <16 3>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_DRC>; + clocks = <&isp_clock CLK_ISP_SMMU_DRC>; #iommu-cells = <0>; }; @@ -377,7 +392,7 @@ interrupts = <16 4>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FD>; + clocks = <&isp_clock CLK_ISP_SMMU_FD>; #iommu-cells = <0>; }; @@ -388,7 +403,7 @@ interrupts = <16 5>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISPCX>; + clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; #iommu-cells = <0>; }; @@ -399,7 +414,8 @@ interrupts = <16 0>; power-domains = <&pd_isp>; clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; + clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE0>; #iommu-cells = <0>; }; @@ -410,7 +426,8 @@ interrupts = <16 1>; power-domains = <&pd_isp>; clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; + clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, + <&isp_clock CLK_ISP_FIMC_LITE1>; #iommu-cells = <0>; }; From patchwork Mon Oct 2 10:47:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 114577 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp532737qgn; Mon, 2 Oct 2017 03:48:36 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCkC+ZH2PyraLtF5EsclQrIvfengmNMVcHruWGJBow6YKm4a3ahMhEEX96O31ReOY39eAUX X-Received: by 10.84.248.138 with SMTP id q10mr13986736pll.431.1506941316811; Mon, 02 Oct 2017 03:48:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506941316; cv=none; d=google.com; s=arc-20160816; b=cwYsU3WeL77dGcLxx4xMEXnq3sV/hFBItqBiYM0NbLIiPoJXHHcw0kpBcZIw31hJVz HpjrhxAURH8eEAL9nuCsUi94hRgUPFr1hdRAgNo+LSuiIlpTEq5zBaRNCcg2d/zMZzZM 498qhJeQwzckoHrKJN48+gFaplDpUeODJSSnktqtz025+nv9V+GL9P5yuFKAKUOT6292 u5+EPITiGAD27H++Ew8REwmIecm8yjU42R3LsY2dkWZhzj33g/zkBs5wlfv9V6cqeeOl HoHRtDlYrBdZ8avyXaDFvjtkOyM+2ck4NOdOGTxARt2/VSiCpZ8UpZ3h/3oXmfVCwzzK xQEw== ARC-Message-Signature: i=1; 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Mon, 02 Oct 2017 11:48:26 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 4/4] clk: samsung: Remove obsolete code for Exynos4412 ISP clocks Date: Mon, 02 Oct 2017 12:47:59 +0200 Message-id: <20171002104759.25944-5-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171002104759.25944-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRmVeSWpSXmKPExsWy7djPc7rVkpciDTbOFbbYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6M5+ePMBVMcar4PKeZuYFxoUUXIyeHhICJxK2P6xghbDGJC/fWs3UxcnEI CSxllJh/5jc7hPOZUeLK7NeMMB3r97YzQySWMUps/nQQymlgkpjRuoEJpIpNwFCi620XG4gt IuAg8fkTSDcXB7NAG5PE2QP7wYqEBYIlJr74DTaWRUBVorVrEjOIzStgK3Hj/SM2iHXyEu8X 3Aer4RSwk2g+sJIFZJCEQA+bRNPF36wQRS4SV98dh2oQlnh1fAs7hC0jcXlyNwuE3c8o0dSq DWHPYJQ495YXwraWOHz8ItgcZgE+iUnbpgMdwQEU55XoaBOCKPGQ+LJ8ETOE7SixZcIbFoiP JzJKrN5+k3ECo/QCRoZVjCKppcW56anFRnrFibnFpXnpesn5uZsYgTF6+t/xjzsY35+wOsQo wMGoxMOrYXIxUog1say4MvcQowQHs5IILy/bpUgh3pTEyqrUovz4otKc1OJDjNIcLErivLZR bZFCAumJJanZqakFqUUwWSYOTqkGxmgldrmD038q7CueXfDxqWbA4aMv106KsHLm/vBzg2Xp 3AMPX2/W/rqD7dbLuANfRHtZ9BtPe/2NDJn8q7njkSXTlk8v//7L3X2ak1Nns61CyRUdy0e6 VWaLKsz6NxYvv3jTysTo5gmN+IkhBq4LtXkq3bdwzw669T6ONeX6z+uuh2td1WsCzyqxFGck GmoxFxUnAgAqnhGEzQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjluLIzCtJLcpLzFFi42I5/e/4Vd0qyUuRBpvOGFpsnLGe1eL6l+es FpPuT2CxOH9+A7vFx557rBYzzu9jslh75C67xeE37awOHB6bVnWyefRtWcXo8XmTXABzFJdN SmpOZllqkb5dAlfG8/NHmAqmOFV8ntPM3MC40KKLkZNDQsBEYv3edmYIW0ziwr31bF2MXBxC AksYJX7f28QCkhASaGKSmPA9HsRmEzCU6HrbxQZiiwg4SHz+9JoRpIFZoINJYs/eh2AJYYFg iYkvfjOC2CwCqhKtXZPANvAK2ErceP+IDWKbvMT7BffBajgF7CSaD6yEWmYrMXftZvYJjLwL GBlWMYqklhbnpucWG+kVJ+YWl+al6yXn525iBIbStmM/t+xg7HoXfIhRgINRiYdXw+RipBBr YllxZe4hRgkOZiURXl62S5FCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeXv3rI4UEkhPLEnNTk0t SC2CyTJxcEo1MG550Dixe//LdpFlSVv2zrx4YbaVgU6cwaeLhxJudX2Zc1pt4vXPk1+uvPr7 wVqHwkNfVm1hYnycmi1YeqbtddZaweZ/VTV576zN5oeeL3GVKP0TFXRuwvvYJi/e6o+cii8n qyz8M31/Suzb8021ShsnN3wWyavT2L4p/qhpeJ4jh+81rsobZx8rsRRnJBpqMRcVJwIA53Vs ISECAAA= X-CMS-MailID: 20171002104826eucas1p17b7ea22d3984f1dea0e3efb45733d728 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20171002104826eucas1p17b7ea22d3984f1dea0e3efb45733d728 X-RootMTR: 20171002104826eucas1p17b7ea22d3984f1dea0e3efb45733d728 References: <20171002104759.25944-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos4412 ISP clock are provided by separate Exynos4412 ISP clock driver, so support for them in Exynos4-clk driver can be removed. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos4.c | 81 ------------------------------------- include/dt-bindings/clock/exynos4.h | 30 -------------- 2 files changed, 111 deletions(-) -- 2.14.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Krzysztof Kozlowski diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index bdd68247e054..69649dc6a9cf 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -123,10 +123,6 @@ #define CLKOUT_CMU_CPU 0x14a00 #define PWR_CTRL1 0x15020 #define E4X12_PWR_CTRL2 0x15024 -#define E4X12_DIV_ISP0 0x18300 -#define E4X12_DIV_ISP1 0x18304 -#define E4X12_GATE_ISP0 0x18800 -#define E4X12_GATE_ISP1 0x18804 /* Below definitions are used for PWR_CTRL settings */ #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) @@ -827,18 +823,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), }; -static struct samsung_div_clock exynos4x12_isp_div_clks[] = { - DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, - CLK_GET_RATE_NOCACHE, 0), - DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, - CLK_GET_RATE_NOCACHE, 0), - DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), - DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, - 4, 3, CLK_GET_RATE_NOCACHE, 0), - DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, - 8, 3, CLK_GET_RATE_NOCACHE, 0), -}; - /* list of gate clocks supported in all exynos4 soc's */ static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { /* @@ -1141,61 +1125,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { 0), }; -static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { - GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), -}; - static const struct samsung_clock_alias exynos4_aliases[] __initconst = { ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), ALIAS(CLK_ARM_CLK, NULL, "armclk"), @@ -1528,8 +1457,6 @@ static void __init exynos4_clk_init(struct device_node *np, e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); } else { - struct resource res; - samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); samsung_clk_register_div(ctx, exynos4x12_div_clks, @@ -1542,14 +1469,6 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4x12_fixed_factor_clks, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); - of_address_to_resource(np, 0, &res); - if (resource_size(&res) > 0x18000) { - samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, - ARRAY_SIZE(exynos4x12_isp_div_clks)); - samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, - ARRAY_SIZE(exynos4x12_isp_gate_clks)); - } - if (of_machine_is_compatible("samsung,exynos4412")) { exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index bf44a7c5eccc..5106943a1fd0 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -190,32 +190,6 @@ #define CLK_MIPI_HSI 349 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 -#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ -#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ -#define CLK_PPMUISPX 355 /* Exynos4x12 only */ -#define CLK_PPMUISPMX 356 /* Exynos4x12 only */ -#define CLK_FIMC_ISP 357 /* Exynos4x12 only */ -#define CLK_FIMC_DRC 358 /* Exynos4x12 only */ -#define CLK_FIMC_FD 359 /* Exynos4x12 only */ -#define CLK_MCUISP 360 /* Exynos4x12 only */ -#define CLK_GICISP 361 /* Exynos4x12 only */ -#define CLK_SMMU_ISP 362 /* Exynos4x12 only */ -#define CLK_SMMU_DRC 363 /* Exynos4x12 only */ -#define CLK_SMMU_FD 364 /* Exynos4x12 only */ -#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ -#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ -#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ -#define CLK_MPWM_ISP 368 /* Exynos4x12 only */ -#define CLK_I2C0_ISP 369 /* Exynos4x12 only */ -#define CLK_I2C1_ISP 370 /* Exynos4x12 only */ -#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ -#define CLK_PWM_ISP 372 /* Exynos4x12 only */ -#define CLK_WDT_ISP 373 /* Exynos4x12 only */ -#define CLK_UART_ISP 374 /* Exynos4x12 only */ -#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ -#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ -#define CLK_SPI0_ISP 377 /* Exynos4x12 only */ -#define CLK_SPI1_ISP 378 /* Exynos4x12 only */ #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ @@ -257,10 +231,6 @@ #define CLK_PPMUACP 415 /* div clocks */ -#define CLK_DIV_ISP0 450 /* Exynos4x12 only */ -#define CLK_DIV_ISP1 451 /* Exynos4x12 only */ -#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ -#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ #define CLK_DIV_ACP 456