From patchwork Mon Apr 20 10:06:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 238080 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Mon, 20 Apr 2020 15:36:06 +0530 Subject: [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash Message-ID: <20200420100607.23009-1-jagan@amarulasolutions.com> Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Micromax has, so reuse the existing code itself. Cc: Sagar Shrikant Kadam Signed-off-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 1 + include/linux/mtd/spi-nor.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 7b6ad495ac..e0f6e4d6c3 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -325,6 +325,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; + case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: if (need_wren) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index ec144a08d8..233fdc341a 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -22,6 +22,7 @@ #define SNOR_MFR_INTEL CFI_MFR_INTEL #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */ #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */ +#define SNOR_MFR_ISSI CFI_MFR_PMC #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST From patchwork Mon Apr 20 10:06:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 238081 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Mon, 20 Apr 2020 15:36:07 +0530 Subject: [PATCH 2/2] mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256 In-Reply-To: <20200420100607.23009-1-jagan@amarulasolutions.com> References: <20200420100607.23009-1-jagan@amarulasolutions.com> Message-ID: <20200420100607.23009-2-jagan@amarulasolutions.com> IS25WP256 flash chips do support 4byte address opcodes, so enable support for it. Cc: Sagar Shrikant Kadam Signed-off-by: Jagan Teki Reviewed-by: Sagar Kadam --- drivers/mtd/spi/spi-nor-ids.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 973b6f86c9..f95bfb59e6 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -135,7 +135,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */