From patchwork Mon Apr 20 08:17:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tan, Ley Foon" X-Patchwork-Id: 238070 List-Id: U-Boot discussion From: ley.foon.tan at intel.com (Ley Foon Tan) Date: Mon, 20 Apr 2020 16:17:27 +0800 Subject: [PATCH] arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset Message-ID: <20200420081727.155029-1-ley.foon.tan@intel.com> Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it. Reported-by: Chee Hong Ang Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index e710aa2f94f0..9d2b3bababe2 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -85,7 +85,7 @@ void cm_basic_init(const struct cm_config * const cfg); #define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c /* Periphpll group */ #define CLKMGR_S10_PERPLL_EN 0xa4 -#define CLKMGR_S10_PERPLL_BYPASS 0xac +#define CLKMGR_S10_PERPLL_BYPASS 0xb0 #define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc #define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0 #define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4