From patchwork Tue Apr 14 22:59:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 237782 List-Id: U-Boot discussion From: marek.behun at nic.cz (=?UTF-8?q?Marek=20Beh=C3=BAn?=) Date: Wed, 15 Apr 2020 00:59:18 +0200 Subject: [PATCH u-boot-marvell 1/1] clk: armada-37xx-periph: fix DDR PHY clock divider values Message-ID: <20200414225918.12844-1-marek.behun@nic.cz> Register value table for DDR PHY clock divider are wrong. They should be 0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current values do not make sense, since 2 cannot be achieved, because the register is only 1 bit long (mask is set to 1). This fixes clk dump reporting DDR PHY clock rate differently from Linux. Signed-off-by: Marek Beh?n Reviewed-by: Stefan Roese --- drivers/clk/mvebu/armada-37xx-periph.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 068e48ea04..855f979b4f 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -89,8 +89,8 @@ static const struct clk_div_table div_table1[] = { }; static const struct clk_div_table div_table2[] = { - { 2, 1 }, - { 4, 2 }, + { 2, 0 }, + { 4, 1 }, { 0, 0 }, };