From patchwork Fri Apr 3 08:28:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Delaunay X-Patchwork-Id: 237135 List-Id: U-Boot discussion From: patrick.delaunay at st.com (Patrick Delaunay) Date: Fri, 3 Apr 2020 10:28:32 +0200 Subject: [PATCH 1/3] arm: caches: protect dram_bank_mmu_setup access to bi_dram Message-ID: <20200403102815.1.I64599059b66bacb531db38c67273754a145dbad8@changeid> Add protection in dram_bank_mmu_setup() to avoid access to bd->bi_dram before relocation. This patch allow to use the generic weak function dram_bank_mmu_setup to activate the MMU and the data cache in SPL or in U-Boot before relocation, when bd->bi_dram is not yet initialized. In this cases, the MMU must be initialized explicitly with mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay --- arch/arm/lib/cache-cp15.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f8d20960da..54509f11c3 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -91,6 +91,10 @@ __weak void dram_bank_mmu_setup(int bank) bd_t *bd = gd->bd; int i; + /* bd->bi_dram is available only after relocation */ + if ((gd->flags & GD_FLG_RELOC) == 0) + return; + debug("%s: bank: %d\n", __func__, bank); for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + From patchwork Fri Apr 3 08:28:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Delaunay X-Patchwork-Id: 237137 List-Id: U-Boot discussion From: patrick.delaunay at st.com (Patrick Delaunay) Date: Fri, 3 Apr 2020 10:28:33 +0200 Subject: [PATCH 2/3] arm: caches: add DCACHE_DEFAULT_OPTION In-Reply-To: <20200403102815.1.I64599059b66bacb531db38c67273754a145dbad8@changeid> References: <20200403102815.1.I64599059b66bacb531db38c67273754a145dbad8@changeid> Message-ID: <20200403102815.2.Ib6abcb05422a74bc6bc03daa71b15c98c99dbc5d@changeid> Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_WRITETHROUGH or CONFIG_SYS_ARM_CACHE_WRITEALLOC. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay --- arch/arm/include/asm/system.h | 8 ++++++++ arch/arm/lib/cache-cp15.c | 11 ++--------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 81ccead112..01ea96e8ad 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -485,6 +485,14 @@ enum dcache_option { }; #endif +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC +#else +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK +#endif + /* Size of an MMU section */ enum { #ifdef CONFIG_ARMV7_LPAE diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 54509f11c3..d15144188b 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -99,15 +99,8 @@ __weak void dram_bank_mmu_setup(int bank) for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) - set_section_dcache(i, DCACHE_WRITEALLOC); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); } /* to activate the MMU we need to set up virtual memory: use 1M areas */ From patchwork Fri Apr 3 08:28:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Delaunay X-Patchwork-Id: 237136 List-Id: U-Boot discussion From: patrick.delaunay at st.com (Patrick Delaunay) Date: Fri, 3 Apr 2020 10:28:34 +0200 Subject: [PATCH 3/3] arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour In-Reply-To: <20200403102815.1.I64599059b66bacb531db38c67273754a145dbad8@changeid> References: <20200403102815.1.I64599059b66bacb531db38c67273754a145dbad8@changeid> Message-ID: <20200403102815.3.Ic2c7c6923035711a4c653d52ae7c0f57ca6f9210@changeid> Detect and solve the overflow on phys_addr_t type for start + size in mmu_set_region_dcache_behaviour() function. This issue occurs for example with ARM32, start = 0xC0000000 and size = 0x40000000: start + size = 0x100000000 and end = 0x0. Overflow is detected when end < start. In normal case the previous behavior is still used: when start is not aligned on MMU section, the end address is only aligned after the sum start + size. Signed-off-by: Patrick Delaunay --- arch/arm/lib/cache-cp15.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index d15144188b..e5a7fd0ef4 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -63,6 +63,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; start = start >> MMU_SECTION_SHIFT; + + /* phys_addr_t overflow detected */ + if (end < start) + end = (~(phys_addr_t)0x0 >> MMU_SECTION_SHIFT) + 1; + #ifdef CONFIG_ARMV7_LPAE debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size, option);