From patchwork Mon Feb 24 13:55:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 236758 List-Id: U-Boot discussion From: lukma at denx.de (Lukasz Majewski) Date: Mon, 24 Feb 2020 14:55:24 +0100 Subject: [PATCH 1/3] clk: imx6: Add definition for IMX6QDL_CLK_ENET clock In-Reply-To: <20200224135526.25534-1-lukma@denx.de> References: <20200224135526.25534-1-lukma@denx.de> Message-ID: <20200224135526.25534-2-lukma@denx.de> After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide IMX6QDL_CLK_ENET. This change defines the missing clock in i.MX6Q's CCF. Signed-off-by: Lukasz Majewski --- drivers/clk/imx/clk-imx6q.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index bd0d3e4f47..ace60ecec6 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -182,6 +182,7 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_I2C2, imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8)); + clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10)); return 0; } From patchwork Mon Feb 24 13:55:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 236759 List-Id: U-Boot discussion From: lukma at denx.de (Lukasz Majewski) Date: Mon, 24 Feb 2020 14:55:25 +0100 Subject: [PATCH 2/3] clk: imx: Add support for pllv3 enet clock In-Reply-To: <20200224135526.25534-1-lukma@denx.de> References: <20200224135526.25534-1-lukma@denx.de> Message-ID: <20200224135526.25534-3-lukma@denx.de> This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski --- drivers/clk/imx/clk-pllv3.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 525442debf..88baf10f6a 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -20,6 +20,7 @@ #define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys" #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb" #define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av" +#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet" #define PLL_NUM_OFFSET 0x10 #define PLL_DENOM_OFFSET 0x20 @@ -34,6 +35,7 @@ struct clk_pllv3 { bool powerup_set; u32 div_mask; u32 div_shift; + unsigned long ref_clock; }; #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk) @@ -224,6 +226,19 @@ static const struct clk_ops clk_pllv3_av_ops = { .set_rate = clk_pllv3_av_set_rate, }; +static ulong clk_pllv3_enet_get_rate(struct clk *clk) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + + return pll->ref_clock; +} + +static const struct clk_ops clk_pllv3_enet_ops = { + .enable = clk_pllv3_generic_enable, + .disable = clk_pllv3_generic_disable, + .get_rate = clk_pllv3_enet_get_rate, +}; + struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) @@ -260,6 +275,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->div_shift = 0; pll->powerup_set = false; break; + case IMX_PLLV3_ENET: + drv_name = UBOOT_DM_CLK_IMX_PLLV3_ENET; + pll->ref_clock = 500000000; + break; default: kfree(pll); return ERR_PTR(-ENOTSUPP); @@ -305,3 +324,9 @@ U_BOOT_DRIVER(clk_pllv3_av) = { .ops = &clk_pllv3_av_ops, .flags = DM_FLAG_PRE_RELOC, }; + +U_BOOT_DRIVER(clk_pllv3_enet) = { + .name = UBOOT_DM_CLK_IMX_PLLV3_ENET, + .id = UCLASS_CLK, + .ops = &clk_pllv3_enet_ops, +}; From patchwork Mon Feb 24 13:55:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 236760 List-Id: U-Boot discussion From: lukma at denx.de (Lukasz Majewski) Date: Mon, 24 Feb 2020 14:55:26 +0100 Subject: [PATCH 3/3] clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clock In-Reply-To: <20200224135526.25534-1-lukma@denx.de> References: <20200224135526.25534-1-lukma@denx.de> Message-ID: <20200224135526.25534-4-lukma@denx.de> After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide PTP clock. On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux kernel's CCF. Code in this change models the simplest case when enet reference clock is generated from 'osc' clock. Signed-off-by: Lukasz Majewski --- drivers/clk/imx/clk-imx6q.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index ace60ecec6..0f4c1f881d 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -112,6 +112,10 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M, imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2)); + clk_dm(IMX6QDL_CLK_PLL6, + imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); + clk_dm(IMX6QDL_CLK_PLL6_ENET, + imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13)); /* CCM clocks */ base = dev_read_addr_ptr(dev); @@ -183,6 +187,9 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8)); clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10)); + clk_dm(IMX6QDL_CLK_ENET_REF, + imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1)); + return 0; }