From patchwork Tue Feb 18 15:02:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 236507 List-Id: U-Boot discussion From: michal.simek at xilinx.com (Michal Simek) Date: Tue, 18 Feb 2020 16:02:45 +0100 Subject: [PATCH] ARM: zynq: Change zc770 xm011 Nand x16 configurations Message-ID: <7eaeb82034087429f691ad56e7abe4a6ddfe04d8.1582038163.git.michal.simek@xilinx.com> Instead of symlink include origin file and just change model description. Difference is not in DT but in ps7_init configurations which is taken based on device tree name that's why the same DT can't be used. Also update model and update comments to match configurations. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc770-xm011-x16.dts | 12 +++++++++++- arch/arm/dts/zynq-zc770-xm011.dts | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-) mode change 120000 => 100644 arch/arm/dts/zynq-zc770-xm011-x16.dts diff --git a/arch/arm/dts/zynq-zc770-xm011-x16.dts b/arch/arm/dts/zynq-zc770-xm011-x16.dts deleted file mode 120000 index 5bd6af39a437..000000000000 --- a/arch/arm/dts/zynq-zc770-xm011-x16.dts +++ /dev/null @@ -1 +0,0 @@ -zynq-zc770-xm011.dts \ No newline at end of file diff --git a/arch/arm/dts/zynq-zc770-xm011-x16.dts b/arch/arm/dts/zynq-zc770-xm011-x16.dts new file mode 100644 index 000000000000..6ff8393d7ebe --- /dev/null +++ b/arch/arm/dts/zynq-zc770-xm011-x16.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM011 board DTS with NAND x16 + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +#include "zynq-zc770-xm011.dts" + +/ { + model = "Xilinx ZC770 XM011 board (NAND x16)"; +}; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 61482017d65c..b6e3e255d731 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZC770 XM013 board DTS + * Xilinx ZC770 XM011 board DTS * * Copyright (C) 2013-2018 Xilinx, Inc. */