From patchwork Mon Jul 20 06:11:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 235754 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1705403ilg; Sun, 19 Jul 2020 23:27:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxAfJlUUSQqhtFWPMgIDDiKQWWdKWkyhcqtlJpPb7lYP42F5PP5nVDbKQPF4aKR8XLokVfO X-Received: by 2002:aa7:c31a:: with SMTP id l26mr19440268edq.61.1595226470581; Sun, 19 Jul 2020 23:27:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595226470; cv=none; d=google.com; s=arc-20160816; b=OXMzrfgRMGOgiJb2IMjtnAKQyd6E3wV8vJa+6jra8zkt/p02QRleo9OeaB2MYfulzV 6lQU2b5yxfY7KWq2vJL8zaUHaFmDwU/gGDWbAjssXTDU7VCfpWeH1JGLpdqD10IQ+rqX bap5FmELKlWsuG8nJva3JCJ9vmeIKF7CbRhmBdBkBusAL5YYHYUZLMj7wEHe62XdKEyh /InKJaH4PrMHcew9Ff1rp/HdnjBYAilWj0hFnWdSby9mY/j3ZWSZ7dckR3+TxMYU9VpA zTkZe+FDhZWhkKinY8MedT7GzfZsDncP5XhC9kRad0038+y7cwJoEVQfe3+nEGa5dI1O hhCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter; bh=ajfXrjRuB0rLVPDDQjNsmNcHActPPCJsNqB8ecJD89c=; b=bMh5h2D9RPQU41ZIuf+47mw3fqmJrzX2mHa4VAqUGxZ/6PuUqLNcnvaIkL/0162Hcq 4NsNby1VuxVqix5Rn+d5R9iONuitXhqHNHbsx0gw8/+SWNVD/BCWRows4VML6isgvULZ vJWwwUAkQIRGDDzteUrTZV/J+1rrMfYqt+l5J5yzI/q1y2xMwONzT6qnR+M5RIjUykqd pTrt9+0A3jETNLJvYeRt8Ex/kXiN991gmbCOBBI530KbINeQgPSnYWw+6REdXyXiEZ12 4UXNgB8mes4quH8jAv35E7m9uMfl/Xeie6hgCWnuC/rlAngD6t9nLXtw8qqTOQ9woc+6 bFkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b="J7C/fXyh"; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c9si9542279ejb.631.2020.07.19.23.27.50; Sun, 19 Jul 2020 23:27:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b="J7C/fXyh"; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726486AbgGTG1t (ORCPT + 5 others); Mon, 20 Jul 2020 02:27:49 -0400 Received: from condef-05.nifty.com ([202.248.20.70]:17566 "EHLO condef-05.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726084AbgGTG1t (ORCPT ); Mon, 20 Jul 2020 02:27:49 -0400 X-Greylist: delayed 371 seconds by postgrey-1.27 at vger.kernel.org; Mon, 20 Jul 2020 02:27:48 EDT Received: from conuserg-12.nifty.com ([10.126.8.75])by condef-05.nifty.com with ESMTP id 06K6CTPX019132 for ; Mon, 20 Jul 2020 15:12:29 +0900 Received: from oscar.flets-west.jp (softbank126025067101.bbtec.net [126.25.67.101]) (authenticated) by conuserg-12.nifty.com with ESMTP id 06K6Bt9l014925; Mon, 20 Jul 2020 15:11:55 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com 06K6Bt9l014925 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1595225516; bh=ajfXrjRuB0rLVPDDQjNsmNcHActPPCJsNqB8ecJD89c=; h=From:To:Cc:Subject:Date:From; b=J7C/fXyhUPfJiiJlAhOEPPbDjm2vC8Z2dwTJfHtX0eN35TFplwpntwKPwp2s7LsQa p/AzyI9623hLu0yUZNFJwD1LsRpKV7LrKcogBMadLnWb+KlmnFuG6KzCq1faN+mo1L Peb1pVise7xPxuuCU4zfmIAp0QIIf+T4cKC6q+2lx8M3SiA4KmMKXp+Wx7JufdHACO MpUUWeY51qM6eoH0ztzbnHQw4NC4H3PjgZc3J5gXpvyaacbS7saWoF50pwRpt6TG7v +OwwSuBF+hRjqu/J9aUoALb+ZAwT3Uc7VIOxbxsiD/FWo/Qed9pkOnGlRtZRl08r3l TYB88tPEGehWQ== X-Nifty-SrcIP: [126.25.67.101] From: Masahiro Yamada To: Adrian Hunter , linux-mmc@vger.kernel.org, Ulf Hansson Cc: Masahiro Yamada , linux-kernel@vger.kernel.org Subject: [PATCH] mmc: sdhci-cadence: do not use hardware tuning for SD mode Date: Mon, 20 Jul 2020 15:11:41 +0900 Message-Id: <20200720061141.172944-1-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org As commit ef6b75671b5f ("mmc: sdhci-cadence: send tune request twice to work around errata") stated, this IP has an errata. This commit applies the second workaround for the SD mode. Due to the errata, it is not possible to use the hardware tuning provided by SDHCI_HOST_CONTROL2. Use the software-controlled tuning like the eMMC mode. Set sdhci_host_ops::platform_execute_tuning instead of overriding mmc_host_ops::execute_tuning. Signed-off-by: Masahiro Yamada --- drivers/mmc/host/sdhci-cadence.c | 123 ++++++++++++++++--------------- 1 file changed, 62 insertions(+), 61 deletions(-) -- 2.25.1 diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 4a6c9ba82538..4d9f7681817c 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -202,57 +202,6 @@ static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp); } -static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, - unsigned int timing) -{ - struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); - u32 mode; - - switch (timing) { - case MMC_TIMING_MMC_HS: - mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; - break; - case MMC_TIMING_MMC_DDR52: - mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; - break; - case MMC_TIMING_MMC_HS200: - mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; - break; - case MMC_TIMING_MMC_HS400: - if (priv->enhanced_strobe) - mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES; - else - mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; - break; - default: - mode = SDHCI_CDNS_HRS06_MODE_SD; - break; - } - - sdhci_cdns_set_emmc_mode(priv, mode); - - /* For SD, fall back to the default handler */ - if (mode == SDHCI_CDNS_HRS06_MODE_SD) - sdhci_set_uhs_signaling(host, timing); -} - -static const struct sdhci_ops sdhci_cdns_ops = { - .set_clock = sdhci_set_clock, - .get_timeout_clock = sdhci_cdns_get_timeout_clock, - .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_reset, - .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, -}; - -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { - .ops = &sdhci_cdns_ops, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, -}; - -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { - .ops = &sdhci_cdns_ops, -}; - static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) { struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); @@ -286,23 +235,24 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) return 0; } -static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode) +/* + * In SD mode, software must not use the hardware tuning and instead perform + * an almost identical procedure to eMMC. + */ +static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode) { - struct sdhci_host *host = mmc_priv(mmc); int cur_streak = 0; int max_streak = 0; int end_of_streak = 0; int i; /* - * This handler only implements the eMMC tuning that is specific to - * this controller. Fall back to the standard method for SD timing. + * Do not execute tuning for UHS_SDR50 or UHS_DDR50. + * The delay is set by probe, based on the DT properties. */ - if (host->timing != MMC_TIMING_MMC_HS200) - return sdhci_execute_tuning(mmc, opcode); - - if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) - return -EINVAL; + if (host->timing != MMC_TIMING_MMC_HS200 && + host->timing != MMC_TIMING_UHS_SDR104) + return 0; for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) { if (sdhci_cdns_set_tune_val(host, i) || @@ -325,6 +275,58 @@ static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode) return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2); } +static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 mode; + + switch (timing) { + case MMC_TIMING_MMC_HS: + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; + break; + case MMC_TIMING_MMC_DDR52: + mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; + break; + case MMC_TIMING_MMC_HS200: + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; + break; + case MMC_TIMING_MMC_HS400: + if (priv->enhanced_strobe) + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES; + else + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; + break; + default: + mode = SDHCI_CDNS_HRS06_MODE_SD; + break; + } + + sdhci_cdns_set_emmc_mode(priv, mode); + + /* For SD, fall back to the default handler */ + if (mode == SDHCI_CDNS_HRS06_MODE_SD) + sdhci_set_uhs_signaling(host, timing); +} + +static const struct sdhci_ops sdhci_cdns_ops = { + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .platform_execute_tuning = sdhci_cdns_execute_tuning, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { + .ops = &sdhci_cdns_ops, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +}; + +static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { + .ops = &sdhci_cdns_ops, +}; + static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -385,7 +387,6 @@ static int sdhci_cdns_probe(struct platform_device *pdev) priv->hrs_addr = host->ioaddr; priv->enhanced_strobe = false; host->ioaddr += SDHCI_CDNS_SRS_BASE; - host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; sdhci_enable_v4_mode(host);