From patchwork Fri Jul 17 08:49:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahisa Kojima X-Patchwork-Id: 235684 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1507031ilg; Fri, 17 Jul 2020 01:50:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyCkm0qHJJKZPEQvzIq9Nt0kx4M6SieQwivR7zczh7c+HWGJNY7CdntFwsjIBp42tLbuWem X-Received: by 2002:a17:906:26d6:: with SMTP id u22mr7934267ejc.271.1594975819584; Fri, 17 Jul 2020 01:50:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594975819; cv=none; d=google.com; s=arc-20160816; b=oCY90ZkC71IgIyLqXtOfrEo+M08LMI819e40UdiyBfoXVEM5haETEKIZdx2gUAWuiS eRwgCnmaiOa/d03/OdFSLhHGJc3vkUSM15j+A+s/pfZwmo0DkAY+Ke0DVv+ehQsnbi+A uhTECXL9rSnU6HD7dxgsE3GgoMbxqvC6TKi8C33XTYsrrC5lis9ROMvazSnEAxOpnTZe m2lnaEcTk4CgP/QUencLxAMZPmkcefAtD6z2PHr8ZIyU/F9pbsz9Jz6ysm58w5b7ect5 /72kYZVZ/QIODYyjiKUxdv7UEig7eeOSZ+RCLVIiN2ntWCGxmkiOX2c5P+cypZA9wyLU XWBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hRI9+M8x3rX5N8lHLXY7VIxGZcILlVx4V1n6t6KTjFI=; b=IX/FNj0iFmKijs9kmhFWY7dyoD4FgzRuCMhlG7QizEdNkfoLXc8WmL9s2XVhn2YFpB g0BtlTRguZCrPcR51vQWZIIIHgh5T6a2tJbomGuMiaWwzQWBy7bk7qs9am0bxkM4Loz+ LuOn4U/pMog2oSG9zGyXUmpS8mNVJEPwcVagPVjnG6jUoLpmcskN6Iqe7UH69IymXzfZ SHOga3XVLQJ1pJ3xn/WEBTPJm79uhv5pewdlN86MwQc9kFr76eFvccr+gsDVi2QDikoE ddVUj5+BdNOA9qb1zgA7UXs6YpLBWaAHkpnepsLmk9SC74B9WXr53RdAQrC7V41kgjKQ ueLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K0ahTUhH; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id jp23si4580533ejb.5.2020.07.17.01.50.19; Fri, 17 Jul 2020 01:50:19 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K0ahTUhH; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726198AbgGQIuS (ORCPT + 6 others); Fri, 17 Jul 2020 04:50:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726113AbgGQIuR (ORCPT ); Fri, 17 Jul 2020 04:50:17 -0400 Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90FDBC08C5C0 for ; Fri, 17 Jul 2020 01:50:17 -0700 (PDT) Received: by mail-pl1-x644.google.com with SMTP id o1so5183780plk.1 for ; Fri, 17 Jul 2020 01:50:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hRI9+M8x3rX5N8lHLXY7VIxGZcILlVx4V1n6t6KTjFI=; b=K0ahTUhH2yynvg7PEUDHiPPwSqKFNHsIuyZQFnsKDydtS2+ENT9Gpcg8PqlC4czLKB enYbOZiLaphhUtjJJMzdpLNB+kGm6nhaHDY0pkS/rkPBYisHjii54xBmf3xuiaRRRqcw HuNvd5wprfgjrC7jPSA0hrAkrTWOgHuWP9RBj+Np03CH4cNkZDIfKSmlcnVMBt0ZDd4L 2uY/ttoFkc1HCEIZgA4SkrKjvjtFkesO/0YrTAoLp8925vMvVN03xHWSlnfXUmoZbsbU Dv48FM4np175PQ7633Iz+ouXAvPZP2nyR02cum4rzvLk8yV1k/7x4/UdCZm0aX6jg5iz 1mDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hRI9+M8x3rX5N8lHLXY7VIxGZcILlVx4V1n6t6KTjFI=; b=H/qIr4/vYZYmmgO+Br5Y3kGEpiicepczFnfN9TtbrxDKIDnEFRnxD5a3NDkJLj+sNI Ibj5i1BDfvT3XYSsi+Q959q/vgYwM/1OjqTRkCHUyhB1KmdVsU8XoK86laQm8CFbpGMB 3YJW60zCOG4SLpyHVmq+FtNO3uTej7So6q1pNwtzDHKXjjK7R5TT08KjAvSF+DpuPkS/ MI3kAvZlEC0hmovNqG5nyQ+AmEY+9M/5CvIjLQlPqXKMK5eudZ+f2l5rfBk494/7quuB kdh3yxIFP+aPo+yzrtga6vgojYdixlfhyWSip87LetmZ7DdQ91Ypk7W1+Ag1oRVcJSc9 kIaA== X-Gm-Message-State: AOAM5305kGJfKL06hPmlFUDdl0RSnqjNjZJEt/QKU1VVLQVFKZ7E/Z3+ ku7lzAVol82IURZaOomyEyNEVw== X-Received: by 2002:a17:902:eb49:: with SMTP id i9mr6459968pli.231.1594975817050; Fri, 17 Jul 2020 01:50:17 -0700 (PDT) Received: from debian.flets-east.jp ([2400:2411:502:a100:c84b:19e2:9b53:48bb]) by smtp.gmail.com with ESMTPSA id f207sm7309364pfa.107.2020.07.17.01.50.14 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Jul 2020 01:50:16 -0700 (PDT) From: Masahisa Kojima To: linux-kernel@vger.kernel.org Cc: masahisa.kojima@linaro.org, jarkko.sakkinen@linux.intel.com, linux-arm-kernel@lists.infradead.org, ardb@kernel.org, devicetree@vger.kernel.org, linux-integrity@vger.kernel.org, peterhuewe@gmx.de, jgg@ziepe.ca Subject: [PATCH v4 1/2] tpm: tis: add support for MMIO TPM on SynQuacer Date: Fri, 17 Jul 2020 17:49:31 +0900 Message-Id: <20200717084932.3449-2-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200717084932.3449-1-masahisa.kojima@linaro.org> References: <20200717084932.3449-1-masahisa.kojima@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When fitted, the SynQuacer platform exposes its SPI TPM via a MMIO window that is backed by the SPI command sequencer in the SPI bus controller. This arrangement has the limitation that only byte size accesses are supported, and so we'll need to provide a separate module that take this into account. Signed-off-by: Ard Biesheuvel Signed-off-by: Masahisa Kojima --- drivers/char/tpm/Kconfig | 12 ++ drivers/char/tpm/Makefile | 1 + drivers/char/tpm/tpm_tis_synquacer.c | 209 +++++++++++++++++++++++++++ 3 files changed, 222 insertions(+) create mode 100644 drivers/char/tpm/tpm_tis_synquacer.c -- 2.20.1 diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig index 58b4c573d176..a18c314da211 100644 --- a/drivers/char/tpm/Kconfig +++ b/drivers/char/tpm/Kconfig @@ -74,6 +74,18 @@ config TCG_TIS_SPI_CR50 If you have a H1 secure module running Cr50 firmware on SPI bus, say Yes and it will be accessible from within Linux. +config TCG_TIS_SYNQUACER + tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)" + depends on ARCH_SYNQUACER + select TCG_TIS_CORE + help + If you have a TPM security chip that is compliant with the + TCG TIS 1.2 TPM specification (TPM1.2) or the TCG PTP FIFO + specification (TPM2.0) say Yes and it will be accessible from + within Linux on Socionext SynQuacer platform. + To compile this driver as a module, choose M here; + the module will be called tpm_tis_synquacer. + config TCG_TIS_I2C_ATMEL tristate "TPM Interface Specification 1.2 Interface (I2C - Atmel)" depends on I2C diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile index 9567e5197f74..84db4fb3a9c9 100644 --- a/drivers/char/tpm/Makefile +++ b/drivers/char/tpm/Makefile @@ -21,6 +21,7 @@ tpm-$(CONFIG_EFI) += eventlog/efi.o tpm-$(CONFIG_OF) += eventlog/of.o obj-$(CONFIG_TCG_TIS_CORE) += tpm_tis_core.o obj-$(CONFIG_TCG_TIS) += tpm_tis.o +obj-$(CONFIG_TCG_TIS_SYNQUACER) += tpm_tis_synquacer.o obj-$(CONFIG_TCG_TIS_SPI) += tpm_tis_spi.o tpm_tis_spi-y := tpm_tis_spi_main.o diff --git a/drivers/char/tpm/tpm_tis_synquacer.c b/drivers/char/tpm/tpm_tis_synquacer.c new file mode 100644 index 000000000000..ac2a1d2a5001 --- /dev/null +++ b/drivers/char/tpm/tpm_tis_synquacer.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linaro Ltd. + * + * This device driver implements MMIO TPM on SynQuacer Platform. + */ +#include +#include +#include +#include +#include +#include +#include +#include "tpm.h" +#include "tpm_tis_core.h" + +struct tpm_tis_synquacer_info { + struct resource res; + /* irq > 0 means: use irq $irq; + * irq = 0 means: autoprobe for an irq; + * irq = -1 means: no irq support + */ + int irq; +}; + +struct tpm_tis_synquacer_phy { + struct tpm_tis_data priv; + void __iomem *iobase; +}; + +static inline struct tpm_tis_synquacer_phy *to_tpm_tis_tcg_phy(struct tpm_tis_data *data) +{ + return container_of(data, struct tpm_tis_synquacer_phy, priv); +} + +static int tpm_tis_synquacer_read_bytes(struct tpm_tis_data *data, u32 addr, + u16 len, u8 *result) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + while (len--) + *result++ = ioread8(phy->iobase + addr); + + return 0; +} + +static int tpm_tis_synquacer_write_bytes(struct tpm_tis_data *data, u32 addr, + u16 len, const u8 *value) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + while (len--) + iowrite8(*value++, phy->iobase + addr); + + return 0; +} + +static int tpm_tis_synquacer_read16_bw(struct tpm_tis_data *data, + u32 addr, u16 *result) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + /* + * Due to the limitation of SPI controller on SynQuacer, + * 16/32 bits access must be done in byte-wise and descending order. + */ + *result = (ioread8(phy->iobase + addr + 1) << 8) | + (ioread8(phy->iobase + addr)); + + return 0; +} + +static int tpm_tis_synquacer_read32_bw(struct tpm_tis_data *data, + u32 addr, u32 *result) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + /* + * Due to the limitation of SPI controller on SynQuacer, + * 16/32 bits access must be done in byte-wise and descending order. + */ + *result = (ioread8(phy->iobase + addr + 3) << 24) | + (ioread8(phy->iobase + addr + 2) << 16) | + (ioread8(phy->iobase + addr + 1) << 8) | + (ioread8(phy->iobase + addr)); + + return 0; +} + +static int tpm_tis_synquacer_write32_bw(struct tpm_tis_data *data, + u32 addr, u32 value) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + /* + * Due to the limitation of SPI controller on SynQuacer, + * 16/32 bits access must be done in byte-wise and descending order. + */ + iowrite8(value >> 24, phy->iobase + addr + 3); + iowrite8(value >> 16, phy->iobase + addr + 2); + iowrite8(value >> 8, phy->iobase + addr + 1); + iowrite8(value, phy->iobase + addr); + + return 0; +} + +static const struct tpm_tis_phy_ops tpm_tcg_bw = { + .read_bytes = tpm_tis_synquacer_read_bytes, + .write_bytes = tpm_tis_synquacer_write_bytes, + .read16 = tpm_tis_synquacer_read16_bw, + .read32 = tpm_tis_synquacer_read32_bw, + .write32 = tpm_tis_synquacer_write32_bw, +}; + +static int tpm_tis_synquacer_init(struct device *dev, + struct tpm_tis_synquacer_info *tpm_info) +{ + struct tpm_tis_synquacer_phy *phy; + + phy = devm_kzalloc(dev, sizeof(struct tpm_tis_synquacer_phy), GFP_KERNEL); + if (phy == NULL) + return -ENOMEM; + + phy->iobase = devm_ioremap_resource(dev, &tpm_info->res); + if (IS_ERR(phy->iobase)) + return PTR_ERR(phy->iobase); + + return tpm_tis_core_init(dev, &phy->priv, tpm_info->irq, &tpm_tcg_bw, + ACPI_HANDLE(dev)); +} + +static SIMPLE_DEV_PM_OPS(tpm_tis_synquacer_pm, tpm_pm_suspend, tpm_tis_resume); + +static int tpm_tis_synquacer_probe(struct platform_device *pdev) +{ + struct tpm_tis_synquacer_info tpm_info = {}; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + return -ENODEV; + } + tpm_info.res = *res; + + tpm_info.irq = -1; + + return tpm_tis_synquacer_init(&pdev->dev, &tpm_info); +} + +static int tpm_tis_synquacer_remove(struct platform_device *pdev) +{ + struct tpm_chip *chip = dev_get_drvdata(&pdev->dev); + + tpm_chip_unregister(chip); + tpm_tis_remove(chip); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id tis_synquacer_of_platform_match[] = { + {.compatible = "socionext,synquacer-tpm-mmio"}, + {}, +}; +MODULE_DEVICE_TABLE(of, tis_synquacer_of_platform_match); +#endif + +#ifdef CONFIG_ACPI +static const struct acpi_device_id tpm_synquacer_acpi_tbl[] = { + { "SCX0009" }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, tpm_synquacer_acpi_tbl); +#endif + +static struct platform_driver tis_synquacer_drv = { + .probe = tpm_tis_synquacer_probe, + .remove = tpm_tis_synquacer_remove, + .driver = { + .name = "tpm_tis_synquacer", + .pm = &tpm_tis_synquacer_pm, + .of_match_table = of_match_ptr(tis_synquacer_of_platform_match), + .acpi_match_table = ACPI_PTR(tpm_synquacer_acpi_tbl), + }, +}; + +static int __init tpm_tis_synquacer_module_init(void) +{ + int rc; + + rc = platform_driver_register(&tis_synquacer_drv); + if (rc) + return rc; + + return 0; +} + +static void __exit tpm_tis_synquacer_module_exit(void) +{ + platform_driver_unregister(&tis_synquacer_drv); +} + +module_init(tpm_tis_synquacer_module_init); +module_exit(tpm_tis_synquacer_module_exit); +MODULE_AUTHOR("Masahisa Kojima (masahisa.kojima@linaro.org)"); +MODULE_DESCRIPTION("TPM MMIO Driver for Socionext SynQuacer platform"); +MODULE_VERSION("2.0"); +MODULE_LICENSE("GPL"); From patchwork Fri Jul 17 08:49:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahisa Kojima X-Patchwork-Id: 235685 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1507096ilg; Fri, 17 Jul 2020 01:50:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwe7o3wvEUDpJ+2SQuUV+nFh8gv7PSZQXvaFiZba3nEcmZNlCPVYng/xhkI2P3s/sgxhmf9 X-Received: by 2002:a17:906:cce6:: with SMTP id ot38mr7503542ejb.266.1594975827652; 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[23.128.96.18]) by mx.google.com with ESMTP id mb7si4771209ejb.316.2020.07.17.01.50.27; Fri, 17 Jul 2020 01:50:27 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lRtQzivE; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726293AbgGQIuX (ORCPT + 6 others); Fri, 17 Jul 2020 04:50:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726234AbgGQIuW (ORCPT ); Fri, 17 Jul 2020 04:50:22 -0400 Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA32AC08C5C0 for ; Fri, 17 Jul 2020 01:50:22 -0700 (PDT) Received: by mail-pf1-x442.google.com with SMTP id t11so5066639pfq.11 for ; Fri, 17 Jul 2020 01:50:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PD2ZLQCvLaWVcoV1PzZsr55F59ipm51nH9LfNuI1BWE=; b=lRtQzivEf2cCiMyei1lVXETGj3wO+frDXypbkG9dastQNt9ukpIkiW1uHKa96n7L1m 9aQxIP3dbyq33eF2GJ+iNrBMDKd5HwIdJ8W1/lzafOBHQXzpqxN0CQrglNxsrkk9IaMT CpB9WBuu7qJGza5D5lxMmfdhxPmqrvFJlMqBZsZe1aFDJ9uTCgV04YaedAyLcrZ3viUy tT91uJD7nyMJ+AY6we1LzwkroN1cK43LBwYex/fypAfMErA0yOrmETET80xy0LT72Hlw 7v536I49sOzpqQJwr+7hOl7JM4xeQ4NMbm1BN5YrJY+vfoN+VZlClYgN5nM7I8T6DQjQ vJ3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PD2ZLQCvLaWVcoV1PzZsr55F59ipm51nH9LfNuI1BWE=; b=W92bXAthrk6OsUQn0mRLo7N2XOMGRbxVw9/YdpWBsPTg28cBBJ2cdQyCFFF+RNECae /Q8aIlGaz0c826T4uQCdaGwzUY9N0PhCywbtKzGlLs/zllW+M4GyH4BN44B3aNLhjvp6 rfjJuE0Plu8X8VXqMVfZbpyG9vOy5luhDpHi4Bj2K9gFyeucbflZ14CVSIZxZu8naEBI NKTS6WxVfu/cZhyG9rnPwPGT68CZpxUBenSuXB9e6VKIsGT4C/U0XRFU1rYO8uCRB2O4 StbwNSkMf1X2h1P2BE4Ar4gQ5ZSVNoacmypcI8ykw5YiVANcY2ifMbQGKO6is+ZgCTaR 7Fcw== X-Gm-Message-State: AOAM533qJ8SUvUJ8YxOoCmAlKVse8oMQbAtK0Q7tPoiITHZ6e1G25Lfy xTcM7M+0RID/3lHqFQ0zAcQzEA== X-Received: by 2002:a63:125a:: with SMTP id 26mr8055436pgs.340.1594975822468; Fri, 17 Jul 2020 01:50:22 -0700 (PDT) Received: from debian.flets-east.jp ([2400:2411:502:a100:c84b:19e2:9b53:48bb]) by smtp.gmail.com with ESMTPSA id f207sm7309364pfa.107.2020.07.17.01.50.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Jul 2020 01:50:21 -0700 (PDT) From: Masahisa Kojima To: linux-kernel@vger.kernel.org Cc: masahisa.kojima@linaro.org, jarkko.sakkinen@linux.intel.com, linux-arm-kernel@lists.infradead.org, ardb@kernel.org, devicetree@vger.kernel.org, linux-integrity@vger.kernel.org, peterhuewe@gmx.de, jgg@ziepe.ca, Rob Herring , Rob Herring Subject: [PATCH v4 2/2] dt-bindings: Add SynQucer TPM MMIO as a trivial device Date: Fri, 17 Jul 2020 17:49:32 +0900 Message-Id: <20200717084932.3449-3-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200717084932.3449-1-masahisa.kojima@linaro.org> References: <20200717084932.3449-1-masahisa.kojima@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a compatible string for the SynQuacer TPM to the binding for a TPM exposed via a memory mapped TIS frame. The MMIO window behaves slightly differently on this hardware, so it requires its own identifier. Cc: Rob Herring Cc: Ard Biesheuvel Acked-by: Rob Herring Signed-off-by: Masahisa Kojima --- Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ 1 file changed, 2 insertions(+) -- 2.20.1 diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 4165352a590a..814148939e5a 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -328,6 +328,8 @@ properties: - silabs,si7020 # Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply - skyworks,sky81452 + # Socionext SynQuacer TPM MMIO module + - socionext,synquacer-tpm-mmio # i2c serial eeprom (24cxx) - st,24c256 # Ambient Light Sensor with SMBUS/Two Wire Serial Interface