From patchwork Mon Jul 13 11:01:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235377 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726097ilg; Mon, 13 Jul 2020 04:02:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwGjFqLyta7Z0em+3Q+qB6NjPZhWFkhScVdyBnINWIA1uKPj2gCwPjSF96Vw6U73DWsVwA6 X-Received: by 2002:a17:907:2108:: with SMTP id qn8mr68010731ejb.16.1594638126453; Mon, 13 Jul 2020 04:02:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638126; cv=none; d=google.com; s=arc-20160816; b=0qtNJWm6InwG3nK4/u6eylqcgIovBDf2qqm1YljUK7nYCh1WLmQs2auGqlRcL6hcMq cuHewxoQYrnz9LA9PtlwTskLGT4FYcAJ2lgZ5c4ZSKjB6IU1NhxSVg+++3Yz9Obs9J0I hCWv2VUDyN8PWwKQIeYPI0rd+7OuDvU2i87kWyqAbZH/C7ii3u42f5qyJgiHDNFMPMk6 sQAqTCLdO8I367l3mIwMd+heQW9lCCbJ0J612Y0rA718l/uvFozPdfXpvOtGySDaJqQm 3L23Q5Q7VlFKUlxEX4fJoxRSu0GaZa1l6NpCrWd/tKVPvUb/g1dbbZM4xbW3KXyipin6 JEZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ZG1VUcH+6tOwwV7BnhCzX/gBAhx0Ee8zky2NKNJPpXQ=; b=eT9oFtFqYd1hns/i5fbh1oneZjEIP0B7dKfDAbaXU74/rdTlnawktEqKs/AVog0pQO ZuM5dhg4KCrutHK/2BJgMnxMC52UejjG8lXho3OiV56AhbXgzVIc/ppATjCGexvs6shh +harrF5MDhnVPRkd+2fC31RIOBYKncO0Gyd53oyNZ1Eu1k7wJShdqh5xsCb7drAqFZHP LyV5VR4fk05JzXkkoe23fJ3V07DeZgaJPtQOVnzG19K501CtLzJwpcKVHKO2FJTWHm3j E/yP5eODRYWKdiKOBgjdVlzaulXXn+OIcyM5lybrjiFqvuIyU3wrc1fHszb1JbhpRDIk oLvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iLcZlaFY; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ca17si9187578ejb.533.2020.07.13.04.02.06; Mon, 13 Jul 2020 04:02:06 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iLcZlaFY; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729613AbgGMLCE (ORCPT + 6 others); Mon, 13 Jul 2020 07:02:04 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:56768 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729594AbgGMLCE (ORCPT ); Mon, 13 Jul 2020 07:02:04 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1rRO101036; Mon, 13 Jul 2020 06:01:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638113; bh=ZG1VUcH+6tOwwV7BnhCzX/gBAhx0Ee8zky2NKNJPpXQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iLcZlaFYgxY+pEddiCt4s0N65g148YmhrBqaWqC72bVb6Z+vCsVZ0j5iDnBkSapkF nduM9TqEoUbGUxHU5ar29OmsrViS8QRqqqXo7IY1GPlp7GxS5GmafIHJES9iZ0XkDn H2v7u9nbw40E9r/qEG7Z9nKVj0qaiKtAoDBVmlhA= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 06DB1rWt009039 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 13 Jul 2020 06:01:53 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:01:53 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:01:53 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVc031460; Mon, 13 Jul 2020 06:01:50 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 02/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Date: Mon, 13 Jul 2020 16:31:29 +0530 Message-ID: <20200713110141.13156-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a macro for aligning down a pointer. This is useful to get an aligned register address when a device allows only word access and doesn't allow half word or byte access. Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- include/linux/kernel.h | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 9b7a8d74a9d6..c3b361b5be54 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -34,6 +34,7 @@ #define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) #define __ALIGN_MASK(x, mask) __ALIGN_KERNEL_MASK((x), (mask)) #define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define PTR_ALIGN_DOWN(p, a) ((typeof(p))ALIGN_DOWN((unsigned long)(p), (a))) #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) /* generic data direction definitions */ From patchwork Mon Jul 13 11:01:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235378 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726211ilg; Mon, 13 Jul 2020 04:02:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxsh3YvynDmOBBL9obFFCYx1B+JsIp4vdpEPlCM7HUKQWrlRf6YyYDtsi6vTpWnUAcMXJTK X-Received: by 2002:a17:907:2489:: with SMTP id zg9mr70864008ejb.48.1594638133025; Mon, 13 Jul 2020 04:02:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638133; cv=none; d=google.com; s=arc-20160816; b=CNAJI28G0Qdv0jgksMEXjsysepX0/3gR7xk14JMATAiD9Gd//4pNREdBfHL77kfDUZ mhYhDy+k3uwvS1ek1U2XQowTwLyyPkT7qzrqkFOqu8GwStx3a4DdZW+gW+A13/aaPZrk fuLlhauYu5IuEaJZ4kTbG+qlrSp+HXvwE6lXA3hiWFVsqLCDJTauKeAEgSwU1edzF+Es 0npqxcFiSPwdJM8VcrK3zVPBY9x3hlQEeKcXoiIJ/GSMog/5sYSPrj4isk2vqjr8TxeC 8vIYjVh35mxN20QpQRQpDSkzTGramz9wpXfqfgjiDJT2eA/EBUHvUMfwaxSMJke8BzF/ Rvng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=fkBtp+U4H+Rsz2F0H88TEXPb+zBTcNhWs4srHjBvzA4=; b=dSXIOdzPHE91JtheI5QM+iDcU3BSIGj/s7YkPfkKUZnvwQ8qgMouVjFulxkqrGXcme kXby40mzddgDJVdYKV/kiJmDjKyMUNO0fEfyGTmQEKJ26ueukiCMkd5G2046//3AsZj0 nMkec8RwGFl7/xmHBcXy5BCXj+CESYEKXRZUhYqd+VxnXXUadV0u6ySMEi/6OGY6oSsC 0w+KcrZEGShakz9tGXihDXa2NLcXeT9Bm2SepMmKT3PbKZIDz2SYxdNRjyNAZTnUX7Pj /shMNiViKXIr+lT3Ca19nS8OQtIiM42xSMbGKok0g5RKs0quRVBb3p7tvW9kDfa2xC/S rN5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OK0K3qEZ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id cy15si8449194edb.22.2020.07.13.04.02.12; Mon, 13 Jul 2020 04:02:13 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OK0K3qEZ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729632AbgGMLCL (ORCPT + 6 others); Mon, 13 Jul 2020 07:02:11 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:48004 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729594AbgGMLCL (ORCPT ); Mon, 13 Jul 2020 07:02:11 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1vAR093286; Mon, 13 Jul 2020 06:01:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638117; bh=fkBtp+U4H+Rsz2F0H88TEXPb+zBTcNhWs4srHjBvzA4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OK0K3qEZNGzaSDMR50dsPoXJco4CcxR/hWjr0TZmsh1MaKkmWmhS3ihKncTyFMZRY uvDN0LY5n9lJCzqgUUiG1BBfQWf579IA8kfPP6szPLvbiDG+vZUYD8WpTIwkshJQdG aGd4igiHHI65zjZ6omo6okAieBFKa12W7f4B3xpY= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 06DB1vF3108455 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 13 Jul 2020 06:01:57 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:01:57 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:01:57 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVd031460; Mon, 13 Jul 2020 06:01:54 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses Date: Mon, 13 Jul 2020 16:31:30 +0530 Message-ID: <20200713110141.13156-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Certain platforms like TI's J721E using Cadence PCIe IP can perform only 32-bit accesses for reading or writing to Cadence registers. Convert all read and write accesses to 32-bit in Cadence PCIe driver in preparation for adding PCIe support in TI's J721E SoC. Also add spin lock to disable interrupts while modifying PCI_STATUS register while raising legacy interrupt since PCI_STATUS is accessible by both remote RC and EP and time between read and write should be minimized. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/cadence/pcie-cadence-ep.c | 4 + drivers/pci/controller/cadence/pcie-cadence.h | 76 ++++++++++++++----- 2 files changed, 62 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 4a829ccff7d0..c6eb2db94680 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -228,6 +228,7 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx, bool is_asserted) { struct cdns_pcie *pcie = &ep->pcie; + unsigned long flags; u32 offset; u16 status; u8 msg_code; @@ -252,11 +253,13 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, msg_code = MSG_CODE_DEASSERT_INTA + intx; } + spin_lock_irqsave(&ep->lock, flags); status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) { status ^= PCI_STATUS_INTERRUPT; cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); } + spin_unlock_irqrestore(&ep->lock, flags); offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | CDNS_PCIE_NORMAL_MSG_CODE(msg_code) | @@ -464,6 +467,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; /* Reserve region 0 for IRQs */ set_bit(0, &ep->ob_region_map); + spin_lock_init(&ep->lock); return 0; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index bc49c22e48a9..a45c11158f49 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -304,6 +304,9 @@ struct cdns_pcie_rc { * @irq_pci_fn: the latest PCI function that has updated the mapping of * the MSI/legacy IRQ dedicated outbound region. * @irq_pending: bitmask of asserted legacy IRQs. + * @lock: spin lock to disable interrupts while modifying PCIe controller + * registers fields (RMW) accessible by both remote RC and EP to + * minimize time between read and write */ struct cdns_pcie_ep { struct cdns_pcie pcie; @@ -315,54 +318,94 @@ struct cdns_pcie_ep { u64 irq_pci_addr; u8 irq_pci_fn; u8 irq_pending; + /* protect writing to PCI_STATUS while raising legacy interrupts */ + spinlock_t lock; }; /* Register access */ -static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) +static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) { - writeb(value, pcie->reg_base + reg); + writel(value, pcie->reg_base + reg); } -static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value) +static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) { - writew(value, pcie->reg_base + reg); + return readl(pcie->reg_base + reg); } -static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) +static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { - writel(value, pcie->reg_base + reg); + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); + unsigned int offset = (unsigned long)addr & 0x3; + u32 val = readl(aligned_addr); + + if (!IS_ALIGNED((uintptr_t)addr, size)) { + WARN(1, "Address %p and size %d are not aligned\n", addr, size); + return 0; + } + + if (size > 2) + return val; + + return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); } -static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) +static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value) { - return readl(pcie->reg_base + reg); + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); + unsigned int offset = (unsigned long)addr & 0x3; + u32 mask; + u32 val; + + if (!IS_ALIGNED((uintptr_t)addr, size)) { + WARN(1, "Address %p and size %d are not aligned\n", addr, size); + return; + } + + if (size > 2) { + writel(value, addr); + return; + } + + mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); + val = readl(aligned_addr) & mask; + val |= value << (offset * 8); + writel(val, aligned_addr); } /* Root Port register access */ static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) { - writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x1, value); } static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, u32 reg, u16 value) { - writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x2, value); } /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) { - writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + cdns_pcie_write_sz(addr, 0x1, value); } static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, u32 reg, u16 value) { - writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + cdns_pcie_write_sz(addr, 0x2, value); } static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, @@ -371,14 +414,11 @@ static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); } -static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg) -{ - return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); -} - static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) { - return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + return cdns_pcie_read_sz(addr, 0x2); } static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) From patchwork Mon Jul 13 11:01:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235389 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2727272ilg; Mon, 13 Jul 2020 04:03:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwo8marVrsyogQdW50kdHV2TBNPqXDFFx0ykuSYrs/JoCgw3tvb8tagqonywEFgTmNTALpd X-Received: by 2002:a17:906:4b59:: with SMTP id j25mr66804300ejv.301.1594638196575; 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The registers to start link and to check link status is in Platform specific PCIe wrapper. Add support for platform specific drivers to add callback functions for the PCIe Cadence core to start link and verify link status. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../pci/controller/cadence/pcie-cadence-ep.c | 8 ++++ .../controller/cadence/pcie-cadence-host.c | 28 ++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 37 ++++++++++++++++++- 3 files changed, 72 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index c6eb2db94680..034cb3cf726e 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -357,8 +357,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; + struct device *dev = pcie->dev; struct pci_epf *epf; u32 cfg; + int ret; /* * BIT(0) is hardwired to 1, hence function 0 is always enabled @@ -369,6 +371,12 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) cfg |= BIT(epf->func_no); cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg); + ret = cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + return 0; } diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 030e828bfd4c..de02fadc4809 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -3,6 +3,7 @@ // Cadence PCIe host controller driver. // Author: Cyrille Pitchen +#include #include #include #include @@ -419,6 +420,23 @@ static int cdns_pcie_host_init(struct device *dev, return err; } +static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev = pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} + int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { struct device *dev = rc->pcie.dev; @@ -467,6 +485,16 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) pcie->mem_res = res; + ret = cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + ret = cdns_pcie_host_wait_for_link(pcie); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) rc->avail_ib_bar[bar] = true; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index a45c11158f49..54e10caf2d4b 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,6 +10,11 @@ #include #include +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + /* * Local Management Registers */ @@ -245,12 +250,20 @@ enum cdns_pcie_msg_routing { MSG_ROUTING_GATHER, }; +struct cdns_pcie_ops { + int (*start_link)(struct cdns_pcie *pcie); + void (*stop_link)(struct cdns_pcie *pcie); + bool (*link_up)(struct cdns_pcie *pcie); +}; + /** * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base * @mem_res: start/end offsets in the physical system memory to map PCI accesses * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. * @bus: In Root Complex mode, the bus number + * @ops: Platform specific ops to control various inputs from Cadence PCIe + * wrapper */ struct cdns_pcie { void __iomem *reg_base; @@ -261,7 +274,7 @@ struct cdns_pcie { int phy_count; struct phy **phy; struct device_link **link; - const struct cdns_pcie_common_ops *ops; + const struct cdns_pcie_ops *ops; }; /** @@ -426,6 +439,28 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); } +static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) +{ + if (pcie->ops->start_link) + return pcie->ops->start_link(pcie); + + return 0; +} + +static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) +{ + if (pcie->ops->stop_link) + pcie->ops->stop_link(pcie); +} + +static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) +{ + if (pcie->ops->link_up) + return pcie->ops->link_up(pcie); + + return true; +} + #ifdef CONFIG_PCIE_CADENCE_HOST int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); #else From patchwork Mon Jul 13 11:01:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235379 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726341ilg; Mon, 13 Jul 2020 04:02:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHxIYkJhvHDUbEQ+OZBhm43aTF3ACPPk/xxS+9xmyFHgfT6SruL3NWp/e+DU28toej2y+g X-Received: by 2002:a17:906:dce:: with SMTP id p14mr71165903eji.442.1594638142392; Mon, 13 Jul 2020 04:02:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638142; cv=none; d=google.com; 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[23.128.96.18]) by mx.google.com with ESMTP id du12si11330949ejc.441.2020.07.13.04.02.22; Mon, 13 Jul 2020 04:02:22 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pfIRhWwi; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729670AbgGMLCT (ORCPT + 6 others); Mon, 13 Jul 2020 07:02:19 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:38236 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729662AbgGMLCR (ORCPT ); Mon, 13 Jul 2020 07:02:17 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB25KP055955; Mon, 13 Jul 2020 06:02:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638125; bh=CWIKltqarvAYPvUpTOXv+9gnETqUvut1kE2gYgu5r3Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pfIRhWwipv6SGa/UAOioj3jvsBWZ4YVbb2F3qs0aPt5zG6ni81aWyp5fYp4eGXqBx IlE51WgF2Uq0UczwVfVbgrM2C5CAuz5+swFuKL8mnXexL/AgysquGT6dh8uHjGk61B Xuh1jYu/5CZCkQ5hLcsLV0w1XuKCALdEIwSFmUf4= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 06DB25BS009571 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 13 Jul 2020 06:02:05 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:02:04 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:02:04 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVf031460; Mon, 13 Jul 2020 06:02:01 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 05/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Date: Mon, 13 Jul 2020 16:31:32 +0530 Message-ID: <20200713110141.13156-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Certain platforms like TI's J721E allows only 32-bit configuration space access. In such cases pci_generic_config_read and pci_generic_config_write cannot be used. Add support in Cadence core to let pci_host_bridge have custom pci_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index de02fadc4809..a8303258874c 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -505,7 +505,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) list_splice_init(&resources, &bridge->windows); bridge->dev.parent = dev; bridge->busnr = pcie->bus; - bridge->ops = &cdns_pcie_host_ops; + if (!bridge->ops) + bridge->ops = &cdns_pcie_host_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; From patchwork Mon Jul 13 11:01:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235384 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726833ilg; Mon, 13 Jul 2020 04:02:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyCzrSHybI0KRtmqIrbciFWjb9qU9b8iuob9zo0VStRN9hdjbxogg6QZkDTGyXXWNZQXVUF X-Received: by 2002:a05:6402:3049:: with SMTP id bu9mr78200212edb.232.1594638173181; Mon, 13 Jul 2020 04:02:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638173; cv=none; d=google.com; s=arc-20160816; b=Z4Jw4jAzRAiM2dlWS8+4XbEo1uxlUGLCvJdAqzNfLYV5j0So8y4HnNPhDDDI3Z/Bw7 LYn13QywEIujc55ALfxyy7DCHbUtnhhBjxjdsU2FUJsYEs2iGM0M0GksgwsyPEjFjLNr NvePKnirQ5q1jWe6wzUmDq2dbXNHsfFf+ibDePz/WKcJdfgULcBsJmJzqKIk07r0U5bI 6WRcXSF2hlQQsMxtQiAk5sk26BKEEczube8H2jHD8l8cyLID41etyDFylO0KuahKQoDS Dc2ZZYtvBj1F8fJnO6t0sSvaUywadORfM92KfvGTJ4oPGEd1+fnNyS43xx/ll4zi4eol cTRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ZmLHKDhhFvQEACU9S2JTUSC0cmWio3Xl+uM9GiBjHGs=; b=S8TMJ5XHyrQtELHcvP+jUsQLVWft6xdlEK2TzQpk7j5lvKXphMzcxXVQZ3urhbRJrG Bj7v1acNgUqglqoeWamwzrUTaXWD9LFKHg/fbKdByXb0QerfOOAZxDJsxGH8SX524kRg L9aPzbNfAo91derFFvJPz2RP5r90ZIStol/6zFcyoCQwb6et8zeahHHH8lMaiNm4To1v 3uR/ou49NH78QwP0DVaN9qqWTnU6ZqN4DL7iUW2xUdLQEazs0xvnvRhnaiIbmgPn1g58 8VfEEVXBYsk4MJTi0c6CdIpOi0X0CaUTju8+XTc7ykPU6YmHp6ZthteKhkQNMnrljMkh 7V8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nax7QOFO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- MAINTAINERS | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index 5bbc2649566b..bdec73c3069e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13119,12 +13119,14 @@ S: Maintained F: Documentation/devicetree/bindings/pci/designware-pcie.txt F: drivers/pci/controller/dwc/*designware* -PCI DRIVER FOR TI DRA7XX +PCI DRIVER FOR TI DRA7XX/J721E M: Kishon Vijay Abraham I L: linux-omap@vger.kernel.org L: linux-pci@vger.kernel.org +L: linux-arm-kernel@lists.infradead.org S: Supported F: Documentation/devicetree/bindings/pci/ti-pci.txt +F: drivers/pci/controller/cadence/pci-j721e.c F: drivers/pci/controller/dwc/pci-dra7xx.c PCI DRIVER FOR TI KEYSTONE