From patchwork Mon Jul 13 11:01:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235376 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726061ilg; Mon, 13 Jul 2020 04:02:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy1Vs4ql1UpcNV7QsN4dokrbo8VJO6sn884JX5DjEBf5YwuMFrYrzhkoi7xt9xcOWHT0E18 X-Received: by 2002:a17:906:35d2:: with SMTP id p18mr76385499ejb.393.1594638124006; Mon, 13 Jul 2020 04:02:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638124; cv=none; d=google.com; s=arc-20160816; b=nVvo6N0SUYVnVHB3q5LjqxiLi+f3Btz46ntIhHagPXMRN+pOx4Fc/krf3SdKXciXwZ 7JRaok8S/ugOM7WzxDSzHTIA/Z8h01L6tNAo2DhdyIxsSFfEDvE1LnTQHesaTNeJ0FD8 lfYwS9/gJtQ0h4bN2IfYVLCngW8yCP3gV9jVallqka+9k1WzcXT/xuVZrMGtWRhS4LXm 743CqqCKFbQkopOf3QEBCOoS4rfAsYQPRg0wRGfbcHEvHK7E4cEV92hWLnjVeret1Giz C5R7j3pN3d5ByaaSs7UwlB5YUllJ+WQUIo3a6arYejCaIP2Pi05KGowV2fZ4AFDYGmyP bHew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4dHzHIcoVceEkhB6z/897N9X5pO/7Q0JzeAzNl+vty8=; b=v+TG0SAeUD+WG5z2YxYuq1ji2db56388MaDAOcHzfIDMK5rnx2XHJp77ebR7XiPSPS Pj+MhQjENWuZEtMwzDViT/zsVb/ruc4Pk8Qu5z8use0w+Y5lzNvZqvE/2XeVqtDs18eN LX+rrUW7BU0Roy0mR2C47fsqiHTGGaVkfWE5cbVOvRJ1oA9QwoTY7iaBsuu7VHyDfkMW AdKlgbABvAWFW/stY1S+wfR0HRe3mgOADVyOYe4tdSNuGhA5cKAHFcIhBJaE+fepLbmY /VcRFxWzvi/DtnR5Bd2NAxTLHxTdvJylImErZaXTTWWqf5NXKZWiQ6n8A854JZtIJhI1 ZMSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=JHuzuEhY; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id gj24si9129496ejb.139.2020.07.13.04.02.03; Mon, 13 Jul 2020 04:02:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=JHuzuEhY; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729581AbgGMLCD (ORCPT + 4 others); Mon, 13 Jul 2020 07:02:03 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:46858 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727035AbgGMLCC (ORCPT ); Mon, 13 Jul 2020 07:02:02 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1oaq071457; Mon, 13 Jul 2020 06:01:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638110; bh=4dHzHIcoVceEkhB6z/897N9X5pO/7Q0JzeAzNl+vty8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JHuzuEhYNd6k3qTxkHgF0NAYPpw43TTtqQlBu5UzVdPZQqsGERTySnr0POTNx/i/r ZzRduNsmF0vl+kEi8AcqLYtLp78emlCGHMb9vwcLhpx+zsLLeTjiUElWuYBXVFlgJ8 14UHisfIr37IQ1HFV5N8w3LZhX0PDUDjlXGZZ/e0= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 06DB1oIJ008983 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 13 Jul 2020 06:01:50 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:01:49 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:01:49 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVb031460; Mon, 13 Jul 2020 06:01:46 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Date: Mon, 13 Jul 2020 16:31:28 +0530 Message-ID: <20200713110141.13156-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org commit bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") while refactoring the Cadence PCIe driver to be used as library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup() and cdns_pcie_host_setup() but missed to remove the corresponding pm_runtime_put_sync() in the error path. Fix it here. Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 ++------- drivers/pci/controller/cadence/pcie-cadence-host.c | 6 +----- 2 files changed, 3 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 1c15c8352125..4a829ccff7d0 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include "pcie-cadence.h" @@ -440,8 +439,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops); if (IS_ERR(epc)) { dev_err(dev, "failed to create epc device\n"); - ret = PTR_ERR(epc); - goto err_init; + return PTR_ERR(epc); } epc_set_drvdata(epc, ep); @@ -453,7 +451,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) resource_size(pcie->mem_res), PAGE_SIZE); if (ret < 0) { dev_err(dev, "failed to initialize the memory space\n"); - goto err_init; + return ret; } ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, @@ -472,8 +470,5 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) free_epc_mem: pci_epc_mem_exit(epc); - err_init: - pm_runtime_put_sync(dev); - return ret; } diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index f42a0acfce00..030e828bfd4c 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -8,7 +8,6 @@ #include #include #include -#include #include "pcie-cadence.h" @@ -473,7 +472,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) ret = cdns_pcie_host_init(dev, &resources, rc); if (ret) - goto err_init; + return ret; list_splice_init(&resources, &bridge->windows); bridge->dev.parent = dev; @@ -491,8 +490,5 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) err_host_probe: pci_free_resource_list(&resources); - err_init: - pm_runtime_put_sync(dev); - return ret; } From patchwork Mon Jul 13 11:01:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235388 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2727218ilg; Mon, 13 Jul 2020 04:03:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzomeYg98cwTJcB0WiiiEuKP6Y+OS+PhDGvYsj6h3nsneTJpk+PEtTFjs3wh/MAid0DUmUr X-Received: by 2002:a17:907:4240:: with SMTP id oi24mr71213063ejb.23.1594638194218; Mon, 13 Jul 2020 04:03:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638194; cv=none; d=google.com; s=arc-20160816; b=jEHVhmTOBs7NJ1bIT2Bzl+DyARPMEUYLd4j4wacjUwCU0D1gcynE+i1ApiRQXtIcqf dovmOvUug12kA77hFPF9tvxfG8NFRQn9ksBEO+5roIlQC3UAoYM2dLnh0azBNTe4flGH OZ9zWvIvz71K8aNxo3iA8Yi53AYkqG03apoMQjIpNsc+2OXHyXV2ZUmcXSQZfQeC0ogg LnrugTZrkjPNLtK2RmqDwi7byft+X1npF7Cv2YpMHDxO1vnbDQrAWLMQ2v1MgUuSWCRg d4Dxt7R33zmDyv2xH4U3OjYZLaKqjzMxZ3XhoNTnQvwtOjmHgwKRH3L0PSAZ9YQaKTev 7Kkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=78wWOd3ZsPARwxc3JQyFkWSrWhbfEtK3ytyjWuF48qg=; b=e5/tyyq8J6+isJLEswBptZ6Bpl40hJrERLE1HJF6RZPJYHrcfAIY+Bj4x9UMz58ySQ RGBrfjPxTno3m8o059VbiTQYbjIUerAr699tc22Bybly8RusQwx1Cew3MG08SvTGgYBo 06kcJizUrU4Ttm93xY0uL6yRxnmeaZeexkgJdFboQ6V2PMsrKLK5DgxHRH4MIK5+Z4a+ +EoSmX7hScHVPFI244NDn7+f1zTfSt2WI0sW6HOl54ErkkdQAUPCofw598YjLoCl/Ftw m3yPz3EEg+0Ae10LgoxpPs4LsN5xstXdQua/3ogilVBez3mswqQlOQHmGZMXDU2LCUkt 6JCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qiMHLkrB; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Remove "mem" from reg binding. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml index 84a8f095d031..6d67067843bf 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -18,13 +18,12 @@ properties: const: cdns,cdns-pcie-host reg: - maxItems: 3 + maxItems: 2 reg-names: items: - const: reg - const: cfg - - const: mem msi-parent: true @@ -49,9 +48,8 @@ examples: device-id = <0x0200>; reg = <0x0 0xfb000000 0x0 0x01000000>, - <0x0 0x41000000 0x0 0x00001000>, - <0x0 0x40000000 0x0 0x04000000>; - reg-names = "reg", "cfg", "mem"; + <0x0 0x41000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; From patchwork Mon Jul 13 11:01:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235380 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726395ilg; Mon, 13 Jul 2020 04:02:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxP+DzZrEr04p5gWTfWH1BQigPPJK+Ky8eQdA7ikOpLhmq80YBmwOmLVHbLezEox2Te1wgl X-Received: by 2002:aa7:c496:: with SMTP id m22mr77596542edq.336.1594638146797; Mon, 13 Jul 2020 04:02:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638146; cv=none; d=google.com; s=arc-20160816; b=0LapeQfqV+ENY3UimsXGC/V64J7YRs3Xu7MUBAwyl/dd9Ur14hhakgVNZwlNZZNMp/ a8ve4YJ+w4uiCzbmtAH904T3jl93fCojc/DjG5p1ZBsx3HvrrJYjn55OI2A2rE+hSawG lOT7u+vVn3j9iroW9dOSsZvKFbO61JUl9yxwxlVRnUQtrmDObwq3Wp/NWwmoTeoMf9nE yjEkPEBB+hF6lmvokmkmBGteBBlTdhKkIPc7EjHFYKewndQoOOm91H8P+a9qsd78Prq/ b0ScUyORJx1DrNzjCvjivJzI4k89KzWvSPhhkxi0z/B6TMJXmkolRSaRTP3LU3mu5GGI mu+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=E77KBnhlOmnDDHPLdMADx+mf8l8Xf4xjtOuMeJCziWM=; b=mGPsPYTQkrnDvGHFLAOVaAfwgQQN21Dqda42S25uD8hGc3BgFXh+UUQo2FxrXkK+qo SG3+ulnVeihgzsv48t3MKP6GVITQ6432B28nMz4iyrVUBGQg3/xkrXfjPdl2XwULeT5i d5w8q1GkwAtbt7uXDUAhYX40fcmVGFW/z6HmA1o2tqs6IONcUj8e5QnkSLLlLq7CfZYC hLRkZ/Mbw/wdjiGaMXhm4fWvfNT+xSdop1/J8deBRPqBjIUd1KRmi+zFnliPDaiMCMeo x64F97+NnLfXXz52QA672t+RL4Fe7PCKMqHGhIIoR/fXrEAXqVE6kKiuzsvkGGH4NP80 diSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OZ+68DQT; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id fi17si8940039ejb.724.2020.07.13.04.02.26; Mon, 13 Jul 2020 04:02:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OZ+68DQT; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729703AbgGMLCZ (ORCPT + 4 others); Mon, 13 Jul 2020 07:02:25 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:46940 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729692AbgGMLCX (ORCPT ); Mon, 13 Jul 2020 07:02:23 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB2D2u071555; Mon, 13 Jul 2020 06:02:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638133; bh=E77KBnhlOmnDDHPLdMADx+mf8l8Xf4xjtOuMeJCziWM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OZ+68DQTIiQw9Zq4P57Mpup5+JYsTmE4E+PXPvQfDFvtyK/E6Kj5IZ6vVrR1s8ZrH t2qjTVvieRGvKlSQjsC5Jkasebk3F/txDheVvPvcersISlKBd8M5iSeSNaqHa3xRyX XZz9P07X9gSWluXE9qwqIxmf2eM/BGOEVmTp2AG0= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 06DB2CCd108836 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 13 Jul 2020 06:02:12 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:02:12 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:02:12 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVh031460; Mon, 13 Jul 2020 06:02:09 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 07/14] PCI: cadence: Add new *ops* for CPU addr fixup Date: Mon, 13 Jul 2020 16:31:34 +0530 Message-ID: <20200713110141.13156-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Cadence driver uses "mem" memory resource to obtain the offset of configuration space address region, memory space address region and message space address region. The obtained offset is used to program the Address Translation Unit (ATU). However certain platforms like TI's J721E SoC require the absolute address to be programmed in the ATU and not just the offset. Add new *ops* for CPU addr fixup for the platform drivers to provide the correct address to be programmed in the ATU. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/cadence/pcie-cadence-host.c | 15 ++++----------- .../pci/controller/cadence/pcie-cadence-plat.c | 13 +++++++++++++ drivers/pci/controller/cadence/pcie-cadence.c | 8 ++++++-- drivers/pci/controller/cadence/pcie-cadence.h | 1 + 4 files changed, 24 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index a8303258874c..10127ea71b83 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -327,15 +327,14 @@ static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc) static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; - struct resource *mem_res = pcie->mem_res; struct resource *bus_range = rc->bus_range; struct resource *cfg_res = rc->cfg_res; struct device *dev = pcie->dev; struct device_node *np = dev->of_node; struct of_pci_range_parser parser; + u64 cpu_addr = cfg_res->start; struct of_pci_range range; u32 addr0, addr1, desc1; - u64 cpu_addr; int r, err; /* @@ -348,7 +347,9 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); - cpu_addr = cfg_res->start - mem_res->start; + if (pcie->ops->cpu_addr_fixup) + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); @@ -477,14 +478,6 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) } rc->cfg_res = res; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); - if (!res) { - dev_err(dev, "missing \"mem\"\n"); - return -EINVAL; - } - - pcie->mem_res = res; - ret = cdns_pcie_start_link(pcie); if (ret) { dev_err(dev, "Failed to start link\n"); diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c index f5c6bf6dfcb8..6f5f07b3eed1 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -13,6 +13,8 @@ #include #include "pcie-cadence.h" +#define CDNS_PLAT_CPU_TO_BUS_ADDR 0x0FFFFFFF + /** * struct cdns_plat_pcie - private data for this PCIe platform driver * @pcie: Cadence PCIe controller @@ -30,6 +32,15 @@ struct cdns_plat_pcie_of_data { static const struct of_device_id cdns_plat_pcie_of_match[]; +static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) +{ + return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR; +} + +static const struct cdns_pcie_ops cdns_plat_ops = { + .cpu_addr_fixup = cdns_plat_cpu_addr_fixup, +}; + static int cdns_plat_pcie_probe(struct platform_device *pdev) { const struct cdns_plat_pcie_of_data *data; @@ -66,6 +77,7 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev) rc = pci_host_bridge_priv(bridge); rc->pcie.dev = dev; + rc->pcie.ops = &cdns_plat_ops; cdns_plat_pcie->pcie = &rc->pcie; cdns_plat_pcie->is_rc = is_rc; @@ -93,6 +105,7 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev) return -ENOMEM; ep->pcie.dev = dev; + ep->pcie.ops = &cdns_plat_ops; cdns_plat_pcie->pcie = &ep->pcie; cdns_plat_pcie->is_rc = is_rc; diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index cd795f6fc1e2..8a02981fd456 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -73,7 +73,9 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); /* Set the CPU address */ - cpu_addr -= pcie->mem_res->start; + if (pcie->ops->cpu_addr_fixup) + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); @@ -100,7 +102,9 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, } /* Set the CPU address */ - cpu_addr -= pcie->mem_res->start; + if (pcie->ops->cpu_addr_fixup) + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 54e10caf2d4b..1d2bdc4e08e4 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -254,6 +254,7 @@ struct cdns_pcie_ops { int (*start_link)(struct cdns_pcie *pcie); void (*stop_link)(struct cdns_pcie *pcie); bool (*link_up)(struct cdns_pcie *pcie); + u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; /** From patchwork Mon Jul 13 11:01:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235381 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726423ilg; Mon, 13 Jul 2020 04:02:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwih+5VCZ6wBflItTdxhtYjJXMkUXwANNbkmfFLrO4tDQribkHfGQxJgrSSODPv1Q4FFUh2 X-Received: by 2002:a17:906:7855:: with SMTP id p21mr61990626ejm.492.1594638148945; Mon, 13 Jul 2020 04:02:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638148; cv=none; d=google.com; s=arc-20160816; b=JfE8qao6a1iN86qztQySjtldCzRODQd2BTxbmcnS6gAqToVkTIo2SoZ8VepRfQ5bba U9iQFA3tvXPJvboHV8RFZwkFDfZ5HbLOrECZJyp/0/NqAUd0n+s1Ye2FkXcvhwH+3vGT QCKoW1tvAheDl2woCSninOoyjmijKIzcTMFcJBnI48qOPlFMgk/yfLT6/40EVi2qV/qp em3e9OstDosDIugyrgrforkfllQ4GR848/R201onLibLJ5aa+6a1yZeSgITPE2jUic+F a35eJt0L56p5zY+irfE7+5yIl1yW74ysyHL1TStQEwmlCARKfXA7ScSUh7n4YFaI6y/4 b60A== ARC-Message-Signature: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id fi17si8940039ejb.724.2020.07.13.04.02.28; Mon, 13 Jul 2020 04:02:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=q8HrSlPo; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729712AbgGMLC2 (ORCPT + 4 others); Mon, 13 Jul 2020 07:02:28 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:38274 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729637AbgGMLC0 (ORCPT ); Mon, 13 Jul 2020 07:02:26 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB2GBQ056006; Mon, 13 Jul 2020 06:02:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638136; bh=oDHixXQpSiTZez44a8+8lE4nJpgDYDjM303UR0TQSis=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=q8HrSlPoGJ/sffUmOMgL+pDWEmXVsiOsdJ9wvTtMXf0oLNpP4ytncyWr8iKmdLCh0 0DNTDHkTvFZ+0XsmTNOKCE+BldVTWGf2TBixLFdzrfPSKIG6g9mjbzc6bf5MomrRqn Qe9STWgeFb0cm0RMB8LsnZqmx6xWhaoRNHHa1h5w= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 06DB2GT7023159 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 13 Jul 2020 06:02:16 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:02:16 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:02:16 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVi031460; Mon, 13 Jul 2020 06:02:12 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Date: Mon, 13 Jul 2020 16:31:35 +0530 Message-ID: <20200713110141.13156-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Commit 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller") in order to update Vendor ID, directly wrote to PCI_VENDOR_ID register. However PCI_VENDOR_ID in root port configuration space is read-only register and writing to it will have no effect. Use local management register to configure Vendor ID and Subsystem Vendor ID. Fixes: 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller") Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-host.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 10127ea71b83..8935f7a37e5a 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -82,6 +82,7 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; u32 value, ctrl; + u32 id; /* * Set the root complex BAR configuration register: @@ -101,8 +102,12 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value); /* Set root port configuration space */ - if (rc->vendor_id != 0xffff) - cdns_pcie_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); + if (rc->vendor_id != 0xffff) { + id = CDNS_PCIE_LM_ID_VENDOR(rc->vendor_id) | + CDNS_PCIE_LM_ID_SUBSYS(rc->vendor_id); + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + if (rc->device_id != 0xffff) cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); From patchwork Mon Jul 13 11:01:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235386 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2727034ilg; Mon, 13 Jul 2020 04:03:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy6gqf0thYH044QhrSFeDYUCm4B1RKnri4xEVpMma1lRbo7Hb8WeTaj5PAxbPP4JnOusuEu X-Received: by 2002:a17:906:1111:: with SMTP id h17mr46194379eja.203.1594638183942; Mon, 13 Jul 2020 04:03:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638183; cv=none; d=google.com; s=arc-20160816; b=gIyUI7fob2U1+Cq1X3cbF7OLdCD3IvMorOIFw0cWk3KlVmfLZtfdMMMvm2nWJcpqFB UXbvew4iB4vtyQfpkclGz2NWnbkDt4rDRDNrNu5Bt1X5tlvlc+bkjuUt1OkJEOURtxVQ k8T8Tx5zfjtBml04WUcq8ggHPOx35O/7I72wHszi0H6ud7sJ6MJeZQ3Zoc2i7zCZ4Owj qWuI0hBAVeayXS9WtOgMKd/vwr7U13C04YDmhDdFOrp9Ij6mo7fxkpwVgt469w/97P8I Ci22ofnzCKciqRBhLzyPVV24uVg2Gg6jpUyce0dMnNbLsletBFKwXIgaojbW3sIBEL2Z 9Clg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=P/tGOXBSgsFmG2C/xoH0jOMCZxBW6F3uPgPZWAAKVCA=; b=v3ShZuMSg7RbleOExCK+pzS9q8CT4UukjzBNbT7rfkl84l+iBstX5PkNPWB+hlLPtD SNr2KOzzvHCtwu9y/T8MtFqnMNxN1SzqJ3ZwhmfCRV2lGxfGerUlmkp6hwtDJf9z0KGn 9PlOFVu57OkfxgV+vo51kSpJMJQ5tmxGwiIK6gkdZqXvrwwigbo3i+EZ8dHK3rjkUsrt qDSgA50h0qQB5Wy8XpXuNl+NJuHl03gvdOH6besq7jTqxDMbzEath6FnP5HasyV7Jidb dq/UjfqLd4WBVqleV0O9o8wDoO2x3ExU5n/j0pwHuHTBrtLjP6SCG+ObeGg1BcGJ9ow0 pHMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SW0AtoAO; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b8si11797917edz.89.2020.07.13.04.03.03; Mon, 13 Jul 2020 04:03:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SW0AtoAO; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729736AbgGMLCf (ORCPT + 4 others); Mon, 13 Jul 2020 07:02:35 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:56896 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729637AbgGMLCd (ORCPT ); Mon, 13 Jul 2020 07:02:33 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB2KtS101173; Mon, 13 Jul 2020 06:02:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638140; bh=P/tGOXBSgsFmG2C/xoH0jOMCZxBW6F3uPgPZWAAKVCA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SW0AtoAOSuKBz0UE80E3ZH6nQ62pkHm11lr6DOU2Z7PlvRUpjWRY3xM9t9q7DP87x VlDpuUmKcii17PotyDWSVoNbsSpe4HjPYsH7fUE62lgdaiC2cX4+Df3kwV+JFEbbTU q/mN+yO+WLXIU7Ko1suDtI+iLsHiCTXWt3VdRfnU= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 06DB2K5V010226 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 13 Jul 2020 06:02:20 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:02:20 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:02:20 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVj031460; Mon, 13 Jul 2020 06:02:16 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 09/14] PCI: cadence: Add MSI-X support to Endpoint driver Date: Mon, 13 Jul 2020 16:31:36 +0530 Message-ID: <20200713110141.13156-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Alan Douglas Implement ->set_msix() and ->get_msix() callback functions in order to configure MSIX capability in the PCIe endpoint controller. Add cdns_pcie_ep_send_msix_irq() to send MSIX interrupts to Host. cdns_pcie_ep_send_msix_irq() gets the MSIX table address (virtual address) from "struct cdns_pcie_epf" that gets initialized in ->set_bar() call back function. Signed-off-by: Alan Douglas [kishon@ti.com: Re-implement MSIX support in accordance with the re-designed core MSI-X interfaces] Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/cadence/pcie-cadence-ep.c | 108 +++++++++++++++++- drivers/pci/controller/cadence/pcie-cadence.h | 11 ++ 2 files changed, 118 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 034cb3cf726e..87c76341eab4 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -51,6 +51,7 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, struct pci_epf_bar *epf_bar) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + struct cdns_pcie_epf *epf = &ep->epf[fn]; struct cdns_pcie *pcie = &ep->pcie; dma_addr_t bar_phys = epf_bar->phys_addr; enum pci_barno bar = epf_bar->barno; @@ -111,6 +112,8 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); cdns_pcie_writel(pcie, reg, cfg); + epf->epf_bar[bar] = epf_bar; + return 0; } @@ -118,6 +121,7 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, struct pci_epf_bar *epf_bar) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + struct cdns_pcie_epf *epf = &ep->epf[fn]; struct cdns_pcie *pcie = &ep->pcie; enum pci_barno bar = epf_bar->barno; u32 reg, cfg, b, ctrl; @@ -139,6 +143,8 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0); cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0); + + epf->epf_bar[bar] = NULL; } static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, @@ -224,6 +230,50 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) return mme; } +static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no) +{ + struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + struct cdns_pcie *pcie = &ep->pcie; + u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + reg = cap + PCI_MSIX_FLAGS; + val = cdns_pcie_ep_fn_readw(pcie, func_no, reg); + if (!(val & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + val &= PCI_MSIX_FLAGS_QSIZE; + + return val; +} + +static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u16 interrupts, + enum pci_barno bir, u32 offset) +{ + struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + struct cdns_pcie *pcie = &ep->pcie; + u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + reg = cap + PCI_MSIX_FLAGS; + val = cdns_pcie_ep_fn_readw(pcie, fn, reg); + val &= ~PCI_MSIX_FLAGS_QSIZE; + val |= interrupts; + cdns_pcie_ep_fn_writew(pcie, fn, reg, val); + + /* Set MSIX BAR and offset */ + reg = cap + PCI_MSIX_TABLE; + val = offset | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + /* Set PBA BAR and offset. BAR must match MSIX BAR */ + reg = cap + PCI_MSIX_PBA; + val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + return 0; +} + static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx, bool is_asserted) { @@ -333,6 +383,52 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, return 0; } +static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, + u16 interrupt_num) +{ + u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 tbl_offset, msg_data, reg, vec_ctrl; + struct cdns_pcie *pcie = &ep->pcie; + struct pci_epf_msix_tbl *msix_tbl; + struct cdns_pcie_epf *epf; + u64 pci_addr_mask = 0xff; + u64 msg_addr; + u16 flags; + u8 bir; + + /* Check whether the MSI-X feature has been enabled by the PCI host. */ + flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS); + if (!(flags & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + reg = cap + PCI_MSIX_TABLE; + tbl_offset = cdns_pcie_ep_fn_readl(pcie, fn, reg); + bir = tbl_offset & PCI_MSIX_TABLE_BIR; + tbl_offset &= PCI_MSIX_TABLE_OFFSET; + + epf = &ep->epf[fn]; + msix_tbl = epf->epf_bar[bir]->addr + tbl_offset; + msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr; + msg_data = msix_tbl[(interrupt_num - 1)].msg_data; + vec_ctrl = msix_tbl[(interrupt_num - 1)].vector_ctrl; + + /* Set the outbound region if needed. */ + if (ep->irq_pci_addr != (msg_addr & ~pci_addr_mask) || + ep->irq_pci_fn != fn) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_set_outbound_region(pcie, fn, 0, + false, + ep->irq_phys_addr, + msg_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr = (msg_addr & ~pci_addr_mask); + ep->irq_pci_fn = fn; + } + writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask)); + + return 0; +} + static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, enum pci_epc_irq_type type, u16 interrupt_num) @@ -346,6 +442,9 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, case PCI_EPC_IRQ_MSI: return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num); + case PCI_EPC_IRQ_MSIX: + return cdns_pcie_ep_send_msix_irq(ep, fn, interrupt_num); + default: break; } @@ -383,7 +482,7 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) static const struct pci_epc_features cdns_pcie_epc_features = { .linkup_notifier = false, .msi_capable = true, - .msix_capable = false, + .msix_capable = true, }; static const struct pci_epc_features* @@ -400,6 +499,8 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = { .unmap_addr = cdns_pcie_ep_unmap_addr, .set_msi = cdns_pcie_ep_set_msi, .get_msi = cdns_pcie_ep_get_msi, + .set_msix = cdns_pcie_ep_set_msix, + .get_msix = cdns_pcie_ep_get_msix, .raise_irq = cdns_pcie_ep_raise_irq, .start = cdns_pcie_ep_start, .get_features = cdns_pcie_ep_get_features, @@ -458,6 +559,11 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) epc->max_functions = 1; + ep->epf = devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf), + GFP_KERNEL); + if (!ep->epf) + return -ENOMEM; + ret = pci_epc_mem_init(epc, pcie->mem_res->start, resource_size(pcie->mem_res), PAGE_SIZE); if (ret < 0) { diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 1d2bdc4e08e4..8057f4a338bd 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -113,6 +113,7 @@ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) #define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 +#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 /* * Root Port Registers (PCI configuration space for the root port function) @@ -302,6 +303,14 @@ struct cdns_pcie_rc { bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; }; +/** + * struct cdns_pcie_epf - Structure to hold info about endpoint function + * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers + */ +struct cdns_pcie_epf { + struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; +}; + /** * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver * @pcie: Cadence PCIe controller @@ -321,6 +330,7 @@ struct cdns_pcie_rc { * @lock: spin lock to disable interrupts while modifying PCIe controller * registers fields (RMW) accessible by both remote RC and EP to * minimize time between read and write + * @epf: Structure to hold info about endpoint function */ struct cdns_pcie_ep { struct cdns_pcie pcie; @@ -334,6 +344,7 @@ struct cdns_pcie_ep { u8 irq_pending; /* protect writing to PCI_STATUS while raising legacy interrupts */ spinlock_t lock; + struct cdns_pcie_epf *epf; }; From patchwork Mon Jul 13 11:01:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235387 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2727060ilg; Mon, 13 Jul 2020 04:03:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycCFVmKPRAbWVrWauUQHJIyxohlW1R7CMaDz7032KODoJYItJfR9BUrqVGkMbO/GzcnM+7 X-Received: by 2002:a17:906:456:: with SMTP id e22mr66708978eja.178.1594638185249; Mon, 13 Jul 2020 04:03:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638185; cv=none; d=google.com; s=arc-20160816; b=LV1GuQj1iNg0XZ5XHQ3CYBGICGuQyHDaY0LKw2qzchSE74TZs29Oa7hZvp13/hDzCX Vv3+eNTksMzuLHjvA0uazxu+di0zTmytp6NKc/hbSQFl6kMrFf2bzG9ckv4CSSKwgz4J 4UUXThuTBLrSAVGVfSG4lTmu3TmgNsIQknoOgJBfpFaAckF6CTvfiqPvDE9wf/4lOoL3 Yy2fXNupfwLsOisFI4zEsOBgeW8GRaF/iRN5FmvpinumRNWMb3ro7lxV3YyM4/vXRhzC xgkwieaDUvcI0hXZm7RsjbWP8QZg+ff+McHRMwoxPbVr7xaVnXDwQ/YdnzBXrwcEIfrt 9YAg== ARC-Message-Signature: i=1; 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Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml new file mode 100644 index 000000000000..d7b60487c6c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI Host (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I + +allOf: + - $ref: "cdns-pcie-host.yaml#" + +properties: + compatible: + enum: + - ti,j721e-pcie-host + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: cfg + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + vendor-id: + const: 0x104c + + device-id: + const: 0xb00d + + msi-map: true + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - vendor-id + - device-id + - msi-map + - dma-coherent + - dma-ranges + - ranges + - reset-gpios + - phys + - phy-names + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + }; From patchwork Mon Jul 13 11:01:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235382 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726674ilg; Mon, 13 Jul 2020 04:02:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzgdOGufd+AhY/Y0OPf4OX8/D+mfPfRWpf9EChgD91X/kDKGP6zOXVx1/PWTzeIJ/wlDR6l X-Received: by 2002:a50:dacf:: with SMTP id s15mr94467556edj.136.1594638163309; Mon, 13 Jul 2020 04:02:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638163; cv=none; d=google.com; s=arc-20160816; b=XEusGCAL2nowsi6Uq1v/rrb6yyrI/FyBM8MD130kLKHvJ/Y8Uhe5GTS8WaBgx6Ceom 4wCd5cFc16AFHGy3jRrteQOP/CoQfQoc4rKC6xyemxmbzSlwLbeI6x9CcrdfVF0+PWi5 vcRs9a3N41DN+BlBo/QLb5Iwrmmsqr0CQ+FHfcucOEH0H6GuQhO3Lff6bdZeP19wNRat iRyiqvZCHqyDHDLdmi/NqtH4a3oLmV+ysvczRAWzejadPCyhT6bgHql3jaFMqhTEUs64 74gkP1mRfsU5/RQRWE3lmsBN0qreN6f8imaDVngqjJMgupQKwCxge2IlgazzPs7GZ4Hz AXqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=6UZy4LDT8vKXxt4wlNP70n/cJtfjFKYF+R5NxIf94Jw=; b=FxcIGDFUyrcp2zBrGdHhzGI/oxYr3Zbz1vsZpE3L9XY24mRxCD11fxTACZqJs2W96C Naw0S/UzFMlXCMYlqJv/dJn+CO/kBNGyGqIrmAzzEJkouDC1tzwixgHOl9OzLqUGqY53 E0qau+c2t2FQf2CPtEZEBr8V3fV42/OEu7Po0iBfyKVwBncscJ7FVhPLwFm94PEpwt/+ ZqSkwy7gWtk7fbt8QnqiC3LDznGzfi+dkJH6KfzQeTm8xp692bzCwyjlbD/Gi1McSE1H /xXsYVyIGHMp5KPxv6cWKH8pjEsRE05SxBP91J5mvD3zmeiz8nsO2UidkqIbiFLQfBCi fYqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Kw0VG7KE; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../bindings/pci/ti,j721e-pci-ep.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml new file mode 100644 index 000000000000..cf96e190189a --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI EP (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I + +allOf: + - $ref: "cdns-pcie-ep.yaml#" + +properties: + compatible: + enum: + - ti,j721e-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: mem + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + dma-coherent: + description: Indicates that the PCIe IP block can ensure the coherency + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - cdns,max-outbound-regions + - dma-coherent + - max-functions + - phys + - phy-names + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_ep: pcie-ep@d000000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + }; + }; From patchwork Mon Jul 13 11:01:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235383 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726753ilg; Mon, 13 Jul 2020 04:02:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx5VQiglAB86gipPCKS9D/EcThNX84SsCM1adH/+zArH5lhGh/ooklFoCeV1iXaC6b9FX70 X-Received: by 2002:a17:907:100a:: with SMTP id ox10mr70845910ejb.351.1594638168513; Mon, 13 Jul 2020 04:02:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638168; cv=none; d=google.com; s=arc-20160816; b=OkcTFVUTSF2cvLE6nkrORtconD/0Ch0gNb7qWkDPTSOdfURSdKSmXuUIcTshBJzdsk qf1uoNwRiza6qn/ddREvlUrmscCfsrzjTN3SVMAbl7qGqYpTVG5HeaGDBdo1GuIyNbq7 SKU5H0J0eLwFiM28xu/m5BVEiw4uQEeAm+rynkGdQWTW3hmNtphco4GOAr8O67djkWsW E/pEt5QeTjkGdno0sAgZe99WlkW55ffm/FACiGyRkjzZolo9dSCwbj/CEkBFN0rSbBQj ilhg++GjGsJ3nxGW7xduMj5MKwg2e/NX2fgA4M+JPIomPWfzcQPHbQSygMtMcKI9gdGX CkIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=xyX3aiXm+07Z01ejgMoUdbkhQAwdUpEtLjGrsDE0wxs=; b=G4L+4y2UCInvKvauxAu1iilYFUQQF+espBpIfn8v5jKn1j9qd7ku0hj0pV9M5CWz+n kCF4jVospIRkk7A+SiSuaDeZzz0tnzYGYPTUrouRl0g5v/o8uDbCT+2QqA1jNyp1kJdB etd6wm/JrxqkOQxzF9/p/VoQNF43IkO4oSfestjYD2X4+5S/hfJ4jT2vyYI+CSQMcCwR I8a8yx0Cdg0m4tQxe5VQFmKqLUG4ANKFRCChvhkbWigpfjM9o9QPUM/r/57RQUlD7g0D ThcaFP95YK68Y95oahIiSuRy5rEyN6j3CyJRIhTyrkW6CjaVdOQUWQ75V7LzrmQdG02S EX6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tNmdBCmT; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b15si9007685edt.394.2020.07.13.04.02.48; Mon, 13 Jul 2020 04:02:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tNmdBCmT; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729768AbgGMLCr (ORCPT + 4 others); Mon, 13 Jul 2020 07:02:47 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:56916 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729762AbgGMLCo (ORCPT ); Mon, 13 Jul 2020 07:02:44 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB2Vh3101291; Mon, 13 Jul 2020 06:02:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638151; bh=xyX3aiXm+07Z01ejgMoUdbkhQAwdUpEtLjGrsDE0wxs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tNmdBCmT+2Vq+7yC/Eoi+p1ejvmXLWfm9bk6PsMDlo+kAFArlMA6yIGc6mRVkC7QT OD3ZNZPfge87A+R2UexkpfMsDTkQA8pCV66JmHsuEi/l3zUb3LheE+i8iFU93JnKNW xD9X38AkYDAu6hKqyq9d7GX9wxfts0MzV3aIKPRc= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB2VRw005761; Mon, 13 Jul 2020 06:02:31 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:02:31 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:02:31 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVm031460; Mon, 13 Jul 2020 06:02:28 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 12/14] PCI: j721e: Add TI J721E PCIe driver Date: Mon, 13 Jul 2020 16:31:39 +0530 Message-ID: <20200713110141.13156-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add support for PCIe controller in J721E SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in both host mode and device mode. Some of the features of the controller are: *) Supports both RC mode and EP mode *) Supports MSI and MSI-X support *) Supports upto GEN3 speed mode *) Supports SR-IOV capability *) Ability to route all transactions via SMMU (support will be added in a later patch). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/Kconfig | 23 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-j721e.c | 493 ++++++++++++++++++ .../controller/cadence/pcie-cadence-host.c | 4 +- drivers/pci/controller/cadence/pcie-cadence.h | 8 + 5 files changed, 527 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/controller/cadence/pci-j721e.c -- 2.17.1 diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index b76b3cf55ce5..5d30564190e1 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,4 +42,27 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. +config PCI_J721E + bool + +config PCI_J721E_HOST + bool "TI J721E PCIe platform host controller" + depends on OF + select PCIE_CADENCE_HOST + select PCI_J721E + help + Say Y here if you want to support the TI J721E PCIe platform + controller in host mode. TI J721E PCIe controller uses Cadence PCIe + core. + +config PCI_J721E_EP + bool "TI J721E PCIe platform endpoint controller" + depends on OF + depends on PCI_ENDPOINT + select PCIE_CADENCE_EP + select PCI_J721E + help + Say Y here if you want to support the TI J721E PCIe platform + controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe + core. endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 232a3f20876a..9bac5fb2f13d 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o +obj-$(CONFIG_PCI_J721E) += pci-j721e.o diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c new file mode 100644 index 000000000000..23ad8fa699c4 --- /dev/null +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * pci-j721e - PCIe controller driver for TI's J721E SoCs + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../pci.h" +#include "pcie-cadence.h" + +#define ENABLE_REG_SYS_2 0x108 +#define STATUS_REG_SYS_2 0x508 +#define STATUS_CLR_REG_SYS_2 0x708 +#define LINK_DOWN BIT(1) + +#define J721E_PCIE_USER_CMD_STATUS 0x4 +#define LINK_TRAINING_ENABLE BIT(0) + +#define J721E_PCIE_USER_LINKSTATUS 0x14 +#define LINK_STATUS GENMASK(1, 0) + +enum link_status { + NO_RECEIVERS_DETECTED, + LINK_TRAINING_IN_PROGRESS, + LINK_UP_DL_IN_PROGRESS, + LINK_UP_DL_COMPLETED, +}; + +#define J721E_MODE_RC BIT(7) +#define LANE_COUNT_MASK BIT(8) +#define LANE_COUNT(n) ((n) << 8) + +#define GENERATION_SEL_MASK GENMASK(1, 0) + +#define MAX_LANES 2 + +struct j721e_pcie { + struct device *dev; + u32 mode; + u32 num_lanes; + struct cdns_pcie *cdns_pcie; + void __iomem *user_cfg_base; + void __iomem *intd_cfg_base; +}; + +enum j721e_pcie_mode { + PCI_MODE_RC, + PCI_MODE_EP, +}; + +struct j721e_pcie_data { + enum j721e_pcie_mode mode; +}; + +static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) +{ + return readl(pcie->user_cfg_base + offset); +} + +static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, + u32 value) +{ + writel(value, pcie->user_cfg_base + offset); +} + +static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) +{ + return readl(pcie->intd_cfg_base + offset); +} + +static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, + u32 value) +{ + writel(value, pcie->intd_cfg_base + offset); +} + +static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) +{ + struct j721e_pcie *pcie = priv; + struct device *dev = pcie->dev; + u32 reg; + + reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); + if (!(reg & LINK_DOWN)) + return IRQ_NONE; + + dev_err(dev, "LINK DOWN!\n"); + + j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, LINK_DOWN); + return IRQ_HANDLED; +} + +static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) +{ + u32 reg; + + reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); + reg |= LINK_DOWN; + j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); +} + +static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) +{ + struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); + reg |= LINK_TRAINING_ENABLE; + j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); + + return 0; +} + +static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) +{ + struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); + reg &= ~LINK_TRAINING_ENABLE; + j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); +} + +static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) +{ + struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); + reg &= LINK_STATUS; + if (reg == LINK_UP_DL_COMPLETED) + return true; + + return false; +} + +static const struct cdns_pcie_ops j721e_pcie_ops = { + .start_link = j721e_pcie_start_link, + .stop_link = j721e_pcie_stop_link, + .link_up = j721e_pcie_link_up, +}; + +static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) +{ + struct device *dev = pcie->dev; + u32 mask = J721E_MODE_RC; + u32 mode = pcie->mode; + u32 val = 0; + int ret = 0; + + if (mode == PCI_MODE_RC) + val = J721E_MODE_RC; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) + dev_err(dev, "failed to set pcie mode\n"); + + return ret; +} + +static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, + struct regmap *syscon) +{ + struct device *dev = pcie->dev; + struct device_node *np = dev->of_node; + int link_speed; + u32 val = 0; + int ret; + + link_speed = of_pci_get_max_link_speed(np); + if (link_speed < 2) + link_speed = 2; + + val = link_speed - 1; + ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val); + if (ret) + dev_err(dev, "failed to set link speed\n"); + + return ret; +} + +static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, + struct regmap *syscon) +{ + struct device *dev = pcie->dev; + u32 lanes = pcie->num_lanes; + u32 val = 0; + int ret; + + val = LANE_COUNT(lanes - 1); + ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val); + if (ret) + dev_err(dev, "failed to set link count\n"); + + return ret; +} + +static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node = dev->of_node; + struct regmap *syscon; + int ret; + + syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); + if (IS_ERR(syscon)) { + dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); + return PTR_ERR(syscon); + } + + ret = j721e_pcie_set_mode(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set pci mode\n"); + return ret; + } + + ret = j721e_pcie_set_link_speed(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set link speed\n"); + return ret; + } + + ret = j721e_pcie_set_lane_count(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set num-lanes\n"); + return ret; + } + + return 0; +} + +static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); + unsigned int busn = bus->number; + + if (busn == rc->bus_range->start) + return pci_generic_config_read32(bus, devfn, where, size, + value); + + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); + unsigned int busn = bus->number; + + if (busn == rc->bus_range->start) + return pci_generic_config_write32(bus, devfn, where, size, + value); + + return pci_generic_config_write(bus, devfn, where, size, value); +} + +static struct pci_ops cdns_ti_pcie_host_ops = { + .map_bus = cdns_pci_map_bus, + .read = cdns_ti_pcie_config_read, + .write = cdns_ti_pcie_config_write, +}; + +static const struct j721e_pcie_data j721e_pcie_rc_data = { + .mode = PCI_MODE_RC, +}; + +static const struct j721e_pcie_data j721e_pcie_ep_data = { + .mode = PCI_MODE_EP, +}; + +static const struct of_device_id of_j721e_pcie_match[] = { + { + .compatible = "ti,j721e-pcie-host", + .data = &j721e_pcie_rc_data, + }, + { + .compatible = "ti,j721e-pcie-ep", + .data = &j721e_pcie_ep_data, + }, + {}, +}; + +static int j721e_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct pci_host_bridge *bridge; + struct j721e_pcie_data *data; + struct cdns_pcie *cdns_pcie; + struct j721e_pcie *pcie; + struct cdns_pcie_rc *rc; + struct cdns_pcie_ep *ep; + struct gpio_desc *gpiod; + void __iomem *base; + u32 num_lanes; + u32 mode; + int ret; + int irq; + + data = (struct j721e_pcie_data *)of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + mode = (u32)data->mode; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->dev = dev; + pcie->mode = mode; + + base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); + if (IS_ERR(base)) + return PTR_ERR(base); + pcie->intd_cfg_base = base; + + base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); + if (IS_ERR(base)) + return PTR_ERR(base); + pcie->user_cfg_base = base; + + ret = of_property_read_u32(node, "num-lanes", &num_lanes); + if (ret || num_lanes > MAX_LANES) + num_lanes = 1; + pcie->num_lanes = num_lanes; + + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) + return -EINVAL; + + irq = platform_get_irq_byname(pdev, "link_state"); + if (irq < 0) + return irq; + + dev_set_drvdata(dev, pcie); + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + ret = j721e_pcie_ctrl_init(pcie); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, + "j721e-pcie-link-down-irq", pcie); + if (ret < 0) { + dev_err(dev, "failed to request link state IRQ %d\n", irq); + goto err_get_sync; + } + + j721e_pcie_config_link_irq(pcie); + + switch (mode) { + case PCI_MODE_RC: + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) { + ret = -ENODEV; + goto err_get_sync; + } + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) { + ret = -ENOMEM; + goto err_get_sync; + } + + bridge->ops = &cdns_ti_pcie_host_ops; + rc = pci_host_bridge_priv(bridge); + + cdns_pcie = &rc->pcie; + cdns_pcie->dev = dev; + cdns_pcie->ops = &j721e_pcie_ops; + pcie->cdns_pcie = cdns_pcie; + + gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(gpiod)) { + ret = PTR_ERR(gpiod); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset GPIO\n"); + goto err_get_sync; + } + + ret = cdns_pcie_init_phy(dev, cdns_pcie); + if (ret) { + dev_err(dev, "Failed to init phy\n"); + goto err_get_sync; + } + + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 + * indicates PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. The REFCLK to the connector in RC + * mode is selected while enabling the PHY. So deassert PERST# + * after 100 us. + */ + if (gpiod) { + usleep_range(100, 200); + gpiod_set_value_cansleep(gpiod, 1); + } + + ret = cdns_pcie_host_setup(rc); + if (ret < 0) + goto err_pcie_setup; + + break; + case PCI_MODE_EP: + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) { + ret = -ENODEV; + goto err_get_sync; + } + + ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); + if (!ep) { + ret = -ENOMEM; + goto err_get_sync; + } + + cdns_pcie = &ep->pcie; + cdns_pcie->dev = dev; + cdns_pcie->ops = &j721e_pcie_ops; + pcie->cdns_pcie = cdns_pcie; + + ret = cdns_pcie_init_phy(dev, cdns_pcie); + if (ret) { + dev_err(dev, "Failed to init phy\n"); + goto err_get_sync; + } + + ret = cdns_pcie_ep_setup(ep); + if (ret < 0) + goto err_pcie_setup; + + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + } + + return 0; + +err_pcie_setup: + cdns_pcie_disable_phy(cdns_pcie); + +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return ret; +} + +static int j721e_pcie_remove(struct platform_device *pdev) +{ + struct j721e_pcie *pcie = platform_get_drvdata(pdev); + struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; + struct device *dev = &pdev->dev; + + cdns_pcie_disable_phy(cdns_pcie); + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return 0; +} + +static struct platform_driver j721e_pcie_driver = { + .probe = j721e_pcie_probe, + .remove = j721e_pcie_remove, + .driver = { + .name = "j721e-pcie", + .of_match_table = of_j721e_pcie_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(j721e_pcie_driver); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 8935f7a37e5a..ba157278fb0f 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -23,8 +23,8 @@ static u8 bar_aperture_mask[] = { [RP_BAR1] = 0xF, }; -static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, - int where) +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) { struct pci_host_bridge *bridge = pci_find_host_bridge(bus); struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 8057f4a338bd..07c3cb63a6fe 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -475,11 +475,19 @@ static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) #ifdef CONFIG_PCIE_CADENCE_HOST int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); #else static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { return 0; } + +static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + return NULL; +} #endif #ifdef CONFIG_PCIE_CADENCE_EP From patchwork Mon Jul 13 11:01:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235385 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2726851ilg; Mon, 13 Jul 2020 04:02:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwZB+Ek7sspIKof0XycFupCDejZoKL/g1KoisVulRf8YPZr1ccJN3kE/KMGS40yPokTyam5 X-Received: by 2002:a17:906:824c:: with SMTP id f12mr71817610ejx.443.1594638174039; Mon, 13 Jul 2020 04:02:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638174; cv=none; d=google.com; s=arc-20160816; b=yJx3hvHd/t+rFvud25ZQIbOhxPIRD1rGcvDCQfzPX0HsoeNQYr1SfJFUjkRY3hwLOT NIfGHS7V/ssZQPYLSgtBnIQWltQgrVGqKytNTPeoQN1If+SaGNuYAEBtrN9U/3HN+dKU kfK4iwmgwsmjfqgSHwEujIUyVGYbV426j4RnitdS9WDy/hpqpmOe0mvlhaizs9szqiqc 9boIT+fRD5Ic7IEBgPkiyQjRXlFr/Td3q88O4JLJB56xtRH9jUQBofzpb+FUmXQfhdp5 K2sLwZaly9vIyWZyQouq+RemQUfCTS3XHPThi3a1JWCyqjhGU9bJ2yl4T+kd76e4wPVw eLRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=7OcnyXAqbvLTfoWs7cVYpAjSlZ1UufTOUaO13t5B4CY=; b=Wi4cg3WrdI6LaBBj4tFgK5Ji2pzg0Xa1hzSeLn1bnZTYoJKezD5BMZYqKsisqOwjIz oF3rTZJPGoLPAQkUmT3i9F3bKj1l1rcFbwQu753CF7GdoVKxcwAZPqTbrWB5mJrAsWiY ZnIHvfBLu1P5FvKcAvDSb6QsYgyWWSFBcNMI5vrGVSGq2Fm7jWJnZPFUGWV4VOMO0tNt 4YGRMnVQYF0anZFRv2vIgLcgqlbIY5W9m3Hbb9CnIwscL88O9Q4GwvGF6zQ6S8wfra7p OjZo9R6CU/m/RiVtqIPFvwzZHrtl7/S/HCbFAlVKTVFy2JDvfoT9osdthMLbn4rqVn4L riPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eTiyN6Iq; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hk1si8570800ejb.497.2020.07.13.04.02.53; Mon, 13 Jul 2020 04:02:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eTiyN6Iq; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729786AbgGMLCw (ORCPT + 4 others); Mon, 13 Jul 2020 07:02:52 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:38342 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728382AbgGMLCq (ORCPT ); Mon, 13 Jul 2020 07:02:46 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB2ZDY056089; Mon, 13 Jul 2020 06:02:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638155; bh=7OcnyXAqbvLTfoWs7cVYpAjSlZ1UufTOUaO13t5B4CY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eTiyN6Iqv66y7VMjRR9bV2l/a0uQgz6Qf2LpR/+sIRMOeplpAeQ/H+Zd0vRU4vTLu 9g7K1pUrnPFUIRVvqTbKVJCv2Sask+LP7UhpXi0CUGzzYIbs4hKI5+80mXamPxzM3f e+uW8FzM21a4fhICBUNW7OzEccHIMIgB6tZetHKg= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 06DB2ZBv010392 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 13 Jul 2020 06:02:35 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:02:35 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:02:35 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVn031460; Mon, 13 Jul 2020 06:02:31 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Date: Mon, 13 Jul 2020 16:31:40 +0530 Message-ID: <20200713110141.13156-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add J721E in pci_device_id table so that pci-epf-test can be used for testing PCIe EP in J721E. Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 41c40971979e..e060796f9caa 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -68,6 +68,7 @@ #define PCI_ENDPOINT_TEST_FLAGS 0x2c #define FLAG_USE_DMA BIT(0) +#define PCI_DEVICE_ID_TI_J721E 0xb00d #define PCI_DEVICE_ID_TI_AM654 0xb00c #define is_am654_pci_dev(pdev) \ @@ -932,6 +933,11 @@ static const struct pci_endpoint_test_data am654_data = { .irq_type = IRQ_TYPE_MSI, }; +static const struct pci_endpoint_test_data j721e_data = { + .alignment = 256, + .irq_type = IRQ_TYPE_MSI, +}; + static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x), .driver_data = (kernel_ulong_t)&default_data, @@ -946,6 +952,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { }, { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0), }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E), + .driver_data = (kernel_ulong_t)&j721e_data, + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);