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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id k3sm5463656pjl.15.2020.07.10.04.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:07:43 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 02/21] mmc: core: UHS-II support, modify power-up sequence Date: Fri, 10 Jul 2020 19:08:19 +0800 Message-Id: <20200710110819.28965-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro According to Fig. 3-35 in "SD Host Controller Simplified Spec. Ver4.20": - Prepare vdd1, vdd2 and ios.timing for using after/in step (2) - chip_select is not used in UHS-II, used to return to the legacy flow Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/core/core.c | 62 ++++++++++++++++++++++++------------ drivers/mmc/core/regulator.c | 14 ++++++++ 2 files changed, 56 insertions(+), 20 deletions(-) -- 2.27.0 diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 8d2b808e9b58..85c83c82ad0c 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1315,33 +1315,51 @@ void mmc_power_up(struct mmc_host *host, u32 ocr) if (host->ios.power_mode == MMC_POWER_ON) return; - mmc_pwrseq_pre_power_on(host); + if (host->flags & MMC_UHS2_SUPPORT) { + /* TODO: handle 'ocr' parameter */ + host->ios.vdd = fls(host->ocr_avail) - 1; + host->ios.vdd2 = fls(host->ocr_avail_uhs2) - 1; + if (mmc_host_is_spi(host)) + host->ios.chip_select = MMC_CS_HIGH; + else + host->ios.chip_select = MMC_CS_DONTCARE; + host->ios.timing = MMC_TIMING_UHS2; + } else { + mmc_pwrseq_pre_power_on(host); - host->ios.vdd = fls(ocr) - 1; - host->ios.power_mode = MMC_POWER_UP; - /* Set initial state and call mmc_set_ios */ - mmc_set_initial_state(host); + host->ios.vdd = fls(ocr) - 1; + host->ios.power_mode = MMC_POWER_UP; + /* Set initial state and call mmc_set_ios */ + mmc_set_initial_state(host); - mmc_set_initial_signal_voltage(host); + mmc_set_initial_signal_voltage(host); - /* - * This delay should be sufficient to allow the power supply - * to reach the minimum voltage. - */ - mmc_delay(host->ios.power_delay_ms); - - mmc_pwrseq_post_power_on(host); + /* + * This delay should be sufficient to allow the power supply + * to reach the minimum voltage. + */ + mmc_delay(host->ios.power_delay_ms); + mmc_pwrseq_post_power_on(host); + } host->ios.clock = host->f_init; - host->ios.power_mode = MMC_POWER_ON; + mmc_set_ios(host); - /* - * This delay must be at least 74 clock sizes, or 1 ms, or the - * time required to reach a stable voltage. - */ - mmc_delay(host->ios.power_delay_ms); + if (host->flags & MMC_UHS2_SUPPORT) + /* + * This delay should be sufficient to allow the power supply + * to reach the minimum voltage. + */ + /* TODO: avoid an immediate value */ + mmc_delay(10); + else + /* + * This delay must be at least 74 clock sizes, or 1 ms, or the + * time required to reach a stable voltage. + */ + mmc_delay(host->ios.power_delay_ms); } void mmc_power_off(struct mmc_host *host) @@ -2307,7 +2325,11 @@ void mmc_start_host(struct mmc_host *host) if (!(host->caps2 & MMC_CAP2_NO_PRESCAN_POWERUP)) { mmc_claim_host(host); - mmc_power_up(host, host->ocr_avail); + + /* Power up here will make UHS2 init ugly. */ + if (!(host->caps & MMC_CAP_UHS2)) + mmc_power_up(host, host->ocr_avail); + mmc_release_host(host); } diff --git a/drivers/mmc/core/regulator.c b/drivers/mmc/core/regulator.c index 96b1d15045d6..05556225d9ac 100644 --- a/drivers/mmc/core/regulator.c +++ b/drivers/mmc/core/regulator.c @@ -247,6 +247,7 @@ int mmc_regulator_get_supply(struct mmc_host *mmc) mmc->supply.vmmc = devm_regulator_get_optional(dev, "vmmc"); mmc->supply.vqmmc = devm_regulator_get_optional(dev, "vqmmc"); + mmc->supply.vmmc2 = devm_regulator_get_optional(dev, "vmmc2"); if (IS_ERR(mmc->supply.vmmc)) { if (PTR_ERR(mmc->supply.vmmc) == -EPROBE_DEFER) @@ -266,6 +267,19 @@ int mmc_regulator_get_supply(struct mmc_host *mmc) dev_dbg(dev, "No vqmmc regulator found\n"); } + if (IS_ERR(mmc->supply.vmmc2)) { + if (PTR_ERR(mmc->supply.vmmc2) == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_dbg(dev, "No vmmc2 regulator found\n"); + } else { + ret = mmc_regulator_get_ocrmask(mmc->supply.vmmc2); + if (ret > 0) + mmc->ocr_avail_uhs2 = ret; + else + dev_warn(dev, "Failed getting UHS2 OCR mask: %d\n", + ret); + } + return 0; } EXPORT_SYMBOL_GPL(mmc_regulator_get_supply); From patchwork Fri Jul 10 11:08:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235215 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp344513ilg; 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id g3sm5581621pfq.19.2020.07.10.04.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:07:54 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 03/21] mmc: core: UHS-II support, skip set_chip_select() Date: Fri, 10 Jul 2020 19:08:38 +0800 Message-Id: <20200710110838.29018-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro mmc_set_chip_select() should be called only in UHS-I mode, and not for UHS-II mode. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/core/core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.27.0 diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 85c83c82ad0c..c6540d56646b 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -898,8 +898,10 @@ static inline void mmc_set_ios(struct mmc_host *host) */ void mmc_set_chip_select(struct mmc_host *host, int mode) { - host->ios.chip_select = mode; - mmc_set_ios(host); + if (!(host->flags & MMC_UHS2_INITIALIZED)) { + host->ios.chip_select = mode; + mmc_set_ios(host); + } } /* From patchwork Fri Jul 10 11:08:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235216 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp344822ilg; Fri, 10 Jul 2020 04:08:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyqXHuxqyET3dY60tjDER0wH0IMR73ZVTmWa4HZZzRcSaetdh2pUSwrEzQ8y2VOCPoGakfe X-Received: by 2002:a17:906:3fc7:: with SMTP id k7mr16640915ejj.332.1594379299905; Fri, 10 Jul 2020 04:08:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379299; cv=none; d=google.com; s=arc-20160816; b=lpO/DFmRe+pueGIej51t+9042VpcD7rc/drz60LB0wmGePE3+bBxk1Z+WBErTrkZF5 3y02PLBd6+1uDNVmWITg1h99ZNhmpT4sFGkXcaaoMa8wb4hDhihuOueUNK64NtCJZauA FV73MY28KgBWt2LRpPCN7QTZPzG9HxSNaOGAZ4Ss858OviFc9NyOY8LG6cXFelpHhYZo ZG+kLhlwnbTuCjhFtn3XrhkwEed8pCz5R9fLYFeyAXcKlwZan/5RjQ7cj28EkNIM1Noq tIPYO8CNXx66InGEi+ChHCLAqa8XIV2BuME8FORBcgSBEmG7ZrmpfcR3kavhN2Wu3r5S DJVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=MBX+zLWZoUU7YT17yBn/8lBjP/8tmr8iWyHaBASouus=; b=bOA3w0EJHyHaQbXdDQKJ9p/Mp1Ckbv07eXmCAsFXX6EFcxXZU+j/mFAvXOkba4NM3P bgg1e6QzyKt+ziYaNJ7rNagGlQreo8mUp6aPDWUr+jkxRWF+tWLbg3+od0rNuy7Usx4J 4WaHnt36iDMhLcRoO/LvePWuuHdzeNmH3v1Eb+c1ZfzDS/7KziKNHsYGqGz+df2JnL0A vwFveBo5YCrHhuMpLQhrjkSFcutq7yZAHBTXthlUJ/v7ZPJjf1heGsMEp1YMcMEjzooV D9Ev2JWz0AyULiUfeMN2b4amcPAuNXd3fkoLCMKVcZHL1M1Pkl2JXUjU534Ee2xlAIlu 1W0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=E+n7ZdWp; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id y80sm5498959pfb.165.2020.07.10.04.08.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:08:15 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 05/21] mmc: core: UHS-II support, skip TMODE setup in some cases Date: Fri, 10 Jul 2020 19:08:58 +0800 Message-Id: <20200710110858.29166-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro UHS-II's data command packet has TMODE fields in which parameters for data transaction, like Duplex Mode(DM) and Length Mode(LM), are specified. In some cases, we don't need to initialize them and so set uhs2_tmode0_flag to 1 in order to skip them in generating a packet. (The code will be added in the next commit.) Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/core/block.c | 7 ++++++- drivers/mmc/core/sd_ops.c | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) -- 2.27.0 diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c index 7896952de1ac..212f872d60bc 100644 --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c @@ -56,6 +56,7 @@ #include "mmc_ops.h" #include "quirks.h" #include "sd_ops.h" +#include "uhs2.h" MODULE_ALIAS("mmc:block"); #ifdef MODULE_PARAM_PREFIX @@ -1526,6 +1527,9 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, struct request *req = mmc_queue_req_to_req(mqrq); struct mmc_blk_data *md = mq->blkdata; bool do_rel_wr, do_data_tag; + bool do_multi; + + do_multi = (card->host->flags & MMC_UHS2_INITIALIZED) ? true : false; mmc_blk_data_prep(mq, mqrq, disable_multi, &do_rel_wr, &do_data_tag); @@ -1536,7 +1540,7 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, brq->cmd.arg <<= 9; brq->cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; - if (brq->data.blocks > 1 || do_rel_wr) { + if (brq->data.blocks > 1 || do_rel_wr || do_multi) { /* SPI multiblock writes terminate using a special * token, not a STOP_TRANSMISSION request. */ @@ -1549,6 +1553,7 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, brq->mrq.stop = NULL; readcmd = MMC_READ_SINGLE_BLOCK; writecmd = MMC_WRITE_BLOCK; + brq->cmd.uhs2_tmode0_flag = 1; } brq->cmd.opcode = rq_data_dir(req) == READ ? readcmd : writecmd; diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c index 22bf528294b9..f58bb50872f6 100644 --- a/drivers/mmc/core/sd_ops.c +++ b/drivers/mmc/core/sd_ops.c @@ -235,6 +235,7 @@ int mmc_app_send_scr(struct mmc_card *card) cmd.opcode = SD_APP_SEND_SCR; cmd.arg = 0; cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; + cmd.uhs2_tmode0_flag = 1; data.blksz = 8; data.blocks = 1; @@ -282,6 +283,7 @@ int mmc_sd_switch(struct mmc_card *card, int mode, int group, cmd.arg &= ~(0xF << (group * 4)); cmd.arg |= value << (group * 4); cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; + cmd.uhs2_tmode0_flag = 1; data.blksz = 64; data.blocks = 1; @@ -323,6 +325,7 @@ int mmc_app_sd_status(struct mmc_card *card, void *ssr) cmd.opcode = SD_APP_SD_STATUS; cmd.arg = 0; cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_ADTC; + cmd.uhs2_tmode0_flag = 1; data.blksz = 64; data.blocks = 1; From patchwork Fri Jul 10 11:09:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235217 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp345134ilg; Fri, 10 Jul 2020 04:08:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx2wsHnbK22k5eHXbtLPVSUSjaRmusp/H+2Uh5hwBkNL+Ina+lP7aKKjBVRMdCt+JcVYqmS X-Received: by 2002:a17:906:35ce:: with SMTP id p14mr60051300ejb.514.1594379325215; Fri, 10 Jul 2020 04:08:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379325; cv=none; d=google.com; s=arc-20160816; b=SUiV+7PfZ8DgaCkHuJVc0ZkUqOhz9X6IAqKij42ZvGrMyOtDDyzzePDyGPYpPSnzOZ 3gLZXqQskT50J7ce/acha1l/jYsw/YDbRqSjppzUWK3qW9dB9wbU1o+bHRnN9Vq+D+L6 YJAqkH12bBUo5ugoffgGVW4TxbZR0MdzsNyWe2Lr9nGtzLL3FEPF/O+6Q85xrk1s7hXc 2mPLLTmQSAP8a7VyG6DCADCL+CrRMaNOF6+VMc+rXYkaJpI+3xOG4RImEhqAC726QBFJ SVsSKeThyWmFUAurZ5oqGHgGtVV0+NPRm7sipg9d/l7Wh/4fdv5l7C4MkZ5TumF0Pawx do0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=F8O0SJiIJfP0hcr2bPL6Gp5kFAhLJphHNCRKgoNomCk=; b=MedDPvXgQ/aC0YJ+PRU/nkysQT7oaMIt5akCAaX/IfhgFc3SXtuFHbJLCT7bARi+q9 n9wgcHxcJeT0OVC7Oob/XWhSlm2lu47UuTzPcP+VKAOJZh4ZzjsNpCoWgtsV3e1bBSP/ XA8kwaneIcsuwy/U4MMmEL+NewVWJiuRxfhdSooV/qcHLS+Byx/ianMtbyEU/ngvd4Vv dGdlzD3Fk2MT3q+DxdTTIg4hTVgAKvjqlsSJ3/0TUCPNfBvld0CgRXxXMf6/Wv9aMvKW YU4ze6OE8HQ0OgRUEscxHRb8WvXsOO170tqmc8XQneH7VsE+ximU1TKwsaaHW8GUBYpK 2+SQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=vQwHVP5j; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Please see section 7.1 and 7.2.1 in "UHS-II Simplified Addendum." Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/core/core.c | 18 +++++++++++ drivers/mmc/core/uhs2.c | 70 +++++++++++++++++++++++++++++++++++++++++ drivers/mmc/core/uhs2.h | 1 + 3 files changed, 89 insertions(+) -- 2.27.0 diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index e2534f3446ce..dfe3a6df7645 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -337,6 +337,8 @@ static int mmc_mrq_prep(struct mmc_host *host, struct mmc_request *mrq) int mmc_start_request(struct mmc_host *host, struct mmc_request *mrq) { + struct uhs2_command uhs2_cmd; + u32 payload[4]; /* for maximum size */ int err; init_completion(&mrq->cmd_completion); @@ -354,6 +356,13 @@ int mmc_start_request(struct mmc_host *host, struct mmc_request *mrq) if (err) return err; + if (host->flags & MMC_UHS2_SUPPORT && + host->flags & MMC_UHS2_INITIALIZED) { + uhs2_cmd.payload = payload; + mrq->cmd->uhs2_cmd = &uhs2_cmd; + uhs2_prepare_sd_cmd(host, mrq); + } + led_trigger_event(host->led, LED_FULL); __mmc_start_request(host, mrq); @@ -433,6 +442,8 @@ EXPORT_SYMBOL(mmc_wait_for_req_done); */ int mmc_cqe_start_req(struct mmc_host *host, struct mmc_request *mrq) { + struct uhs2_command uhs2_cmd; + u32 payload[4]; /* for maximum size */ int err; /* @@ -453,6 +464,13 @@ int mmc_cqe_start_req(struct mmc_host *host, struct mmc_request *mrq) if (err) goto out_err; + if (host->flags & MMC_UHS2_SUPPORT && + host->flags & MMC_UHS2_INITIALIZED) { + uhs2_cmd.payload = payload; + mrq->cmd->uhs2_cmd = &uhs2_cmd; + uhs2_prepare_sd_cmd(host, mrq); + } + err = host->cqe_ops->cqe_request(host, mrq); if (err) goto out_err; diff --git a/drivers/mmc/core/uhs2.c b/drivers/mmc/core/uhs2.c index a3b20ac6f315..6e26de429726 100644 --- a/drivers/mmc/core/uhs2.c +++ b/drivers/mmc/core/uhs2.c @@ -798,3 +798,73 @@ int mmc_uhs2_rescan_try_freq(struct mmc_host *host, unsigned int freq) return err; } EXPORT_SYMBOL_GPL(mmc_uhs2_rescan_try_freq); + +/** + * uhs2_prepare_sd_cmd - prepare for SD command packet + * @host: MMC host + * @mrq: MMC request + * + * Initialize and fill in a header and a payload of SD command packet. + * The caller should allocate uhs2_command in host->cmd->uhs2_cmd in + * advance. + * + * Return: 0 on success, non-zero error on failure + */ +int uhs2_prepare_sd_cmd(struct mmc_host *host, struct mmc_request *mrq) +{ + struct mmc_command *cmd; + struct uhs2_command *uhs2_cmd; + u16 header = 0, arg = 0; + u32 *payload; + u8 plen = 0; + + cmd = mrq->cmd; + header = host->uhs2_dev_prop.node_id; + if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) + header |= UHS2_PACKET_TYPE_DCMD; + else + header |= UHS2_PACKET_TYPE_CCMD; + + arg = cmd->opcode << UHS2_SD_CMD_INDEX_POS; + + uhs2_cmd = cmd->uhs2_cmd; + payload = uhs2_cmd->payload; + plen = 2; /* at the maximum */ + + if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC && + !cmd->uhs2_tmode0_flag) { + if (host->flags & MMC_UHS2_2L_HD) + arg |= UHS2_DCMD_2L_HD_MODE; + + arg |= UHS2_DCMD_LM_TLEN_EXIST; + + if (cmd->data->blocks == 1 && + cmd->data->blksz != 512 && + cmd->opcode != MMC_READ_SINGLE_BLOCK && + cmd->opcode != MMC_WRITE_BLOCK) { + arg |= UHS2_DCMD_TLUM_BYTE_MODE; + payload[1] = uhs2_dcmd_convert_msb(cmd->data->blksz); + } else { + payload[1] = uhs2_dcmd_convert_msb(cmd->data->blocks); + } + + if (cmd->opcode == SD_IO_RW_EXTENDED) { + arg &= ~(UHS2_DCMD_LM_TLEN_EXIST | + UHS2_DCMD_TLUM_BYTE_MODE | + UHS2_NATIVE_DCMD_DAM_IO); + payload[1] = 0; + plen = 1; + } + } else { + plen = 1; + } + + payload[0] = uhs2_dcmd_convert_msb(cmd->arg); + pr_debug("%s: %s: sd_cmd->arg = 0x%x, payload[0]= 0x%x.\n", + mmc_hostname(host), __func__, cmd->arg, payload[0]); + + uhs2_cmd_assemble(cmd, uhs2_cmd, header, arg, payload, plen, NULL, 0); + + return 0; +} +EXPORT_SYMBOL_GPL(uhs2_prepare_sd_cmd); diff --git a/drivers/mmc/core/uhs2.h b/drivers/mmc/core/uhs2.h index e3389d4dda3b..48486ba21062 100644 --- a/drivers/mmc/core/uhs2.h +++ b/drivers/mmc/core/uhs2.h @@ -16,5 +16,6 @@ #define UHS2_PHY_INIT_ERR 1 int mmc_uhs2_rescan_try_freq(struct mmc_host *host, unsigned int freq); +int uhs2_prepare_sd_cmd(struct mmc_host *host, struct mmc_request *mrq); #endif /* MMC_UHS2_H */ From patchwork Fri Jul 10 11:09:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235218 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp345290ilg; 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id v2sm5395427pje.19.2020.07.10.04.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:08:53 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 07/21] mmc: core: UHS-II support, set APP_CMD bit if necessary Date: Fri, 10 Jul 2020 19:09:37 +0800 Message-Id: <20200710110937.29283-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro In UHS-II mode, MMC_APP_CMD command need not to be sent. Instead, APP_CMD bit in a packet should be set. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/core/sd_ops.c | 9 +++++++++ drivers/mmc/core/uhs2.c | 4 ++++ 2 files changed, 13 insertions(+) -- 2.27.0 diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c index f58bb50872f6..9dc296356928 100644 --- a/drivers/mmc/core/sd_ops.c +++ b/drivers/mmc/core/sd_ops.c @@ -26,6 +26,15 @@ int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card) if (WARN_ON(card && card->host != host)) return -EINVAL; + /* UHS2 packet has APP bit so only set APP_CMD flag here. + * Will set the APP bit when assembling UHS2 packet. + */ + if (host->flags & MMC_UHS2_SUPPORT && + host->flags & MMC_UHS2_INITIALIZED) { + host->flags |= MMC_UHS2_APP_CMD; + return 0; + } + cmd.opcode = MMC_APP_CMD; if (card) { diff --git a/drivers/mmc/core/uhs2.c b/drivers/mmc/core/uhs2.c index 6e26de429726..2fbd7b6d9dea 100644 --- a/drivers/mmc/core/uhs2.c +++ b/drivers/mmc/core/uhs2.c @@ -826,6 +826,10 @@ int uhs2_prepare_sd_cmd(struct mmc_host *host, struct mmc_request *mrq) header |= UHS2_PACKET_TYPE_CCMD; arg = cmd->opcode << UHS2_SD_CMD_INDEX_POS; + if (host->flags & MMC_UHS2_APP_CMD) { + arg |= UHS2_SD_CMD_APP; + host->flags &= ~MMC_UHS2_APP_CMD; + } uhs2_cmd = cmd->uhs2_cmd; payload = uhs2_cmd->payload; From patchwork Fri Jul 10 11:10:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235219 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp345647ilg; Fri, 10 Jul 2020 04:09:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyX6nbfTqqY0LpUpgH4kasVv6UW2ajI4oRxyVmsnTw0CQkXJmo/bEeJUS5PeLHbARDgjtGH X-Received: by 2002:aa7:d50d:: with SMTP id y13mr76502452edq.230.1594379369135; Fri, 10 Jul 2020 04:09:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379369; cv=none; d=google.com; s=arc-20160816; b=Dw2Nl8Wl18Bf0vgmaXRaFkwB+veYURxaFN4Ep1Z1QrmEdYQul55DwZsUqWjT0aXMja d6vinSxdAgGVIa3bNIPwIe/zGyOfAiUUA+6qWs9aKvs+fQ3Sgi85BHpHhoabVzd5mfIA AP4v+WzB3eFkV84VNLqGFvI3n2ON+tlCcnhuMqk93pbbsN1FF6ySZl/4PGogmP9f7o6N 7ClprwJV2/GOGqMg8YBtpDpsTCUw+ibyfCfLqj3B/QhlzdxAqRbsRC50C0VZf/eBrmgF yELgP3MAm6rXMbaTKkV8irIM90PfP1NG4tiT2O8p9dxxKfwfNpWUFZXX2ygtFFUTqheA VCeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=ge6tP7aJVA2/arYXridWtv60L0GDRBud+3BiIv4iGwU=; b=BfQk3W6ufiIbF3mGNsc9VvmrDowFJ/1y3l9tHsqCX3Uf6mnzHzCEjyjgGZRx3X/SQ+ 0ttAllUHXLtTYavj4oezNm8vEUYcDUJkZWuL58eTI72b1g/P/Hu1dXf5Ltg6btX2vFE1 a8qnW6In6oWRgWdksJl8P2EdyrS7n3U+Pw4QMIOVvl0iIIH+y5f520S3p2cpCSFGS4is PAS0sb3QwYZOWTqu76KvrvB/9TsmRSXBCBNL4T0Gzat7pYNd10eBJlxFOAYLKIe3WJcR 6lQRmHakLppO6MnAByRAaJUX8Lz73cZi0vEAApNvWoiTM237rjaGQZJ8Nj5hZglHjuH4 6SKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=ndy1tJ6F; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id m1sm5211496pjy.0.2020.07.10.04.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:09:26 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 08/21] mmc: sdhci: add a kernel configuration for enabling UHS-II support Date: Fri, 10 Jul 2020 19:10:10 +0800 Message-Id: <20200710111010.29345-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro This kernel configuration, CONFIG_MMC_SDHCI_UHS2, will be used in the following commits to indicate UHS-II specific code in sdhci controllers. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.27.0 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 3b706af35ec3..ffeef38264c0 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -89,6 +89,15 @@ config MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER This is the case for the Nintendo Wii SDHCI. +config MMC_SDHCI_UHS2 + tristate "UHS2 support on SDHCI controller" + depends on MMC_SDHCI + help + This option is selected by SDHCI controller drivers that want to + support UHS2-capable devices. + + If you have a controller with this feature, say Y or M here. + config MMC_SDHCI_PCI tristate "SDHCI support on PCI bus" depends on MMC_SDHCI && PCI From patchwork Fri Jul 10 11:10:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235220 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp345850ilg; Fri, 10 Jul 2020 04:09:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxWeCxhE7cyhpEc45rBBDJd5Ki68lB4JxHbJUWmXbKYAhVAldSxbb8n4uGk+PW4qNwyV6Qk X-Received: by 2002:aa7:cf94:: with SMTP id z20mr78852120edx.82.1594379381857; Fri, 10 Jul 2020 04:09:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379381; cv=none; d=google.com; s=arc-20160816; b=li5wlSWBUHR3UwYl9VBk031CA3SJU14Ef91eiYlbamI3Iqj354PvUFSG0911XUk7UF MFiRBURPeCwUC70gaAAW3BjfsrPqYw1xwqw/Y+3FkerVcvfjyBXJys7q1kR0KFm12UoB aD47aROZd1eyvnCJWn6N8MflQGm8wiRxep9Mu+59vclG4OeRliI0qHqSilt/s++uk+JS ru5SYTiXO3Yt8nuG+TkXXWA6n9aOznnwKzFw+r8Uwh5R0BkRmPWJHeSH4WF5POT20dJo LltwEv4SitRbx72yIznUfpYvS2HuYsjWXQ2uvz+Tf9P6eqjaOi/ha1PHOZtt9lTSkxhg ZV5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=xrjk59egYvJ8GHaDhNEmPkttWVMBNW7KFE/O0I7RbgU=; b=VeTamAcJqNLTDbRqhyKHdZ/zJ2bwJJXNYYfUERsTwWuUGl/l4o+nvESuag4PYCL/4Y PGuJav/y4dU1wYHadxmAi/R1jkxhTwEs8K+TdDuUmxQVfF1gXdddliKh4ghgAk/T9ITU L2H6xu9hy7ZYeQBP1wFraO5J7PkCAP/oyrJHPMIx8XlMMtvGjZdzL4NR+zitrlpiMRYH U5kk+RKfQfdsERNzKKXZLt06uWhadcWtT2X8NlJYVAv2aSF1JkHeK3hxAIPZ9W3grmnM ndi15hktG/VM6AU4djs1Tcu/Uv5n1+BE/4V8h+ysBum2igOSBs3uH3Xx4FH88oMv74t+ xueA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=QUzNqglx; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id y65sm5630152pfb.75.2020.07.10.04.09.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:09:39 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 09/21] mmc: sdhci: add UHS-II related definitions in headers Date: Fri, 10 Jul 2020 19:10:21 +0800 Message-Id: <20200710111021.29397-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro Add UHS-II related definitions in shdci.h and sdhci-uhs2.h. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci-uhs2.h | 215 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 91 +++++++++++++- 2 files changed, 305 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/host/sdhci-uhs2.h -- 2.27.0 diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h new file mode 100644 index 000000000000..a7f53f95d69a --- /dev/null +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * linux/drivers/mmc/host/sdhci-uhs2.h - Secure Digital Host Controller + * Interface driver + * + * Header file for Host Controller UHS2 related registers and I/O accessors. + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + */ +#ifndef __SDHCI_UHS2_H +#define __SDHCI_UHS2_H + +#include +#include +#include + +/* + * UHS-II Controller registers + * 0x74 preset in sdhci.h + * 0x80 + * 0x84-0xB4 + * 0xB8-0xCF + * 0xE0-0xE7 + */ +/* UHS2 */ +#define SDHCI_UHS2_BLOCK_SIZE 0x80 +#define SDHCI_UHS2_MAKE_BLKSZ(dma, blksz) \ + ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF)) + +#define SDHCI_UHS2_BLOCK_COUNT 0x84 + +#define SDHCI_UHS2_CMD_PACKET 0x88 +#define SDHCI_UHS2_CMD_PACK_MAX_LEN 20 + +#define SDHCI_UHS2_TRANS_MODE 0x9C +#define SDHCI_UHS2_TRNS_DMA 0x0001 +#define SDHCI_UHS2_TRNS_BLK_CNT_EN 0x0002 +#define SDHCI_UHS2_TRNS_DATA_TRNS_WRT 0x0010 +#define SDHCI_UHS2_TRNS_BLK_BYTE_MODE 0x0020 +#define SDHCI_UHS2_TRNS_RES_R5 0x0040 +#define SDHCI_UHS2_TRNS_RES_ERR_CHECK_EN 0x0080 +#define SDHCI_UHS2_TRNS_RES_INT_DIS 0x0100 +#define SDHCI_UHS2_TRNS_WAIT_EBSY 0x4000 +#define SDHCI_UHS2_TRNS_2L_HD 0x8000 + +#define SDHCI_UHS2_COMMAND 0x9E +#define SDHCI_UHS2_COMMAND_SUB_CMD 0x0004 +#define SDHCI_UHS2_COMMAND_DATA 0x0020 +#define SDHCI_UHS2_COMMAND_TRNS_ABORT 0x0040 +#define SDHCI_UHS2_COMMAND_CMD12 0x0080 +#define SDHCI_UHS2_COMMAND_DORMANT 0x00C0 +#define SDHCI_UHS2_COMMAND_PACK_LEN_MASK 0x1F00 +#define SDHCI_UHS2_COMMAND_PACK_LEN_SHIFT 8 + +#define SDHCI_UHS2_RESPONSE 0xA0 +#define SDHCI_UHS2_RESPONSE_MAX_LEN 20 + +#define SDHCI_UHS2_MSG_SELECT 0xB4 +#define SDHCI_UHS2_MSG_SELECT_CURR 0x0 +#define SDHCI_UHS2_MSG_SELECT_ONE 0x1 +#define SDHCI_UHS2_MSG_SELECT_TWO 0x2 +#define SDHCI_UHS2_MSG_SELECT_THREE 0x3 + +#define SDHCI_UHS2_MSG 0xB8 + +#define SDHCI_UHS2_DEV_INT_STATUS 0xBC + +#define SDHCI_UHS2_DEV_SELECT 0xBE +#define SDHCI_UHS2_DEV_SELECT_DEV_SEL_MASK 0x0F +#define SDHCI_UHS2_DEV_SELECT_INT_MSG_EN 0x80 + +#define SDHCI_UHS2_DEV_INT_CODE 0xBF + +#define SDHCI_UHS2_SW_RESET 0xC0 +#define SDHCI_UHS2_SW_RESET_FULL 0x0001 +#define SDHCI_UHS2_SW_RESET_SD 0x0002 + +#define SDHCI_UHS2_TIMER_CTRL 0xC2 +#define SDHCI_UHS2_TIMER_CTRL_DEADLOCK_SHIFT 4 + +#define SDHCI_UHS2_ERR_INT_STATUS 0xC4 +#define SDHCI_UHS2_ERR_INT_STATUS_EN 0xC8 +#define SDHCI_UHS2_ERR_INT_SIG_EN 0xCC +#define SDHCI_UHS2_ERR_INT_STATUS_HEADER 0x00000001 +#define SDHCI_UHS2_ERR_INT_STATUS_RES 0x00000002 +#define SDHCI_UHS2_ERR_INT_STATUS_RETRY_EXP 0x00000004 +#define SDHCI_UHS2_ERR_INT_STATUS_CRC 0x00000008 +#define SDHCI_UHS2_ERR_INT_STATUS_FRAME 0x00000010 +#define SDHCI_UHS2_ERR_INT_STATUS_TID 0x00000020 +#define SDHCI_UHS2_ERR_INT_STATUS_UNRECOVER 0x00000080 +#define SDHCI_UHS2_ERR_INT_STATUS_EBUSY 0x00000100 +#define SDHCI_UHS2_ERR_INT_STATUS_ADMA 0x00008000 +#define SDHCI_UHS2_ERR_INT_STATUS_RES_TIMEOUT 0x00010000 +#define SDHCI_UHS2_ERR_INT_STATUS_DEADLOCK_TIMEOUT 0x00020000 +#define SDHCI_UHS2_ERR_INT_STATUS_VENDOR 0x08000000 +#define SDHCI_UHS2_ERR_INT_STATUS_MASK \ + (SDHCI_UHS2_ERR_INT_STATUS_HEADER | \ + SDHCI_UHS2_ERR_INT_STATUS_RES | \ + SDHCI_UHS2_ERR_INT_STATUS_RETRY_EXP | \ + SDHCI_UHS2_ERR_INT_STATUS_CRC | \ + SDHCI_UHS2_ERR_INT_STATUS_FRAME | \ + SDHCI_UHS2_ERR_INT_STATUS_TID | \ + SDHCI_UHS2_ERR_INT_STATUS_UNRECOVER | \ + SDHCI_UHS2_ERR_INT_STATUS_EBUSY | \ + SDHCI_UHS2_ERR_INT_STATUS_ADMA | \ + SDHCI_UHS2_ERR_INT_STATUS_RES_TIMEOUT | \ + SDHCI_UHS2_ERR_INT_STATUS_DEADLOCK_TIMEOUT) +#define SDHCI_UHS2_ERR_INT_STATUS_CMD_MASK \ + (SDHCI_UHS2_ERR_INT_STATUS_HEADER | \ + SDHCI_UHS2_ERR_INT_STATUS_RES | \ + SDHCI_UHS2_ERR_INT_STATUS_FRAME | \ + SDHCI_UHS2_ERR_INT_STATUS_TID | \ + SDHCI_UHS2_ERR_INT_STATUS_RES_TIMEOUT) +/* CRC Error occurs during a packet receiving */ +#define SDHCI_UHS2_ERR_INT_STATUS_DATA_MASK \ + (SDHCI_UHS2_ERR_INT_STATUS_RETRY_EXP | \ + SDHCI_UHS2_ERR_INT_STATUS_CRC | \ + SDHCI_UHS2_ERR_INT_STATUS_UNRECOVER | \ + SDHCI_UHS2_ERR_INT_STATUS_EBUSY | \ + SDHCI_UHS2_ERR_INT_STATUS_ADMA | \ + SDHCI_UHS2_ERR_INT_STATUS_DEADLOCK_TIMEOUT) + +#define SDHCI_UHS2_SET_PTR 0xE0 +#define SDHCI_UHS2_GEN_SET_POWER_LOW 0x0001 +#define SDHCI_UHS2_GEN_SET_N_LANES_POS 8 +#define SDHCI_UHS2_GEN_SET_2L_FD_HD 0x0 +#define SDHCI_UHS2_GEN_SET_2D1U_FD 0x2 +#define SDHCI_UHS2_GEN_SET_1D2U_FD 0x3 +#define SDHCI_UHS2_GEN_SET_2D2U_FD 0x4 + +#define SDHCI_UHS2_PHY_SET_SPEED_POS 6 +#define SDHCI_UHS2_PHY_SET_HIBER_EN 0x00008000 +#define SDHCI_UHS2_PHY_SET_N_LSS_SYN_MASK 0x000F0000 +#define SDHCI_UHS2_PHY_SET_N_LSS_SYN_POS 16 +#define SDHCI_UHS2_PHY_SET_N_LSS_DIR_MASK 0x00F00000 +#define SDHCI_UHS2_PHY_SET_N_LSS_DIR_POS 20 + +#define SDHCI_UHS2_TRAN_SET_N_FCU_MASK 0x0000FF00 +#define SDHCI_UHS2_TRAN_SET_N_FCU_POS 8 +#define SDHCI_UHS2_TRAN_SET_RETRY_CNT_MASK 0x00030000 +#define SDHCI_UHS2_TRAN_SET_RETRY_CNT_POS 16 + +#define SDHCI_UHS2_TRAN_SET_1_N_DAT_GAP_MASK 0x000000FF + +#define SDHCI_UHS2_HOST_CAPS_PTR 0xE2 +#define SDHCI_UHS2_HOST_CAPS_GEN_OFFSET 0 +#define SDHCI_UHS2_HOST_CAPS_GEN_DAP_MASK 0x0000000F +#define SDHCI_UHS2_HOST_CAPS_GEN_GAP_MASK 0x000000F0 +#define SDHCI_UHS2_HOST_CAPS_GEN_GAP(gap) ((gap) * 360) +#define SDHCI_UHS2_HOST_CAPS_GEN_GAP_SHIFT 4 +#define SDHCI_UHS2_HOST_CAPS_GEN_LANE_MASK 0x00003F00 +#define SDHCI_UHS2_HOST_CAPS_GEN_LANE_SHIFT 8 +#define SDHCI_UHS2_HOST_CAPS_GEN_2L_HD_FD 1 +#define SDHCI_UHS2_HOST_CAPS_GEN_2D1U_FD 2 +#define SDHCI_UHS2_HOST_CAPS_GEN_1D2U_FD 4 +#define SDHCI_UHS2_HOST_CAPS_GEN_2D2U_FD 8 +#define SDHCI_UHS2_HOST_CAPS_GEN_ADDR_64 0x00004000 +#define SDHCI_UHS2_HOST_CAPS_GEN_BOOT 0x00008000 +#define SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_MASK 0x00030000 +#define SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_SHIFT 16 +#define SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_RMV 0 +#define SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_EMB 1 +#define SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_EMB_RMV 2 +#define SDHCI_UHS2_HOST_CAPS_GEN_NUM_DEV_MASK 0x003C0000 +#define SDHCI_UHS2_HOST_CAPS_GEN_NUM_DEV_SHIFT 18 +#define SDHCI_UHS2_HOST_CAPS_GEN_BUS_TOPO_MASK 0x00C00000 +#define SDHCI_UHS2_HOST_CAPS_GEN_BUS_TOPO_SHIFT 22 +#define SDHCI_UHS2_HOST_CAPS_GEN_BUS_TOPO_P2P 0 +#define SDHCI_UHS2_HOST_CAPS_GEN_BUS_TOPO_RING 1 +#define SDHCI_UHS2_HOST_CAPS_GEN_BUS_TOPO_HUB 2 +#define SDHCI_UHS2_HOST_CAPS_GEN_BUS_TOPO_HUB_RING 3 + +#define SDHCI_UHS2_HOST_CAPS_PHY_OFFSET 4 +#define SDHCI_UHS2_HOST_CAPS_PHY_REV_MASK 0x0000003F +#define SDHCI_UHS2_HOST_CAPS_PHY_RANGE_MASK 0x000000C0 +#define SDHCI_UHS2_HOST_CAPS_PHY_RANGE_SHIFT 6 +#define SDHCI_UHS2_HOST_CAPS_PHY_RANGE_A 0 +#define SDHCI_UHS2_HOST_CAPS_PHY_RANGE_B 1 +#define SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_MASK 0x000F0000 +#define SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_SHIFT 16 +#define SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_MASK 0x00F00000 +#define SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_SHIFT 20 +#define SDHCI_UHS2_HOST_CAPS_TRAN_OFFSET 8 +#define SDHCI_UHS2_HOST_CAPS_TRAN_LINK_REV_MASK 0x0000003F +#define SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_MASK 0x0000FF00 +#define SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_SHIFT 8 +#define SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_MASK 0x00070000 +#define SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_SHIFT 16 +#define SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_MASK 0xFFF00000 +#define SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_SHIFT 20 + +#define SDHCI_UHS2_HOST_CAPS_TRAN_1_OFFSET 12 +#define SDHCI_UHS2_HOST_CAPS_TRAN_1_N_DATA_GAP_MASK 0x000000FF + +#define SDHCI_UHS2_TEST_PTR 0xE4 +#define SDHCI_UHS2_TEST_ERR_HEADER 0x00000001 +#define SDHCI_UHS2_TEST_ERR_RES 0x00000002 +#define SDHCI_UHS2_TEST_ERR_RETRY_EXP 0x00000004 +#define SDHCI_UHS2_TEST_ERR_CRC 0x00000008 +#define SDHCI_UHS2_TEST_ERR_FRAME 0x00000010 +#define SDHCI_UHS2_TEST_ERR_TID 0x00000020 +#define SDHCI_UHS2_TEST_ERR_UNRECOVER 0x00000080 +#define SDHCI_UHS2_TEST_ERR_EBUSY 0x00000100 +#define SDHCI_UHS2_TEST_ERR_ADMA 0x00008000 +#define SDHCI_UHS2_TEST_ERR_RES_TIMEOUT 0x00010000 +#define SDHCI_UHS2_TEST_ERR_DEADLOCK_TIMEOUT 0x00020000 +#define SDHCI_UHS2_TEST_ERR_VENDOR 0x08000000 + +#define SDHCI_UHS2_EMBED_CTRL 0xE6 +#define SDHCI_UHS2_VENDOR 0xE8 + +void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); +void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set); + +#endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 0008bbd27127..ecf55394ea46 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -43,8 +43,27 @@ #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 +/* + * Defined in Host Version 4.10. + * 1 - R5 (SDIO) + * 0 - R1 (Memory) + */ +#define SDHCI_TRNS_RES_TYPE 0x40 +#define SDHCI_TRNS_RES_ERR_CHECK 0x80 +#define SDHCI_TRNS_RES_INT_DIS 0x0100 + #define SDHCI_COMMAND 0x0E #define SDHCI_CMD_RESP_MASK 0x03 + +/* + * Host Version 4.10 adds this bit to distinguish a main command or + * sub command. + * CMD53(SDIO) - main command + * CMD52(SDIO) - sub command which doesn't have data block or doesn't + * indicate busy. + */ +#define SDHCI_CMD_SUB_CMD 0x04 + #define SDHCI_CMD_CRC 0x08 #define SDHCI_CMD_INDEX 0x10 #define SDHCI_CMD_DATA 0x20 @@ -60,11 +79,19 @@ #define SDHCI_RESPONSE 0x10 +#define SDHCI_RESPONSE_CM_TRAN_ABORT_OFFSET 0x10 +#define SDHCI_RESPONSE_CM_TRAN_ABORT_SIZE 4 +#define SDHCI_RESPONSE_SD_TRAN_ABORT_OFFSET 0x18 +#define SDHCI_RESPONSE_SD_TRAN_ABORT_SIZE 8 + #define SDHCI_BUFFER 0x20 #define SDHCI_PRESENT_STATE 0x24 #define SDHCI_CMD_INHIBIT 0x00000001 #define SDHCI_DATA_INHIBIT 0x00000002 + +#define SDHCI_DATA_HIGH_LVL_MASK 0x000000F0 + #define SDHCI_DOING_WRITE 0x00000100 #define SDHCI_DOING_READ 0x00000200 #define SDHCI_SPACE_AVAILABLE 0x00000400 @@ -80,6 +107,13 @@ #define SDHCI_DATA_0_LVL_MASK 0x00100000 #define SDHCI_CMD_LVL 0x01000000 +#define SDHCI_HOST_REGULATOR_STABLE 0x02000000 +#define SDHCI_CMD_NOT_ISSUE_ERR 0x08000000 +#define SDHCI_SUB_CMD_STATUS 0x10000000 +#define SDHCI_UHS2_IN_DORMANT_STATE 0x20000000 +#define SDHCI_UHS2_LANE_SYNC 0x40000000 +#define SDHCI_UHS2_IF_DETECT 0x80000000 + #define SDHCI_HOST_CONTROL 0x28 #define SDHCI_CTRL_LED 0x01 #define SDHCI_CTRL_4BITBUS 0x02 @@ -100,6 +134,11 @@ #define SDHCI_POWER_300 0x0C #define SDHCI_POWER_330 0x0E +/* VDD2 - UHS2 */ +#define SDHCI_VDD2_POWER_ON 0x10 +#define SDHCI_VDD2_POWER_180 0xA0 +#define SDHCI_VDD2_POWER_120 0x80 + #define SDHCI_BLOCK_GAP_CONTROL 0x2A #define SDHCI_WAKE_UP_CONTROL 0x2B @@ -110,7 +149,7 @@ #define SDHCI_CLOCK_CONTROL 0x2C #define SDHCI_DIVIDER_SHIFT 8 #define SDHCI_DIVIDER_HI_SHIFT 6 -#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK 0xFF #define SDHCI_DIV_MASK_LEN 8 #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 @@ -139,6 +178,10 @@ #define SDHCI_INT_CARD_REMOVE 0x00000080 #define SDHCI_INT_CARD_INT 0x00000100 #define SDHCI_INT_RETUNE 0x00001000 + +/* Host Version 4.10 */ +#define SDHCI_INT_FX_EVENT 0x00002000 + #define SDHCI_INT_CQE 0x00004000 #define SDHCI_INT_ERROR 0x00008000 #define SDHCI_INT_TIMEOUT 0x00010000 @@ -152,6 +195,9 @@ #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 #define SDHCI_INT_ADMA_ERROR 0x02000000 +/* Host Version 4.0 */ +#define SDHCI_INT_RESPONSE_ERROR 0x08000000 + #define SDHCI_INT_NORMAL_MASK 0x00007FFF #define SDHCI_INT_ERROR_MASK 0xFFFF8000 @@ -178,6 +224,9 @@ #define SDHCI_AUTO_CMD_END_BIT 0x00000008 #define SDHCI_AUTO_CMD_INDEX 0x00000010 +/* Host Version 4.10 */ +#define SDHCI_ACMD_RESPONSE_ERROR 0x0020 + #define SDHCI_HOST_CONTROL2 0x3E #define SDHCI_CTRL_UHS_MASK 0x0007 #define SDHCI_CTRL_UHS_SDR12 0x0000 @@ -186,6 +235,7 @@ #define SDHCI_CTRL_UHS_SDR104 0x0003 #define SDHCI_CTRL_UHS_DDR50 0x0004 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_UHS_2 0x0007 /* UHS-2 */ #define SDHCI_CTRL_VDD_180 0x0008 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 @@ -194,9 +244,12 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_UHS2_INTERFACE_EN 0x0100 /* UHS-2 */ +#define SDHCI_CTRL_ADMA2_LEN_MODE 0x0400 #define SDHCI_CMD23_ENABLE 0x0800 #define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_64BIT_ADDR 0x2000 +#define SDHCI_CTRL_ASYNC_INT_EN 0x4000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -217,11 +270,13 @@ #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_ASYNC_INT 0x20000000 #define SDHCI_CAPABILITIES_1 0x44 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 #define SDHCI_SUPPORT_DDR50 0x00000004 +#define SDHCI_SUPPORT_UHS2 0x00000008 /* UHS-2 support */ #define SDHCI_DRIVER_TYPE_A 0x00000010 #define SDHCI_DRIVER_TYPE_C 0x00000020 #define SDHCI_DRIVER_TYPE_D 0x00000040 @@ -230,19 +285,28 @@ #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) #define SDHCI_CAN_DO_ADMA3 0x08000000 +#define SDHCI_SUPPORT_VDD2_180 0x10000000 /* UHS-2 1.8V VDD2 */ +#define SDHCI_RSVD_FOR_VDD2 0x20000000 /* Rsvd for future VDD2 */ #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ #define SDHCI_MAX_CURRENT 0x48 +#define SDHCI_MAX_CURRENT_1 0x4C #define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0) #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) +#define SDHCI_MAX_CURRENT_VDD2_180_MASK GENMASK(7, 0) /* UHS2 */ #define SDHCI_MAX_CURRENT_MULTIPLIER 4 /* 4C-4F reserved for more max current */ #define SDHCI_SET_ACMD12_ERROR 0x50 +/* Host Version 4.10 */ +#define SDHCI_SET_ACMD_RESPONSE_ERROR 0x20 #define SDHCI_SET_INT_ERROR 0x52 +/* Host Version 4.10 */ +#define SDHCI_SET_INT_TUNING_ERROR 0x0400 +#define SDHCI_SET_INT_RESPONSE_ERROR 0x0800 #define SDHCI_ADMA_ERROR 0x54 @@ -259,10 +323,16 @@ #define SDHCI_PRESET_FOR_SDR104 0x6C #define SDHCI_PRESET_FOR_DDR50 0x6E #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ + +/* TODO: 0x74 is used for UHS2 in 4.10. How about HS400? */ +/* UHS2 */ +#define SDHCI_PRESET_FOR_UHS2 0x74 #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) #define SDHCI_PRESET_CLKGEN_SEL BIT(10) #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) +#define SDHCI_ADMA3_ADDRESS 0x78 + #define SDHCI_SLOT_INT_STATUS 0xFC #define SDHCI_HOST_VERSION 0xFE @@ -653,6 +723,25 @@ struct sdhci_ops { void (*dump_vendor_regs)(struct sdhci_host *host); }; +struct sdhci_uhs2_ops { + /* UHS-2 support */ + void (*reset)(struct sdhci_host *host, u16 mask); + void (*set_timeout)(struct sdhci_host *host); + void (*set_transfer_mode)(struct sdhci_host *host, + struct mmc_command *cmd); + void (*send_command)(struct sdhci_host *host, + struct mmc_command *cmd); + void (*finish_command)(struct sdhci_host *host); + void (*do_set_ios)(struct sdhci_host *host, struct mmc_ios *ios); + int (*do_detect_init)(struct sdhci_host *host); + int (*do_set_reg)(struct sdhci_host *host, enum uhs2_act act); + void (*irq)(struct sdhci_host *host); + int (*add_host)(struct sdhci_host *host, u32 caps1); + void (*remove_host)(struct sdhci_host *host, int dead); +}; + +extern struct sdhci_uhs2_ops sdhci_uhs2_ops; + #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) From patchwork Fri Jul 10 11:10:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235221 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp345988ilg; Fri, 10 Jul 2020 04:09:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwCU4sVjQCydNVUyoAxRYkK17v3p4ZZ+U/hnUiGEiVYqI5t3NPYv3AgyymcuuXLeJZ0Hpra X-Received: by 2002:a17:906:d78f:: with SMTP id pj15mr64109448ejb.283.1594379392633; Fri, 10 Jul 2020 04:09:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379392; cv=none; d=google.com; s=arc-20160816; b=y9+HUKjQG0BFSiAMUaJOa/1b+MlDj04Y3hFcYpW/sl9RCLFUG8qVOUZhWrZ2ivdxgY VRQfiYLK4vloN2hqsaausKROYLPdUXVqWH5uLdZiUNNSdA2LGK6TZFq4gzqV5cSkSbSj QEYAhD+ao2/qV838zm2ixyTvj6NwQTeXDCboz7o6fLL3iIJHwQFDSOeKmjEP6JDura5J SxNxuHG2KD11MKarrQtkEwBsKqyPnXeqI09ySrZbUt+w/ShChuwLehbXdIaBM9uVPdQ9 fMCvZlKjb87J3Az1NavSCgvsRRMDFjEBgQgge5BvQNKXyCX+l3oJnl9JOwNXkcnp5fOo 7jSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=PXSanc4gimjYlUQVCO8YZAntIkVCDxhB7ClBTFnZorw=; b=S3gaV8TAOsl8AkEOTm0QC11XbL04SWeH2nmnPxQXtLQj4f68mkAF7ajNdhz8fwLVao 2xb5LnFj/BHmzviG/f9Enf3d/p1+r57504m7mtUCZX+s0yCCbUuZE8+Lk2wQTnabV1Kr dEmqXUGGyFLQ3xiZ951UlOLrgRXpdyvS6hjCm+oU1Nq8Lv8gtvD/7SVErYQJTTn2rksj 5wnsfKsktReO7lFjtFq4HashtAh/OpO1oNyj6EqfoiaRH8MN3TDpGSRzf+BmpO3I3LtR q0uxapze37OMDOvBhhk8pSYntweO3JD2izUpm3k11fez5kCZKBWY8vUgoN0CK1wRNpqk bjCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=JjzbtFfd; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id b4sm5619415pfo.137.2020.07.10.04.09.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:09:50 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 10/21] mmc: sdhci: UHS-II support, dump UHS-II registers Date: Fri, 10 Jul 2020 19:10:34 +0800 Message-Id: <20200710111034.29456-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro Dump UHS-II specific registers, if available, in sdhci_dumpregs() for informative/debugging use. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) -- 2.27.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 37b1158c1c0c..c2f6923d296c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -111,6 +111,30 @@ void sdhci_dumpregs(struct sdhci_host *host) } } + if (IS_ENABLED(CONFIG_MMC_SDHCI_UHS2) && + host->mmc && host->mmc->flags & MMC_UHS2_SUPPORT) { + SDHCI_DUMP("==================== UHS2 ==================\n"); + SDHCI_DUMP("Blk Size: 0x%08x | Blk Cnt: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_BLOCK_SIZE), + sdhci_readl(host, SDHCI_UHS2_BLOCK_COUNT)); + SDHCI_DUMP("Cmd: 0x%08x | Trn mode: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_COMMAND), + sdhci_readw(host, SDHCI_UHS2_TRANS_MODE)); + SDHCI_DUMP("Int Stat: 0x%08x | Dev Sel : 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_DEV_INT_STATUS), + sdhci_readb(host, SDHCI_UHS2_DEV_SELECT)); + SDHCI_DUMP("Dev Int Code: 0x%08x\n", + sdhci_readb(host, SDHCI_UHS2_DEV_INT_CODE)); + SDHCI_DUMP("Reset: 0x%08x | Timer: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_SW_RESET), + sdhci_readw(host, SDHCI_UHS2_TIMER_CTRL)); + SDHCI_DUMP("ErrInt: 0x%08x | ErrIntEn: 0x%08x\n", + sdhci_readl(host, SDHCI_UHS2_ERR_INT_STATUS), + sdhci_readl(host, SDHCI_UHS2_ERR_INT_STATUS_EN)); + SDHCI_DUMP("ErrSigEn: 0x%08x\n", + sdhci_readl(host, SDHCI_UHS2_ERR_INT_SIG_EN)); + } + if (host->ops->dump_vendor_regs) host->ops->dump_vendor_regs(host); From patchwork Fri Jul 10 11:10:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235222 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp346135ilg; Fri, 10 Jul 2020 04:10:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwIhh8AcQh/sv0tEZAX8y70O2VA8m9pdiHYE4oCDj8pZ/MAfbSZA9tTcY1rfuZYikZtylbE X-Received: by 2002:a17:906:3c56:: with SMTP id i22mr49920839ejg.12.1594379404178; Fri, 10 Jul 2020 04:10:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379404; cv=none; d=google.com; s=arc-20160816; b=UpKZkmNWtgXdbD/GqAPfMzPJCrctrOYTVaMNEOLhMos/bqyF9cZLkTdQsyv1+65Psl YIsH4WNo3IcS9Mo4It7bDbpn/8mh0uD9fm/3igig35Jx7QJUS7JpbN7w0IxUTEmnozWt pJ1By9bDFxfDmqRm7KX6O13kbhAW+OI8G0K47rMiLugyHDhFCxuYZrVhtI5TJG2rvfcl /1uUQ6uQUUR5nyRjYblJj+AyDeQNOqKstLVY2VXn7Cl08My1FmC5Ze+9U9UHchzda9yu VxRLfQx+WSSqygIs9ZwrgRKrD3W1zdrB0BoaO7Grolv1/V3mLX9rwABQMUNVHytc+J/l rOqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=BZxklyfbFjwycZmQoHtOvFDmfd5AMpO1Q2JX3/+fCok=; b=ep8nUnNSxIX1HGCyAofHXQ3upRmywj41K0wmwqKYMtfrjWE+sElFIEOQ3CaEcxZn34 IAH91PT5DduT7YlqY8tnch95831EPbjkJAZ2Gs9l+Mx6Anv+MY7/afzt2/vxtAuG+dRf EBxipG8kVYL0/ncIGdSB7kStdlfVYSj5eKvUtJ4ATDkbSfV2vIm8TaYRVWSI/U59/f0x TBeep2+Zbukau0qXOA/M2MRFHLhTTaEHDFrv8bhpcTNb/8iv4WQxNh0J0JluUkhF0Vqx orb5nXvRaZpdWSvgjleke2GdyA7hi1aZq7qXjVuYQ69owEzlsN6IAF/IQPx3Du0IRwah 0WNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=pvyejGdj; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id x8sm5437293pfn.61.2020.07.10.04.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:10:00 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 11/21] mmc: sdhci: UHS-II support, export host operations to core Date: Fri, 10 Jul 2020 19:10:44 +0800 Message-Id: <20200710111044.29509-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro Export sdhci-specific UHS-II operations to core. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci.c | 70 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) -- 2.27.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index c2f6923d296c..aaf41954511a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2977,6 +2977,70 @@ static void sdhci_card_event(struct mmc_host *mmc) spin_unlock_irqrestore(&host->lock, flags); } +#if IS_ENABLED(CONFIG_MMC_SDHCI_UHS2) +static int sdhci_uhs2_detect_init(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + int ret; + + if (sdhci_uhs2_ops.do_detect_init) + ret = sdhci_uhs2_ops.do_detect_init(host); + else + return 0; + + return ret; +} + +static int sdhci_uhs2_set_reg(struct mmc_host *mmc, enum uhs2_act act) +{ + struct sdhci_host *host = mmc_priv(mmc); + int ret; + + if (sdhci_uhs2_ops.do_set_reg) + ret = sdhci_uhs2_ops.do_set_reg(host, act); + else + ret = 0; + + return ret; +} + +static void sdhci_uhs2_disable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); +} + +static void sdhci_uhs2_enable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + ktime_t timeout; + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 20 ms */ + timeout = ktime_add_ms(ktime_get(), 20); + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { + pr_err("%s: Internal clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } +} +#endif /* CONFIG_MMC_SDHCI_UHS2 */ + static const struct mmc_host_ops sdhci_ops = { .request = sdhci_request, .post_req = sdhci_post_req, @@ -2992,6 +3056,12 @@ static const struct mmc_host_ops sdhci_ops = { .execute_tuning = sdhci_execute_tuning, .card_event = sdhci_card_event, .card_busy = sdhci_card_busy, +#if IS_ENABLED(CONFIG_MMC_SDHCI_UHS2) + .uhs2_detect_init = sdhci_uhs2_detect_init, + .uhs2_set_reg = sdhci_uhs2_set_reg, + .uhs2_disable_clk = sdhci_uhs2_disable_clk, + .uhs2_enable_clk = sdhci_uhs2_enable_clk, +#endif /* CONFIG_MMC_SDHCI_UHS2 */ }; /*****************************************************************************\ From patchwork Fri Jul 10 11:11:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235223 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp346382ilg; Fri, 10 Jul 2020 04:10:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxIp1rTdjFnrKzd6H7ioeCnNzuJlKQWqqVeOGnEqjHpoo6FXRctSfV9dho9jLZhabFHqu7C X-Received: by 2002:aa7:cf94:: with SMTP id z20mr78854619edx.82.1594379422606; Fri, 10 Jul 2020 04:10:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379422; cv=none; d=google.com; s=arc-20160816; b=eMzezg3zKahBybaOJikfvKGC3KVqQ3SG369+Lb+ugTp42bOnuLPSYcCR9mzmUoe1zD krEdPuK2GnloJHRwJhV8dx0hC0ZX8LIy36z5xBpSCSad9HctbYizk58AIOiRolvTNGFF n3+nJahkfJYQ+zYGtWRZAWpYfYpLVypqBOND4fPHjNjjk5gr3Dg5cXtEW7WldugywtmS W+wIesbqYQTKNcQzKH+x4x2xhCtYsPnL80c2Dhn5cM8Dmc+SSShqa7i2cLrNku8UIgYv srR07kKvhqXv2mUlPQuThsait6ofZFuGRoOsV1l0JdCQ8gLZH/VJyLQZugWSE1cKcdLE 1NLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=dLfBKiqpz5EiKywgE0yB9WT/RYihQi2mbssOelfoHw0=; b=lqbPlS96hwml+lh2OcMM5s3+gB/RBRRylj/mUwS0znyMd1BvaGmzXape7alD+gxKGg rdGp5Lu3ODdVEf1462J6LijdV4gJsbg7HBuoIzKYc1A2zGrL2vR+erJMD71N4arD9+y6 5VBCYZhZAKISllkeNTj7O1lXTRwrkHyYUBH0kBEUoJADiZOEivbIUPuaA6Lt8Jf43+qJ 7dqFR/Oxb/suH/9Uuwe2QmB14OBLqx4zK/TZsu66TGAok+okghkWhT0ddj3TdYYAsjHu bc/aF8PnO8vKyiznwft/Mt5sK2n/HDbJ3ZbEZsyiByNTyc0SdJme2fMYVxzgn5skz+Kz 2j1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=vJ9Ca77b; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id q5sm5617263pfc.130.2020.07.10.04.10.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:10:20 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 13/21] mmc: sdhci: UHS-II support, skip signal_voltage_switch() Date: Fri, 10 Jul 2020 19:11:04 +0800 Message-Id: <20200710111104.29616-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro sdhci_start_signal_voltage_switch() should be called only in UHS-I mode, and not for UHS-II mode. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.27.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 5511649946b9..7f2537648a08 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2623,8 +2623,13 @@ int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, /* * Signal Voltage Switching is only applicable for Host Controllers * v3.00 and above. + * But for UHS2, the signal voltage is supplied by vdd2 which is + * already 1.8v so no voltage switch required. */ - if (host->version < SDHCI_SPEC_300) + if (host->version < SDHCI_SPEC_300 || + (IS_ENABLED(CONFIG_MMC_SDHCI_UHS2) && + host->version >= SDHCI_SPEC_400 && + host->mmc->flags & MMC_UHS2_SUPPORT)) return 0; ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); From patchwork Fri Jul 10 11:11:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235224 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp346619ilg; Fri, 10 Jul 2020 04:10:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz6muT2NwAFEva06cSpjfmiMtv5K0hO+9anlMEiQYcukM+IyTXX5RCk5pRrxemNdx3srW46 X-Received: by 2002:a05:6402:1250:: with SMTP id l16mr78332508edw.362.1594379443437; Fri, 10 Jul 2020 04:10:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379443; cv=none; d=google.com; s=arc-20160816; b=kfEG/jh/WsBSISJQIArdfrj3q9TS42wvn5/om16NVq5+VvSaN6JgKbH8m0N1eu7h6e 2xT1UiH5XDal4qbI978W2QR7gWGKqwS6FjkTsVi3cpYl0t1XsbZQ9bb0Mt8l5KWIoQFR FiZ4yWI16huBD+HErOvlO8ylL0cqHqE38zZJmBcOmrkdH1a5YsKPjBfuAde0v819LFiD wDAAQvLkAkE0u3iEeexE6z6G5unB15xz5ASkNE92lpSSkjwCmuLmUUVrvCctwxYmgcLE vpJ4jp4ytK/fPwXCd/JJssrweyJnZ3JvmdeIfbAQHjZGVRJZPbYtq6Hcq/1x3mS4zw3d 0zmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=bgoBg0vT86NrsTuwHUuY0qnUVNcClhUjdRlVz8Y7TKE=; b=aiPfxY3aHIb6GL/iPYxAJtuTonIRgcHJo7ijN62s5ABrzXCunA+B1EblfA0CkjGxlI UocaEw+6wKfeXxTbehobpYDtQUf8v7nsK3TuLUP2caFpFQUQUv2Bdaxwztx9RsbffFHo efz/7nhty+YQgdQdonaSgolgGdc+O0Ad9JDg5lvXunMhJCRGH9LT4dSTLqU4XQ/H+tZY d5zQMf/qsfp0woPi7E9UZhoiIi/4TXzi6VofCZRCEPmfRVIDB4o+FcuHqw1BDSxw5Zd8 T+VITk1bP3KXFErH68sT3LDXVlxztJNw2ieUIenEdkz/IhLCpK6TMn7hF/AtLYv07gHx ruyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=DaHGgEEG; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id v15sm5415890pgo.15.2020.07.10.04.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:10:41 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 14/21] mmc: sdhci: UHS-II support, handle vdd2 in case of power-off Date: Fri, 10 Jul 2020 19:11:21 +0800 Message-Id: <20200710111121.29671-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro Configure a regulator for VDD2 in case of power-off. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.27.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 7f2537648a08..d38d734ec83f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2333,6 +2333,11 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (!IS_ERR(mmc->supply.vmmc) && ios->power_mode == MMC_POWER_OFF) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + if (IS_ENABLED(CONFIG_MMC_SDHCI_UHS2) && + host->mmc->caps & MMC_CAP_UHS2 && + !IS_ERR(mmc->supply.vmmc2) && + ios->power_mode == MMC_POWER_OFF) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc2, 0); return; } From patchwork Fri Jul 10 11:11:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235225 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp346881ilg; Fri, 10 Jul 2020 04:11:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzaiakgSZzGjTr40EiN3rYJbr1Z4jrDtyLzi4mX8eTN51CWV10gOFjq8bfq+Dnz05SjaZxN X-Received: by 2002:a17:906:9348:: with SMTP id p8mr39163286ejw.467.1594379468497; Fri, 10 Jul 2020 04:11:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379468; cv=none; d=google.com; s=arc-20160816; b=xDJQkLpiNstk4ae3aBkKcCGvFIO/fjQ9RIBDorurymLa7KKZaqe1fERP0PQceEamu3 +wdgUZ5LEmQkNRqoomV5N1NJrNuaDbKqy79JAaPT2XfpE1Iir/55OveiIi8hNSLsMK3Y Xp/zCEYagnvh/i6DGYtxmdEHw2CeJ4o0hSSv195uP3vr/lzF9FCzED8b+/j3DJyf4tME BbVIYt3CtOpZ73eb8RmfXLOuP6l4JwGbKBgZ94CIQfa0iFxqnDzHwukOLmjyDjj6RO1o wkAG9KoqLjwYODS+4Q7Lp+c55rk10wBZPgeclQc+ccZZRKkq5VU3c/XfYqfFIoX3Vu8B 4Ddg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=g3VOa+Y0HTmbN1kJlGhfKpuHNVKRU2nXIafR93epWKM=; b=LR1B5Htc6rrPMqu8DK1AuDWpQKBGlNs2dTfDc7JGFypOtnjGe31Xy4k5ng9Quu8/k9 u/8j7xTTj9Jq/D3ksPgOEOspsQq4clUnIM8fdSjNMkZEc+dYrhPrkPbbL9YfXWLQ8kHV brPlrqKLDO0D/ovl9pVLDf2MVkvP8Y9Ir2rllrNeM3cDjEQU461Eh0RIp7lPXprblXMJ 3uyuFnhprvVId4AhZR5/n5UFeBweRZaZVGWiY4NiOQQgBixEHYexwcMa7V3LoG+1QTuU AmQl7HHq2aTdHR/n1r9eQrTpxAC+0iaAqtpCeMC5hGceZX8u71MRdwoAYZu+ljKODKPT QRiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=m608z0q3; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id h6sm5825010pfo.123.2020.07.10.04.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:11:06 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 15/21] mmc: sdhci: UHS-II support, modify set_power() to handle vdd2 Date: Fri, 10 Jul 2020 19:11:40 +0800 Message-Id: <20200710111140.29725-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro VDD2 is used for powering UHS-II interface. Modify sdhci_set_power_and_bus_voltage(), sdhci_set_power_noreg() and sdhci_set_power_noreg() to handle VDD2. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci-omap.c | 2 +- drivers/mmc/host/sdhci-pci-core.c | 4 +-- drivers/mmc/host/sdhci-pxav3.c | 4 +-- drivers/mmc/host/sdhci-xenon.c | 4 +-- drivers/mmc/host/sdhci.c | 42 ++++++++++++++++++++++++------- drivers/mmc/host/sdhci.h | 9 +++---- 6 files changed, 43 insertions(+), 22 deletions(-) -- 2.27.0 diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index 1ec74c2d5c17..1926585debe5 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -678,7 +678,7 @@ static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock) } static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode, - unsigned short vdd) + unsigned short vdd, unsigned short vdd2) { struct mmc_host *mmc = host->mmc; diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index bb6802448b2f..40f5a24a8982 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -629,12 +629,12 @@ static int bxt_get_cd(struct mmc_host *mmc) #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, - unsigned short vdd) + unsigned short vdd, unsigned short vdd2) { int cntr; u8 reg; - sdhci_set_power(host, mode, vdd); + sdhci_set_power(host, mode, vdd, -1); if (mode == MMC_POWER_OFF) return; diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index e55037ceda73..457e9425339a 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -298,12 +298,12 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) } static void pxav3_set_power(struct sdhci_host *host, unsigned char mode, - unsigned short vdd) + unsigned short vdd, unsigned short vdd2) { struct mmc_host *mmc = host->mmc; u8 pwr = host->pwr; - sdhci_set_power_noreg(host, mode, vdd); + sdhci_set_power_noreg(host, mode, vdd, -1); if (host->pwr == pwr) return; diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c index 4703cd540c7f..2b0ebb91895a 100644 --- a/drivers/mmc/host/sdhci-xenon.c +++ b/drivers/mmc/host/sdhci-xenon.c @@ -214,12 +214,12 @@ static void xenon_set_uhs_signaling(struct sdhci_host *host, } static void xenon_set_power(struct sdhci_host *host, unsigned char mode, - unsigned short vdd) + unsigned short vdd, unsigned short vdd2) { struct mmc_host *mmc = host->mmc; u8 pwr = host->pwr; - sdhci_set_power_noreg(host, mode, vdd); + sdhci_set_power_noreg(host, mode, vdd, -1); if (host->pwr == pwr) return; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index d38d734ec83f..ca3d4a506e01 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2089,12 +2089,15 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) EXPORT_SYMBOL_GPL(sdhci_set_clock); static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, - unsigned short vdd) + unsigned short vdd, unsigned short vdd2) { struct mmc_host *mmc = host->mmc; mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + if (mmc->caps & MMC_CAP_UHS2 && !IS_ERR(mmc->supply.vmmc2)) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc2, vdd2); + if (mode != MMC_POWER_OFF) sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); else @@ -2102,7 +2105,7 @@ static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, } void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, - unsigned short vdd) + unsigned short vdd, unsigned short vdd2) { u8 pwr = 0; @@ -2133,6 +2136,20 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, } } + if (mode != MMC_POWER_OFF) { + if (vdd2 != (unsigned short)-1) { + switch (1 << vdd2) { + case MMC_VDD2_165_195: + pwr |= SDHCI_VDD2_POWER_180; + break; + default: + WARN(1, "%s: Invalid vdd2 %#x\n", + mmc_hostname(host->mmc), vdd2); + break; + } + } + } + if (host->pwr == pwr) return; @@ -2159,7 +2176,13 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); pwr |= SDHCI_POWER_ON; + if (vdd2 != (unsigned short)-1) + pwr |= SDHCI_VDD2_POWER_ON; + + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); + mdelay(5); sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + mdelay(5); if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) sdhci_runtime_pm_bus_on(host); @@ -2175,12 +2198,12 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, EXPORT_SYMBOL_GPL(sdhci_set_power_noreg); void sdhci_set_power(struct sdhci_host *host, unsigned char mode, - unsigned short vdd) + unsigned short vdd, unsigned short vdd2) { if (IS_ERR(host->mmc->supply.vmmc)) - sdhci_set_power_noreg(host, mode, vdd); + sdhci_set_power_noreg(host, mode, vdd, vdd2); else - sdhci_set_power_reg(host, mode, vdd); + sdhci_set_power_reg(host, mode, vdd, vdd2); } EXPORT_SYMBOL_GPL(sdhci_set_power); @@ -2192,14 +2215,15 @@ EXPORT_SYMBOL_GPL(sdhci_set_power); */ void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, unsigned char mode, - unsigned short vdd) + unsigned short vdd, + unsigned short vdd2) { if (!IS_ERR(host->mmc->supply.vmmc)) { struct mmc_host *mmc = host->mmc; mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); } - sdhci_set_power_noreg(host, mode, vdd); + sdhci_set_power_noreg(host, mode, vdd, -1); } EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage); @@ -2377,9 +2401,9 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) } if (host->ops->set_power) - host->ops->set_power(host, ios->power_mode, ios->vdd); + host->ops->set_power(host, ios->power_mode, ios->vdd, -1); else - sdhci_set_power(host, ios->power_mode, ios->vdd); + sdhci_set_power(host, ios->power_mode, ios->vdd, -1); /* 4.0 host support */ if (host->version >= SDHCI_SPEC_400) { diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index ecf55394ea46..f6732f33f29f 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -689,7 +689,7 @@ struct sdhci_ops { void (*set_clock)(struct sdhci_host *host, unsigned int clock); void (*set_power)(struct sdhci_host *host, unsigned char mode, - unsigned short vdd); + unsigned short vdd, unsigned short vdd2); u32 (*irq)(struct sdhci_host *host, u32 intmask); @@ -852,13 +852,10 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock); void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); void sdhci_enable_clk(struct sdhci_host *host, u16 clk); -void sdhci_set_power(struct sdhci_host *host, unsigned char mode, - unsigned short vdd); void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, unsigned char mode, - unsigned short vdd); -void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, - unsigned short vdd); + unsigned short vdd, + unsigned short vdd2); void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); void sdhci_set_bus_width(struct sdhci_host *host, int width); From patchwork Fri Jul 10 11:12:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235226 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp347148ilg; Fri, 10 Jul 2020 04:11:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsBxfSxF5KnjlaIqF8o0mewawdUAzTZekFm8Y2WBPcQ9QzTJiLOUQqtdkBgHmz7M7IoZSJ X-Received: by 2002:a17:906:cc0e:: with SMTP id ml14mr59156503ejb.432.1594379493541; Fri, 10 Jul 2020 04:11:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379493; cv=none; d=google.com; s=arc-20160816; b=KArOuhElJ9RYg6OPLRnby/T6y+tW1yJSbrfaW284sU+s5ddH8CxH3gjXx8O9XgFKQQ O4tj7sD8IkSfdLg9L4pi3vlfQ266Dmv7esFEvB29Z06SYFGaOAUygvTq2MZO4lQ7sxCt mNNJLfQspp50VWjzqK1uBTiAAKSlbDsF++PsmXw9rZdaFbQ+XHums0N5bZSgYmSTUNFJ NvSZsLNDokUtKiVusjL4de1SOQJ9rh5AXsjsDQZwxJeAJvSkvGyV9SDboS+Gpfafoc4a r32/cRYm2L+YsMPLMFscxOmgNGVJq/8qscIVfwtK1x21BAWOr4P7BpDPzRdoy6vBS0EB DUMQ== ARC-Message-Signature: i=1; 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id i63sm5602434pfc.22.2020.07.10.04.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:11:31 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 16/21] mmc: sdhci: UHS-II support, export helper functions to a module Date: Fri, 10 Jul 2020 19:12:15 +0800 Message-Id: <20200710111215.29779-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro Those exported functions will be utilized in the following commit to implement UHS-II support as a kernel module. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci.c | 14 ++++++++------ drivers/mmc/host/sdhci.h | 10 ++++++++++ 2 files changed, 18 insertions(+), 6 deletions(-) -- 2.27.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ca3d4a506e01..5d84e61f6ad9 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -57,8 +57,6 @@ EXPORT_SYMBOL_GPL(sdhci_uhs2_ops); static unsigned int debug_quirks = 0; static unsigned int debug_quirks2; -static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); - static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); void sdhci_dumpregs(struct sdhci_host *host) @@ -225,13 +223,14 @@ static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) pm_runtime_get_noresume(host->mmc->parent); } -static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) +void sdhci_runtime_pm_bus_off(struct sdhci_host *host) { if (!host->bus_on) return; host->bus_on = false; pm_runtime_put_noidle(host->mmc->parent); } +EXPORT_SYMBOL_GPL(sdhci_runtime_pm_bus_off); void sdhci_reset(struct sdhci_host *host, u8 mask) { @@ -1560,12 +1559,13 @@ static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) sdhci_led_deactivate(host); } -static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) +void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) { __sdhci_finish_mrq(host, mrq); queue_work(host->complete_wq, &host->complete_work); } +EXPORT_SYMBOL_GPL(sdhci_finish_mrq); static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout) { @@ -1644,10 +1644,11 @@ static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout) } } -static void sdhci_finish_data(struct sdhci_host *host) +void sdhci_finish_data(struct sdhci_host *host) { __sdhci_finish_data(host, false); } +EXPORT_SYMBOL_GPL(sdhci_finish_data); static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) { @@ -2991,7 +2992,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) } EXPORT_SYMBOL_GPL(sdhci_execute_tuning); -static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) +void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) { /* Host Controller v3.00 defines preset value registers */ if (host->version < SDHCI_SPEC_300) @@ -3019,6 +3020,7 @@ static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) host->preset_enabled = enable; } } +EXPORT_SYMBOL_GPL(sdhci_enable_preset_value); static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int err) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f6732f33f29f..927aaba28932 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -893,4 +893,14 @@ void sdhci_switch_external_dma(struct sdhci_host *host, bool en); void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable); void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); +/* sdhci_uhs2.c needed */ +void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); +void sdhci_finish_data(struct sdhci_host *host); +void sdhci_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd, unsigned short vdd2); +void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, + unsigned short vdd, unsigned short vdd2); +void sdhci_runtime_pm_bus_off(struct sdhci_host *host); +void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); + #endif /* __SDHCI_HW_H */ From patchwork Fri Jul 10 11:12:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235227 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp347280ilg; Fri, 10 Jul 2020 04:11:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8uAJt/qo22/C77IJdlxDlgEPNYsDi9lj1CTHLb17rXN1k/Tl1kuRFRoSS88Te+ozyVBRW X-Received: by 2002:a17:906:40d7:: with SMTP id a23mr58524324ejk.421.1594379506013; Fri, 10 Jul 2020 04:11:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id u8sm5336222pjn.24.2020.07.10.04.11.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:11:42 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 17/21] mmc: sdhci: UHS-II support, implement operations as a module Date: Fri, 10 Jul 2020 19:12:26 +0800 Message-Id: <20200710111226.29831-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro All the UHS-II operations in struct sdhci_uhs2_ops are implemented here and exported as a kernel module. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-uhs2.c | 794 ++++++++++++++++++++++++++++++++++ 2 files changed, 795 insertions(+) create mode 100644 drivers/mmc/host/sdhci-uhs2.c -- 2.27.0 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 4d5bcb0144a0..e51430d8f85d 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_MMC_PXA) += pxamci.o obj-$(CONFIG_MMC_MXC) += mxcmmc.o obj-$(CONFIG_MMC_MXS) += mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o +obj-$(CONFIG_MMC_SDHCI_UHS2) += sdhci-uhs2.o obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \ sdhci-pci-dwc-mshc.o sdhci-pci-gli.o diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c new file mode 100644 index 000000000000..3cb13071dd9d --- /dev/null +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -0,0 +1,794 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * linux/drivers/mmc/host/sdhci_uhs2.c - Secure Digital Host Controller + * Interface driver + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + * Copyright (C) 2020 Genesys Logic, Inc. + * Authors: Ben Chuang + * Copyright (C) 2020 Linaro Limited + * Author: AKASHI Takahiro + */ + +#include +#include +#include + +#include + +#include "sdhci.h" +#include "sdhci-uhs2.h" + +#define DRIVER_NAME "sdhci_uhs2" +#define DBG(f, x...) \ + pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) + +static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) +{ + u32 ier; + + ier = sdhci_readl(host, SDHCI_INT_ENABLE); + ier &= ~clear; + ier |= set; + sdhci_writel(host, ier, SDHCI_INT_ENABLE); + sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); +} + +/** + * sdhci_uhs2_clear_set_irqs - set Error Interrupt Status Enable register + * @host: SDHCI host + * @clear: bit-wise clear mask + * @set: bit-wise set mask + * + * Set/unset bits in UHS-II Error Interrupt Status Enable register + */ +void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) +{ + u32 ier; + + ier = sdhci_readl(host, SDHCI_UHS2_ERR_INT_STATUS_EN); + ier &= ~clear; + ier |= set; + sdhci_writel(host, ier, SDHCI_UHS2_ERR_INT_STATUS_EN); + sdhci_writel(host, ier, SDHCI_UHS2_ERR_INT_SIG_EN); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_clear_set_irqs); + +/** + * sdhci_uhs2_reset - invoke SW reset + * @host: SDHCI host + * @mask: Control mask + * + * Invoke SW reset, depending on a bit in @mask and wait for completion. + */ +void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask) +{ + unsigned long timeout; + + if (!(host->mmc->caps & MMC_CAP_UHS2)) + return; + + sdhci_writew(host, mask, SDHCI_UHS2_SW_RESET); + + if (mask & SDHCI_UHS2_SW_RESET_FULL) { + host->clock = 0; + /* Reset-all turns off SD Bus Power */ + if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) + sdhci_runtime_pm_bus_off(host); + } + + /* Wait max 100 ms */ + timeout = 10000; + + /* hw clears the bit when it's done */ + while (sdhci_readw(host, SDHCI_UHS2_SW_RESET) & mask) { + if (timeout == 0) { + pr_err("%s: %s: Reset 0x%x never completed.\n", + __func__, mmc_hostname(host->mmc), (int)mask); + pr_err("%s: clean reset bit\n", + mmc_hostname(host->mmc)); + sdhci_writeb(host, 0, SDHCI_UHS2_SW_RESET); + return; + } + timeout--; + udelay(10); + } +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_reset); + +static u8 sdhci_calc_timeout_uhs2(struct sdhci_host *host, u8 *cmd_res, + u8 *dead_lock) +{ + u8 count; + unsigned int cmd_res_timeout, dead_lock_timeout, current_timeout; + + /* + * If the host controller provides us with an incorrect timeout + * value, just skip the check and use 0xE. The hardware may take + * longer to time out, but that's much better than having a too-short + * timeout value. + */ + if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { + *cmd_res = 0xE; + *dead_lock = 0xE; + return 0xE; + } + + /* timeout in us */ + cmd_res_timeout = 5 * 1000; + dead_lock_timeout = 1 * 1000 * 1000; + + /* + * Figure out needed cycles. + * We do this in steps in order to fit inside a 32 bit int. + * The first step is the minimum timeout, which will have a + * minimum resolution of 6 bits: + * (1) 2^13*1000 > 2^22, + * (2) host->timeout_clk < 2^16 + * => + * (1) / (2) > 2^6 + */ + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < cmd_res_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + if (count >= 0xF) { + DBG("%s: Too large timeout 0x%x requested for CMD_RES!\n", + mmc_hostname(host->mmc), count); + count = 0xE; + } + *cmd_res = count; + + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < dead_lock_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + if (count >= 0xF) { + DBG("%s: Too large timeout 0x%x requested for DEADLOCK!\n", + mmc_hostname(host->mmc), count); + count = 0xE; + } + *dead_lock = count; + + return count; +} + +static void sdhci_uhs2_set_timeout(struct sdhci_host *host) +{ + u8 cmd_res, dead_lock; + + sdhci_calc_timeout_uhs2(host, &cmd_res, &dead_lock); + cmd_res |= dead_lock << SDHCI_UHS2_TIMER_CTRL_DEADLOCK_SHIFT; + sdhci_writeb(host, cmd_res, SDHCI_UHS2_TIMER_CTRL); +} + +static void sdhci_uhs2_set_transfer_mode(struct sdhci_host *host, + struct mmc_command *cmd) +{ + u16 mode; + struct mmc_data *data = cmd->data; + u16 arg; + + if (!data) { + /* clear Auto CMD settings for no data CMDs */ + arg = cmd->uhs2_cmd->arg; + if ((((arg & 0xF) << 8) | ((arg >> 8) & 0xFF)) == + UHS2_DEV_CMD_TRANS_ABORT) { + mode = 0; + } else { + mode = sdhci_readw(host, SDHCI_UHS2_TRANS_MODE); + if (cmd->opcode == MMC_STOP_TRANSMISSION || + cmd->opcode == MMC_ERASE) + mode |= SDHCI_UHS2_TRNS_WAIT_EBSY; + else + /* send status mode */ + if (cmd->opcode == MMC_SEND_STATUS) + mode = 0; + } + + if (IS_ENABLED(CONFIG_MMC_DEBUG)) + DBG("UHS2 no data trans mode is 0x%x.\n", mode); + + sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); + return; + } + + WARN_ON(!host->data); + + mode = SDHCI_UHS2_TRNS_BLK_CNT_EN | SDHCI_UHS2_TRNS_WAIT_EBSY; + if (data->flags & MMC_DATA_WRITE) + mode |= SDHCI_UHS2_TRNS_DATA_TRNS_WRT; + + if (data->blocks == 1 && + data->blksz != 512 && + cmd->opcode != MMC_READ_SINGLE_BLOCK && + cmd->opcode != MMC_WRITE_BLOCK) { + mode &= ~SDHCI_UHS2_TRNS_BLK_CNT_EN; + mode |= SDHCI_UHS2_TRNS_BLK_BYTE_MODE; + } + + if (host->flags & SDHCI_REQ_USE_DMA) + mode |= SDHCI_UHS2_TRNS_DMA; + + if ((host->mmc->flags & MMC_UHS2_2L_HD) && !cmd->uhs2_tmode0_flag) + mode |= SDHCI_UHS2_TRNS_2L_HD; + + sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); + + if (IS_ENABLED(CONFIG_MMC_DEBUG)) + DBG("UHS2 trans mode is 0x%x.\n", mode); +} + +static void sdhci_uhs2_send_command(struct sdhci_host *host, + struct mmc_command *cmd) +{ + int i, j; + int cmd_reg; + + if (host->mmc->flags & MMC_UHS2_INITIALIZED) { + if (!cmd->uhs2_cmd) { + pr_err("%s: fatal error, no uhs2_cmd!\n", + mmc_hostname(host->mmc)); + return; + } + } + + i = 0; + sdhci_writel(host, + ((u32)cmd->uhs2_cmd->arg << 16) | + (u32)cmd->uhs2_cmd->header, + SDHCI_UHS2_CMD_PACKET + i); + i += 4; + + /* + * Per spec, playload (config) should be MSB before sending out. + * But we don't need convert here because had set payload as + * MSB when preparing config read/write commands. + */ + for (j = 0; j < cmd->uhs2_cmd->payload_len / sizeof(u32); j++) { + sdhci_writel(host, *(cmd->uhs2_cmd->payload + j), + SDHCI_UHS2_CMD_PACKET + i); + i += 4; + } + + for ( ; i < SDHCI_UHS2_CMD_PACK_MAX_LEN; i += 4) + sdhci_writel(host, 0, SDHCI_UHS2_CMD_PACKET + i); + + if (IS_ENABLED(CONFIG_MMC_DEBUG)) { + DBG("UHS2 CMD packet_len = %d.\n", cmd->uhs2_cmd->packet_len); + for (i = 0; i < cmd->uhs2_cmd->packet_len; i++) + DBG("UHS2 CMD_PACKET[%d] = 0x%x.\n", i, + sdhci_readb(host, SDHCI_UHS2_CMD_PACKET + i)); + } + + cmd_reg = cmd->uhs2_cmd->packet_len << + SDHCI_UHS2_COMMAND_PACK_LEN_SHIFT; + if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) + cmd_reg |= SDHCI_UHS2_COMMAND_DATA; + if (cmd->opcode == MMC_STOP_TRANSMISSION) + cmd_reg |= SDHCI_UHS2_COMMAND_CMD12; + + /* UHS2 Native ABORT */ + if ((cmd->uhs2_cmd->header & UHS2_NATIVE_PACKET) && + ((((cmd->uhs2_cmd->arg & 0xF) << 8) | + ((cmd->uhs2_cmd->arg >> 8) & 0xFF)) == UHS2_DEV_CMD_TRANS_ABORT)) + cmd_reg |= SDHCI_UHS2_COMMAND_TRNS_ABORT; + + /* UHS2 Native DORMANT */ + if ((cmd->uhs2_cmd->header & UHS2_NATIVE_PACKET) && + ((((cmd->uhs2_cmd->arg & 0xF) << 8) | + ((cmd->uhs2_cmd->arg >> 8) & 0xFF)) == + UHS2_DEV_CMD_GO_DORMANT_STATE)) + cmd_reg |= SDHCI_UHS2_COMMAND_DORMANT; + + DBG("0x%x is set to UHS2 CMD register.\n", cmd_reg); + + sdhci_writew(host, cmd_reg, SDHCI_UHS2_COMMAND); +} + +static void sdhci_uhs2_finish_command(struct sdhci_host *host) +{ + int i; + bool b_read_a0 = 0; + + if (host->mmc->flags & MMC_UHS2_INITIALIZED) { + u8 resp; + u8 ecode; + + resp = sdhci_readb(host, SDHCI_UHS2_RESPONSE + 2); + if (resp & UHS2_RES_NACK_MASK) { + ecode = (resp >> UHS2_RES_ECODE_POS) & + UHS2_RES_ECODE_MASK; + pr_err("%s: NACK is got, ECODE=0x%x.\n", + mmc_hostname(host->mmc), ecode); + } + b_read_a0 = 1; + } + + if (host->cmd->uhs2_resp && + host->cmd->uhs2_resp_len && + host->cmd->uhs2_resp_len <= 20) { + /* Get whole response of some native CCMD, like + * DEVICE_INIT, ENUMERATE. + */ + for (i = 0; i < host->cmd->uhs2_resp_len; i++) + host->cmd->uhs2_resp[i] = + sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i); + } else { + /* Get SD CMD response and Payload for some read + * CCMD, like INQUIRY_CFG. + */ + /* Per spec (p136), payload field is divided into + * a unit of DWORD and transmission order within + * a DWORD is big endian. + */ + if (!b_read_a0) + sdhci_readl(host, SDHCI_UHS2_RESPONSE); + for (i = 4; i < 20; i += 4) { + host->cmd->resp[i / 4 - 1] = + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i) << 24) | + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i + 1) + << 16) | + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i + 2) + << 8) | + sdhci_readb(host, SDHCI_UHS2_RESPONSE + i + 3); + } + } +} + +static void sdhci_uhs2_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) +{ + u8 cmd_res, dead_lock; + u16 ctrl_2; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + + /* UHS2 Timeout Control */ + sdhci_calc_timeout_uhs2(host, &cmd_res, &dead_lock); + + /* change to use calculate value */ + cmd_res |= dead_lock << SDHCI_UHS2_TIMER_CTRL_DEADLOCK_SHIFT; + + sdhci_uhs2_clear_set_irqs(host, + SDHCI_UHS2_ERR_INT_STATUS_RES_TIMEOUT | + SDHCI_UHS2_ERR_INT_STATUS_DEADLOCK_TIMEOUT, + 0); + sdhci_writeb(host, cmd_res, SDHCI_UHS2_TIMER_CTRL); + sdhci_uhs2_clear_set_irqs(host, 0, + SDHCI_UHS2_ERR_INT_STATUS_RES_TIMEOUT | + SDHCI_UHS2_ERR_INT_STATUS_DEADLOCK_TIMEOUT); + + /* UHS2 timing */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (ios->timing == MMC_TIMING_UHS2) + ctrl_2 |= SDHCI_CTRL_UHS_2 | SDHCI_CTRL_UHS2_INTERFACE_EN; + else + ctrl_2 &= ~(SDHCI_CTRL_UHS_2 | SDHCI_CTRL_UHS2_INTERFACE_EN); + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + + if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) + sdhci_enable_preset_value(host, true); + + /* Set VDD2 */ + ios->vdd = fls(host->mmc->ocr_avail) - 1; + ios->vdd2 = fls(host->mmc->ocr_avail_uhs2) - 1; + + sdhci_set_power(host, ios->power_mode, ios->vdd, ios->vdd2); + udelay(100); + + host->timing = ios->timing; + sdhci_set_clock(host, host->clock); + + spin_unlock_irqrestore(&host->lock, flags); +} + +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) +{ + int timeout = 100; + + udelay(200); /* wait for 200us before check */ + + while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & + SDHCI_UHS2_IF_DETECT)) { + if (timeout == 0) { + pr_warn("%s: not detect UHS2 interface in 200us.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + timeout--; + mdelay(1); + } + + /* Enable UHS2 error interrupts */ + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, + SDHCI_UHS2_ERR_INT_STATUS_MASK); + + timeout = 150; + while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & + SDHCI_UHS2_LANE_SYNC)) { + if (timeout == 0) { + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + timeout--; + mdelay(1); + } + + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", + mmc_hostname(host->mmc)); + return 0; +} + +static int sdhci_uhs2_init(struct sdhci_host *host) +{ + u16 caps_ptr = 0; + u32 caps_gen = 0; + u32 caps_phy = 0; + u32 caps_tran[2] = {0, 0}; + struct mmc_host *mmc = host->mmc; + + /* + * TODO: may add corresponding members in sdhci_host to + * keep these caps. + */ + caps_ptr = sdhci_readw(host, SDHCI_UHS2_HOST_CAPS_PTR); + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { + pr_err("%s: SDHCI_UHS2_HOST_CAPS_PTR(%d) is wrong.\n", + mmc_hostname(mmc), caps_ptr); + return -ENODEV; + } + caps_gen = sdhci_readl(host, + caps_ptr + SDHCI_UHS2_HOST_CAPS_GEN_OFFSET); + caps_phy = sdhci_readl(host, + caps_ptr + SDHCI_UHS2_HOST_CAPS_PHY_OFFSET); + caps_tran[0] = sdhci_readl(host, + caps_ptr + SDHCI_UHS2_HOST_CAPS_TRAN_OFFSET); + caps_tran[1] = sdhci_readl(host, + caps_ptr + + SDHCI_UHS2_HOST_CAPS_TRAN_1_OFFSET); + + /* General Caps */ + mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_DAP_MASK; + mmc->uhs2_caps.gap = (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_GAP_MASK) >> + SDHCI_UHS2_HOST_CAPS_GEN_GAP_SHIFT; + mmc->uhs2_caps.n_lanes = (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_LANE_MASK) + >> SDHCI_UHS2_HOST_CAPS_GEN_LANE_SHIFT; + mmc->uhs2_caps.addr64 = + (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_ADDR_64) ? 1 : 0; + mmc->uhs2_caps.card_type = + (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_MASK) >> + SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_SHIFT; + + /* PHY Caps */ + mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_REV_MASK; + mmc->uhs2_caps.speed_range = + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_RANGE_MASK) + >> SDHCI_UHS2_HOST_CAPS_PHY_RANGE_SHIFT; + mmc->uhs2_caps.n_lss_sync = + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_MASK) + >> SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_SHIFT; + mmc->uhs2_caps.n_lss_dir = + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_MASK) + >> SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_SHIFT; + if (mmc->uhs2_caps.n_lss_sync == 0) + mmc->uhs2_caps.n_lss_sync = 16 << 2; + else + mmc->uhs2_caps.n_lss_sync <<= 2; + if (mmc->uhs2_caps.n_lss_dir == 0) + mmc->uhs2_caps.n_lss_dir = 16 << 3; + else + mmc->uhs2_caps.n_lss_dir <<= 3; + + /* LINK/TRAN Caps */ + mmc->uhs2_caps.link_rev = + caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_LINK_REV_MASK; + mmc->uhs2_caps.n_fcu = + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_MASK) + >> SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_SHIFT; + if (mmc->uhs2_caps.n_fcu == 0) + mmc->uhs2_caps.n_fcu = 256; + mmc->uhs2_caps.host_type = + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_MASK) + >> SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_SHIFT; + mmc->uhs2_caps.maxblk_len = + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_MASK) + >> SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_SHIFT; + mmc->uhs2_caps.n_data_gap = + caps_tran[1] & SDHCI_UHS2_HOST_CAPS_TRAN_1_N_DATA_GAP_MASK; + + return 0; +} + +static int sdhci_uhs2_do_detect_init(struct sdhci_host *host) +{ + unsigned long flags; + int ret = -EIO; + + DBG("%s: begin UHS2 init.\n", __func__); + spin_lock_irqsave(&host->lock, flags); + + if (sdhci_uhs2_interface_detect(host)) { + pr_warn("%s: cannot detect UHS2 interface.\n", + mmc_hostname(host->mmc)); + goto out; + } + + if (sdhci_uhs2_init(host)) { + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); + goto out; + } + + /* Init complete, do soft reset and enable UHS2 error irqs. */ + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, + SDHCI_UHS2_ERR_INT_STATUS_MASK); + /* + * !!! SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared + * by SDHCI_UHS2_SW_RESET_SD + */ + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + + ret = 0; +out: + spin_unlock_irqrestore(&host->lock, flags); + return ret; +} + +static void sdhci_uhs2_set_config(struct sdhci_host *host) +{ + u32 value; + u16 sdhci_uhs2_set_ptr = sdhci_readw(host, SDHCI_UHS2_SET_PTR); + u16 sdhci_uhs2_gen_set_reg = (sdhci_uhs2_set_ptr + 0); + u16 sdhci_uhs2_phy_set_reg = (sdhci_uhs2_set_ptr + 4); + u16 sdhci_uhs2_tran_set_reg = (sdhci_uhs2_set_ptr + 8); + u16 sdhci_uhs2_tran_set_1_reg = (sdhci_uhs2_set_ptr + 12); + + /* Set Gen Settings */ + sdhci_writel(host, host->mmc->uhs2_caps.n_lanes_set << + SDHCI_UHS2_GEN_SET_N_LANES_POS, sdhci_uhs2_gen_set_reg); + + /* Set PHY Settings */ + value = (host->mmc->uhs2_caps.n_lss_dir_set << + SDHCI_UHS2_PHY_SET_N_LSS_DIR_POS) | + (host->mmc->uhs2_caps.n_lss_sync_set << + SDHCI_UHS2_PHY_SET_N_LSS_SYN_POS); + if (host->mmc->flags & MMC_UHS2_SPEED_B) + value |= 1 << SDHCI_UHS2_PHY_SET_SPEED_POS; + sdhci_writel(host, value, sdhci_uhs2_phy_set_reg); + + /* Set LINK-TRAN Settings */ + value = (host->mmc->uhs2_caps.max_retry_set << + SDHCI_UHS2_TRAN_SET_RETRY_CNT_POS) | + (host->mmc->uhs2_caps.n_fcu_set << + SDHCI_UHS2_TRAN_SET_N_FCU_POS); + sdhci_writel(host, value, sdhci_uhs2_tran_set_reg); + sdhci_writel(host, host->mmc->uhs2_caps.n_data_gap_set, + sdhci_uhs2_tran_set_1_reg); +} + +static int sdhci_uhs2_check_dormant(struct sdhci_host *host) +{ + int timeout = 100; + + while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & + SDHCI_UHS2_IN_DORMANT_STATE)) { + if (timeout == 0) { + pr_warn("%s: UHS2 IN_DORMANT fail in 100ms.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + timeout--; + mdelay(1); + } + return 0; +} + +static int sdhci_uhs2_do_set_reg(struct sdhci_host *host, enum uhs2_act act) +{ + unsigned long flags; + int err = 0; + u16 sdhci_uhs2_set_ptr = sdhci_readw(host, SDHCI_UHS2_SET_PTR); + u16 sdhci_uhs2_phy_set_reg = (sdhci_uhs2_set_ptr + 4); + + DBG("Begin sdhci_uhs2_set_reg, act %d.\n", act); + spin_lock_irqsave(&host->lock, flags); + + switch (act) { + case SET_CONFIG: + sdhci_uhs2_set_config(host); + break; + case ENABLE_INT: + sdhci_clear_set_irqs(host, 0, SDHCI_INT_CARD_INT); + break; + case DISABLE_INT: + sdhci_clear_set_irqs(host, SDHCI_INT_CARD_INT, 0); + break; + case SET_SPEED_B: + sdhci_writeb(host, 1 << SDHCI_UHS2_PHY_SET_SPEED_POS, + sdhci_uhs2_phy_set_reg); + break; + case CHECK_DORMANT: + err = sdhci_uhs2_check_dormant(host); + break; + default: + pr_err("%s: input action %d is wrong!\n", + mmc_hostname(host->mmc), act); + err = -EIO; + break; + } + + spin_unlock_irqrestore(&host->lock, flags); + return err; +} + +static void sdhci_uhs2_irq(struct sdhci_host *host) +{ + u32 uhs2mask; + struct mmc_command *cmd = host->cmd; + + uhs2mask = sdhci_readl(host, SDHCI_UHS2_ERR_INT_STATUS); + DBG("*** %s got UHS2 interrupt: 0x%08x\n", + mmc_hostname(host->mmc), uhs2mask); + + sdhci_writel(host, uhs2mask & SDHCI_UHS2_ERR_INT_STATUS_MASK, + SDHCI_UHS2_ERR_INT_STATUS); + + if (!(uhs2mask & SDHCI_UHS2_ERR_INT_STATUS_MASK)) + return; + + if (uhs2mask & SDHCI_UHS2_ERR_INT_STATUS_CMD_MASK) { + if (!host->cmd) { + pr_err("%s: Got cmd interrupt 0x%08x but no cmd.\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + sdhci_dumpregs(host); + return; + } + host->cmd->error = -EILSEQ; + if (uhs2mask & SDHCI_UHS2_ERR_INT_STATUS_RES_TIMEOUT) + host->cmd->error = -ETIMEDOUT; + } + + if (uhs2mask & SDHCI_UHS2_ERR_INT_STATUS_DATA_MASK) { + if (!host->data) { + pr_err("%s: Got data interrupt 0x%08x but no data.\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + sdhci_dumpregs(host); + return; + } + + if (uhs2mask & SDHCI_UHS2_ERR_INT_STATUS_DEADLOCK_TIMEOUT) { + pr_err("%s: Got deadlock timeout interrupt 0x%08x\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + host->data->error = -ETIMEDOUT; + } else if (uhs2mask & SDHCI_UHS2_ERR_INT_STATUS_ADMA) { + pr_err("%s: ADMA error = 0x %x\n", + mmc_hostname(host->mmc), + sdhci_readb(host, SDHCI_ADMA_ERROR)); + host->data->error = -EIO; + } else { + host->data->error = -EILSEQ; + } + } + + if (host->data && host->data->error) + sdhci_finish_data(host); + else + sdhci_finish_mrq(host, cmd->mrq); +} + +static int sdhci_uhs2_add_host(struct sdhci_host *host, u32 caps1) +{ + struct mmc_host *mmc; + u32 max_current_caps2; + + if (host->version < SDHCI_SPEC_400) + return 0; + + mmc = host->mmc; + + /* Support UHS2 */ + if (caps1 & SDHCI_SUPPORT_UHS2) { + mmc->caps |= MMC_CAP_UHS2; + mmc->flags |= MMC_UHS2_SUPPORT; + } + + max_current_caps2 = sdhci_readl(host, SDHCI_MAX_CURRENT_1); + + if ((caps1 & SDHCI_SUPPORT_VDD2_180) && + !max_current_caps2 && + !IS_ERR(mmc->supply.vmmc2)) { + /* UHS2 - VDD2 */ + int curr = regulator_get_current_limit(mmc->supply.vmmc2); + + if (curr > 0) { + /* convert to SDHCI_MAX_CURRENT format */ + curr = curr / 1000; /* convert to mA */ + curr = curr / SDHCI_MAX_CURRENT_MULTIPLIER; + curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); + max_current_caps2 = curr; + } + } + + if (caps1 & SDHCI_SUPPORT_VDD2_180) { + mmc->ocr_avail_uhs2 |= MMC_VDD2_165_195; + /* + * UHS2 doesn't require this. Only UHS-I bus needs to set + * max current. + */ + mmc->max_current_180_vdd2 = (max_current_caps2 & + SDHCI_MAX_CURRENT_VDD2_180_MASK) * + SDHCI_MAX_CURRENT_MULTIPLIER; + } else { + mmc->caps &= ~MMC_CAP_UHS2; + mmc->flags &= ~MMC_UHS2_SUPPORT; + } + + return 0; +} + +static void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead) +{ + if (!(host->mmc) || !(host->mmc->flags & MMC_UHS2_SUPPORT)) + return; + + if (!dead) + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_FULL); + + sdhci_writel(host, 0, SDHCI_UHS2_ERR_INT_STATUS_EN); + sdhci_writel(host, 0, SDHCI_UHS2_ERR_INT_SIG_EN); + host->mmc->flags &= ~MMC_UHS2_SUPPORT; + host->mmc->flags &= ~MMC_UHS2_INITIALIZED; +} + +static int __init sdhci_uhs2_host_init(void) +{ + sdhci_uhs2_ops.reset = sdhci_uhs2_reset; + sdhci_uhs2_ops.set_timeout = sdhci_uhs2_set_timeout; + sdhci_uhs2_ops.set_transfer_mode = sdhci_uhs2_set_transfer_mode; + sdhci_uhs2_ops.send_command = sdhci_uhs2_send_command; + sdhci_uhs2_ops.finish_command = sdhci_uhs2_finish_command; + sdhci_uhs2_ops.do_set_ios = sdhci_uhs2_do_set_ios; + sdhci_uhs2_ops.do_detect_init = sdhci_uhs2_do_detect_init; + sdhci_uhs2_ops.do_set_reg = sdhci_uhs2_do_set_reg; + sdhci_uhs2_ops.irq = sdhci_uhs2_irq; + sdhci_uhs2_ops.add_host = sdhci_uhs2_add_host; + sdhci_uhs2_ops.remove_host = sdhci_uhs2_remove_host; + + return 0; +} +module_init(sdhci_uhs2_host_init); + +static void __exit sdhci_uhs2_exit(void) +{ + struct sdhci_uhs2_ops nops = {}; + + sdhci_uhs2_ops = nops; +} +module_exit(sdhci_uhs2_exit); + +MODULE_AUTHOR("Intel, Genesys Logic, Linaro"); +MODULE_DESCRIPTION("MMC UHS-II Support"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Jul 10 11:12:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 235228 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp347863ilg; Fri, 10 Jul 2020 04:12:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxISev2zKaqgpLtOyQXkwVYcRuf5/Otn1n/XpSdodhrKDuu3HQalIjCk76sUa05rRH+GVG+ X-Received: by 2002:a50:eb02:: with SMTP id y2mr74188930edp.281.1594379550881; Fri, 10 Jul 2020 04:12:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594379550; cv=none; d=google.com; s=arc-20160816; b=B98JUSEfIN71a8y4+kzQysFuv1HKngtfsf9Qnd4yaikvIHB8m0g18+m8mZYo7xPnpF Kp5x4rWxwZurMCNiM8qt7wL6CUzrq1YBOL45+gzgXZXwDFwzLcDCRMr/1TS9w0ws75UM AEMz9LBpYsCinZ+mkNa49Rf+Jzi7ai5gcZlBFGR7YupyZIX8cVoHh6UNTUsyQ+g6Oi/7 6vPyZoo/cEyV8Up+SimmryOXxokqzIoN8JMqHwXg2uJ0mzeoBJr2lLHzBs7X5ckzFTEF 3kNLAaqtmxhE9UocuuUgwvZjWlQ2j2ZC8175a2zx59U8zZJBV3O5v2xLGwT31J3qV8kY hq+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=S7yVpx9Ygx5/VQ/WoaheeloIQ6g4ecPLVpX/LrJKnQ8=; b=oZlh+snvSopUaSqf8oloSqF/+kFBBUXD3uaxJjm84sRHQmdZDT9PI0RppTQHTrdpI9 SSMTYISpZeLWuOwyW0KtnYeGrUgs2Qeryo2AIwvbjGtrPzlpLDmvJH3dajJLK0Gkuppd k6bg9Xyteec1Mb8AmT7/6J7G1tuzoPnTo/zPqr5pQJi5UFJNBUrJKY+zZ8PjJe2GsA2G wD4hvffgauwOSUQstTfCG1eocUyp0cKDcisHBlJCzE2dsxMhFofuAQTj4wuQBKj2axy0 RM1g23m6XNfsqOqbfAqGKycIN3TP0OIVywSg4Qz2D5cZlg5J4zA0UpYRKzb4yz9vLYWf tJFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Os8uLJ7q; spf=pass (google.com: domain of linux-mmc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id x7sm5842904pfq.197.2020.07.10.04.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 04:12:03 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, takahiro.akashi@linaro.org, greg.tu@genesyslogic.com.tw, Ben Chuang Subject: [RFC PATCH V3 19/21] mmc: core: add post-mmc_attach_sd hook Date: Fri, 10 Jul 2020 19:12:47 +0800 Message-Id: <20200710111247.29937-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro This "post" hook for mmc_attach_sd() will be required to enable UHS-II support, at least, on GL9755. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/core/sd.c | 6 ++++++ include/linux/mmc/host.h | 1 + 2 files changed, 7 insertions(+) -- 2.27.0 diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index c5b071bd98b3..fd4cae4ed747 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -1381,6 +1381,12 @@ int mmc_attach_sd(struct mmc_host *host) goto remove_card; mmc_claim_host(host); + + /* TODO: Is this the right place? */ + if ((host->flags & MMC_UHS2_INITIALIZED) && + host->ops->uhs2_post_attach_sd) + host->ops->uhs2_post_attach_sd(host); + return 0; remove_card: diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 56bdb153ef16..e61e0ae62cff 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -180,6 +180,7 @@ struct mmc_host_ops { int (*uhs2_set_reg)(struct mmc_host *host, enum uhs2_act act); void (*uhs2_disable_clk)(struct mmc_host *host); void (*uhs2_enable_clk)(struct mmc_host *host); + void (*uhs2_post_attach_sd)(struct mmc_host *host); }; struct mmc_cqe_ops {