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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h15sm999974pjc.14.2020.07.08.22.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2020 22:01:41 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org Subject: [PATCH 1/5] iommu/arm-smmu: Make all valid stream mappings BYPASS Date: Wed, 8 Jul 2020 22:01:41 -0700 Message-Id: <20200709050145.3520931-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200709050145.3520931-1-bjorn.andersson@linaro.org> References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Turn all stream mappings marked as valid into BYPASS. This allows the platform specific implementation to configure stream mappings to match the boot loader's configuration for e.g. display to continue to function through the reset of the SMMU. Suggested-by: Robin Murphy Signed-off-by: Bjorn Andersson --- drivers/iommu/arm-smmu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.26.2 Reported-by: kernel test robot Reported-by: kernel test robot diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 243bc4cb2705..2e27cf9815ab 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1924,6 +1924,22 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) return 0; } +int arm_smmu_setup_identity(struct arm_smmu_device *smmu) +{ + int i; + + for (i = 0; i < smmu->num_mapping_groups; i++) { + if (smmu->smrs[i].valid) { + smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = 0xff; + smmu->s2crs[i].count++; + } + } + + return 0; +} + struct arm_smmu_match_data { enum arm_smmu_arch_version version; enum arm_smmu_implementation model; @@ -2181,6 +2197,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (err) return err; + err = arm_smmu_setup_identity(smmu); + if (err) + return err; + if (smmu->version == ARM_SMMU_V2) { if (smmu->num_context_banks > smmu->num_context_irqs) { dev_err(dev, From patchwork Thu Jul 9 05:01:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 235125 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1067762ilg; Wed, 8 Jul 2020 22:02:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwPJFu+pUT+PzVU4UWV8tEq69016boKz6b9Oa3AG99mLuWIDuxsiZ6BLj/Gb871CRsfkgHG X-Received: by 2002:a17:906:8157:: with SMTP id z23mr33312251ejw.349.1594270924477; Wed, 08 Jul 2020 22:02:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594270924; cv=none; d=google.com; s=arc-20160816; b=BtJ155p6YYRwPC8nu3WQi6W5wtXJfnXOqBRwkL500173/GPBBDM/iQpaAIyyZ3nSdt wWHoW11UTH1PAO1s4KVJDBt2iK6waKXrq+yUsCDAtnU6vS/UG92RcR+gtYSL3waWCZi8 wEGNgA/Gggj/mHn1s6w+Ei3taywtmoYcmPz8LU2kgSkC1HX5biXCYSDBN/ns74+7cXJs cLy8j/wFZXRKm4/te5vZ7M2PefQVdKNc51SDd5X+DsBXOB/kzenxtpQ2XKV5dZWlaaBQ 9gJWq3YNrdXCl4V1yDGkETnPzhRJx1RFBfw1iWl+dlfwYOFOx1AKef+15sO3t2hgJl0J 0OTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fL1oj/82czdR0WXUznCgbOV1KIBa6gJW0wdl0Fe8bqk=; b=PiJyBhmcp8f/5bsr+taKds61CdqH42hyGBoMFMJ1YirLeyYId4PvcuaWJJaRd3Iu29 k4b3tFwFmZoHyE/AzrWS3q1SBWCha6zl3+X/VTWoo/V/uAcd1hNegGOnMwffEBAoi/B6 k6Fh/LiN9sTyLVJxM89F+8VJnm1vqEcmJrQeS84AfbuBhKvu0HNH4FSXsphmNrHwmiae x58n5gNo7N54c8mCOfekDfGp4VmLb6f1gKr8MIXvpCGEgBzswofpzMoFPE1MsUHPAuDs /WZzFsK0PqmCuMVaJ2d9bM5dv0sF4wk2rh/uhw6+a2MDstq/DUMnrqC/hI9NrfCXLVw4 NVSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YQWuQBQH; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h15sm999974pjc.14.2020.07.08.22.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2020 22:01:42 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org Subject: [PATCH 2/5] iommu/arm-smmu: Emulate bypass by using context banks Date: Wed, 8 Jul 2020 22:01:42 -0700 Message-Id: <20200709050145.3520931-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200709050145.3520931-1-bjorn.andersson@linaro.org> References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some firmware found on various Qualcomm platforms traps writes to S2CR of type BYPASS and writes FAULT into the register. This prevents us from marking the streams for the display controller as BYPASS to allow continued scanout of the screen through the initialization of the ARM SMMU. This adds a Qualcomm specific cfg_probe function, which probes the behavior of the S2CR registers and if found faulty enables the related quirk. Based on this quirk context banks are allocated for IDENTITY domains as well, but with ARM_SMMU_SCTLR_M omitted. The result is valid stream mappings, without translation. Signed-off-by: Bjorn Andersson --- drivers/iommu/arm-smmu-qcom.c | 21 +++++++++++++++++++++ drivers/iommu/arm-smmu.c | 14 ++++++++++++-- drivers/iommu/arm-smmu.h | 3 +++ 3 files changed, 36 insertions(+), 2 deletions(-) -- 2.26.2 diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index cf01d0215a39..e8a36054e912 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -23,6 +23,26 @@ static const struct of_device_id qcom_smmu_client_of_match[] = { { } }; +static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) +{ + unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); + u32 reg; + + /* + * With some firmware writes to S2CR of type FAULT are ignored, and + * writing BYPASS will end up as FAULT in the register. Perform a write + * to S2CR to detect if this is the case with the current firmware. + */ + arm_smmu_gr0_write(smmu, last_s2cr, FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | + FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | + FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT)); + reg = arm_smmu_gr0_read(smmu, last_s2cr); + if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) + smmu->qcom_bypass_quirk = true; + + return 0; +} + static int qcom_smmu_def_domain_type(struct device *dev) { const struct of_device_id *match = @@ -61,6 +81,7 @@ static int qcom_smmu500_reset(struct arm_smmu_device *smmu) } static const struct arm_smmu_impl qcom_smmu_impl = { + .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, }; diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 2e27cf9815ab..f33eda3117fa 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -654,7 +654,9 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) /* SCTLR */ reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE | ARM_SMMU_SCTLR_AFE | - ARM_SMMU_SCTLR_TRE | ARM_SMMU_SCTLR_M; + ARM_SMMU_SCTLR_TRE; + if (cfg->m) + reg |= ARM_SMMU_SCTLR_M; if (stage1) reg |= ARM_SMMU_SCTLR_S1_ASIDPNE; if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) @@ -678,7 +680,11 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, if (smmu_domain->smmu) goto out_unlock; - if (domain->type == IOMMU_DOMAIN_IDENTITY) { + /* + * Nothing to do for IDENTITY domains,unless disabled context banks are + * used to emulate bypass mappings on Qualcomm platforms. + */ + if (domain->type == IOMMU_DOMAIN_IDENTITY && !smmu->qcom_bypass_quirk) { smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; smmu_domain->smmu = smmu; goto out_unlock; @@ -826,6 +832,10 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, domain->geometry.aperture_end = (1UL << ias) - 1; domain->geometry.force_aperture = true; + /* Enable translation for non-identity context banks */ + if (domain->type != IOMMU_DOMAIN_IDENTITY) + cfg->m = true; + /* Initialise the context bank with our page table cfg */ arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); arm_smmu_write_context_bank(smmu, cfg->cbndx); diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index d172c024be61..a71d193073e4 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -305,6 +305,8 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + + bool qcom_bypass_quirk; }; enum arm_smmu_context_fmt { @@ -323,6 +325,7 @@ struct arm_smmu_cfg { }; enum arm_smmu_cbar_type cbar; enum arm_smmu_context_fmt fmt; + bool m; }; #define ARM_SMMU_INVALID_IRPTNDX 0xff From patchwork Thu Jul 9 05:01:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 235123 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1067744ilg; Wed, 8 Jul 2020 22:02:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwPjwlcWeWP+IiXOuyiuvIRWHtj3H/gytjc/43P7pUmh06CkhyfR/q0hOXyR55o07mjafYs X-Received: by 2002:a17:906:c943:: with SMTP id fw3mr53771378ejb.55.1594270922921; Wed, 08 Jul 2020 22:02:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594270922; cv=none; d=google.com; s=arc-20160816; b=kraDkdKSOxE5DC1huU+kqvdnFVr6xmRACdSVlIdAqyEyhpFhzRb5bL1i3lFHcsMGh6 TJ1sVVAjVerqsfg8t43Vpy/Lwn4WuwWJ6LnbH1JJcydW6jN19xXf8v73KxGVUcE/ubjh yO134pY/CXVLF+u/01yb/Z0TPACsVxs2uoOm6219gJkQUrNfcYbOZWtlbu/x2KlWJSD4 nhaUMZUL5m4OyfH8CcBYI2fx/6b011fVbajkLYILFUdFAEybbaFskY2soHi1W6YxYT3Y o8DAIwBLY05ziOaySBdnkzmzEI59T4ClUmoj6pnoLFle+8Ow6z8SOVzdHJzx0C5lj1kh I4IQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Hqoe1VtzzAa4w0lrTNILxm5TZOFtQ6ZqFKD8K8ft5H8=; b=1A1u7KeaiWKIIT9+3djhqN0Kp3a5crJ1YS/sUGyD2fpHLa5HTAsEd0judNGyKeU3R8 YUvGikkvi9DvwMVBk7wdHoZJg61RJ2SIXqFlrf2FOtd/VBgcc3X8Hw+S6ez3elSjbNcQ RdF4hrEv3lllEbFDt/KPga5aSOCNTEIsACrfLwp5F9iaWaM7EkSEJLfl95zkNUp8wTxz 53cmDP8veQnuVYyVpv9DmKwvNDb/KOnY4bYb8gh7kxRKgpXyCphUXAxpfnKzsvX9Lmsz 8EI6zKxQ17IeRW4XkYlyRqUbrDCldLNOnpazWTgUFWOhj4vci835IXOYNmcqL4AWv9lr 4zKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oi9P502f; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h15sm999974pjc.14.2020.07.08.22.01.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2020 22:01:43 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org Subject: [PATCH 3/5] iommu/arm-smmu: Move SMR and S2CR definitions to header file Date: Wed, 8 Jul 2020 22:01:43 -0700 Message-Id: <20200709050145.3520931-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200709050145.3520931-1-bjorn.andersson@linaro.org> References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Expose the SMR and S2CR structs in the header file, to allow platform specific implementations to populate/initialize the smrs and s2cr arrays. Signed-off-by: Bjorn Andersson --- drivers/iommu/arm-smmu.c | 14 -------------- drivers/iommu/arm-smmu.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 14 deletions(-) -- 2.26.2 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index f33eda3117fa..e2d6c0aaf1ea 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -68,24 +68,10 @@ module_param(disable_bypass, bool, S_IRUGO); MODULE_PARM_DESC(disable_bypass, "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU."); -struct arm_smmu_s2cr { - struct iommu_group *group; - int count; - enum arm_smmu_s2cr_type type; - enum arm_smmu_s2cr_privcfg privcfg; - u8 cbndx; -}; - #define s2cr_init_val (struct arm_smmu_s2cr){ \ .type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS, \ } -struct arm_smmu_smr { - u16 mask; - u16 id; - bool valid; -}; - struct arm_smmu_cb { u64 ttbr[2]; u32 tcr[2]; diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index a71d193073e4..bcd160d01c53 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -251,6 +251,21 @@ enum arm_smmu_implementation { QCOM_SMMUV2, }; +struct arm_smmu_s2cr { + struct iommu_group *group; + int count; + enum arm_smmu_s2cr_type type; + enum arm_smmu_s2cr_privcfg privcfg; + u8 cbndx; +}; + +struct arm_smmu_smr { + u16 mask; + u16 id; + bool valid; + bool pinned; +}; + struct arm_smmu_device { struct device *dev; From patchwork Thu Jul 9 05:01:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 235121 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1067601ilg; Wed, 8 Jul 2020 22:01:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxfWP12VGmn7Bn7ya9SFSLwFFxvDltMS7R6yECU68bltOwC3W1sPBOWUDY+BZNfh1GbMW8h X-Received: by 2002:a17:906:4bc1:: with SMTP id x1mr45234949ejv.377.1594270912586; Wed, 08 Jul 2020 22:01:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594270912; cv=none; d=google.com; s=arc-20160816; b=E2E3626EOUkNMziPN+xqxKq5Vf7Vx/tPgO7lg4uP02jSXFfXBc2IPOVooDex39P+x0 2jj2XYNstmwgYCM48RxleyTOACQ9PRsivqXfnwuE56VvLrg6hRFxlJ75sQp5x+BjJEBs +/m69FexCac3rb6xYE047tJDBAH4zss/PzzXPD89tvTnN00LJuor4f/awWUnJQAYNOBh VJ3e35V8h+JG5JjDOIZNysWcz9j7/EQgK7FcG7+lpdCD+XwGoA13tTyCSUJsc91eURpv Fi+N8AvbBsJBP+6SU9CzILSFYU8AMoq0cB0ZboWtnd9gYge99U1g6kw2cl+bRpRHATu2 ueNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=410aRxR/jUVzarYYA7FRja4VMLxxjmJi5LB1naX7CXw=; b=dty/bvpPB5ajOTWaL+hVqzVijVTMLv8QVDAeTZz8RcdxDBoAhL2GTAiPY9r2Qi5/5b gVhqOSHTmK9Dr69oMqBTTTQa3CGSi9fFZf8PvUoJFggVRtfJL7odrU5KvayrtK076jvj F9ivQ+CT2yR0YRQDtVxfhfcODgaPStZJjCMu25GgpzhIculo9aMlfNe47DmRPtODmpL/ mlmLqkW8t4a9MgJA6M3cd/6oo+yeu2nLFBYKOi83+J4RdJfj0w6u9gtqebBcUXeMddaS ILX0O6w9ZB+3WnyUuDdTO4BTj0kWpukDexDfj9Zb9urT8kRZ8WiV3hzL7IjUvLbwBzLl 1ESw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pMadG799; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h15sm999974pjc.14.2020.07.08.22.01.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2020 22:01:45 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org Subject: [PATCH 4/5] iommu/arm-smmu-qcom: Consstently initialize stream mappings Date: Wed, 8 Jul 2020 22:01:44 -0700 Message-Id: <20200709050145.3520931-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200709050145.3520931-1-bjorn.andersson@linaro.org> References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Firmware that traps writes to S2CR to translate BYPASS into FAULT also ignores writes of type FAULT. As such booting with "disable_bypass" set will result in all S2CR registers left as configured by the bootloader. This has been seen to result in indeterministic results, as these mappings might linger and reference context banks that Linux is reconfiguring. Use the fact that BYPASS writes result in FAULT type to force all stream mappings to FAULT. Signed-off-by: Bjorn Andersson --- drivers/iommu/arm-smmu-qcom.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -- 2.26.2 diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index e8a36054e912..86b1917459a4 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -27,6 +27,7 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) { unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); u32 reg; + int i; /* * With some firmware writes to S2CR of type FAULT are ignored, and @@ -37,9 +38,24 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT)); reg = arm_smmu_gr0_read(smmu, last_s2cr); - if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) + if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { smmu->qcom_bypass_quirk = true; + /* + * With firmware ignoring writes of type FAULT, booting the + * Linux kernel with disable_bypass disabled (i.e. "enable + * bypass") the initialization during probe will leave mappings + * in an inconsistent state. Avoid this by configuring all + * S2CRs to BYPASS. + */ + for (i = 0; i < smmu->num_mapping_groups; i++) { + smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = 0xff; + smmu->s2crs[i].count = 0; + } + } + return 0; } From patchwork Thu Jul 9 05:01:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 235122 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1067615ilg; Wed, 8 Jul 2020 22:01:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwDbavyLtA5NomXdntsi1/byx46zV+Tj/V8svWE6iCyfNAtufQimD8mQbQecf5IEJ9IAFlQ X-Received: by 2002:a17:906:dce:: with SMTP id p14mr53351957eji.442.1594270913725; Wed, 08 Jul 2020 22:01:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594270913; cv=none; d=google.com; s=arc-20160816; b=IpbWDQCgo07etVK7PHuMKSQHsX/egfOwuFuPQhCClkOvOZ9DYaSzflpxybXlEB7jWc wMI0dVDuQVHMiNC+tlvMdi9FL2vl647/FYs+KHGbMJJfglXOPqlUtCU16vRY28olptSd AC3WtiahRAh9J3rQrkC2UHafoCOWrGZ07IGtmsw4EOERtYiqewhgEWZniIMESsiSyFox Lbiqr4cDFAKp2gxMAVtQBrpSs7eq4l+7I2drRkgwtoirfew6qXu+yekCBgailQNQRV3c cUjO5/+izTae8HFAueAN9A4fmNpAqApecgEbklSKrVFqgvcRbz5j0uBQtE6HQ5fmp/po tC3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fpwjVW7Z+irWop7fAETDGc/ua6yC0KP+NMCvyoQB9RI=; b=WGUnr08mKR7JQnxD2QHb1FW2Uduc9Xx+8m1uDQ3EaOcR+0CbntNbX4MTUGgOohfuWL aOZPXfCxSexSmTbu0bv2KZT+hb3a2qD+sifa9qSigMFdvyd9LxnTtKPwMDJONG0E5gR5 XlwmbDF0LVozjxYJTV/vuWtpDB3CbespAJbeieCrZB928OCiZXYu73W0MZsTHeFDa2ev VCszv++Qx+9t+D4UGBk5769CB8TYiyz8ZPKLslKB5KP5kYcR9LYbN4U2ug15JYSG31UK 9DPtcnp3R7u5w9iXNQIYhwbIttVt0R6k1KGKaxRyEYvUNxVcfMB6tMh3utlbkhhJURGt /9QA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sJK6emFs; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h15sm999974pjc.14.2020.07.08.22.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2020 22:01:46 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org Subject: [PATCH 5/5] iommu/arm-smmu: Setup identity domain for boot mappings Date: Wed, 8 Jul 2020 22:01:45 -0700 Message-Id: <20200709050145.3520931-6-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200709050145.3520931-1-bjorn.andersson@linaro.org> References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org With many Qualcomm platforms not having functional S2CR BYPASS a temporary IOMMU domain, without translation, needs to be allocated in order to allow these memory transactions. Unfortunately the boot loader uses the first few context banks, so rather than overwriting a active bank the last context bank is used and streams are diverted here during initialization. This also performs the readback of SMR registers for the Qualcomm platform, to trigger the mechanism. This is based on prior work by Thierry Reding and Laurentiu Tudor. Signed-off-by: Bjorn Andersson --- drivers/iommu/arm-smmu-qcom.c | 11 +++++ drivers/iommu/arm-smmu.c | 80 +++++++++++++++++++++++++++++++++-- drivers/iommu/arm-smmu.h | 3 ++ 3 files changed, 90 insertions(+), 4 deletions(-) -- 2.26.2 Tested-by: Laurentiu Tudor diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index 86b1917459a4..397df27c1d69 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -26,6 +26,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] = { static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) { unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); + u32 smr; u32 reg; int i; @@ -56,6 +57,16 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) } } + for (i = 0; i < smmu->num_mapping_groups; i++) { + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); + + if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { + smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); + smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); + smmu->smrs[i].valid = true; + } + } + return 0; } diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index e2d6c0aaf1ea..a7cb27c1a49e 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -652,7 +652,8 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) } static int arm_smmu_init_domain_context(struct iommu_domain *domain, - struct arm_smmu_device *smmu) + struct arm_smmu_device *smmu, + bool boot_domain) { int irq, start, ret = 0; unsigned long ias, oas; @@ -770,6 +771,15 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, ret = -EINVAL; goto out_unlock; } + + /* + * Use the last context bank for identity mappings during boot, to + * avoid overwriting in-use bank configuration while we're setting up + * the new mappings. + */ + if (boot_domain) + start = smmu->num_context_banks - 1; + ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); if (ret < 0) @@ -1149,7 +1159,10 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct arm_smmu_master_cfg *cfg; struct arm_smmu_device *smmu; + bool free_identity_domain = false; + int idx; int ret; + int i; if (!fwspec || fwspec->ops != &arm_smmu_ops) { dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); @@ -1174,7 +1187,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; /* Ensure that the domain is finalised */ - ret = arm_smmu_init_domain_context(domain, smmu); + ret = arm_smmu_init_domain_context(domain, smmu, false); if (ret < 0) goto rpm_put; @@ -1190,9 +1203,34 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) goto rpm_put; } + /* Decrement use counter for any references to the identity domain */ + mutex_lock(&smmu->stream_map_mutex); + if (smmu->identity) { + struct arm_smmu_domain *identity = to_smmu_domain(smmu->identity); + + for_each_cfg_sme(cfg, fwspec, i, idx) { + dev_err(smmu->dev, "%s() %#x\n", __func__, smmu->smrs[idx].id); + if (smmu->s2crs[idx].cbndx == identity->cfg.cbndx) { + smmu->num_identity_masters--; + if (smmu->num_identity_masters == 0) + free_identity_domain = true; + } + } + } + mutex_unlock(&smmu->stream_map_mutex); + /* Looks ok, so add the device to the domain */ ret = arm_smmu_domain_add_master(smmu_domain, cfg, fwspec); + /* + * The last stream map to reference the identity domain has been + * overwritten, so it's now okay to free it. + */ + if (free_identity_domain) { + arm_smmu_domain_free(smmu->identity); + smmu->identity = NULL; + } + /* * Setup an autosuspend delay to avoid bouncing runpm state. * Otherwise, if a driver for a suspended consumer device @@ -1922,17 +1960,51 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) int arm_smmu_setup_identity(struct arm_smmu_device *smmu) { + struct device *dev = smmu->dev; + int cbndx = 0xff; + int type = S2CR_TYPE_BYPASS; + int ret; int i; + if (smmu->qcom_bypass_quirk) { + /* Create a IDENTITY domain to use for all inherited streams */ + smmu->identity = arm_smmu_domain_alloc(IOMMU_DOMAIN_IDENTITY); + if (!smmu->identity) { + dev_err(dev, "failed to create identity domain\n"); + return -ENOMEM; + } + + smmu->identity->pgsize_bitmap = smmu->pgsize_bitmap; + smmu->identity->type = IOMMU_DOMAIN_IDENTITY; + smmu->identity->ops = &arm_smmu_ops; + + ret = arm_smmu_init_domain_context(smmu->identity, smmu, true); + if (ret < 0) { + dev_err(dev, "failed to initialize identity domain: %d\n", ret); + return ret; + } + + type = S2CR_TYPE_TRANS; + cbndx = to_smmu_domain(smmu->identity)->cfg.cbndx; + } + for (i = 0; i < smmu->num_mapping_groups; i++) { if (smmu->smrs[i].valid) { - smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].type = type; smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; - smmu->s2crs[i].cbndx = 0xff; + smmu->s2crs[i].cbndx = cbndx; smmu->s2crs[i].count++; + + smmu->num_identity_masters++; } } + /* If no mappings where found, free the identiy domain again */ + if (smmu->identity && !smmu->num_identity_masters) { + arm_smmu_domain_free(smmu->identity); + smmu->identity = NULL; + } + return 0; } diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index bcd160d01c53..37257ede86fa 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -321,6 +321,9 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + struct iommu_domain *identity; + unsigned int num_identity_masters; + bool qcom_bypass_quirk; };