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[23.128.96.18]) by mx.google.com with ESMTP id dh2si16863975edb.55.2020.07.08.02.30.46; Wed, 08 Jul 2020 02:30:47 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=HJahAXyB; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728280AbgGHJal (ORCPT + 6 others); Wed, 8 Jul 2020 05:30:41 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58106 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726445AbgGHJal (ORCPT ); Wed, 8 Jul 2020 05:30:41 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689UVkr077802; Wed, 8 Jul 2020 04:30:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200631; bh=ZG1VUcH+6tOwwV7BnhCzX/gBAhx0Ee8zky2NKNJPpXQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HJahAXyB6Z34ypn9y3jD+pIOIszCEcBFXiT4dOI4C47tZpeT4idB2dcYMSf+Pcm3X rvC3YooTWdS92WgLE11+7NCWgNIDAn5oO29UMV4hunsoPtDFhwn047EPfVZ7w5k+q2 JXirucwvxnKF81rbsau43+Fbp22nnFtogulMNh+M= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UVG8021580; Wed, 8 Jul 2020 04:30:31 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:30:30 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:30:30 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEJ098512; Wed, 8 Jul 2020 04:30:27 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 02/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Date: Wed, 8 Jul 2020 15:00:06 +0530 Message-ID: <20200708093018.28474-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a macro for aligning down a pointer. This is useful to get an aligned register address when a device allows only word access and doesn't allow half word or byte access. Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- include/linux/kernel.h | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 9b7a8d74a9d6..c3b361b5be54 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -34,6 +34,7 @@ #define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) #define __ALIGN_MASK(x, mask) __ALIGN_KERNEL_MASK((x), (mask)) #define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define PTR_ALIGN_DOWN(p, a) ((typeof(p))ALIGN_DOWN((unsigned long)(p), (a))) #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) /* generic data direction definitions */ From patchwork Wed Jul 8 09:30:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235051 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp264993ilg; Wed, 8 Jul 2020 02:30:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx+cZjBJDmp8+Q0Wll3ckaYWyoKClk0jCXgvoHQwomCYEsZPYJHChIwch02IDdt8t9NeYST X-Received: by 2002:a50:ee01:: with SMTP id g1mr57771362eds.264.1594200653027; Wed, 08 Jul 2020 02:30:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200653; cv=none; d=google.com; s=arc-20160816; b=WjoPyPmF0Ti1KLqADTmsSOlDPTwpMmTfWcien2gjHkkAhRoq4imEs44b6jLWNZyrQe 7GeNS304c/cSHkzLshpGiuLNz/o58R/nb42Ny01eiYFGEmmP8RArQtkwZ+pKi6D/tqRN ZOysrlyuArWzA4sjnK/FlLMdbHDUuKjhx6dWTwyKArrEWwNdnSugLr5S4tuoPH6yrcB+ 0H4u4a6hovfET0bAX75VtbjqQj5XBNBbrneM1MoO15tOMaOyX4OmdsZPQZdM7x+EVDEu a7AWae+K31fB6RjP1bd7X4MuZX+bsggy4dPK86RA+sOCC2xArDmP1JKxOoXZIsWF51TE W+Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=MZf42sPBwBopHgxh/3zJoW1MM7sBcf1j/itzNs7qpps=; b=iC4jRf3E9muxy0ZCHpluk5uI1Vw24IFTGt5yKA30/Y44kMYyn0l9kuzlv0KRT3tY6+ d4tGzcqjFRPUMWbFn7Z8dS5ITuaM1yOJL+Uu72U1SzWRYNjVq6tOKMKkvFfR2aH0m0Of NHLR6mjsKdkYARX7FCDI0qmRBd0i2thb9D7G2lOpGAnG5Z9S56H8W40AIHkiYBMl2Dda ri5j6qSjjf0D7iAYL11V67PV0Hb6Jorp3nFeBCh+PpYBwgU61mNwK339CNcH9LrW5yRk drx18lxXdBn9Ti6S9U51AIRdOnpYUCqvqJQHXcg5hAUOfMxvVenk6CuOSqPH8JgFtqne tzbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="i/KslzbF"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y15si17861722edm.260.2020.07.08.02.30.52; Wed, 08 Jul 2020 02:30:53 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="i/KslzbF"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728346AbgGHJaw (ORCPT + 6 others); Wed, 8 Jul 2020 05:30:52 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:38926 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726445AbgGHJav (ORCPT ); Wed, 8 Jul 2020 05:30:51 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689UcY4109455; Wed, 8 Jul 2020 04:30:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200638; bh=MZf42sPBwBopHgxh/3zJoW1MM7sBcf1j/itzNs7qpps=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=i/KslzbFcr01l4BlPbqXIPHif/xZ8ESa/x4+fXWWCM1fm8F3lQubBu/oX/OyNZ8om fJ+CkoyFFFYbVZB4dS4StrG8q2cH3KfhIt7C43cOFvuelbIOobzAebLDK7Kfhj6ML2 8SCskCRcKTSiMwwDQYRiscTsDIDiympzti4YV5ko= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0689Uc0k043589 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 8 Jul 2020 04:30:38 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:30:38 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:30:38 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEL098512; Wed, 8 Jul 2020 04:30:35 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 04/14] PCI: cadence: Add support to start link and verify link status Date: Wed, 8 Jul 2020 15:00:08 +0530 Message-ID: <20200708093018.28474-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add cdns_pcie_ops to start link and verify link status. The registers to start link and to check link status is in Platform specific PCIe wrapper. Add support for platform specific drivers to add callback functions for the PCIe Cadence core to start link and verify link status. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../pci/controller/cadence/pcie-cadence-ep.c | 8 ++++ .../controller/cadence/pcie-cadence-host.c | 28 ++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 37 ++++++++++++++++++- 3 files changed, 72 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index c6eb2db94680..034cb3cf726e 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -357,8 +357,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; + struct device *dev = pcie->dev; struct pci_epf *epf; u32 cfg; + int ret; /* * BIT(0) is hardwired to 1, hence function 0 is always enabled @@ -369,6 +371,12 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) cfg |= BIT(epf->func_no); cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg); + ret = cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + return 0; } diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 030e828bfd4c..de02fadc4809 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -3,6 +3,7 @@ // Cadence PCIe host controller driver. // Author: Cyrille Pitchen +#include #include #include #include @@ -419,6 +420,23 @@ static int cdns_pcie_host_init(struct device *dev, return err; } +static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev = pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} + int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { struct device *dev = rc->pcie.dev; @@ -467,6 +485,16 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) pcie->mem_res = res; + ret = cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + ret = cdns_pcie_host_wait_for_link(pcie); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) rc->avail_ib_bar[bar] = true; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index a45c11158f49..54e10caf2d4b 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,6 +10,11 @@ #include #include +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + /* * Local Management Registers */ @@ -245,12 +250,20 @@ enum cdns_pcie_msg_routing { MSG_ROUTING_GATHER, }; +struct cdns_pcie_ops { + int (*start_link)(struct cdns_pcie *pcie); + void (*stop_link)(struct cdns_pcie *pcie); + bool (*link_up)(struct cdns_pcie *pcie); +}; + /** * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base * @mem_res: start/end offsets in the physical system memory to map PCI accesses * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. * @bus: In Root Complex mode, the bus number + * @ops: Platform specific ops to control various inputs from Cadence PCIe + * wrapper */ struct cdns_pcie { void __iomem *reg_base; @@ -261,7 +274,7 @@ struct cdns_pcie { int phy_count; struct phy **phy; struct device_link **link; - const struct cdns_pcie_common_ops *ops; + const struct cdns_pcie_ops *ops; }; /** @@ -426,6 +439,28 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); } +static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) +{ + if (pcie->ops->start_link) + return pcie->ops->start_link(pcie); + + return 0; +} + +static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) +{ + if (pcie->ops->stop_link) + pcie->ops->stop_link(pcie); +} + +static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) +{ + if (pcie->ops->link_up) + return pcie->ops->link_up(pcie); + + return true; +} + #ifdef CONFIG_PCIE_CADENCE_HOST int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); #else From patchwork Wed Jul 8 09:30:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235055 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265175ilg; Wed, 8 Jul 2020 02:31:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwT53/ejTXbdUGDNbrFeamTOPUw73428d07dmcVo6OA+jRGQCKszRf9++YSqFc4Qa9EzWd7 X-Received: by 2002:a17:906:6dd7:: with SMTP id j23mr35118122ejt.529.1594200669451; Wed, 08 Jul 2020 02:31:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200669; cv=none; d=google.com; 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[23.128.96.18]) by mx.google.com with ESMTP id w9si17326727edr.171.2020.07.08.02.31.09; Wed, 08 Jul 2020 02:31:09 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UNExrCnR; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728451AbgGHJbI (ORCPT + 6 others); Wed, 8 Jul 2020 05:31:08 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39032 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726973AbgGHJbG (ORCPT ); Wed, 8 Jul 2020 05:31:06 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689Us6N109489; Wed, 8 Jul 2020 04:30:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200654; bh=oDHixXQpSiTZez44a8+8lE4nJpgDYDjM303UR0TQSis=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UNExrCnRq/70xH4/LUjTSGYx9q5Y+kcahjQJgM8n5KhuRfU4Zjfo9MXZ4RNwN2PKK EiPf2bYV0LTYNj2WmjvT1CCX0UPZE8ApT8yibOqpv0SWm3Rasyrt4sENeTtkqGiQ5U GTdXky8D3oXLQStBbiQB8p6Vhq4IIJ60RZGTThkM= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UsPa022079; Wed, 8 Jul 2020 04:30:54 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:30:54 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:30:54 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEP098512; Wed, 8 Jul 2020 04:30:51 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Date: Wed, 8 Jul 2020 15:00:12 +0530 Message-ID: <20200708093018.28474-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller") in order to update Vendor ID, directly wrote to PCI_VENDOR_ID register. However PCI_VENDOR_ID in root port configuration space is read-only register and writing to it will have no effect. Use local management register to configure Vendor ID and Subsystem Vendor ID. Fixes: 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller") Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-host.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 10127ea71b83..8935f7a37e5a 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -82,6 +82,7 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; u32 value, ctrl; + u32 id; /* * Set the root complex BAR configuration register: @@ -101,8 +102,12 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value); /* Set root port configuration space */ - if (rc->vendor_id != 0xffff) - cdns_pcie_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); + if (rc->vendor_id != 0xffff) { + id = CDNS_PCIE_LM_ID_VENDOR(rc->vendor_id) | + CDNS_PCIE_LM_ID_SUBSYS(rc->vendor_id); + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + if (rc->device_id != 0xffff) cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); From patchwork Wed Jul 8 09:30:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235056 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265245ilg; Wed, 8 Jul 2020 02:31:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwKLshMdcc1kPyrbBhda7GBvikcSaB1GWYI5atoCfUzx3GJDMw5EkY16iJG8jCvw8MJyBh6 X-Received: by 2002:a50:9a82:: with SMTP id p2mr64597852edb.130.1594200675538; Wed, 08 Jul 2020 02:31:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200675; cv=none; d=google.com; s=arc-20160816; b=DErtPkAhnHZi2jUhbXfE/c1Dwe5H24dGowl99Mc0CSVcCbXV4nWWc7r8+3wwNz7nms +HLoAXXGY7rp8piPU2BKZCdkiGwnGXL5NROP6T3l1eoJj00I/2M8+i8ASrqWnczrlGee M/wF/Jf82lGJG0eLdL5pN+LSgk9BdSlnvjExGsWiQKQLaELZpyVktx6+hCj5Cdk3D3Zz /iSgRilRocLUCNSMvvzZ8jkrozugJzVTJ2PzR1ABtYAGj1+fjwX8mqO8yRfVRGOxYKGw rIXe7cdcLlqF4Rfwn4AsyqQEM7mhPWZ0kMTAZ4WpV5a85GStDFGKnLTwtnQaouWSsZmw JmNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=P/tGOXBSgsFmG2C/xoH0jOMCZxBW6F3uPgPZWAAKVCA=; b=doe/tcJmfw+S3ogP1tPtMwbPgD+3abj0FSvS57xS08VefdvGcO8b6KVcHtRWfeN28z KJ1vKbOSOZubsDe7tQn8uj1/HT1T/yCkgMt8DFGjDHRLeQsnM8b9pK+dm5FEdWyds7rg MEatLT4YV1xDoFSeZj9clpYj8BwKNaG2jThcg5bYT/fwYhfgimaqc/8oxrq7i5/ZBxch 5IkGJ+aoKW/mmNKh1qaLiofWqhf0wm++svZfXFUyOWjd1UEdABQQ37SJ6yYdSV7zw5fS 9NLCAf84iQe/XdpUQd0xrS9fyRNvev4zH1rCuPNzngoef0M16WgVNf0hgyW/YjzS/Lxx 8unA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iwy9hyEz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ss14si16493917ejb.732.2020.07.08.02.31.15; Wed, 08 Jul 2020 02:31:15 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iwy9hyEz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728481AbgGHJbK (ORCPT + 6 others); Wed, 8 Jul 2020 05:31:10 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:55988 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728466AbgGHJbJ (ORCPT ); Wed, 8 Jul 2020 05:31:09 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689UwsZ068311; Wed, 8 Jul 2020 04:30:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200658; bh=P/tGOXBSgsFmG2C/xoH0jOMCZxBW6F3uPgPZWAAKVCA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iwy9hyEz4Ix/J2eK25oQNmkNLTWTXJktYhTX8mtH88tKzw9uz912S2Pm4RIz9eIM0 It5m6Tm+GslQH3PuqHNn7eUSF79DWkYWfpH7eu1hNL1f5bHcm5UQbiO/5LZzd5kfGm fXlEdTspmc+CI+aBFE9lI5c1tYUgthiI1I0XxC08= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0689UwuY103074 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 8 Jul 2020 04:30:58 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:30:58 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:30:58 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEQ098512; Wed, 8 Jul 2020 04:30:55 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 09/14] PCI: cadence: Add MSI-X support to Endpoint driver Date: Wed, 8 Jul 2020 15:00:13 +0530 Message-ID: <20200708093018.28474-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Alan Douglas Implement ->set_msix() and ->get_msix() callback functions in order to configure MSIX capability in the PCIe endpoint controller. Add cdns_pcie_ep_send_msix_irq() to send MSIX interrupts to Host. cdns_pcie_ep_send_msix_irq() gets the MSIX table address (virtual address) from "struct cdns_pcie_epf" that gets initialized in ->set_bar() call back function. Signed-off-by: Alan Douglas [kishon@ti.com: Re-implement MSIX support in accordance with the re-designed core MSI-X interfaces] Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/cadence/pcie-cadence-ep.c | 108 +++++++++++++++++- drivers/pci/controller/cadence/pcie-cadence.h | 11 ++ 2 files changed, 118 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 034cb3cf726e..87c76341eab4 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -51,6 +51,7 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, struct pci_epf_bar *epf_bar) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + struct cdns_pcie_epf *epf = &ep->epf[fn]; struct cdns_pcie *pcie = &ep->pcie; dma_addr_t bar_phys = epf_bar->phys_addr; enum pci_barno bar = epf_bar->barno; @@ -111,6 +112,8 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); cdns_pcie_writel(pcie, reg, cfg); + epf->epf_bar[bar] = epf_bar; + return 0; } @@ -118,6 +121,7 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, struct pci_epf_bar *epf_bar) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + struct cdns_pcie_epf *epf = &ep->epf[fn]; struct cdns_pcie *pcie = &ep->pcie; enum pci_barno bar = epf_bar->barno; u32 reg, cfg, b, ctrl; @@ -139,6 +143,8 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0); cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0); + + epf->epf_bar[bar] = NULL; } static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, @@ -224,6 +230,50 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) return mme; } +static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no) +{ + struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + struct cdns_pcie *pcie = &ep->pcie; + u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + reg = cap + PCI_MSIX_FLAGS; + val = cdns_pcie_ep_fn_readw(pcie, func_no, reg); + if (!(val & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + val &= PCI_MSIX_FLAGS_QSIZE; + + return val; +} + +static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u16 interrupts, + enum pci_barno bir, u32 offset) +{ + struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + struct cdns_pcie *pcie = &ep->pcie; + u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + reg = cap + PCI_MSIX_FLAGS; + val = cdns_pcie_ep_fn_readw(pcie, fn, reg); + val &= ~PCI_MSIX_FLAGS_QSIZE; + val |= interrupts; + cdns_pcie_ep_fn_writew(pcie, fn, reg, val); + + /* Set MSIX BAR and offset */ + reg = cap + PCI_MSIX_TABLE; + val = offset | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + /* Set PBA BAR and offset. BAR must match MSIX BAR */ + reg = cap + PCI_MSIX_PBA; + val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + return 0; +} + static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx, bool is_asserted) { @@ -333,6 +383,52 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, return 0; } +static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, + u16 interrupt_num) +{ + u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 tbl_offset, msg_data, reg, vec_ctrl; + struct cdns_pcie *pcie = &ep->pcie; + struct pci_epf_msix_tbl *msix_tbl; + struct cdns_pcie_epf *epf; + u64 pci_addr_mask = 0xff; + u64 msg_addr; + u16 flags; + u8 bir; + + /* Check whether the MSI-X feature has been enabled by the PCI host. */ + flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS); + if (!(flags & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + reg = cap + PCI_MSIX_TABLE; + tbl_offset = cdns_pcie_ep_fn_readl(pcie, fn, reg); + bir = tbl_offset & PCI_MSIX_TABLE_BIR; + tbl_offset &= PCI_MSIX_TABLE_OFFSET; + + epf = &ep->epf[fn]; + msix_tbl = epf->epf_bar[bir]->addr + tbl_offset; + msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr; + msg_data = msix_tbl[(interrupt_num - 1)].msg_data; + vec_ctrl = msix_tbl[(interrupt_num - 1)].vector_ctrl; + + /* Set the outbound region if needed. */ + if (ep->irq_pci_addr != (msg_addr & ~pci_addr_mask) || + ep->irq_pci_fn != fn) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_set_outbound_region(pcie, fn, 0, + false, + ep->irq_phys_addr, + msg_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr = (msg_addr & ~pci_addr_mask); + ep->irq_pci_fn = fn; + } + writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask)); + + return 0; +} + static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, enum pci_epc_irq_type type, u16 interrupt_num) @@ -346,6 +442,9 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, case PCI_EPC_IRQ_MSI: return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num); + case PCI_EPC_IRQ_MSIX: + return cdns_pcie_ep_send_msix_irq(ep, fn, interrupt_num); + default: break; } @@ -383,7 +482,7 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) static const struct pci_epc_features cdns_pcie_epc_features = { .linkup_notifier = false, .msi_capable = true, - .msix_capable = false, + .msix_capable = true, }; static const struct pci_epc_features* @@ -400,6 +499,8 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = { .unmap_addr = cdns_pcie_ep_unmap_addr, .set_msi = cdns_pcie_ep_set_msi, .get_msi = cdns_pcie_ep_get_msi, + .set_msix = cdns_pcie_ep_set_msix, + .get_msix = cdns_pcie_ep_get_msix, .raise_irq = cdns_pcie_ep_raise_irq, .start = cdns_pcie_ep_start, .get_features = cdns_pcie_ep_get_features, @@ -458,6 +559,11 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) epc->max_functions = 1; + ep->epf = devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf), + GFP_KERNEL); + if (!ep->epf) + return -ENOMEM; + ret = pci_epc_mem_init(epc, pcie->mem_res->start, resource_size(pcie->mem_res), PAGE_SIZE); if (ret < 0) { diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 1d2bdc4e08e4..8057f4a338bd 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -113,6 +113,7 @@ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) #define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 +#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 /* * Root Port Registers (PCI configuration space for the root port function) @@ -302,6 +303,14 @@ struct cdns_pcie_rc { bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; }; +/** + * struct cdns_pcie_epf - Structure to hold info about endpoint function + * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers + */ +struct cdns_pcie_epf { + struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; +}; + /** * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver * @pcie: Cadence PCIe controller @@ -321,6 +330,7 @@ struct cdns_pcie_rc { * @lock: spin lock to disable interrupts while modifying PCIe controller * registers fields (RMW) accessible by both remote RC and EP to * minimize time between read and write + * @epf: Structure to hold info about endpoint function */ struct cdns_pcie_ep { struct cdns_pcie pcie; @@ -334,6 +344,7 @@ struct cdns_pcie_ep { u8 irq_pending; /* protect writing to PCI_STATUS while raising legacy interrupts */ spinlock_t lock; + struct cdns_pcie_epf *epf; }; From patchwork Wed Jul 8 09:30:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235059 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265436ilg; Wed, 8 Jul 2020 02:31:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzV86+/wQ9vstjhko+0zRLKAx3c6Ug8pznvh+Ro2P2RBCC4xjmCQ7JbSJz38NE8HJdMlsu0 X-Received: by 2002:aa7:da90:: with SMTP id q16mr57347375eds.44.1594200689608; Wed, 08 Jul 2020 02:31:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200689; cv=none; d=google.com; s=arc-20160816; b=ge9HrmBSvBbYHnZSqZycXMiRCuoSsP7H8nfnu3uNgmnqYeL3Imw1IHbpvzlbcfdcUs vCYlfUeTTqHD1cvi7mrPONWrnaZsKo2RG97hoQIdZrpJB7p4I/APpdrhXbvUIVoz9IqB +GpxW1zGF0f5MVvjnh//Xy1lOFb/vX6F5DrD8HC3K0x3M9L1x1PdJ21Y/dIkhBW4s+ls cuH+dyTJc8nkJuiaqUj37kh0w+HsVbljrvHdxKz62hzJCZznmWhkUDleacqFMo5LjURC Uy2zTmUscXVflTR0gt2rxPOSMoWyZZaxV9BnQ+v8baVGjtgMZtd0K8duDEKRLM2dBnuD MZbw== ARC-Message-Signature: i=1; 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Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- MAINTAINERS | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index 5bbc2649566b..bdec73c3069e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13119,12 +13119,14 @@ S: Maintained F: Documentation/devicetree/bindings/pci/designware-pcie.txt F: drivers/pci/controller/dwc/*designware* -PCI DRIVER FOR TI DRA7XX +PCI DRIVER FOR TI DRA7XX/J721E M: Kishon Vijay Abraham I L: linux-omap@vger.kernel.org L: linux-pci@vger.kernel.org +L: linux-arm-kernel@lists.infradead.org S: Supported F: Documentation/devicetree/bindings/pci/ti-pci.txt +F: drivers/pci/controller/cadence/pci-j721e.c F: drivers/pci/controller/dwc/pci-dra7xx.c PCI DRIVER FOR TI KEYSTONE