From patchwork Wed Jul 8 08:52:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 235042 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp240136ilg; Wed, 8 Jul 2020 01:52:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxAha2TJcU+HeWCMwIp4M6mLE79o6RrwDmyKS8fM0LZzEqW5tSqH9jca+GcXQAHfHGTLdGn X-Received: by 2002:a17:906:9147:: with SMTP id y7mr47303317ejw.399.1594198326359; Wed, 08 Jul 2020 01:52:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594198326; cv=none; d=google.com; s=arc-20160816; b=yZhs3RTENOobMTjTynEpGU4hkMpTBa9vR7+HB0BIazTupOZNsaI0Hbi3omzukMtrAN toZYQ2bp3EeR9n0G28iCN3JbrMEocGdPmtyNk+2caqYAsH5PZl4MsVcscfjXWQJW+pcN kvmSbMYYpGHBvZyFtTFcyHE4YnuO4bxBV1ygZgj847TQixQwgJei4TToD+eZ7sNFSCoV QatVlG+rShJcVJizeghzN1vCHghn8PkGcNitG2+qCcw7tGEh38b07Bgl5QAoyGmWsu9R Bs4Bjgh/1rf1LFEyPEGQDyv6qDqGfGkFWdceWNkmzhP04eE9KSXYDSFSysjevwLSPANq YHIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=UM6UYI71+CVhzhPNNl2sjpYAkMlGBSiHjii7W5sLQRk=; b=twiPlGfaR471bHqzVMAHm+hTmpynFzoqkiQK1Et7rUWb5APul1/Etz1YEoYnTHusmi fi6vi3uW16FNi5CH01vO6AdQdx1jaGIKao0CioXsJoROg0DR7n1GIQRbpw6hY+ZcxZzp V6I2pe+Uv8g8SsoDfPKtJ6yo/UnB6moNPrqYTNDGwjL1ecrAwy/YhXg5b+n711nNvt3g sSx8vNGohl9ygOcWJeAfc9FS7oA0AKs+S8Pi+ZEQkUPGLDt6n/wmLvfmrhUdvgYPtKr+ Bye7Uq8mmMTFMnnOjTIOivCG9q4VYp/SBz69yxWLpK5uKZnEY7L1dxnaipucj4HEG0Sd UzFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id lv11si15691795ejb.106.2020.07.08.01.52.06; Wed, 08 Jul 2020 01:52:06 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728106AbgGHIwF (ORCPT + 6 others); Wed, 8 Jul 2020 04:52:05 -0400 Received: from mx.socionext.com ([202.248.49.38]:18877 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727903AbgGHIwF (ORCPT ); Wed, 8 Jul 2020 04:52:05 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Jul 2020 17:52:03 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 77ADC60060; Wed, 8 Jul 2020 17:52:03 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 8 Jul 2020 17:52:03 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id CEB341A0507; Wed, 8 Jul 2020 17:52:02 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Masahiro Yamada Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH] ARM: dts: uniphier: Add PCIe endpoint and PHY node for Pro5 Date: Wed, 8 Jul 2020 17:52:00 +0900 Message-Id: <1594198320-28900-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds PCIe endpoint controller and PHY nodes for Pro5 SoC, and also adds pinctrl node for PCIe. Signed-off-by: Kunihiko Hayashi --- arch/arm/boot/dts/uniphier-pinctrl.dtsi | 5 +++++ arch/arm/boot/dts/uniphier-pro5.dtsi | 30 ++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) -- 2.7.4 diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi index bfdfb76..c0fd029 100644 --- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi @@ -126,6 +126,11 @@ function = "nand"; }; + pinctrl_pcie: pcie { + groups = "pcie"; + function = "pcie"; + }; + pinctrl_sd: sd { groups = "sd"; function = "sd"; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index feadb4a..3525125 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -613,6 +613,36 @@ }; }; + pcie_ep: pcie-ep@66000000 { + compatible = "socionext,uniphier-pro5-pcie-ep", + "snps,dw-pcie-ep"; + status = "disabled"; + reg-names = "dbi", "dbi2", "link", "addr_space"; + reg = <0x66000000 0x1000>, <0x66001000 0x1000>, + <0x66010000 0x10000>, <0x67000000 0x400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 24>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 24>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-lanes = <4>; + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + }; + + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-pro5-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 24>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 24>; + }; + nand: nand-controller@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled";