From patchwork Tue Feb 11 12:47:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thermal-bot for Julien Panis X-Patchwork-Id: 231594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5FC7C352A3 for ; Tue, 11 Feb 2020 12:49:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AA368246BB for ; Tue, 11 Feb 2020 12:49:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728604AbgBKMrx (ORCPT ); Tue, 11 Feb 2020 07:47:53 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:45983 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728481AbgBKMrx (ORCPT ); Tue, 11 Feb 2020 07:47:53 -0500 Received: from [5.158.153.53] (helo=tip-bot2.lab.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1j1Ux8-0007Yz-6r; Tue, 11 Feb 2020 13:47:46 +0100 Received: from [127.0.1.1] (localhost [IPv6:::1]) by tip-bot2.lab.linutronix.de (Postfix) with ESMTP id CE64B1C2017; Tue, 11 Feb 2020 13:47:45 +0100 (CET) Date: Tue, 11 Feb 2020 12:47:45 -0000 From: "tip-bot2 for Kim Phillips" Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/amd: Add missing L2 misses event spec to AMD Family 17h's event map Cc: Babu Moger , Kim Phillips , "Peter Zijlstra (Intel)" , Ingo Molnar , stable@vger.kernel.org, x86 , LKML In-Reply-To: <20200121171232.28839-1-kim.phillips@amd.com> References: <20200121171232.28839-1-kim.phillips@amd.com> MIME-Version: 1.0 Message-ID: <158142526559.411.16112962778577638815.tip-bot2@tip-bot2> X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1, SHORTCIRCUIT=-0.0001 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 25d387287cf0330abf2aad761ce6eee67326a355 Gitweb: https://git.kernel.org/tip/25d387287cf0330abf2aad761ce6eee67326a355 Author: Kim Phillips AuthorDate: Tue, 21 Jan 2020 11:12:31 -06:00 Committer: Ingo Molnar CommitterDate: Tue, 11 Feb 2020 13:17:51 +01:00 perf/x86/amd: Add missing L2 misses event spec to AMD Family 17h's event map Commit 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h"), claimed L2 misses were unsupported, due to them not being found in its referenced documentation, whose link has now moved [1]. That old documentation listed PMCx064 unit mask bit 3 as: "LsRdBlkC: LS Read Block C S L X Change to X Miss." and bit 0 as: "IcFillMiss: IC Fill Miss" We now have new public documentation [2] with improved descriptions, that clearly indicate what events those unit mask bits represent: Bit 3 now clearly states: "LsRdBlkC: Data Cache Req Miss in L2 (all types)" and bit 0 is: "IcFillMiss: Instruction Cache Req Miss in L2." So we can now add support for L2 misses in perf's genericised events as PMCx064 with both the above unit masks. [1] The commit's original documentation reference, "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors", originally available here: https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf is now available here: https://developer.amd.com/wordpress/media/2017/11/54945_PPR_Family_17h_Models_00h-0Fh.pdf [2] "Processor Programming Reference (PPR) for Family 17h Model 31h, Revision B0 Processors", available here: https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf Fixes: 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h") Reported-by: Babu Moger Signed-off-by: Kim Phillips Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Tested-by: Babu Moger Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20200121171232.28839-1-kim.phillips@amd.com --- arch/x86/events/amd/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 1f22b6b..39eb276 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -250,6 +250,7 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60, + [PERF_COUNT_HW_CACHE_MISSES] = 0x0964, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x0287, From patchwork Tue Jan 21 17:12:32 2020 Content-Type: text/plain; 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Tue, 21 Jan 2020 17:12:56 +0000 From: Kim Phillips To: Peter Zijlstra , Ingo Molnar , Ingo Molnar , kim.phillips@amd.com Cc: Alexander Shishkin , Andi Kleen , Arnaldo Carvalho de Melo , Babu Moger , Borislav Petkov , Fenghua Yu , Frank van der Linden , "H . Peter Anvin" , Huang Rui , Janakarajan Natarajan , Jan Beulich , Jiaxun Yang , Jiri Olsa , Josh Poimboeuf , Linus Torvalds , Luwei Kang , =?utf-8?q?Martin_Li=C5=A1ka?= , Matt Fleming , Namhyung Kim , Paolo Bonzini , Pawan Gupta , Suravee Suthikulpanit , Thomas Gleixner , Tom Lendacky , x86@kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH 2/2 v2] x86/cpu/amd: Enable the fixed intructions retired free counter IRPERF Date: Tue, 21 Jan 2020 11:12:32 -0600 Message-Id: <20200121171232.28839-2-kim.phillips@amd.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200121171232.28839-1-kim.phillips@amd.com> References: <20200121171232.28839-1-kim.phillips@amd.com> X-ClientProxiedBy: DM6PR17CA0025.namprd17.prod.outlook.com (2603:10b6:5:1b3::38) To SN6PR12MB2845.namprd12.prod.outlook.com (2603:10b6:805:75::33) MIME-Version: 1.0 Received: from fritz.amd.com (165.204.77.1) by DM6PR17CA0025.namprd17.prod.outlook.com (2603:10b6:5:1b3::38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2644.20 via Frontend Transport; Tue, 21 Jan 2020 17:12:53 +0000 X-Mailer: git-send-email 2.25.0 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: a10f20cd-1577-4c5c-5f95-08d79e952846 X-MS-TrafficTypeDiagnostic: SN6PR12MB2703:|SN6PR12MB2703: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2150; X-Forefront-PRVS: 0289B6431E X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4636009)(39860400002)(136003)(396003)(346002)(376002)(366004)(189003)(199004)(186003)(16526019)(8676002)(26005)(8936002)(478600001)(966005)(81166006)(6486002)(2616005)(81156014)(956004)(2906002)(1076003)(316002)(66574012)(4326008)(36756003)(44832011)(86362001)(5660300002)(7696005)(52116002)(54906003)(7416002)(110136005)(6666004)(66946007)(66556008)(66476007); DIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR12MB2703; H:SN6PR12MB2845.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PryH9lGOmhD38Uo3kvM0M6wgTafMoAZj2nccPTfZ5rW+bBfCtuM1ANTIrB6DMje8/aYeP9RebvQbdrdCdnVr4UKHbeDzxP0BvKAv15E/vraGFMK5PNTqnrV1BrAJNzQ3YUB6Q6fWZFW5BJ2ksg4RKjPCm+PVTF8+yrumM6Fw1UV/S0sXP3ZE/jP5MhkVXl/dB/lWiUCLxbDe/hWQn2oFJJb5iXQmdi7ozgULTURScKcMjCRg8CBGzezNufILmm1lh82qSxDdTiayWhp7zTIas4i4rF3n8ZwTDlhgGbW/O2Z86m0EBiI9rJRovWLzB8ceWzBzbZZcuMDV8O3MEOT4cYGg/wofwrpsZvezmG99VolujElB2cJJ+CUFGbF5SIhgjja2KL6HXzXoQ1nMggLhekdx9H68mvAg9UXhBxJM/ws+/tNP6ltXBwD+AEKNUIX9Z7AXnx57gjSV91rvkUf19TV0ZxKwOTRLw13n1DFEAKYa7rUDkxlbdcPAY8jaNeA9vfK4lPLHsSpIOga5KTVXvw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a10f20cd-1577-4c5c-5f95-08d79e952846 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2020 17:12:56.0740 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: RB1Br0Pv+wFtYAgt0qdOkIaXmsrfQvb9iLa8tbII3mzl/q6rB4kDf2X62lp+8QFh2F5LJAqba03EMQOCQ+GdTQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2703 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org commit aaf248848db50 ("perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter") added support for 'perf -e msr/irperf/', but when exercised, we always get a 0 count: BEFORE: $ sudo perf stat -e instructions,msr/irperf/ true Performance counter stats for 'true': 624,833 instructions # 0.00 stalled cycles per insn 0 msr/irperf/ It turns out it simply needs its enable bit - HWCR bit 30 - set. This patch does just that. Enablement is restricted to all machines advertising IRPERF capability, except those susceptible to an erratum that makes the IRPERF return bad values. That erratum occurs in Family 17h models 00-1fh [1], but not in F17h models 20h and above [2]. AFTER (on a family 17h model 31h machine): $ sudo perf stat -e instructions,msr/irperf/ true Performance counter stats for 'true': 621,690 instructions # 0.00 stalled cycles per insn 622,490 msr/irperf/ [1] "Revision Guide for AMD Family 17h Models 00h-0Fh Processors", currently available here: https://www.amd.com/system/files/TechDocs/55449_Fam_17h_M_00h-0Fh_Rev_Guide.pdf [2] "Revision Guide for AMD Family 17h Models 30h-3Fh Processors", currently available here: https://developer.amd.com/wp-content/resources/56323-PUB_0.74.pdf Cc: Alexander Shishkin Cc: Andi Kleen Cc: Arnaldo Carvalho de Melo Cc: Babu Moger Cc: Borislav Petkov Cc: Fenghua Yu Cc: Frank van der Linden Cc: H. Peter Anvin Cc: Huang Rui Cc: Ingo Molnar Cc: Ingo Molnar Cc: Janakarajan Natarajan Cc: Jan Beulich Cc: Jiaxun Yang Cc: Jiri Olsa Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Luwei Kang Cc: Martin Liška Cc: Matt Fleming Cc: Namhyung Kim Cc: Paolo Bonzini Cc: Pawan Gupta Cc: Peter Zijlstra Cc: Suravee Suthikulpanit Cc: Thomas Gleixner Cc: Tom Lendacky Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org Fixes: aaf248848db50 ("perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter") Signed-off-by: Kim Phillips --- v2: Based on Andi Kleen's review: https://lore.kernel.org/lkml/20200116040324.GI302770@tassilo.jf.intel.com/ Add an amd_erratum_1054 and use cpu_has_bug infrastructure instead of open-coding the {family,model} check. arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 17 +++++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index f3327cb56edf..1c1600e7476b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -404,5 +404,6 @@ #define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */ #define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */ #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */ +#define X86_BUG_AMD_E1054 X86_BUG(24) /* CPU is among the affected by Erratum 1054 */ #endif /* _ASM_X86_CPUFEATURES_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ebe1685e92dd..d5e517d1c3dd 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -512,6 +512,8 @@ #define MSR_K7_HWCR 0xc0010015 #define MSR_K7_HWCR_SMMLOCK_BIT 0 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) +#define MSR_K7_HWCR_IRPERF_EN_BIT 30 +#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 62c30279be77..c067234a271f 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -28,6 +28,7 @@ static const int amd_erratum_383[]; static const int amd_erratum_400[]; +static const int amd_erratum_1054[]; static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); /* @@ -701,6 +702,9 @@ static void early_init_amd(struct cpuinfo_x86 *c) if (cpu_has_amd_erratum(c, amd_erratum_400)) set_cpu_bug(c, X86_BUG_AMD_E400); + if (cpu_has_amd_erratum(c, amd_erratum_1054)) + set_cpu_bug(c, X86_BUG_AMD_E1054); + early_detect_mem_encrypt(c); /* Re-enable TopologyExtensions if switched off by BIOS */ @@ -978,6 +982,15 @@ static void init_amd(struct cpuinfo_x86 *c) /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ if (!cpu_has(c, X86_FEATURE_XENPV)) set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); + + /* + * Turn on the Instructions Retired free counter on machines not + * susceptible to erratum #1054 "Instructions Retired Performance + * Counter May Be Inaccurate" + */ + if (cpu_has(c, X86_FEATURE_IRPERF) && + !cpu_has_bug(c, X86_BUG_AMD_E1054)) + msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); } #ifdef CONFIG_X86_32 @@ -1105,6 +1118,10 @@ static const int amd_erratum_400[] = static const int amd_erratum_383[] = AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); +/* #1054: Instructions Retired Performance Counter May Be Inaccurate */ +static const int amd_erratum_1054[] = + AMD_OSVW_ERRATUM(0, AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); + static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) {