From patchwork Thu Sep 21 15:22:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113273 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2155136qgf; Thu, 21 Sep 2017 08:23:27 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBDMDMaxEDIFU2pxXjJkjI4dMzTqSWk406aBeitURSAQMlOTah6BAon1/Lvng+ljujDwTpT X-Received: by 10.80.131.6 with SMTP id 6mr1608975edh.138.1506007407770; Thu, 21 Sep 2017 08:23:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506007407; cv=none; d=google.com; s=arc-20160816; b=CiR4UyCtkymflb99qKt5poTv2EfiBCidDok3UrfhMPfsS2Ep8yRyd7TuDRt41/qeY9 SC3NzAiNYl7yzuelXlIjDhVW0gQfzcedB4UVx+puVDVyDmVl+3e3GmPmCTx56XtkU3er InObM8lepmDm+4ZyLFKOeZ7qhb2CR/DItKC3xiOMamuaPdIgTNpYtlDLNQ0IyUqqR8GM mpk1oisxkPVf87uylyjqeRoe2KdIWBr0IGhifkaXtT3KbyCrYTv4UIcp8UFXaLNmWr1U k08KdnlMWdH8aQfM44BLYsnLW5kN16Tbjta/Tdeig7hS9i+eL6DlDhMYaFy+jGmImvV5 ch7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=XQdG6CdT9cffJBDk2/1dBbjbN0tDuiGT9GnR0ry+pso=; b=XNulj9JKW0BnhbV5q10WEPjqBFWZN9GyrDfCIY00PU3WLaqla0lPOp6Bejxvthc1ZK Ioe8QuzGBsscN282uogYNjZ7kG9ss0wGEv/OhTjfWDnv9WnfHN9EA9NT1gyRVOnv7Xij hrBxxxRS8xPkA4wIAuXpDuUfMCMzgzHXwwkk1KTcdN0DVz31G2/yL2bwLwZM4DDCj7G6 MzvKKaDYjzjBDOGHF0uI1eJLFUAeX7vzWeXRbyH1TjcuyuVLvtlemBlXoFxt/LPsDJZ/ 0XWWZhSG4k0J+JAc7//0K/55WhXEXIoT+kJf9PdGotpHkB7V+gruxn6joWjew04srtHD VSbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jBfoq82p; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id t26si1597685edc.390.2017.09.21.08.23.27; Thu, 21 Sep 2017 08:23:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jBfoq82p; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 51C98C21E5B; Thu, 21 Sep 2017 15:23:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B4FCFC21FCF; Thu, 21 Sep 2017 15:22:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9938BC21C54; Thu, 21 Sep 2017 15:22:43 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 008E2C21C4E for ; Thu, 21 Sep 2017 15:22:42 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMefZ013899; Thu, 21 Sep 2017 10:22:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007360; bh=JIe6eYjyfUNRSu3kAUH5M/tkknd8EjmUZQpZkC1CMhE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jBfoq82p6UubcrdnEa0PW6T2zhtgxFv6ctD+L+UyCE4L5i+oTg4LiRHjW3V8mpni9 IHOzTvNm5glC3qv2L6t86hePEccPgipYgENZRt4Ineslw2+q13B65/PlJtWtCfP3hy w5mve2cPew5G3GQHHU2k5fLuVG0Yb8bo88zeFoOM= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMet5009283; Thu, 21 Sep 2017 10:22:40 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:40 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:40 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMdGh022746; Thu, 21 Sep 2017 10:22:40 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:04 +0200 Message-ID: <1506007346-10037-2-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 01/23] mmc: omap_hsmmc: cleanup clock configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Add a separate function for starting the clock, stopping the clock and setting the clock. Starting the clock and stopping the clock can be used irrespective of setting the clock (For example during iodelay recalibration). Also set the clock only if there is a change in frequency. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 2 ++ drivers/mmc/omap_hsmmc.c | 74 ++++++++++++++++++++++++++++------------- 2 files changed, 52 insertions(+), 24 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index bf9de9b..102aec2 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -172,6 +172,8 @@ struct omap_hsmmc_plat { #define CLK_400KHZ 1 #define CLK_MISC 2 +#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ + #define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 1c3d1a5..6ef8295 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -62,6 +62,7 @@ struct omap_hsmmc_data { #if !CONFIG_IS_ENABLED(DM_MMC) struct mmc_config cfg; #endif + uint clock; #ifdef OMAP_HSMMC_USE_GPIO #if CONFIG_IS_ENABLED(DM_MMC) struct gpio_desc cd_gpio; /* Change Detect GPIO */ @@ -114,6 +115,8 @@ struct omap_hsmmc_adma_desc { static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); +static void omap_hsmmc_start_clock(struct hsmmc *mmc_base); +static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base); static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) { @@ -762,6 +765,51 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, return 0; } +static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base) +{ + writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl); +} + +static void omap_hsmmc_start_clock(struct hsmmc *mmc_base) +{ + writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); +} + +static void omap_hsmmc_set_clock(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct hsmmc *mmc_base; + unsigned int dsor = 0; + ulong start; + + mmc_base = priv->base_addr; + omap_hsmmc_stop_clock(mmc_base); + + /* TODO: Is setting DTO required here? */ + mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK), + (ICE_STOP | DTO_15THDTO)); + + if (mmc->clock != 0) { + dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock); + if (dsor > CLKD_MAX) + dsor = CLKD_MAX; + } + + mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, + (dsor << CLKD_OFFSET) | ICE_OSCILLATE); + + start = get_timer(0); + while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { + if (get_timer(0) - start > MAX_RETRY_MS) { + printf("%s: timedout waiting for ics!\n", __func__); + return; + } + } + + priv->clock = mmc->clock; + omap_hsmmc_start_clock(mmc_base); +} + #if !CONFIG_IS_ENABLED(DM_MMC) static int omap_hsmmc_set_ios(struct mmc *mmc) { @@ -774,8 +822,6 @@ static int omap_hsmmc_set_ios(struct udevice *dev) struct mmc *mmc = upriv->mmc; #endif struct hsmmc *mmc_base; - unsigned int dsor = 0; - ulong start; mmc_base = priv->base_addr; /* configue bus width */ @@ -801,28 +847,8 @@ static int omap_hsmmc_set_ios(struct udevice *dev) break; } - /* configure clock with 96Mhz system clock. - */ - if (mmc->clock != 0) { - dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); - if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) - dsor++; - } - - mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO)); - - mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, - (dsor << CLKD_OFFSET) | ICE_OSCILLATE); - - start = get_timer(0); - while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { - if (get_timer(0) - start > MAX_RETRY_MS) { - printf("%s: timedout waiting for ics!\n", __func__); - return -ETIMEDOUT; - } - } - writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); + if (priv->clock != mmc->clock) + omap_hsmmc_set_clock(mmc); return 0; } From patchwork Thu Sep 21 15:22:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113280 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2166246qgf; Thu, 21 Sep 2017 08:33:23 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCRv6GFj2JTAlrti1ccjr6ifyR1fuTfTknEOMhoRxx3j+SXyv5pirH1CI1iefkKqtHMBX+N X-Received: by 10.80.213.155 with SMTP id v27mr1632056edi.124.1506008003332; Thu, 21 Sep 2017 08:33:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008003; cv=none; d=google.com; s=arc-20160816; b=rsZFHK3QIkeyvmW8EG/3KCLdfUkz1xiVG7jnmRXy5OCkeKYkzYIiWFdPtfogxgSTAc j8UN8t6N5CYHNqbnvGy828L7ScuvPD+zhFw7yWZSHI5sslQZwRyo3VwdxBWcwyqX9VrH xAO0piyh92I2vBQa+WAJvB2fvb9d2Ylmmpba0ORUypUyfHeUhwbb+dHQ3PgMvVLyI3L8 +6vFAW7ecWyHV3O13eG8wEXvW32PvpqDPduWN9XtGBUOHd05dEvYRAD3f6yM/W1FbV7e gCHp5eqEfSssD5aQ/0K2x63QNlV5HHvQxmO2kgFJQS2dcN88rMyq9DqtiAZPkgF4b+rF QcSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=Pj3ZXfs7qeYsaU7ZpTESX+S04voRR/Ts0KL8kzF2S2Y=; b=nx1mpQ9Q602qeOWsyT+WoOwJMGCutUs+oIpKkiNHE255FuAD7KJRWgJiP8Vsa83RWt /FdYQQMJriB3h9ZmtEMAbTDdaFA7rH/ZRKMSMaFWFHDjhXmsim+dFLszGbUwAhq+5mGv oGX65bUGp7CVAkvX+1faFPWnADsLqzL44T2CpUYgGwyxl5n0I06Wa3ib3MMtearRLR/7 goDN1T2qIzpqyDK0kr7jHH8Z/kC9LlL7Ts4yk3Ha1CZVAKadwaMkUuS34yCAOO2FjfQb 4sNp9PPJNJUO76G+vXsjxVReZBiAPAf6kFUtf4G4p3JeQMhm3Ij+ChZ3h+ilemBN0bhI Dm4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=gpmgxUVM; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. 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Move bus width configuration setting to a separate function and invoke it only if there is a change in the bus width. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- drivers/mmc/omap_hsmmc.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 6ef8295..bab0cef 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -62,6 +62,7 @@ struct omap_hsmmc_data { #if !CONFIG_IS_ENABLED(DM_MMC) struct mmc_config cfg; #endif + uint bus_width; uint clock; #ifdef OMAP_HSMMC_USE_GPIO #if CONFIG_IS_ENABLED(DM_MMC) @@ -810,17 +811,9 @@ static void omap_hsmmc_set_clock(struct mmc *mmc) omap_hsmmc_start_clock(mmc_base); } -#if !CONFIG_IS_ENABLED(DM_MMC) -static int omap_hsmmc_set_ios(struct mmc *mmc) +static void omap_hsmmc_set_bus_width(struct mmc *mmc) { struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); -#else -static int omap_hsmmc_set_ios(struct udevice *dev) -{ - struct omap_hsmmc_data *priv = dev_get_priv(dev); - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct mmc *mmc = upriv->mmc; -#endif struct hsmmc *mmc_base; mmc_base = priv->base_addr; @@ -847,6 +840,24 @@ static int omap_hsmmc_set_ios(struct udevice *dev) break; } + priv->bus_width = mmc->bus_width; +} + +#if !CONFIG_IS_ENABLED(DM_MMC) +static int omap_hsmmc_set_ios(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); +#else +static int omap_hsmmc_set_ios(struct udevice *dev) +{ + struct omap_hsmmc_data *priv = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = upriv->mmc; +#endif + + if (priv->bus_width != mmc->bus_width) + omap_hsmmc_set_bus_width(mmc); + if (priv->clock != mmc->clock) omap_hsmmc_set_clock(mmc); From patchwork Thu Sep 21 15:22:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113285 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2170410qgf; Thu, 21 Sep 2017 08:37:28 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBgVZW14ppUEcAFZyYAa11xqE5bAsstDP/h0HUCElVVnbmPyF22m0xvUOizA7N+mh4sSuVr X-Received: by 10.80.241.146 with SMTP id x18mr1635312edl.119.1506008247981; Thu, 21 Sep 2017 08:37:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008247; cv=none; d=google.com; s=arc-20160816; b=KuoUFcxYwCcR6C2VJomgmo/o2PrMmAXsF2RXJZykgkdy/2VwPaFyR8j021i/r5YOnE kNaNgsYNgA8CdAXjntDoXe7EY+c/G1aFSmYVxmSIUYkR+87z6YyIjfwYaZ+hgVP4Y5kJ xIncHeBRMFbG5YPPligyI8GEM4jVEOHbocmh3CCR5dFw28955UeyYFcKovt/ZhA2mEAg mdqneQOReqCb2pf1IUZ3Kpgmzw3NLdRbTAEDGwoNPT1XXoqrRNbm38hPwC1Gk3vbR2gh 5Q8ZFfwnUa5Ei91fxhiBgpbIO9+oHavEUuSRqXMhLYSFsJ/M6sN2Nq4+jwsOQsH5fBzv m25A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=o28EGRIH3UlroqEszezgjxJqHfAtiXuNbWU14DQ8inM=; b=fIVc1RA234buw/n64IGuiQizgfKy3CjNmenF0OLtHVRcbxTCV9sEMvxGbWLmYNNGJ7 soDocC5X2bznUQbUbM4AUq/THb3ekROZvVSQdKgOa/sXdFD3ICB7f+YWuUdhgpNSvDxQ RKJjepzl+MwgjkTZdYBthiw1jT6EjQ+jcWs0g+Oo/x+2RYJur2yfGdiUKJ9S2V7QzwPQ O3VTf4IeAqKnxBb+660sPIeweZ5TqBYKqq+8dIztKDF5x0imlcRYDpxUAUvuqngKA0ZD OtXpj+66dccGoDN9L7V8+hymODdhSxWBle1i5sFi4i66oEbL9XUAOd2Q2RyZeiSs3Iwj nI4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Q888BPDi; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id g10si1730268edg.87.2017.09.21.08.37.27; Thu, 21 Sep 2017 08:37:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Q888BPDi; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 9642DC2204C; Thu, 21 Sep 2017 15:30:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 20103C220A9; Thu, 21 Sep 2017 15:30:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3EF8CC22096; Thu, 21 Sep 2017 15:23:54 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 64EA0C22096 for ; Thu, 21 Sep 2017 15:23:50 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMmEQ009111; Thu, 21 Sep 2017 10:22:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007368; bh=KEFIStLZ8PrAMJ7lhRwV4tl84kEDSLxeH61dQj3uGbg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Q888BPDiZwTvmNanrGf+QKlEcTLAbFmlxhm/l+cO8jX/NXNWvDmv5n76hCDg8q1Qm SQFjHTo7Tt7PE8yjmhZCSrNbE/Cuv6tKPadKU3ojaPit3bWFClUOZxodYZDdlrXA4n hcLqcINgIJII27NIdtYJfkB1rsTRJGxrikgBUAC8= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMh1u009339; Thu, 21 Sep 2017 10:22:43 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:43 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:42 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMgIH000957; Thu, 21 Sep 2017 10:22:42 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:06 +0200 Message-ID: <1506007346-10037-4-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 03/23] mmc: omap_hsmmc: add support to set default io voltage X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I "ti,dual-volt" is used in linux kernel to set the voltage capabilities. For host controller dt nodes that doesn't have "ti,dual-volt", it's assumed 1.8v is the io voltage. This is not always true (like in the case of beagle-x15 where the io lines are connected to 3.3v). Hence if "no-1-8-v" property is set, io voltage will be set to 3v. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 12 ++++++-- drivers/mmc/omap_hsmmc.c | 67 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 102aec2..c4d326d 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -65,6 +65,7 @@ struct omap_hsmmc_plat { struct hsmmc *base_addr; struct mmc mmc; bool cd_inverted; + u32 controller_flags; }; /* @@ -124,8 +125,10 @@ struct omap_hsmmc_plat { #define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ #define SDBP_PWROFF (0x0 << 8) #define SDBP_PWRON (0x1 << 8) +#define SDVS_MASK (0x7 << 9) #define SDVS_1V8 (0x5 << 9) #define SDVS_3V0 (0x6 << 9) +#define SDVS_3V3 (0x7 << 9) #define DMA_SELECT (0x2 << 3) #define ICE_MASK (0x1 << 0) #define ICE_STOP (0x0 << 0) @@ -159,8 +162,13 @@ struct omap_hsmmc_plat { #define IE_CERR (0x01 << 28) #define IE_BADA (0x01 << 29) -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) +#define VS33_3V3SUP BIT(24) +#define VS30_3V0SUP BIT(25) +#define VS18_1V8SUP BIT(26) + +#define IOV_3V3 3300000 +#define IOV_3V0 3000000 +#define IOV_1V8 1800000 /* Driver definitions */ #define MMCSD_SECTOR_SIZE 512 diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index bab0cef..e0c7067 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -74,6 +74,9 @@ struct omap_hsmmc_data { int wp_gpio; #endif #endif +#if CONFIG_IS_ENABLED(DM_MMC) + uint iov; +#endif u8 controller_flags; #ifndef CONFIG_OMAP34XX struct omap_hsmmc_adma_desc *adma_desc_table; @@ -111,6 +114,8 @@ struct omap_hsmmc_adma_desc { * that the bandwidth is always above 3MB/s). */ #define DMA_TIMEOUT_PER_MB 333 +#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) +#define OMAP_HSMMC_NO_1_8_V BIT(1) #define OMAP_HSMMC_USE_ADMA BIT(2) static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); @@ -252,6 +257,58 @@ void mmc_init_stream(struct hsmmc *mmc_base) writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); } +#if CONFIG_IS_ENABLED(DM_MMC) +static void omap_hsmmc_conf_bus_power(struct mmc *mmc) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + + mmc_base = priv->base_addr; + + val = readl(&mmc_base->hctl) & ~SDVS_MASK; + + switch (priv->iov) { + case IOV_3V3: + val |= SDVS_3V3; + break; + case IOV_3V0: + val |= SDVS_3V0; + break; + case IOV_1V8: + val |= SDVS_1V8; + break; + } + + writel(val, &mmc_base->hctl); +} + +static void omap_hsmmc_set_capabilities(struct mmc *mmc) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + + mmc_base = priv->base_addr; + val = readl(&mmc_base->capa); + + if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { + val |= (VS30_3V0SUP | VS18_1V8SUP); + priv->iov = IOV_3V0; + } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) { + val |= VS30_3V0SUP; + val &= ~VS18_1V8SUP; + priv->iov = IOV_3V0; + } else { + val |= VS18_1V8SUP; + val &= ~VS30_3V0SUP; + priv->iov = IOV_1V8; + } + + writel(val, &mmc_base->capa); +} +#endif + static int omap_hsmmc_init_setup(struct mmc *mmc) { struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); @@ -286,9 +343,15 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) if (reg_val & MADMA_EN) priv->controller_flags |= OMAP_HSMMC_USE_ADMA; #endif + +#if CONFIG_IS_ENABLED(DM_MMC) + omap_hsmmc_set_capabilities(mmc); + omap_hsmmc_conf_bus_power(mmc); +#else writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, &mmc_base->capa); +#endif reg_val = readl(&mmc_base->con) & RESERVED_MASK; @@ -1067,6 +1130,10 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + if (fdtdec_get_bool(fdt, node, "ti,dual-volt")) + plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; + if (fdtdec_get_bool(fdt, node, "no-1-8-v")) + plat->controller_flags |= OMAP_HSMMC_NO_1_8_V; #ifdef OMAP_HSMMC_USE_GPIO plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); From patchwork Thu Sep 21 15:22:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113278 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2162100qgf; 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[81.169.180.215]) by mx.google.com with ESMTP id q25si1757247eda.48.2017.09.21.08.29.52; Thu, 21 Sep 2017 08:29:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=l6YFY3hv; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 75A9CC22099; Thu, 21 Sep 2017 15:27:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CF8E2C22090; Thu, 21 Sep 2017 15:27:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9EB00C22092; Thu, 21 Sep 2017 15:23:55 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 35210C21EAB for ; Thu, 21 Sep 2017 15:23:52 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMnFJ009116; Thu, 21 Sep 2017 10:22:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007369; bh=2MYujNQwlVYcBV7SvRsB1S5thbLC6c+oburFtNxPO3I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=l6YFY3hvGRdfVkl27Mapmfipp3K64KawSm06A9kC/CS+KYTjwwoGSknTVYO4ECqqA QfuX4JXqN3bHQ54/dG9KKELUeRJvzzxap1bAoOAbizvRRubKraXyKFYF14AYDlrJfV 2CTsOpvef6/1JLDUubO7HUQtIIR3rx3Faru/bllA= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMiqb032697; Thu, 21 Sep 2017 10:22:44 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:44 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:44 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMhbx000975; Thu, 21 Sep 2017 10:22:44 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:07 +0200 Message-ID: <1506007346-10037-5-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 04/23] mmc: omap_hsmmc: set MMC mode in the UHSMS bit field X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Use the timing parameter set in the MMC core to set the mode in UHSMS bit field. This is in preparation for adding HS200 support in omap hsmmc driver. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 12 ++++++++++- drivers/mmc/omap_hsmmc.c | 47 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index c4d326d..3f94f2e 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -53,7 +53,8 @@ struct hsmmc { unsigned int sysctl; /* 0x12C */ unsigned int stat; /* 0x130 */ unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; + unsigned char res4[0x4]; + unsigned int ac12; /* 0x13C */ unsigned int capa; /* 0x140 */ unsigned char res5[0x10]; unsigned int admaes; /* 0x154 */ @@ -170,6 +171,15 @@ struct omap_hsmmc_plat { #define IOV_3V0 3000000 #define IOV_1V8 1800000 +#define AC12_ET (1 << 22) +#define AC12_UHSMC_MASK (7 << 16) +#define AC12_UHSMC_DDR50 (4 << 16) +#define AC12_UHSMC_SDR104 (3 << 16) +#define AC12_UHSMC_SDR50 (2 << 16) +#define AC12_UHSMC_SDR25 (1 << 16) +#define AC12_UHSMC_SDR12 (0 << 16) +#define AC12_UHSMC_RES (0x7 << 16) + /* Driver definitions */ #define MMCSD_SECTOR_SIZE 512 #define MMC_CARD 0 diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index e0c7067..4a65a46 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -76,6 +76,7 @@ struct omap_hsmmc_data { #endif #if CONFIG_IS_ENABLED(DM_MMC) uint iov; + enum bus_mode mode; #endif u8 controller_flags; #ifndef CONFIG_OMAP34XX @@ -258,6 +259,48 @@ void mmc_init_stream(struct hsmmc *mmc_base) } #if CONFIG_IS_ENABLED(DM_MMC) +static void omap_hsmmc_set_timing(struct mmc *mmc) +{ + u32 val; + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + + mmc_base = priv->base_addr; + + val = readl(&mmc_base->ac12); + val &= ~AC12_UHSMC_MASK; + priv->mode = mmc->selected_mode; + + switch (priv->mode) { + case MMC_HS_200: + case UHS_SDR104: + val |= AC12_UHSMC_SDR104; + break; + case UHS_SDR50: + val |= AC12_UHSMC_SDR50; + break; + case MMC_DDR_52: + case UHS_DDR50: + val |= AC12_UHSMC_DDR50; + break; + case SD_HS: + case MMC_HS_52: + case UHS_SDR25: + val |= AC12_UHSMC_SDR25; + break; + case MMC_LEGACY: + case MMC_HS: + case SD_LEGACY: + case UHS_SDR12: + val |= AC12_UHSMC_SDR12; + break; + default: + val |= AC12_UHSMC_RES; + break; + } + writel(val, &mmc_base->ac12); +} + static void omap_hsmmc_conf_bus_power(struct mmc *mmc) { struct hsmmc *mmc_base; @@ -924,6 +967,10 @@ static int omap_hsmmc_set_ios(struct udevice *dev) if (priv->clock != mmc->clock) omap_hsmmc_set_clock(mmc); +#if CONFIG_IS_ENABLED(DM_MMC) + if (priv->mode != mmc->selected_mode) + omap_hsmmc_set_timing(mmc); +#endif return 0; } From patchwork Thu Sep 21 15:22:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113275 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2159600qgf; Thu, 21 Sep 2017 08:27:33 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCahByUd1BdJXvYhZZSQqJbKuEqzrufUatXWkAsQuMotqs7eC8mCE7f34JpkhToqYPurQOI X-Received: by 10.80.146.115 with SMTP id j48mr1541790eda.132.1506007652951; Thu, 21 Sep 2017 08:27:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506007652; cv=none; d=google.com; s=arc-20160816; b=L3ZFXo5Ozx9I4jV90AzB8ViwqRZm8OuKGVijLzaQn1NJjnF9c1sQAwt30juK3ZTi7M buLDjuACvvh3frqlWlI3B39zWJPa6dGs2sMHXA0nXuugh7qpvGEC00c+tUPDVAgoFIOq rsSIwhEf6mGbhuSkzI6v4gJ44HGiExy5EaAzwjT4qEeOoihprLWNdVrDDGCt1xzdDPvj Wyfq92PdAzuO5d/TjJfv6LK0X2HK06+np9aM1ZXpw/A6fMe6fwke9kQU2fMdtN4U/hG+ g8DJrpS/5TE5rOdPqEXnFXQDfA+AaHLzdQahvLw40ego/wiAGSLbX59R+STYaSggaIBX wlKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=moOut4gYcdeRrZI7IatWnqBx7UpIPxmlXUsnCZT1+Z4=; b=PvFXEyyg+gzxk4S2hni2PqNL+EWQfxoojKuvw7ybydYLMh5BGVr3eRIxVfARCeC85z 9s5fYpNYmFaH3uT1hYiLGlxEfljQoD8jYbdCWNStqK2lrfgP8Vu8bm5szS7i9TlSkUiF jU5VKwy8fVqW+LN5SYFYkYP+8vtoUStCduzJKooGgcAM/GMFf+2bwCFIT0NDUjn2EEMt EXYAApY9o54IvQ3xnECK/Crp9WpBwd8iNU6gI1o7iTSLL0e0ggCMSJC5VO8XpQkQ3ezV g+jBhEAjV+KMo0U+QJpZBRWejNpjuxtkOGhwpOkqyI5rj3iHeoRa/SieP8Gdy+YBkJ6o B5kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=qb9hZQH7; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. 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Set it here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 1 + drivers/mmc/omap_hsmmc.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 3f94f2e..341a2e2 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -89,6 +89,7 @@ struct omap_hsmmc_plat { #define WPP_ACTIVEHIGH (0x0 << 8) #define RESERVED_MASK (0x3 << 9) #define CTPL_MMC_SD (0x0 << 11) +#define DDR (0x1 << 19) #define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 4a65a46..d5cd826 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -271,6 +271,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc) val &= ~AC12_UHSMC_MASK; priv->mode = mmc->selected_mode; + if (mmc_is_mode_ddr(priv->mode)) + writel(readl(&mmc_base->con) | DDR, &mmc_base->con); + else + writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); + switch (priv->mode) { case MMC_HS_200: case UHS_SDR104: From patchwork Thu Sep 21 15:22:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113282 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2168513qgf; Thu, 21 Sep 2017 08:35:35 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBzoIUcBnjXEo/mW8uai8/GV6CtOU8FCHbhzJQuxWiv58WdRmr4LdTY7albkUXvBo2xlK7V X-Received: by 10.80.179.47 with SMTP id q44mr1604744edd.123.1506008135157; Thu, 21 Sep 2017 08:35:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008135; cv=none; d=google.com; s=arc-20160816; b=p5PnsIyQ5rbhN8MM8P/ENPEIzMpn0Q+FvoN9ujWpi6ciIjMQ4U84KhHZh08xPFbvS8 Ic82rigMrkwnsuuHgHJaYW+V6v9T+AgI6UQm0+XPzdkw1rblpTAJM9schc6BKW9rlMsl LNzV+6KeS+itDN0nGVoAOchC/7sJqME1mmQV/lqCgd3TeW997Ug/qjG22h2RTom1C+UD 6voF3Qtej36av1EUkJ+lUk5lwN7nztOeOKvYGdfqmLEATb/7jRCnOFGXk+X9VJ2FBqwC qjDlvCdEyPRzO5APiiQugPHBkN5TIBSyU82PILt4t10lVyXpJZVfK5FEx+XT3jbJUvRB PvKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=vd41RABdxN/i1KFHos+SAJWunL9ZsecrWMU0UtY6tPs=; b=g0UiOUqjMpb7/0/rP0YFR3Hb3FT6+CZ2RxBagddwo6QPZPDYSQZQc9eIUJsXCLaNWz P3HIuRd3/ZH6+VHs4tH+IbWH1aymqcsQfb+O/ClIQ+nKyf7jFeqNvNosOoBQnD53wFf8 +lRRfufos+WSP262I4UzhWMh80C2VvdcEy50TdmlP7dt3cN701GBKXQ+M7hHVG/uNF+s XKlpqvJYJTAxGG27JxxaYQTjSEigjql0wYOnakg1s2ZdEKfYAiPZPZZSJy5QIe6Qkvhy NbRuEcH3aZsqWZGaZtGTdvIXpmKkfAaC90ceMiEFwArGIFu0rcyTt8QLv7JmTaGjz7yk PVQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=o2DpegYt; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id b13si1733064edi.30.2017.09.21.08.35.34; Thu, 21 Sep 2017 08:35:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=o2DpegYt; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id B9215C22117; Thu, 21 Sep 2017 15:28:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C458BC220B6; Thu, 21 Sep 2017 15:28:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 64F2CC22091; Thu, 21 Sep 2017 15:23:58 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id B588FC2205D for ; Thu, 21 Sep 2017 15:23:54 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMqJs009127; Thu, 21 Sep 2017 10:22:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007372; bh=Ucm4lqVe13YFtZDnIHUxkESLqTrwu2lHDaw+tuZA0E0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=o2DpegYtAZk9FpPc9IeOyf/ObvbguEz+0GJT0kLWODSHCGeUQ46eoWNeCrdM/TCV8 vUQUR2ADufoB3a2oIih5eCHSMZpp9ID9Om9ySGrLKR2KS9SWjffOv0Sn5v7NtK36U/ SNVYwwrrz7J6zGlnjKpnpazbrDWruCQL8Pi3r6Fw= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMlGi032760; Thu, 21 Sep 2017 10:22:47 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:47 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:47 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMkwu014784; Thu, 21 Sep 2017 10:22:46 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:09 +0200 Message-ID: <1506007346-10037-7-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 06/23] mmc: omap_hsmmc: Add tuning support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I HS200/SDR104 requires tuning command to be sent to the card. Use the mmc_send_tuning library function to send the tuning command and configure the internal DLL. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 21 ++++++- drivers/mmc/omap_hsmmc.c | 118 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 137 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 341a2e2..0293281 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -39,7 +39,9 @@ struct hsmmc { unsigned int sysstatus; /* 0x14 */ unsigned char res2[0x14]; unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; + unsigned int pwcnt; /* 0x30 */ + unsigned int dll; /* 0x34 */ + unsigned char res3[0xcc]; unsigned int blk; /* 0x104 */ unsigned int arg; /* 0x108 */ unsigned int cmd; /* 0x10C */ @@ -56,7 +58,8 @@ struct hsmmc { unsigned char res4[0x4]; unsigned int ac12; /* 0x13C */ unsigned int capa; /* 0x140 */ - unsigned char res5[0x10]; + unsigned int capa2; /* 0x144 */ + unsigned char res5[0xc]; unsigned int admaes; /* 0x154 */ unsigned int admasal; /* 0x158 */ }; @@ -173,6 +176,8 @@ struct omap_hsmmc_plat { #define IOV_1V8 1800000 #define AC12_ET (1 << 22) +#define AC12_V1V8_SIGEN (1 << 19) +#define AC12_SCLK_SEL (1 << 23) #define AC12_UHSMC_MASK (7 << 16) #define AC12_UHSMC_DDR50 (4 << 16) #define AC12_UHSMC_SDR104 (3 << 16) @@ -199,6 +204,18 @@ struct omap_hsmmc_plat { /* Clock Configurations and Macros */ #define MMC_CLOCK_REFERENCE 96 /* MHz */ +/* DLL */ +#define DLL_SWT (1 << 20) +#define DLL_FORCE_SR_C_SHIFT 13 +#define DLL_FORCE_SR_C_MASK 0x7f +#define DLL_FORCE_VALUE (1 << 12) +#define DLL_CALIB (1 << 1) + +#define MAX_PHASE_DELAY 0x7c + +/* CAPA2 */ +#define CAPA2_TSDR50 (1 << 13) + #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index d5cd826..321a091 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -124,6 +124,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); static void omap_hsmmc_start_clock(struct hsmmc *mmc_base); static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base); +static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit); static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) { @@ -355,6 +356,122 @@ static void omap_hsmmc_set_capabilities(struct mmc *mmc) writel(val, &mmc_base->capa); } + +static void omap_hsmmc_disable_tuning(struct mmc *mmc) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + + mmc_base = priv->base_addr; + val = readl(&mmc_base->ac12); + val &= ~(AC12_SCLK_SEL); + writel(val, &mmc_base->ac12); + + val = readl(&mmc_base->dll); + val &= ~(DLL_FORCE_VALUE | DLL_SWT); + writel(val, &mmc_base->dll); +} + +static void omap_hsmmc_set_dll(struct mmc *mmc, int count) +{ + int i; + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + + mmc_base = priv->base_addr; + val = readl(&mmc_base->dll); + val |= DLL_FORCE_VALUE; + val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT); + val |= (count << DLL_FORCE_SR_C_SHIFT); + writel(val, &mmc_base->dll); + + val |= DLL_CALIB; + writel(val, &mmc_base->dll); + for (i = 0; i < 1000; i++) { + if (readl(&mmc_base->dll) & DLL_CALIB) + break; + } + val &= ~DLL_CALIB; + writel(val, &mmc_base->dll); +} + +static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) +{ + struct omap_hsmmc_data *priv = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = upriv->mmc; + struct hsmmc *mmc_base; + u32 val; + u8 cur_match, prev_match = 0; + int ret; + u32 phase_delay = 0; + u32 start_window = 0, max_window = 0; + u32 length = 0, max_len = 0; + + mmc_base = priv->base_addr; + val = readl(&mmc_base->capa2); + + /* clock tuning is not needed for upto 52MHz */ + if (!((mmc->selected_mode == MMC_HS_200) || + (mmc->selected_mode == UHS_SDR104) || + ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50)))) + return 0; + + val = readl(&mmc_base->dll); + val |= DLL_SWT; + writel(val, &mmc_base->dll); + while (phase_delay <= MAX_PHASE_DELAY) { + omap_hsmmc_set_dll(mmc, phase_delay); + + cur_match = !mmc_send_tuning(mmc, opcode, NULL); + + if (cur_match) { + if (prev_match) { + length++; + } else { + start_window = phase_delay; + length = 1; + } + } + + if (length > max_len) { + max_window = start_window; + max_len = length; + } + + prev_match = cur_match; + phase_delay += 4; + } + + if (!max_len) { + ret = -EIO; + goto tuning_error; + } + + val = readl(&mmc_base->ac12); + if (!(val & AC12_SCLK_SEL)) { + ret = -EIO; + goto tuning_error; + } + + phase_delay = max_window + 4 * ((3 * max_len) >> 2); + omap_hsmmc_set_dll(mmc, phase_delay); + + mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); + mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); + + return 0; + +tuning_error: + + omap_hsmmc_disable_tuning(mmc); + mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); + mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); + + return ret; +} #endif static int omap_hsmmc_init_setup(struct mmc *mmc) @@ -1046,6 +1163,7 @@ static const struct dm_mmc_ops omap_hsmmc_ops = { .get_cd = omap_hsmmc_getcd, .get_wp = omap_hsmmc_getwp, #endif + .execute_tuning = omap_hsmmc_execute_tuning, }; #else static const struct mmc_ops omap_hsmmc_ops = { From patchwork Thu Sep 21 15:22:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113287 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2170981qgf; Thu, 21 Sep 2017 08:38:01 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDZidmwOqjql1egMCIvnPbtI6WFmWjpxYOJxyLkMdQxgCzAnQu6g3q1r/1yRC2w2Luk95zb X-Received: by 10.80.151.210 with SMTP id f18mr1598481edb.141.1506008281719; Thu, 21 Sep 2017 08:38:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008281; cv=none; d=google.com; s=arc-20160816; b=KIUbdnLimKsHyCMo+D2CmPzbCR7Z01qtifdxSvcJ5naTYCSGKKA+qtlPQ59I8mOhB2 kZEpX7VLNHjqe9y31yr2jVZzFtCgYYeODQoSJk1WRzpyx/OcuxloTfLtST+ZKL6Sfz4w QqGCA/VvlB1UEe0lBtjgpk7k46qesyhz2Br0JInra6YEtFkBN5ArZIBKv8khWEXyeDU2 hskNLO5jX8QxLJ0PeghZ8wnvXIw/ERfS3IJ78/rQ5+Tm3F7WMf314mniNewHt0x33NR/ 5mW0zolwNFA1Z4q36jH8pX8qu/DgNUIeECAtcc+rZMi9zN28jaUC2KtQEE3z593WFNRV 6rnQ== ARC-Message-Signature: i=1; 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[81.169.180.215]) by mx.google.com with ESMTP id j33si850486eda.5.2017.09.21.08.38.01; Thu, 21 Sep 2017 08:38:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=DmvdPdg+; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 36027C2209A; Thu, 21 Sep 2017 15:33:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9B90EC220C2; Thu, 21 Sep 2017 15:33:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B86CFC220BE; Thu, 21 Sep 2017 15:24:00 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 56A35C2203D for ; Thu, 21 Sep 2017 15:23:56 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMrZf009137; Thu, 21 Sep 2017 10:22:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007373; bh=DZcVRjVwQzmUyTgLDhVKFenjVJKeZrWFN43MF0d2RSs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DmvdPdg+AY+nAcaU+dRyfJuBYZJmyCSHiQsL2RDERd003M3WO+zsrUCh+sVyFQfWA iKj4127+1Msph5PybcMC/d9dFeDF1IsND9Inhbm3fNJ4ohQdTrp6uK12+13Opxsg+Z 3iwQ3Rx3DATA8CVVFo5ErwuI7iHOeNKEKhqvg4dI= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMm5o000326; Thu, 21 Sep 2017 10:22:48 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:48 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:48 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMllK001053; Thu, 21 Sep 2017 10:22:48 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:10 +0200 Message-ID: <1506007346-10037-8-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 07/23] mmc: omap_hsmmc: Workaround for errata id i802 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I According to errata i802, DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure. The DCRC interrupt, occurs when the last tuning block fails (the last ratio tested). The delay from CRC check until the interrupt is asserted is bigger than the delay until assertion of the tuning end flag. Assertion of tuning end flag is what masks the interrupts. Because of this race, an erroneous DCRC interrupt occurs. The suggested workaround is to disable DCRC interrupts during the tuning procedure which is implemented here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 4 ++++ drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++++++++++---- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 0293281..0893844 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -219,6 +219,10 @@ struct omap_hsmmc_plat { #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) +#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\ + IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\ + IE_BRR | IE_BWR | IE_TC | IE_CC) + int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, int wp_gpio); diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 321a091..8e42410 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -474,6 +474,25 @@ tuning_error: } #endif +static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct hsmmc *mmc_base = priv->base_addr; + u32 irq_mask = INT_EN_MASK; + + /* + * TODO: Errata i802 indicates only DCRC interrupts can occur during + * tuning procedure and DCRC should be disabled. But see occurences + * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These + * interrupts occur along with BRR, so the data is actually in the + * buffer. It has to be debugged why these interrutps occur + */ + if (cmd && mmc_is_tuning_cmd(cmd->cmdidx)) + irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC); + + writel(irq_mask, &mmc_base->ie); +} + static int omap_hsmmc_init_setup(struct mmc *mmc) { struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); @@ -540,10 +559,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); - writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | - IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC | - IE_CC, &mmc_base->ie); - + mmc_enable_irq(mmc, NULL); mmc_init_stream(mmc_base); return 0; @@ -806,6 +822,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, #endif } + mmc_enable_irq(mmc, cmd); + writel(cmd->cmdarg, &mmc_base->arg); udelay(20); /* To fix "No status update" error on eMMC */ writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); From patchwork Thu Sep 21 15:22:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113286 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2170675qgf; Thu, 21 Sep 2017 08:37:44 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBzZjjGzhv84JFTqYUygju5Yuj8im78uwbIUcCnF0folEih4GkBadLidLrjpZuJE66DjBn3 X-Received: by 10.80.163.248 with SMTP id t53mr1619595edb.160.1506008264606; Thu, 21 Sep 2017 08:37:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008264; cv=none; d=google.com; s=arc-20160816; b=Rh4egMYZ8b7KNRCheTCJV8vidL3TtZQ0GsGZXzyYs1mSuiU8AcRT1ZK5v9/NuNv9AH FyZACLq/2e6xt7RZ5k9uYSy2+H1NFjDwoyHH06xMQvb89o8AkUgsp0KrMZ7PXx5nlTV/ lDcbOqBNMZgdT6t96PKpmm19c4zsa2pgKCIks1lcAwkjbtF+ifIiDpbxQIVzirpQpizf cv6cSp7IrjCp7Vu0rJhsrY6OXX2J1bg9kdy8wMXAda9SgTQoeYMlWO9ZXUUUy1T84Smy yfVvxK1fkJvoRkydX2RMLwKYLWgyrczCsNeBx9AgT/YMRsUiLDnb3EWye3b+5uIBk1eh xZZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=4nnE567/DzLDdUhTewykEJZz2JKibE9YxXHDuvmUrRY=; b=fBcqRbvCfWIZnHSvapXbv66bnU73ENjz+5G/z+MHIT4lY/HsbaDTFSti8xFyNk4X4W GtwaBr3pRTJvDO/YwNN28c6EiKzfWfNgER4oebGEcBjSRDO0H+eUqtfUFZkN/9IPVc+o 29CViTt6RSnBCIYevcmc0z4O6z8jfyxD5oNhG6kyQ7AdJlh7LZe+EVXKqQjvPSl81jv6 qU0GUjHBzg7EQCyeWhXcyY2iYlj/mj0Bz6pq2cRtAUjpSHeX6LlVmARrXR/r+0LgAYH9 OaOejH4qTzb54o1qAnFv2dysSEkvGCCw3LW32NRSNiFEcROOXk5Guqx/vRkhS72dGiRH M58Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=qvbSVrPQ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id n17si1495966eda.165.2017.09.21.08.37.44; Thu, 21 Sep 2017 08:37:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=qvbSVrPQ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 3261EC220D0; Thu, 21 Sep 2017 15:29:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B5760C220A7; Thu, 21 Sep 2017 15:29:47 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4D8B2C220B2; Thu, 21 Sep 2017 15:24:03 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 6A6E6C2209A for ; Thu, 21 Sep 2017 15:23:58 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMuJp009145; Thu, 21 Sep 2017 10:22:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007376; bh=HW6K30WwGce274dn/NrhbWe1bpu3ys9vi+h7e446rOI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qvbSVrPQdf9BAoy7Jj2KaZILTQCJ/SMGmYA7JJqZFDBhhGW+Rcby8+8ZFmlUBJNbZ Opi/N7Fe8EnaRKPKL6Lq7yrl6JTEUa4Iu42534QipFojRC8wWH5mfx92jofZ67kq0a jpLOxTsxQnNeaB+xwfu/aBd8u0UUiYXPyX53rutQ= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMpvd000341; Thu, 21 Sep 2017 10:22:51 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:51 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:50 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMoZY001081; Thu, 21 Sep 2017 10:22:50 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:12 +0200 Message-ID: <1506007346-10037-10-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 09/23] mmc: omap_hsmmc: use mmc_of_parse to populate mmc_config X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Use the mmc_of_parse library function to populate mmc_config instead of repeating the same code in host controller driver. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- drivers/mmc/omap_hsmmc.c | 24 +++++------------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 116aa31..734854b 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -1291,32 +1291,18 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) struct mmc_config *cfg = &plat->cfg; const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); - int val; + int ret; plat->base_addr = map_physmem(devfdt_get_addr(dev), sizeof(struct hsmmc *), MAP_NOCACHE); - cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; - val = fdtdec_get_int(fdt, node, "bus-width", -1); - if (val < 0) { - printf("error: bus-width property missing\n"); - return -ENOENT; - } - - switch (val) { - case 0x8: - cfg->host_caps |= MMC_MODE_8BIT; - case 0x4: - cfg->host_caps |= MMC_MODE_4BIT; - break; - default: - printf("error: invalid bus-width property\n"); - return -ENOENT; - } + ret = mmc_of_parse(fdt, node, cfg); + if (ret < 0) + return ret; + cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; cfg->f_min = 400000; - cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; if (fdtdec_get_bool(fdt, node, "ti,dual-volt")) From patchwork Thu Sep 21 15:22:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113276 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2159712qgf; Thu, 21 Sep 2017 08:27:38 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBC7b+H96Wo4vb2lRI35+5wcmEMrEdGoND7vKSd6VwdjzXyUsxnVl7X0BcFDGfDXeB5n8/C X-Received: by 10.80.212.40 with SMTP id t40mr1627732edh.67.1506007658457; Thu, 21 Sep 2017 08:27:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506007658; cv=none; d=google.com; s=arc-20160816; b=ekhYsGCXlwee5Lo5/K9ZcI0e9CLysYo7BUfWRBSsJK3EhsywV9/3l5g5P/mFkxJSXb RUYOKXCeD+VGztSE8pInLO/7X9BDIM15R1RUTuk1Jnoy17Hk3Wzw3qvcm2GSjQwq9Y5+ 4EiEQk/tE4UVC/DyBCZ9DgG+qUhO+JARTkVBT7gpuDmYFX5gp91iTnUVlkiQFnZLAOaa nH5IkMnnrEIkiNu31ApUIAe/vylY4GdQSVQnp8N/lo4hT/G/Ojlrr4EY65vpEYknNv6k AqbtLNRaJmHhq8TBCrPagjzLOGgMFcnx1WX6WeArOCI5sn9c6SLjzc+sQAulDT58Pxxq XzJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=yh98QEK3t9aVJW4a/JQln3tZh7tWAzQetAft3LyV9I0=; b=hpi7rzrOJk79kYkjlrjsJM88FQyaDyzl0LQA6OD/a56cYypyTDMvGCscsUbWIp9+Au kNaWkr2RK8w7l8sVaAv5a9d8VxjE2Cl5xBbN2/zx12HP3XvD0E4GpmG5qFAaWmgIfoYv bfdITfCrdMvmLCkmmxcl+jinsqI4onkFRV7KCB5OS3hNJISoRDSpml3aQT1Z2JhjNkEn lAaFjOiQ25DwjpMp/z/6yLppJ5WImmlL0Rrx3OVkS7/kIvUJRz9SPp30CfJm7Um60Snq 4zNjXlYRgB75AgjVm4tA1+RPtxQis+JZ9lrHfbIAPtQrdrZN3pv0Qy7+TC/GaZxkrzN0 V9cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=y6+7Mhoy; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id c3si1825406edc.15.2017.09.21.08.27.38; Thu, 21 Sep 2017 08:27:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=y6+7Mhoy; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 08DABC2208E; Thu, 21 Sep 2017 15:23:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 58500C22068; Thu, 21 Sep 2017 15:23:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1C7DCC21FD0; Thu, 21 Sep 2017 15:22:58 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id 7B482C2203F for ; Thu, 21 Sep 2017 15:22:54 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMqoH010598; Thu, 21 Sep 2017 10:22:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007372; bh=92M/OmzV5qovTuXugUlI8oC6LFq00Y4thloiiCM0MK4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=y6+7MhoyCkXW8sE1zYLZpcxbeg+PmpN3SP5CsdBTxnRgWq552mgElqnd5IhXJNaxY GEWneG78RJCcop5HG6vDui8iSQ7G/ToPqL7tlC0kZRAoq5XJDrQ2EvwOyDWXMv+H1A zAfBg8OY2jQSaqUW0Dbn7HyEXXIZjl7fBAxrcYR4= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMq4s009461; Thu, 21 Sep 2017 10:22:52 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:52 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:52 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMp3x020830; Thu, 21 Sep 2017 10:22:51 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:13 +0200 Message-ID: <1506007346-10037-11-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 10/23] ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Add a new API to perform iodelay recalibration without isolate io to be used in uboot. The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. The MMC driver can use the new API to set the IO delay values depending on the MMC mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 3 +++ arch/arm/mach-omap2/omap5/dra7xx_iodelay.c | 30 ++++++++++++++++++++++++ include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 4 files changed, 33 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index c997004..a8780ee 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -83,6 +83,9 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, struct iodelay_cfg_entry const *iodelay, int niodelays); +void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays); int __recalibrate_iodelay_start(void); void __recalibrate_iodelay_end(int ret); diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c index 8798730..a9a9f75 100644 --- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c +++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c @@ -272,3 +272,33 @@ err: __recalibrate_iodelay_end(ret); } + +void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays) +{ + int ret = 0; + + /* unlock IODELAY CONFIG registers */ + writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); + + ret = calibrate_iodelay((*ctrl)->iodelay_config_base); + if (ret) + goto err; + + ret = update_delay_mechanism((*ctrl)->iodelay_config_base); + + /* Configure Mux settings */ + do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads); + + /* Configure Manual IO timing modes */ + ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); + if (ret) + goto err; + +err: + /* lock IODELAY CONFIG registers */ + writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); +} diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 0c70c53..4125391 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -15,9 +15,7 @@ #include #include -#ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION -#endif #define CONFIG_NR_DRAM_BANKS 2 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 6c0fc35..435284a 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -14,9 +14,7 @@ #include -#ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION -#endif #define CONFIG_VERY_BIG_RAM #define CONFIG_NR_DRAM_BANKS 2 From patchwork Thu Sep 21 15:22:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113274 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2158493qgf; Thu, 21 Sep 2017 08:26:38 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCXexYxFEZ/6tBt4aoQeCpMI1Mq/e2Z8f0VwEEYB8kIq56H7LbRUf6n5Y97D1SG+Fj2qHRq X-Received: by 10.80.148.124 with SMTP id q57mr1639831eda.198.1506007598003; Thu, 21 Sep 2017 08:26:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506007597; cv=none; d=google.com; s=arc-20160816; b=evWb+0g8EH44ylTcksq/76NsTsOIeYhxw3dmQJwhoZ5HjPhelhW7hdffF10FURj7TO CQiJTkpMYIEwToiqrDn/WgQJEAShCpI1091mUo64uMX5eDdRS/Jhf+yWxcFsFpbTUtW2 6r+wOkfpG+3obtMUP2xN6EwuFAEkJM53tZynJ5blqbyHqEV4nyRqn1Q6EPZ1eHMISJO4 2DiPjPW/g35SLkvVxYqIwxhsJfC2BqEQ3A/7KbOUueSO9/E5orM5xo8fIeCjEax+cu8W 5eh2+8fZCNKedFCceMiKOViac1DsUSpJKIYuv0in6aO5yOxnGxJW0f1RarzSoBnnL4eh 0IiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=lXpYuy9aSuGxCIDAgY75pWJyQfKxOO5bMDYflqyHpls=; b=crRccQ2LfVtg7dR7PE8GzgADH9OJRPlJkvltTXaTaapZS1teGQo5EH6IWVim96uMvb KXp5/VY25TrELRPgVsvt/Y1WqEmnenmgVcWrrnaIZpUKAV0IJAArbAcQFUoBeBlwCurw T4nFRL+ikgJDgcYsVkLQNhfoSaeQnB59WHlRValbzQyHu5QLuUwhyw1NgMnfn2yq1O7V QBJzzoB6C8s/n/UwPbcX1zrZ0vb6bX/G0FOszpuREJ3YCebttEHfMOSNno0FklHKORKQ cEjtp91lfrbfWV78PmQeyWnO0xogyh3y6W9tQEgsjx0vwP+5IOL4lFyTa0AoyHTGtvKC WYtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=UnK2yUAW; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id b12si1588060edm.95.2017.09.21.08.26.37; Thu, 21 Sep 2017 08:26:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=UnK2yUAW; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 81DAAC22071; Thu, 21 Sep 2017 15:24:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E406FC22050; Thu, 21 Sep 2017 15:23:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CEB16C21F67; Thu, 21 Sep 2017 15:23:00 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 5DE76C22027 for ; Thu, 21 Sep 2017 15:22:56 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMsuh007936; Thu, 21 Sep 2017 10:22:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007374; bh=7JKcrDIm0NZCIEv+WNjgsKrgziVictTDtMmC0/6RIUQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UnK2yUAWtWBa0R0JdSLNU4A/g8Z/oUcgpuQ9wzZeJO8pVrQDKwyilLvvZTRFp5n8p z55kkhiZUwUX0oGVazbelb2kJnc6jxNVM6Sem/lAOdlmAGXP2CFWmX8uBeFVO80V6t dmSI1wBFTqwuYv/JwLtX9/u/vW+5KEin0qskqGTE= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMrdH009488; Thu, 21 Sep 2017 10:22:53 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:53 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:53 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMqHi022918; Thu, 21 Sep 2017 10:22:53 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:14 +0200 Message-ID: <1506007346-10037-12-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 11/23] mmc: omap_hsmmc: Add support to set IODELAY values X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. Add support to parse mux values and iodelay values from device tree and set these depending on the enumerated MMC mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- drivers/mmc/omap_hsmmc.c | 372 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 372 insertions(+) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 734854b..67ba31e 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -34,6 +34,10 @@ #include #include #include +#ifdef CONFIG_OMAP54XX +#include +#include +#endif #if !defined(CONFIG_SOC_KEYSTONE) #include #include @@ -57,6 +61,15 @@ DECLARE_GLOBAL_DATA_PTR; #define SYSCTL_SRC (1 << 25) #define SYSCTL_SRD (1 << 26) +#ifdef CONFIG_IODELAY_RECALIBRATION +struct omap_hsmmc_pinctrl_state { + struct pad_conf_entry *padconf; + int npads; + struct iodelay_cfg_entry *iodelay; + int niodelays; +}; +#endif + struct omap_hsmmc_data { struct hsmmc *base_addr; #if !CONFIG_IS_ENABLED(DM_MMC) @@ -83,6 +96,17 @@ struct omap_hsmmc_data { struct omap_hsmmc_adma_desc *adma_desc_table; uint desc_slot; #endif +#ifdef CONFIG_IODELAY_RECALIBRATION + struct omap_hsmmc_pinctrl_state *default_pinctrl_state; + struct omap_hsmmc_pinctrl_state *hs_pinctrl_state; + struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state; + struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state; + struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state; + struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state; + struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state; + struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state; + struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state; +#endif }; #ifndef CONFIG_OMAP34XX @@ -93,6 +117,10 @@ struct omap_hsmmc_adma_desc { u32 addr; }; +struct omap_mmc_of_data { + u8 controller_flags; +}; + #define ADMA_MAX_LEN 63488 /* Decriptor table defines */ @@ -119,6 +147,7 @@ struct omap_hsmmc_adma_desc { #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) #define OMAP_HSMMC_NO_1_8_V BIT(1) #define OMAP_HSMMC_USE_ADMA BIT(2) +#define OMAP_HSMMC_REQUIRE_IODELAY BIT(3) static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, @@ -261,6 +290,56 @@ void mmc_init_stream(struct hsmmc *mmc_base) } #if CONFIG_IS_ENABLED(DM_MMC) +#ifdef CONFIG_IODELAY_RECALIBRATION +static void omap_hsmmc_io_recalibrate(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct omap_hsmmc_pinctrl_state *pinctrl_state; + + switch (priv->mode) { + case MMC_HS_200: + pinctrl_state = priv->hs200_1_8v_pinctrl_state; + break; + case UHS_SDR104: + pinctrl_state = priv->sdr104_pinctrl_state; + break; + case UHS_SDR50: + pinctrl_state = priv->sdr50_pinctrl_state; + break; + case UHS_DDR50: + pinctrl_state = priv->ddr50_pinctrl_state; + break; + case UHS_SDR25: + pinctrl_state = priv->sdr25_pinctrl_state; + break; + case UHS_SDR12: + pinctrl_state = priv->sdr12_pinctrl_state; + break; + case SD_HS: + case MMC_HS: + case MMC_HS_52: + pinctrl_state = priv->hs_pinctrl_state; + break; + case MMC_DDR_52: + pinctrl_state = priv->ddr_1_8v_pinctrl_state; + default: + pinctrl_state = priv->default_pinctrl_state; + break; + } + + if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) { + if (pinctrl_state->iodelay) + late_recalibrate_iodelay(pinctrl_state->padconf, + pinctrl_state->npads, + pinctrl_state->iodelay, + pinctrl_state->niodelays); + else + do_set_mux32((*ctrl)->control_padconf_core_base, + pinctrl_state->padconf, + pinctrl_state->npads); + } +} +#endif static void omap_hsmmc_set_timing(struct mmc *mmc) { u32 val; @@ -269,6 +348,7 @@ static void omap_hsmmc_set_timing(struct mmc *mmc) mmc_base = priv->base_addr; + omap_hsmmc_stop_clock(mmc_base); val = readl(&mmc_base->ac12); val &= ~AC12_UHSMC_MASK; priv->mode = mmc->selected_mode; @@ -306,6 +386,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc) break; } writel(val, &mmc_base->ac12); + +#ifdef CONFIG_IODELAY_RECALIBRATION + omap_hsmmc_io_recalibrate(mmc); +#endif + omap_hsmmc_start_clock(mmc_base); } static void omap_hsmmc_conf_bus_power(struct mmc *mmc) @@ -1284,10 +1369,271 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, return 0; } #else + +#ifdef CONFIG_IODELAY_RECALIBRATION +static struct pad_conf_entry * +omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count) +{ + int index = 0; + struct pad_conf_entry *padconf; + + padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count); + if (!padconf) { + debug("failed to allocate memory\n"); + return 0; + } + + while (index < count) { + padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]); + padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]); + index++; + } + + return padconf; +} + +static struct iodelay_cfg_entry * +omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count) +{ + int index = 0; + struct iodelay_cfg_entry *iodelay; + + iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count); + if (!iodelay) { + debug("failed to allocate memory\n"); + return 0; + } + + while (index < count) { + iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]); + iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]); + iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]); + index++; + } + + return iodelay; +} + +static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle, + const char *name, int *len) +{ + const void *fdt = gd->fdt_blob; + int offset; + const fdt32_t *pinctrl; + + offset = fdt_node_offset_by_phandle(fdt, phandle); + if (offset < 0) { + debug("failed to get pinctrl node %s.\n", + fdt_strerror(offset)); + return 0; + } + + pinctrl = fdt_getprop(fdt, offset, name, len); + if (!pinctrl) { + debug("failed to get property %s\n", name); + return 0; + } + + return pinctrl; +} + +static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc, + char *prop_name) +{ + const void *fdt = gd->fdt_blob; + const __be32 *phandle; + int node = dev_of_offset(mmc->dev); + + phandle = fdt_getprop(fdt, node, prop_name, NULL); + if (!phandle) { + debug("failed to get property %s\n", prop_name); + return 0; + } + + return fdt32_to_cpu(*phandle); +} + +static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc, + char *prop_name) +{ + const void *fdt = gd->fdt_blob; + const __be32 *phandle; + int len; + int count; + int node = dev_of_offset(mmc->dev); + + phandle = fdt_getprop(fdt, node, prop_name, &len); + if (!phandle) { + debug("failed to get property %s\n", prop_name); + return 0; + } + + /* No manual mode iodelay values if count < 2 */ + count = len / sizeof(*phandle); + if (count < 2) + return 0; + + return fdt32_to_cpu(*(phandle + 1)); +} + +static struct pad_conf_entry * +omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads) +{ + int len; + int count; + struct pad_conf_entry *padconf; + u32 phandle; + const fdt32_t *pinctrl; + + phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name); + if (!phandle) + return ERR_PTR(-EINVAL); + + pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins", + &len); + if (!pinctrl) + return ERR_PTR(-EINVAL); + + count = (len / sizeof(*pinctrl)) / 2; + padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count); + if (!padconf) + return ERR_PTR(-EINVAL); + + *npads = count; + + return padconf; +} + +static struct iodelay_cfg_entry * +omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay) +{ + int len; + int count; + struct iodelay_cfg_entry *iodelay; + u32 phandle; + const fdt32_t *pinctrl; + + phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name); + /* Not all modes have manual mode iodelay values. So its not fatal */ + if (!phandle) + return 0; + + pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array", + &len); + if (!pinctrl) + return ERR_PTR(-EINVAL); + + count = (len / sizeof(*pinctrl)) / 3; + iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count); + if (!iodelay) + return ERR_PTR(-EINVAL); + + *niodelay = count; + + return iodelay; +} + +static struct omap_hsmmc_pinctrl_state * +omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode) +{ + int index; + int npads = 0; + int niodelays = 0; + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(mmc->dev); + char prop_name[11]; + struct omap_hsmmc_pinctrl_state *pinctrl_state; + + pinctrl_state = (struct omap_hsmmc_pinctrl_state *) + malloc(sizeof(*pinctrl_state)); + if (!pinctrl_state) { + debug("failed to allocate memory\n"); + return 0; + } + + index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode); + if (index < 0) { + debug("fail to find %s mode %s\n", mode, fdt_strerror(index)); + goto err_pinctrl_state; + } + + sprintf(prop_name, "pinctrl-%d", index); + + pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name, + &npads); + if (IS_ERR(pinctrl_state->padconf)) + goto err_pinctrl_state; + pinctrl_state->npads = npads; + + pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name, + &niodelays); + if (IS_ERR(pinctrl_state->iodelay)) + goto err_padconf; + pinctrl_state->niodelays = niodelays; + + return pinctrl_state; + +err_padconf: + kfree(pinctrl_state->padconf); + +err_pinctrl_state: + kfree(pinctrl_state); + return 0; +} + +#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode) \ + do { \ + struct omap_hsmmc_pinctrl_state *s; \ + if (!(cfg->host_caps & capmask)) \ + break; \ + \ + s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \ + if (!s) { \ + debug("%s: no pinctrl for %s\n", \ + mmc->dev->name, #mode); \ + cfg->host_caps &= ~(capmask); \ + } else { \ + priv->mode##_pinctrl_state = s; \ + } \ + } while (0) + +static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); + struct omap_hsmmc_pinctrl_state *default_pinctrl; + + if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) + return 0; + + default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default"); + if (!default_pinctrl) { + printf("no pinctrl state for default mode\n"); + return -EINVAL; + } + + priv->default_pinctrl_state = default_pinctrl; + + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12); + + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v); + OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs); + + return 0; +} +#endif + #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) { struct omap_hsmmc_plat *plat = dev_get_platdata(dev); + struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev); + struct mmc_config *cfg = &plat->cfg; const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); @@ -1309,6 +1655,8 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; if (fdtdec_get_bool(fdt, node, "no-1-8-v")) plat->controller_flags |= OMAP_HSMMC_NO_1_8_V; + if (of_data) + plat->controller_flags |= of_data->controller_flags; #ifdef OMAP_HSMMC_USE_GPIO plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); @@ -1334,9 +1682,13 @@ static int omap_hsmmc_probe(struct udevice *dev) struct omap_hsmmc_data *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; struct mmc *mmc; +#ifdef CONFIG_IODELAY_RECALIBRATION + int ret; +#endif cfg->name = "OMAP SD/MMC"; priv->base_addr = plat->base_addr; + priv->controller_flags = plat->controller_flags; #ifdef OMAP_HSMMC_USE_GPIO priv->cd_inverted = plat->cd_inverted; #endif @@ -1357,14 +1709,34 @@ static int omap_hsmmc_probe(struct udevice *dev) mmc->dev = dev; upriv->mmc = mmc; +#ifdef CONFIG_IODELAY_RECALIBRATION + ret = omap_hsmmc_get_pinctrl_state(mmc); + /* + * disable high speed modes for the platforms that require IO delay + * and for which we don't have this information + */ + if ((ret < 0) && + (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) { + priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY; + cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) | + UHS_CAPS); + } +#endif + return omap_hsmmc_init_setup(mmc); } #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + +static const struct omap_mmc_of_data dra7_mmc_of_data = { + .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY, +}; + static const struct udevice_id omap_hsmmc_ids[] = { { .compatible = "ti,omap3-hsmmc" }, { .compatible = "ti,omap4-hsmmc" }, { .compatible = "ti,am33xx-hsmmc" }, + { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data }, { } }; #endif From patchwork Thu Sep 21 15:22:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113277 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2160739qgf; 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[81.169.180.215]) by mx.google.com with ESMTP id x14si1759175edb.123.2017.09.21.08.28.34; Thu, 21 Sep 2017 08:28:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=SDI3/ZPs; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id D77F3C22090; Thu, 21 Sep 2017 15:25:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 03E13C22040; Thu, 21 Sep 2017 15:23:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 788CFC2203F; Thu, 21 Sep 2017 15:23:01 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 6F6FFC22020 for ; Thu, 21 Sep 2017 15:22:57 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMtPC013941; Thu, 21 Sep 2017 10:22:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007375; bh=rKP17F2MlPEGEoPgTLqhBifHPzoMTglj4VCrXkz6/RA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SDI3/ZPs7beepsJFT15Qgbt5ZDURtXO6AG8bUwYRfcis26VEmm54bDB2ZDQ9Rhro7 J4fMosbvyZWyEsey2y+v+tBCitwKykP7pvJBgPhsh9kZn3PdDtYkPnzu4pS9hlOxE+ oyZnWB0wghT1qIHr4bqD96cdACCEfJZQOGsh5Efs= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMtTJ009527; Thu, 21 Sep 2017 10:22:55 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:54 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:55 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMsr0022934; Thu, 21 Sep 2017 10:22:54 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:15 +0200 Message-ID: <1506007346-10037-13-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 12/23] mmc: omap_hsmmc: Add support to get pinctrl values and max frequency for different hw revisions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I AM572x SR1.1 requires different IODelay values to be used than that used in AM572x SR2.0. These values are populated in device tree. Add capability in omap_hsmmc driver to extract IOdelay values for different silicon revision. The maximum frequency is also reduced when using a ES1.1. To keep the ability to boot both revsions with the same dtb, those values can be provided by the platform code. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/arch-omap5/sys_proto.h | 7 ++++ arch/arm/include/asm/omap_mmc.h | 1 + drivers/mmc/omap_hsmmc.c | 58 ++++++++++++++++++++++------- 3 files changed, 52 insertions(+), 14 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index ab0e7fa..d391ee5 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -35,6 +35,12 @@ struct pad_conf_entry { u32 val; }; +struct mmc_platform_fixups { + const char *hw_rev; + u32 unsupported_caps; + u32 max_freq; +}; + struct omap_sysinfo { char *board_string; }; @@ -70,6 +76,7 @@ void force_emif_self_refresh(void); void get_ioregs(const struct ctrl_ioregs **regs); void srcomp_enable(void); void setup_warmreset_time(void); +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr); static inline u32 div_round_up(u32 num, u32 den) { diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 0893844..3073805 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -70,6 +70,7 @@ struct omap_hsmmc_plat { struct mmc mmc; bool cd_inverted; u32 controller_flags; + const char *hw_rev; }; /* diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 67ba31e..a83c589 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -96,6 +96,7 @@ struct omap_hsmmc_data { struct omap_hsmmc_adma_desc *adma_desc_table; uint desc_slot; #endif + const char *hw_rev; #ifdef CONFIG_IODELAY_RECALIBRATION struct omap_hsmmc_pinctrl_state *default_pinctrl_state; struct omap_hsmmc_pinctrl_state *hs_pinctrl_state; @@ -1362,6 +1363,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) cfg->b_max = 1; #endif + mmc = mmc_create(cfg, priv); if (mmc == NULL) return -1; @@ -1581,20 +1583,28 @@ err_pinctrl_state: return 0; } -#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode) \ - do { \ - struct omap_hsmmc_pinctrl_state *s; \ - if (!(cfg->host_caps & capmask)) \ - break; \ - \ - s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \ - if (!s) { \ - debug("%s: no pinctrl for %s\n", \ - mmc->dev->name, #mode); \ - cfg->host_caps &= ~(capmask); \ - } else { \ - priv->mode##_pinctrl_state = s; \ - } \ +#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode) \ + do { \ + struct omap_hsmmc_pinctrl_state *s = NULL; \ + char str[20]; \ + if (!(cfg->host_caps & capmask)) \ + break; \ + \ + if (priv->hw_rev) { \ + sprintf(str, "%s-%s", #mode, priv->hw_rev); \ + s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \ + } \ + \ + if (!s) \ + s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \ + \ + if (!s) { \ + debug("%s: no pinctrl for %s\n", \ + mmc->dev->name, #mode); \ + cfg->host_caps &= ~(capmask); \ + } else { \ + priv->mode##_pinctrl_state = s; \ + } \ } while (0) static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) @@ -1629,12 +1639,22 @@ static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) #endif #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#ifdef CONFIG_OMAP54XX +__weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + return NULL; +} +#endif + static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) { struct omap_hsmmc_plat *plat = dev_get_platdata(dev); struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev); struct mmc_config *cfg = &plat->cfg; +#ifdef CONFIG_OMAP54XX + const struct mmc_platform_fixups *fixups; +#endif const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); int ret; @@ -1658,6 +1678,15 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) if (of_data) plat->controller_flags |= of_data->controller_flags; +#ifdef CONFIG_OMAP54XX + fixups = platform_fixups_mmc(devfdt_get_addr(dev)); + if (fixups) { + plat->hw_rev = fixups->hw_rev; + cfg->host_caps &= ~fixups->unsupported_caps; + cfg->f_max = fixups->max_freq; + } +#endif + #ifdef OMAP_HSMMC_USE_GPIO plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); #endif @@ -1689,6 +1718,7 @@ static int omap_hsmmc_probe(struct udevice *dev) cfg->name = "OMAP SD/MMC"; priv->base_addr = plat->base_addr; priv->controller_flags = plat->controller_flags; + priv->hw_rev = plat->hw_rev; #ifdef OMAP_HSMMC_USE_GPIO priv->cd_inverted = plat->cd_inverted; #endif From patchwork Thu Sep 21 15:22:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113281 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2166750qgf; Thu, 21 Sep 2017 08:33:50 -0700 (PDT) X-Google-Smtp-Source: AOwi7QA5DCbH29fQU3JEemI9UMVIuJTmSB12ZK4PU5Qbe4yvggkLqZin8wehmqQJ4+6B9lGyS0q+ X-Received: by 10.80.165.141 with SMTP id a13mr1591641edc.200.1506008030202; Thu, 21 Sep 2017 08:33:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008030; cv=none; d=google.com; s=arc-20160816; b=ZcZgwya0E3/RYQglhMhaFLtnXowhIYIcB4+1qYIW6KyZxtESPy6Stb7X4zJhKB7J/8 Fh5nW8QeVXzttHpIoBDaaZCJbQ/nQtik7BphUj1uLQ554QLmIxVIsIa8AyUmZnhnp9Ju +Qgx4wgSIZ8j4tmfzCg8SjAIJqyBvSCe3j9CTxzLZKrT2aj2bPO6n3P2FfsyCyIzKBQZ /0k4uyCg0dmw0wAcTlwX4S20wvsEmQQW8/F4sgKxAmGh04Anf6lUh61ADdPrJP4Xlu77 wx09/Xa717N+4p8Npa41SUzd9QndXSm+p+kIXQm8lvfPOVLudGIjsLpeTOr+A/K7yN4X Ie7w== ARC-Message-Signature: i=1; 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[81.169.180.215]) by mx.google.com with ESMTP id 92si623767edn.391.2017.09.21.08.33.49; Thu, 21 Sep 2017 08:33:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=qWgCHM0O; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id D9151C220EC; Thu, 21 Sep 2017 15:26:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2A7DEC21FFE; Thu, 21 Sep 2017 15:24:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 45E0DC21E5B; Thu, 21 Sep 2017 15:23:06 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 4C2F7C2203F for ; Thu, 21 Sep 2017 15:23:02 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFN0Pm007954; Thu, 21 Sep 2017 10:23:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007380; bh=oLkroCB5WIGj/iPoCXrGFfaWlC1lPrmyV67J/DAaKOA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qWgCHM0OC0Jq+jFcLiZlb5M24AcSbLqAUpVGRBKkaKw3fnO5b0LOeOjrlyp8Lw4Pk ff1/ZnSm7gg9SDBsZdWiTYlJcxBKZJ5qmQa1DxD+Rd85BJSUUu9gJuka1BLADvUlt7 XOReQTf2BAGMWUQgaAvxSVhi1JrYkJKy6X/iSXjA= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN0f1000595; Thu, 21 Sep 2017 10:23:00 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:23:00 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:59 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMxjf020995; Thu, 21 Sep 2017 10:22:59 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:19 +0200 Message-ID: <1506007346-10037-17-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 16/23] mmc: omap_hsmmc: allow mmc clock to be gated X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I mmc core has defined a new parameter *clk_disable* to gate the clock. Disable the clock here if *clk_disable* is set. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- drivers/mmc/omap_hsmmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 0a4f8a7..f3da446 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -1203,6 +1203,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct mmc *mmc = upriv->mmc; #endif + struct hsmmc *mmc_base = priv->base_addr; if (priv->bus_width != mmc->bus_width) omap_hsmmc_set_bus_width(mmc); @@ -1210,6 +1211,11 @@ static int omap_hsmmc_set_ios(struct udevice *dev) if (priv->clock != mmc->clock) omap_hsmmc_set_clock(mmc); + if (mmc->clk_disable) + omap_hsmmc_stop_clock(mmc_base); + else + omap_hsmmc_start_clock(mmc_base); + #if CONFIG_IS_ENABLED(DM_MMC) if (priv->mode != mmc->selected_mode) omap_hsmmc_set_timing(mmc); From patchwork Thu Sep 21 15:22:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113284 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2169994qgf; Thu, 21 Sep 2017 08:37:01 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDj2LFYuW8O8Xi/p2lkQX19DXwXr9bfDTj41ZTgCCcANAJpNnnWEt5oGnSeI/LbxWjQTdpg X-Received: by 10.80.144.242 with SMTP id d47mr1624499eda.79.1506008221820; Thu, 21 Sep 2017 08:37:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008221; cv=none; d=google.com; s=arc-20160816; b=VEdyxO+Y84mwKgv6lczklFz8s968D+iTBJZBfbaxt5nmOsNsF04nt2Byhl8jvlG1Yn MfqTVv4ECyEo0Xz2eA2FSR8DrkczYP2mqxnt3G8M5I3wXuUzRRe4ZEKEFO4DGVOqs6Tw ej7bJx3cmhz5PKYvbN0vlY9OWnhClImBZxZaDVZAJtZy5GQ7frYloZdcGccDsdzKi0BB 34N6fKYELf1IjQFcC0FHPiRUwEPbk+2MiZLN8sX7Rsmba9gE0NLnV74FOn3OBzFE9laY LnweE9ntXkKus5twMX0ESyuIcKKYEoElrhAxvo/seUMwbODafQDZBP08GyR3/N4kYl0A d+6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=EO1XApAFEMvQwlI2hWs26o2YeEkoF8gIov2I52NMPD8=; b=WDyNkOjDm/OCv8PKhZ5f5zUFXqJkn/7hpcmztxWfrcjyIM9/iHqe4tc4q4dTVRDLMr 7g7TOIV5p44EoiXejb7P6MobOFVzGm92ONjqVD9zPnxeCX+o2WFoEy4A+beq73jA0WP3 nS30B2WfynTNOU59Z5eluBgKO45umva9jWcYqTrTVcusc7B6TExiF5VSlsIOijz7YKIM NwAwTFr/7UjK6kIVULTITI+aqNqTjGHsAnx2LgldU8VHnhpkLrWh2MQMH/1KVJxmztPi rYzAyqVDJfhUcIL0Yfm3SMHzJi3Q4Y/IDw6PSrtJ5fN544kXLHFIdgKWbl3WDrDOFhXp 5TRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=vjqWAi0e; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. 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Also change the REFERENCE CLOCK frequency to 192MHz based on which the internal mmc clock divider is calculated. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/arch-omap5/clock.h | 2 +- arch/arm/include/asm/omap_mmc.h | 4 ++++ arch/arm/mach-omap2/omap5/hw_data.c | 10 +++++----- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index ee2e78b..3d718c0 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -135,7 +135,7 @@ /* CM_L3INIT_HSMMCn_CLKCTRL */ #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) -#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) /* CM_L3INIT_SATA_CLKCTRL */ #define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 6871f54..d604b79 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -199,7 +199,11 @@ struct omap_hsmmc_plat { #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) /* Clock Configurations and Macros */ +#ifdef CONFIG_OMAP54XX +#define MMC_CLOCK_REFERENCE 192 /* MHz */ +#else #define MMC_CLOCK_REFERENCE 96 /* MHz */ +#endif /* DLL */ #define DLL_SWT (1 << 20) diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index 3bdb114..30e3b68 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -438,17 +438,17 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, GPIO4_CLKCTRL_OPTFCLKEN_MASK); - /* Enable 96 MHz clock for MMC1 & MMC2 */ + /* Enable 192 MHz clock for MMC1 & MMC2 */ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); /* Set the correct clock dividers for mmc */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); /* Select 32KHz clock as the source of GPTIMER1 */ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, From patchwork Thu Sep 21 15:22:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113283 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2169221qgf; Thu, 21 Sep 2017 08:36:13 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAWisJdnu/+RGpSrHd9flUX3JQ/nq9v+Tz2+5Y1v9z2a7peagTvsHUQfF5AghYgyRMqBZGW X-Received: by 10.80.192.71 with SMTP id u7mr1649821edd.153.1506008173389; Thu, 21 Sep 2017 08:36:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008173; cv=none; d=google.com; s=arc-20160816; b=PoiRbJ0AAbOu3GD6UgrFd5DyKCl1veFZ4z6dvoQPNi5ArMWi3JcTwg0kx6xSOB/Z+v LLWgTpsGrVbQu+zaBe+9wDnQuhQybozT54GI7KKP5WJ/ZIIeUSGU4isDa/lkesYUo9F6 2jKrJJGD1W2/SyR+X6xe7bHC1DDmi7gPtcutRjd0f9O4Ylcm7xIi/EgH/drO9N8i6sq/ RaBifBsCDOAsH8Aj0KCPaTvcadoEwPInrk9dyfZUpJPGz9WsF33yuXznUmncaM8AyGPV 7cZAH9v5RNE0PJveNb1m7/ZiiSfXKKn7kBki/rCIC1uerVTcmQw5sDaf8NJCDMTBBPqy hO/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=yEUihYcgYTtboqazFqCb3HzNvmN6spU8e6xXvT3ZhVU=; b=dHf207Obr65Ba3XQ468NjWfu/3OAbhesQ/E4r/kvbG6hBuBr9Qf9aFBRKdlTE2wcHE 5OqPM7Iqe9b5Vq5Mxusfe+QjbxIHv6eZzJp4Yd+9dWjxW6UHKNFYGWm5uWLVQFZ4Knqk ZjRURT6IFyCkDzExwsj6xQXQAySDHgPxaKjYAlAGrMxvH0fCoXFNZLBanQOSqgmpyqf/ W5/UiTqpaezUVn8kQWdFwjqGvTFousb7lGreZ1QahXTqcRgLZEke/eG3ay6ul5SWnxWB ulNxh4KM451C2P84SYdwe/a/FAv+xiDeKv5UoafMTj1BZcpsNsgWs22yIUT+o27K3243 3pKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Xaa78Ys+; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. 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This is required since for dra7 and dra72 processors iodelay values has to be set unlike other processors. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Jean-Jacques Hiblot --- arch/arm/dts/dra7.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index 02a136a..9061843 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -1056,7 +1056,7 @@ }; mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; interrupts = ; ti,hwmods = "mmc1"; @@ -1070,7 +1070,7 @@ }; mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; interrupts = ; ti,hwmods = "mmc2"; @@ -1082,7 +1082,7 @@ }; mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; interrupts = ; ti,hwmods = "mmc3"; @@ -1095,7 +1095,7 @@ }; mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; interrupts = ; ti,hwmods = "mmc4"; From patchwork Thu Sep 21 15:22:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113279 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2166251qgf; Thu, 21 Sep 2017 08:33:23 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAZtWIlzdRbsSgFis3huBWTVuo7r+5XU/Th2aA6cCLTfbGAfqCZWeQ9XJUZ9c5GpizOcAn9 X-Received: by 10.80.134.183 with SMTP id r52mr1637214eda.152.1506008003341; Thu, 21 Sep 2017 08:33:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008003; cv=none; d=google.com; s=arc-20160816; b=hHNNDat7cMsIIEGq9chzqShxZLBg/YCieQxsZPktQTSXy5woGUMhC4Gg8HgpYlb/WK HUL93xmfN1Opey+HNxWtuG8fpy144hk4TVVGUJ6516G2u7ifHLIRHMNL1sNLZc4yB/T/ l7T5qcFqRhDPXmtb/W2PZruxLno64xeGeG68er+SedcfjfSb8p6jVJKKVP6uvMc8POpp inZz8e6keMm56dKX4DACUZHuYn//licFLPQFTx2+iupy+9IAtwNLrlFhL9UR3aeHo+Lw o0gXzPjQgSwwDxGVrd3TfWSSpq+foGrgzFldfXuyEXnUQvE7z7k8B4THz7p3hjHZBZbe fZAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=7aoiF8lyLtTv2y/xBOY+fXr5hJcbpYrQ5gmX2hFvMG8=; b=ECdP1BfqfCeFvx1IuzvWzb8eZzqeN7zvUbznkzU2w6hR4aklpA+RF28vLmgrUkkkQ4 /xEVw/rCxs5srlDnbjubaKkKd1GeIc7ooa9Llx049rOE34odYH6RlJfe5fabCSi1xzLA 5KN9w9MQo+WZcwK7IGoKiWKNOO84AxVY9uD/7Vf9Pi5BggzhnV8dmTj13RSsKaXBXVgD G6nWaDFSPN2f1yDjty8EM5whbe2csj+6imD/4aOwmtb0Ne0XitPkAzTQ6bc9BAUR3mCT fz20RpALz4wwZXvMQbA3h8RZSWH8ADbtHHPVmzEuG2lmxekZvxVNEdYWlngOAOYqQsWi W2/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=b3s6/zP/; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id t2si1082219edj.454.2017.09.21.08.33.23; Thu, 21 Sep 2017 08:33:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=b3s6/zP/; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id EC4B8C21FED; Thu, 21 Sep 2017 15:26:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E115CC22033; Thu, 21 Sep 2017 15:25:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E7083C22046; Thu, 21 Sep 2017 15:23:15 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id 1B38EC21FD0 for ; Thu, 21 Sep 2017 15:23:10 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFN9X4010637; Thu, 21 Sep 2017 10:23:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007389; bh=5LOHNyz7V5DiDn8LO4y4svg6Dg0kNsG4QjyB+UbkzXg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=b3s6/zP/b6yJU/AdjyI46eM/iUORHYdwLbvp/VsnAaXsfqc6VICbVzlzJ9XQGhtJ1 dPW705h/s01HElEHYOb8TemFTV0+TaqWvxu8RUN1IawaC2o1XvsyF3utUVNfTg2uLA LAfcs1aTq3gX6In3jK+bdoTb25MPZ0MCmrcUv9Lo= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN9dk001141; Thu, 21 Sep 2017 10:23:09 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:23:08 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:23:08 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN8TM023372; Thu, 21 Sep 2017 10:23:08 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:26 +0200 Message-ID: <1506007346-10037-24-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 23/23] ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Since DRA7xx/AM57xx SR1.1 and SR1.0 has errata to limit the frequency of MMC1 to 96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1, limit the frequency and disable higher speed modes for those revision. Also use the recommended IO delays (those tagged with "rev11") Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- board/ti/am57xx/board.c | 30 ++++++++++++++++++++++++++++++ board/ti/dra7xx/evm.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index f79aefd..4f2f8ef 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "../common/board_detect.h" #include "mux_data.h" @@ -762,6 +763,35 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104), + .max_freq = 96000000, +}; + +static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104) | + MMC_CAP(UHS_SDR50), + .max_freq = 48000000, +}; + +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + if (addr == OMAP_HSMMC1_BASE) + return &am57x_es1_1_mmc1_fixups; + else + return &am57x_es1_1_mmc23_fixups; + default: + return NULL; + } +} #endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 97aae01..f82e4c0 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -846,6 +846,35 @@ void board_mmc_poweron_ldo(uint voltage) palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage); } } + +static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104), + .max_freq = 96000000, +}; + +static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104) | + MMC_CAP(UHS_SDR50), + .max_freq = 48000000, +}; + +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + if (addr == OMAP_HSMMC1_BASE) + return &dra7x_es1_1_mmc1_fixups; + else + return &dra7x_es1_1_mmc23_fixups; + default: + return NULL; + } +} #endif #ifdef CONFIG_USB_DWC3